ADM1028
a
REV. PrD 05/2000
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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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Tel: 781/329-4700 W or ld Wide Web Site: http://www.analog.com
F ax: 781/326-8703 Analog Devices, Inc., 1998
Low Cost PC Temperature
Monitor and Fan Control ASIC
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
FEATURES
On-Chip Temperature Sensor
External Temperature Measurement with Remote Diode
Interrupt and Overtemperature Outputs
Fault Tolerant Fan Control With Auto Hardware Trip Point
Remote Reset and Power Down Functions
LDCM Support
System Management Bus (SMBus) Communications
Standby Mode to Minimize Power Consumption
Limit Comparison of all Monitored Values
APPLICATIONS
Network Servers and Personal Computers
Microprocessor-Based Office Equipment
Test Equipment and Measuring Instruments
GENERAL DESCRIPTION
The ADM1028 is a low-cost temperature monitor and fan
controller for microprocessor-based systems. The tem-
perature of a remote sensor diode may be measured, al-
lowing monitoring of processor temperature in single
processor systems. An on-chip temp sensor monitors
ambient system temperature.
Measured values can be read out via the System Manage-
ment Bus, and values for limit comparisons can be pro-
grammed in over the same serial bus.
The ADM1028 also contains a DAC for fan speed con-
trol. An automatic hardware temperature trip point is pro-
vided and the fan will be driven to full speed if it is
exceeded.
Finally, the chip has remote reset and power down
functionality, allowing it to be remotely shutdown via the
SMBus.
The ADM1028’s 3.0V to 5.5V supply voltage range, low
supply current, and SMBus make it ideal for a wide range
of applications. These include hardware monitoring
applications in PCs, electronic test equipment, and office
electronics.
FUNCTIONAL BLOCK DIAGRAM
MASK
GATING
INT M A SK
REGISTER
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
CONFIGURATION
REGISTER
INTERRUPT
STATUS
REGISTERS
ANALOG
OUTP UT RE G ISTE R
AND 8-BIT DAC
AUXRST
INT
ADM1028
ADDRESS
POINTER
REGISTER
ADC
2.5V
BANDGAP
REFERENCE
D-
D+
ANALOG
SIGNAL
CONDITIONING
SERIAL BUS
INTERFACE
SDA
SCL
VCC3AUX
GND
FAN_SPD/TEST_IN
FAN_OFF
VCC3AUX
10kV
VV
V
RST
GPI
THERMA/TEST_OUT
THERMB
ALERT
STATUS
REGISTER
POWER ON
RESET
REMOTE
FUNCTION
REGISTER
VCC3AUX
10kV
VV
V
R_RST
R_OFF
RESET
FAN_SPD SH UTO FF &
R_OFF RESE T
13
7
3
6
10
9
11
12
24
1
14
8
15
16
5
–2– REV. PrD
ADM1028–SPECIFICATIONS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted)
PRELIMINARY
TECHNICAL
DATA
PARAMETER Min Typ Max Units Test Conditions
POWER SUPPLY
Supply Voltage, V
CC
3.0 3.30 5.5 V
Supply Current, I
CC
1.4 2.0 mA Interface Inactive, ADC Active
32 <100 µA Standby Mode
TEMP.-TO-DIGITAL CONVERTER
Internal Sensor Accuracy ±3
o
C
±2 °C +60
O
C# T
A
# +100
o
C
Resolution 1
o
C
External Diode Sensor Accuracy ±5
o
C
±3
o
C +60
O
C# T
A
# +100
o
C
Resolution 1
o
C
Remote Sensor Source Current 60 90 130 µA High Level (D+ = D- +0.65V)
3.5 5.5 7.5 µA Low Level (D+ = D- +0.65V)
Total Monitoring Cycle Time, t
c
1.0 1.4 s
ANALOG OUTPUT
Output Voltage Range 0 2.5 V
Total Unadjusted Error, TUE ±3 % I
L
= 2mA
Full-Scale Error ±1 ±3 %
Zero Error ±2 LSB No Load
Differential Non-Linearity, DNL ±1 LSB Monotonic by Design
Integral Non-Linearity ±1 LSB
Output Source Current 2 mA
Output Sink Current 1 mA
VOLTAGE MONITOR THRESHOLDS
Reset Threshold, V
CC3AUX
2.85 2.925 3.00 V Measured with Vcc falling.
Hysteresis 50 mV
R_RST OUTPUT
Reset Output Voltage, V
OL
0.3 V I
SINK
= 1.2mA;
V
CC
= V
TH
(MAX)
Reset Output Pulse Width, t
R_RST#
125 4000 µs
V
CC
to Reset Delay, t
D
20 µs
THERMATHERMA
THERMATHERMA
THERMA OUTPUT
THERMA pull-up resistance 7 10 13 kΩ
–3–REV. PrD
ADM1028
PRELIMINARY
TECHNICAL
DATA
Preliminary Technical Data
Specifications (Continued)
PARAMETER Min Typ Max Units Test Conditions/Comments
DIGITAL OUTPUT THERMATHERMA
THERMATHERMA
THERMA/TEST_OUT,
R_OFF
Output High Voltage, V
OH
2.4 V I
OUT
= 3.0mA
Output Low Voltage, V
OL
0.4 V
OPEN-DRAIN DIGITAL OUTPUTS
(INT, THERMB, FAN_OFF, R_RST)
Output Low Voltage, V
OL
0.4 V I
OUT
= -3.0mA
High Level Output Leakage Current, I
OH
0.1 1 µA V
OUT
= V
CC
OPEN-DRAIN SERIAL DATA
BUS OUTPUT (SDA)
Output Low Voltage, V
OL
0.4 V I
OUT
= -3.0mA
High Level Output Leakage Current, I
OH
0.1 1 µA V
OUT
= V
CC
SERIAL BUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, V
IH
2.1 V (min)
Input Low Voltage, V
IL
0.8 V (max)
Input Leakage Current ±5 µA
Hysteresis 500 mV
DIGITAL INPUT LOGIC LEVELS
(FAN_SPD/TEST_IN, GPI)
Input High Voltage, V
IH
2.2 V
Input Low Voltage, V
IL
0.8 V
DIGITAL INPUT LEAKAGE CURRENT
(ALL DIGITAL INPUTS)
Input High Current, I
IH
-1 -0.005 µA V
IN
= V
CC
Input Low Current, I
IL
0.005 1 µA V
IN
= 0
Input Capacitance, C
IN
5pF
SERIAL BUS TIMING
Clock Frequency, f
SCLK
100 kHz See Figure 1
Bus Free Time, t
BUF
4.7 µs See Figure 1
Start Setup Time, t
SU;STA
4.0 µs See Figure 1
Start Hold Time, t
HD;STA
4.0 µs See Figure 1
Stop Condition Setup Time, t
SU;STO
4.0 µs See Figure 1
SCL Low Time, t
LOW
4.7 µs See Figure 1
SCL High Time, t
HIGH
4.0 µs See Figure 1
SCL, SDA Rise Time, t
r
1000 ns See Figure 1
SCL, SDA Fall Time, t
f
300 ns See Figure 1
Data Setup Time, t
SU;DAT
250 ns See Figure 1
Data Hold Time, t
HD;DAT
300 ns See Figure 1
NOTES
1
Typicals are at T
A
=25°C and represent most likely parametric norm. Standby current typ is measured with V
CC
= 3.3V.
3
Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.2 V for a rising edge.
ADM1028
–4– REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (V
CC
) 6.5 V
Voltage on Digital Inputs except Therm -0.3V to 6.5V
Voltage on Therm pin -0.3V to Vcc +0.3V
Voltage on Any other Input -0.3V to V
CC
+0.3V
or Output Pin
Input Current at any pin ±5mA
Package Input Current ±20mA
Maximum Junction Temperature (T
J
max) 150 °C
Storage Temperature Range –65°C to +150°C
Lead Temperature
Soldering 10 sec +300°C
IR Reflow Peak temperature +220°C
ESD Rating (Human Body Model) 4000 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only; functional. Operation of the device
at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
THERMAL CHARACTERISTICS
16-Pin QSOP Package:
θ
JA
= 105°C/Watt, θ
JC
= 39°C/Watt
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
ADM1028ARQ 0°C to +100°C 16-Pin QSOP RQ-16
Package
ADM1028 PINOUT
FAN_OFF
GPI
AUXRST INT
GND
1
2
3
4
16
15
14
13
ADM1028
TOP VIEW
(Not to Scale)
SCL
SDA
R_OFF
512
VCC3AUX THERMB
6
7
89
10
11
FAN_SPD/NTEST_IN
THERMA/NTEST_OUT
D+
D-
R_RST
RST
Figure 1. Diagram for Serial Bus Timing
P SSP
tBUF
tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO
tLOW tRtFtHD;STA
SCL
SDA
ADM1028
–5–REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
PIN FUNCTION DESCRIPTION
PIN NO. MNEMONIC DESCRIPTION
1 FAN_OFF Digital Output (Open Drain) Fan Off Request. When asser ted low this indicates a
request to shut the fan off independent of the FAN_SPD output. When negated
(output FET off) it indicates that the fan may be turned on.
2 GPI Digital Input (12V tolerant). This pin is a general purpose logic input with 12V
tolerance. It can be programmed as an active high or active low input that sets bit 4
of the Interr upt Status Register. A voltage >2.2V on this pin, represents a log ic “1”
while a floating condition is interpreted as logic “0”.
3AUXRST Digital Input. This pin can be driven low as an input to reset the ADM1028.
4GND GROUND. Power and signal ground.
5V
CC3AUX POWER +3.3Vaux. Power source and voltage monitor input for power on reset.
6RST Digital Input. This pin can be pulled low externally to indicate to the ADM1028
that the main system power has been removed. The ADM1028 will shut off the
FAN_SPD output and reset its R_OFF output.
7R_RST Digital Output (Open drain). This pin is a remote reset output which pulses low
on receipt of a specific SMBus message.
8 FAN_SPD/TEST_IN Analog Output/Test Input. An active-high input that enables NAND board-
level connectivity testing. Refer to section on NAND testing.
Used as an analog output for fan speed control when NAND test is not selected.
9 D - Remote Ther mal Diode Negative Input. This is the negative input (current sink)
from the remote ther mal diode. This also ser ves as the negative input into the A/D.
10 D + Remote Ther mal Diode Positive Input. This is the positive input (current source)
from the remote ther mal diode. This ser ves as the positive input into the A/D.
11 THERMA/TEST_OUT Digital Output (Open Drain with integrated VCC3AUX pull-up). An active low thermal
overload output that indicates a violation of a temperature set point (over
-temperature). The f an is on full-speed whenever this pin is asserted low. Acts as the
output of the NAND Tree when the ADM1028 is in NAND Tree Test Mode.
12 THERMB Digital Output (Open Drain). This pin is a second THERM signal. It can be used
to drive external circuitry with a different external pull-up supply rail.
13 R_OFF Digital Output or Open Drain with integ rated VCC3AUX pull-up. Remote off (power
down) output. This pin is dr iven high on receipt of a specific SMBus message. The
pin (and its associated register bit) remain high until the RST input is asserted low.
14 INT Digital Output (Open Drain), System Interrupt Output. This signal indicates a
violation of a set trip point. The output is enabled when Bit 1 of the Configuration
Register is set to 1. The default state is disabled.
15 SCL Digital Input SMBus Clock
16 SDA Digital I/O(Open Drain) SMBus bi-directional Data
ADM1028
–6– REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
Figure 2. Temperature Error vs. PC Board Track Resistance
Figure 3. Temperature Error vs. Power Supply Noise
Frequency
Figure 4. Temperature Error vs. Common-Mode Noise
Frequency
Figure 5. Pentium III Temperature Measurement vs.
ADM1028 Reading
Figure 6. Temperature Error vs. Capacitance Between D+
and D-
Figure 7. Standby Current vs. Clock Frequency
AWAITING
DATA
AWAITING
DATA
AWAITING
DATA
AWAITING
DATA
ADM1028
–7–REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
Figure 8. Temperature Error vs. Differential-Mode Noise
Frequency
Figure 9. Standby Supply Current vs. Supply Voltage
Figure 10. Power-up Reset vs. Temperature
AWAITING
DATA
AWAITING
DATA
AWAITING
DATA
ADM1028
–8– REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
FUNCTIONAL DESCRIPTION
GENERAL DESCRIPTION
The ADM1028 is a low-cost temperature monitor and
fan controller for microprocessor-based systems. The
temperature of a remote sensor diode may be measured,
allowing monitoring of processor temperature in a single-
processor system. An on-chip temperature sensor allows
monitoring of system ambient temperature.
Measured values can be read out via the serial System
Management Bus, and values for limit comparisons can be
programmed in over the same serial bus.
The ADM1028 also contains a DAC for fan speed con-
trol. An automatic hardware temperature trip point is
provided for fault tolerant fan control and the fan will be
driven to full speed if this is exceeded. Two interrupt
outputs are provided, which will be asserted if the software
or hardware limits are exceeded.
Finally, the chip has remote reset and shutdown
capabilities.
INTERNAL REGISTERS OF THE ADM1028
A brief description of the ADM1028's principal internal
registers is given below. More detailed information on the
function of each register is given in Tables 4 to 10.
Configuration Register: Provides control and configuration.
Address Pointer Register: This register contains the address
that selects one of the other internal registers. When writing to
the ADM1028, the first byte of data is always a register ad-
dress, which is written to the Address Pointer Register.
Interrupt (INT) Status Register: This register provides
status of each Interrupt event.
Interrupt (INT) Mask Register: Allows masking of indi-
vidual interrupt sources.
Value and Limit Registers: The results of temperature
measurements are stored in these registers, along with
their limit values.
Analog Output Register: The code controlling the analog
output DAC is stored in this register.
Alert Status Register: Indicates the status of the THERM
signal and GPI pin.
Remote Function Register: This register allows control of
the R_RST and R_OFF outputs.
SERIAL BUS INTERFACE
Control of the ADM1028 is carried out via the serial bus.
The ADM1028 is connected to this bus as a slave device,
under the control of a master device, e.g. the 810 chipset.
The ADM1028 has a 7-bit serial bus address. When the
device is powered up, it will do so with a default serial bus
address. The SMBus address for the ADM1028 is
0101110 binary.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line
SCL remains high. This indicates that an address/data
stream will follow. All slave peripherals connected to
the serial bus respond to the START condition, and
shift in the next 8 bits, consisting of a 7-bit address
(MSB first) plus a R/W bit, which determines the direc-
tion of the data transfer, i.e. whether data will be writ-
ten to or read from the slave device.
The peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit. All other devices on the
bus now remain idle whilst the selected device waits for
data to be read from or written to it. If the R/W bit is a
0 then the master will write to the slave device. If the
R/W bit is a 1 the master will read from the slave de-
vice.
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit
from the slave device.Transitions on the data line must
occur during the low period of the clock signal and
remain stable during the high period, as a low to high
transition when the clock is high may be interpreted as
a STOP signal. The number of data bytes that can be
transmitted over the serial bus in a single READ or
WRITE operation is limited only by what the master
and slave devices can handle.
3. When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the master
will pull the data line high during the 10th clock pulse
to assert a STOP condition. In READ mode, the mas-
ter device will override the acknowledge bit by pulling
the data line high during the low period before the 9th
clock pulse. This is known as No Acknowledge. The
master will then take the data line low during the low
period before the 10th clock pulse, then high during the
10th clock pulse to assert a STOP condition.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix
read and write in one operation, because the type of opera-
tion is determined at the beginning and cannot subse-
quently be changed without starting a new operation.
In the case of the ADM1028, write operations contain
either one or two bytes, and read operations contain one
byte, and perform the following functions:
To write data to one of the device data registers or read
data from it, the Address Pointer Register must be set so
that the correct data register is addressed, then data can be
written into that register or read from it. The first byte of
a write operation always contains an address that is stored
in the Address Pointer Register. If data is to be written to
the device, then the write operation contains a second data
byte that is written to the register selected by the address
pointer register.
This is illustrated in figure 11a. The device address is sent
over the bus followed by R/W set to 0. This is followed by
two data bytes.The first data byte is the address of the
internal data register to be written to, which is stored in
the Address Pointer Register. The second data byte is the
data to be written to the internal data register.
When reading data from a register there is only one
possibility:
ADM1028
–9–REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
1. The serial bus address is written to the device along
with the address pointer register value. The ADM1028
should then acknowledge the write by pulling SDA low
during the 9th clock pulse. The master does not
generate a STOP condition but issues a new START
condition. The serial bus address is again sent but with
the R/W bit high indicating a READ operation. The
ADM1028 will then return the data from the selected
register, and a No Acknowledge is generated to signify
the end of the read operation. The master will then
initiate a STOP condition to end the transaction and
release the SMBus.
In figures 11a & 11b, the serial bus address is shown as
the default value 01011(A1)(A0), where A1 and A0 are
the lowest two bits of the device SMBus address.
TEMPERATURE MEASUREMENT SYSTEM
INTERNAL TEMPERATURE MEASUREMENT
The ADM1028 contains an on-chip bandgap temperature
sensor. The on-chip ADC performs conversions on the
output of this sensor and outputs the temperature data in
8-bit two's complement format. The format of the tem-
perature data is shown in Table 2.
EXTERNAL TEMPERATURE MEASUREMENT
The ADM1028 can measure the temperature of an exter-
nal diode sensor or diode-connected transistor, connected
to pins 9 and 10.
Pins 9 and 10 are a dedicated temperature input channel.
The default functions of pins Pins 11 and 12 are as
THERM outputs to indicate overtemperature conditions.
The forward voltage of a diode or diode-connected tran-
sistor, operated at a constant current, exhibits a negative
temperature coefficient of about -2mV/
o
C.Unfortunately,
the absolute value of V
be
, varies from device to device, and
individual calibration is required to null this out, so the
technique is unsuitable for mass-production.
The technique used in the ADM1028 is to measure the
change in V
be
when the device is operated at two different
currents.
This is given by:
R/W
0
SCL
SDA 1 0 1 1 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADM1028
ST ART BY
MASTER
FRAM E 1
SERIAL BUS ADDRESS BYTE FRAME 2
ADDRESS POINTER RE GISTER BY TE
191
ACK. BY
ADM1028
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADM1028 STOP BY
MASTER
FRAM E 3
DATA BY TE
19
SCL (CONTINUED)
SDA (CONTINUED)
Figure 11a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
R/W
0
SCL
SDA 1 0 1 1 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADM1028
ST ART BY
MASTER
FR AME 1
SERIAL BUS ADDRESS BYTE FR AME 2
ADDR ESS P OINT ER REGISTER BYTE
191
ACK. BY
ADM1028
9
R/W
0
SCL
SDA
1 0 1 1 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
NO ACK.
BY M ASTER ST OP BY
MASTER
ST ART BY
MASTER
FRAME 3
SERIAL BUS ADDRESS BYT E FRAM E 4
DA TA B Y TE F RO M AD M 1028
191
ACK. BY
ADM1028
9
Figure 11b. Reading Data from the ADM1028
ADM1028
–10– REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
∆V
be
= KT/q x ln(N)
where:
K is Boltzmann’s constant
q is charge on the carrier
T is absolute temperature in Kelvins
N is ratio of the two currents
Figure 12 shows the input signal conditioning used to
measure the output of an external temperature sensor.
This figure shows the external sensor as a substrate tran-
sistor, provided for temperature monitoring on some mi-
croprocessors, but it could equally well be a discrete
transistor.
If a discrete transistor is used, the collector will not be
grounded, and should be linked to the base. If a PNP
transistor is used the base is connected to the D- input
and the emitter to the D+ input. If an NPN transistor is
used, the emitter is connected to the D- input and the
base to the D+ input.
TABLE 2. TEMPERATURE DATA FORMAT
Temperature Digital Output
-128 °C 1000 0000
-125 °C 1000 0011
-100 °C 1001 1100
-75 °C 1011 0101
-50 °C 1100 1110
-25 °C 1110 0111
-1 °C 1111 1111
0 °C 0000 0000
+1 °C 0000 0001
+10 °C 0000 1010
+25 °C 0001 1001
+50 °C 0011 0010
+75 °C 0100 1011
+100 °C 0110 0100
+125 °C 0111 1101
+127 °C 0111 1111
To prevent ground noise interfering with the measure-
ment, the more negative terminal of the sensor is not ref-
erenced to ground, but is biased above ground by an
internal diode at the D- input. If the sensor is used in a
very noisy environment, a capacitor of value up to 1000pF
may be placed between the D+ and D- inputs to filter the
noise.
To measure ∆V
be
, the sensor is switched between operat-
ing currents of I and N x I. The resulting waveform is
passed through a 65kHz lowpass filter to remove noise,
thence to a chopper-stabilized amplifier that performs the
functions of amplification and rectification of the wave-
form to produce a DC voltage proportional to ∆V
be
. This
voltage is measured by the ADC to give a temperature
output in 8-bit two’s complement format. To further re-
duce the effects of noise, digital filtering is performed by
averaging the results of 16 measurement cycles. An exter-
nal temperature measurement takes nominally 9.6ms.
LAYOUT CONSIDERATIONS
Digital boards can be electrically noisy environments, and
care must be taken to protect the analog inputs from
noise, particularly when measuring the very small voltages
from a remote diode sensor. The following precautions
should be taken:
1. Place the ADM1028 as close as possible to the remote
sensing diode. Provided that the worst noise sources
such as clock generators, data/address buses and CRTs
are avoided, this distance can be 4 to 8 inches.
2. Route the D+ and D- tracks close together, in parallel,
with grounded guard tracks on each side. Provide a
ground plane under the tracks if possible.
3. Use wide tracks to minimize inductance and reduce
noise pickup. 10 mil track minimum width and spacing
is recommended.
D+
D-
REMOTE
SENSING
TRANSISTOR
LOWPASS FILTER
fc = 65kHz
VDD
TO ADC
VOUT+
VOUT-
IN x I IBIAS
BIAS
DIODE
Figure 12. ADM1028 Signal Conditioning
ADM1028
–11–REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
GND
D+
D-
GND
10 mil
10 mil
.
10 mil
10 mil
.
10 mil
10 mil
.
10 mil
Figure 13. Arrangement of Signal Tracks
4. Try to minimize the number of copper/solder joints,
which can cause thermocouple effects. Where copper/
solder joints are used, make sure that they are in both
the D+ and D- path and at the same temperature.
Thermocouple effects should not be a major problem as
1
o
C corresponds to about 200µV, and thermocouple
voltages are about 3µV/
o
C of temperature difference.
Unless there are two thermocouples with a big tem-
perature differential between them, thermocouple volt-
ages should be much less than 200µV.
5. Place 0.1µF bypass and 2200pF input filter capacitors
close to the ADM1028.
6. If the distance to the remote sensor is more than 8
inches, the use of twisted pair cable is recommended.
This will work up to about 6 to 12 feet.
7. For really long distances (up to 100 feet) use shielded
twisted pair such as Belden #8451 microphone cable.
Connect the twisted pair to D+ and D- and the shield
to GND close to the ADM1028. Leave the remote end
of the shield unconnected to avoid ground loops.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect
the measurement. When using long cables, the filter ca-
pacitor C1 may be reduced or removed. In any case the
total shunt capacitance should not exceed 1000pF.
Cable resistance can also introduce errors. 1Ω series resis-
tance introduces about 0.5
o
C error.
ANALOG OUTPUT
The ADM1028 has a single analog output (FAN_SPD)
from an unsigned 8 bit DAC which produces 0 - 2.5V.
The analog output register defaults to 00 during power-on
reset, which produces minimum fan speed. The analog
output may be amplified and buffered with external cir-
cuitry such as an op-amp and transistor to provide fan
speed control.
Suitable fan drive circuits are given in Figures 14a to 14e.
When using any of these circuits, the following points
should be noted:
1. All of these circuits will provide an output range from
zero to almost +V
FAN
.
2. To amplify the 2.5V range of the analog output up to
+V
FAN
, the gain of these circuits needs to be set as
shown.
3. Care must be taken when choosing the op-amp to en-
sure that its input common-mode range and output
voltage swing are suitable.
4. The op-amp may be powered from the +V rail alone.
If it is powered from +V then the input common-mode
range should include ground to accommodate the
minimum output voltage of the DAC, and the output
voltage should swing below 0.6V to ensure that the
transistor can be turned fully off.
5. In all these circuits, the output transistor must have an
I
CMAX
greater than the maximum fan current, and be
capable of dissipating power due to the voltage
dropped across it when the fan is not operating at full-
speed.
6. If the fan motor produces a large back e.m.f when
switched off, it may be necessary to add clamp diodes
to protect the output transistors in the event that the
output goes from full-scale to zero very quickly.
Figure 14c shows how the FAN_OFF signal may be used
(with any of the control circuits) to gate the fan on and off
independent of the value on the FAN_SPD/TEST_IN
pin.
FAULT TOLERANT FAN CONTROL
The ADM1028 incorporates a fault tolerant fan control
capability that is tied to operation of the THERMA,
THERMB outputs. It can override the setting of the ana-
log output and force it to maximum to give full fan speed
in the event of a critical overtemperature problem, even if,
for some reason, this has not been handled by the system
software.
There are two temperature set point registers that will
activate the fault tolerant fan control. One of these limits
is programmable by the user and one is a hardware (read-
only) register that will operate if the user does not pro-
gram any limit. The fault tolerant fan control is activated
if a limit is exceeded for three or more consecutive read-
ings. These limits are separate from the normal high and
low temperature limits for the INT output, which do not
affect the fault tolerant fan control or THERM outputs.
A hardware limit of 100
o
C is programmed in to the
register at address 18h, for the remote diode Default
THERM limit. This is the default limit and the analog
output will be forced to full-scale if the remote sensor
reads more than 100
o
C. This makes the fault tolerant fan
control failsafe in that it will operate at this temperature
even if the user has programmed no other limit, or in the
event of a software malfunction. Similarly, the Default
Internal Temp THERM limit held in register 17h, forces
the analog output full-scale if the ambient temperature
measured is more than 70
o
C.
The user may override the default limits by programming
a new limit into register 14h for the remote sensor and a
new limit into register 13h for the internal sensor. The
default value in register 14h is the same as for the read-
only register (100
o
C), but it may be programmed with
higher or lower values.
Once registers 13h and 14h have been programmed, or if
the defaults are acceptable, bit 3 of the configuration
ADM1028
–12– REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
FAN_SPD
+12V
R3
100kV
VV
V
R4
100kV
VV
V
R2
3.9kV
VV
V
R1
1kV
VV
V
Q3
NDT452P
Q1/Q2
MBT3904
DUAL
R5
5kV
VV
V
Figure 14d. Discrete 12V Fan Drive Circuit with P-Channel
MOSFET, SIngle Supply
FAN_SPD
+12V
R5
100kV
VV
V
R4
100kV
VV
V
R2
3.9kV
VV
V
R1
1kV
VV
V
R3
100V
VV
V
Q3
BC556
2N3906
Q4
BD132
TIP32A
Q1/Q2
MBT3904
DUAL
R6
5kV
VV
V
Figure 14e. Discrete 12V Fan Drive Circuit with Bipolar
Output Single Supply
Figure 14a. 5V Fan Circuit with Op-Amp
+12V
+
-
FAN_SPD
R2
39kV
VV
V
R1
10kV
VV
V
R3
1kV
VV
V
R4
1kV
VV
V
Q1
BD136
2SA968
AD8519
Figure 14b. 12V Fan Circuit with Op-Amp and PNP Transistor
+12V
+
-
FAN_SPD
R2
39kV
VV
V
R3
100kV
VV
V
R1
10kV
VV
V
Q1
NDT452P
AD8519
FAN_OFF
+3.3V
R4
1kV
VV
V
Q2
MMFT3055V
Figure 14c. 12V Fan Circuit with Op-Amp and P-Channel
MOSFET
+5V
+
-
FAN_SPD
R2
15kV
VV
V
R1
10kV
VV
V
Q1
NDT452P
AD8541
5V
FAN
ADM1028
–13–REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
register must be set to ‘1’. This bit is a write-once bit that
can only be written to ‘1’ and it has two effects:
1. it makes the values in registers 13h and 14h the active
limits, and disables read-only registers 17h and 18h.
2. it locks the data into registers 13h and 14h, so that it
cannot be changed until the lock bit is reset, either
when AUXRST or RST is asserted, or a Power On
Reset occurs.
Once the hardware override of the analog output is trig-
gered, it will only return to normal operation after three
consecutive measurements that are 5 degrees lower than
the set limit.
Whenever FAN_SPD output is forced to full-scale, the
FAN_OFF output is negated.
THE ADM1028 INTERRUPT SYSTEM
The ADM1028 has three interrupt outputs, INT,
THERMA and THERMB. These have different functions.
INT responds to violations of software programmed
temperature limits and its interrupt sources are maskable,
as described in more detail later. Interrupts and status bits
are only set if a limit is exceeded for at least 3 consecutive
conversions.
Operation of the INT output is illustrated in Figure 15.
Assuming that the temperature starts off within the pro-
grammed limits and that temperature interrupt sources are
not masked, INT will go low if the temperature measured
by the external sensor goes outside the programmed high
or low temperature limit for the sensor. INT also goes low
whenever THERM is low.
100oC
90oC
80oC
70oC
60oC
50oC
40oC
INT
Temp.
*INT cle ared by
software
**
HIG H LI MI T
LOW LIMI T
THIGH interrupt
logic re-armed
here
Figure 15. Operation of
INT
Output
Once the interrupt has been cleared, it will not be re-
asserted even if the temperature remains outside the limit
previously exceeded. However, INT will be re-armed if
the temperature falls back within the set limits for 3
consecutive conversions. Once the INT function has been
re-armed, it will then be re-asserted once a limit is
exceeded for 3 consecutive conversions.
INTERRUPT MASKING
Any of the bits in the Interrupt Status Register can be
masked out by setting the corresponding mask bit in the
Interrupt Mask Register. That interrupt source will then
no longer generate an interrupt. However, the bits in the
status register will be set as normal.
INTERRUPT CLEARING
The Interrupt Status Register reflects out-of-limit
conditions. The Status bits may be individually cleared by
writing a “1” to the appropriate status bits. Writing a “1”
to bits 1 & 2 cause software interrupts to be generated. Bit
4 (GPI) of the Interrupt Status Register reflects the
current status of the GPI pin, and so cannot be cleared by
writing to this bit.
The INT output is cleared with the INT_Enable bit,
which is Bit 1 of the Configuration Register, without
affecting the contents of the Interrupt (INT) Status
Registers.
THERM OUTPUTS
The THERMA, THERMB signals are functionally
identical. These system overtemperature outputs will
assert together when an overtemperature is detected.
THERMA (pin 11) is an open drain digital output which
has an integrated pullup resistor to V
CC3AUX
. THERMB is
an open drain digital output, intended to drive external
circuitry operating at a different supply voltage level.
THERM OPERATING MODE
THERM only responds to the “hardware” temperature
limits at addresses 14h and 18h, not to the software pro-
grammed limits. The function of these registers was
described earlier with regard to fault tolerant fan speed
control.
THERM
HARDWARE
TRIP P OINT
TEMP
5o
PROGRAMMED
VALUE FFh
ANALOG
OUTPUT
PREVIOUS FAN
SPEED VALUE
Figure 16. Operation of
THERM
Outputs
THERM will go low if the hardware temperature limit is
exceeded for three consecutive measurements. It will re-
main low until the temperature falls 5 degrees below the
limit for three consecutive measurements. While THERM
is low, the analog output will go to FFh to boost a con-
trolled fan to full speed and FAN_OFF will be negated.
When the Fault Tolerant Fan Control state is exited, the
analog FAN_SPD output returns to its previously pro-
grammed value, which may have been changed during the
time that the FAN_SPD output was forced to FFh.
ADM1028
–14– REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
INTERRUPT STRUCTURE
The Interrupt Structure of the ADM1028 is shown in
more detail in Figure 17. As each measurement value is
obtained and stored in the appropriate value register, the
value and the limits from the corresponding limit registers
are fed to the high and low limit comparators. The result
of each comparison (1 = out of limit, 0 = in limit) is
routed to the corresponding bit input of the Interrupt Sta-
tus Register via a data demultiplexer, and used to set that
bit high or low as appropriate.
The Interrupt Mask Register has bits corresponding to
each of the Interrupt Status Register Bits. Setting an Inter-
rupt Mask Bit high forces the corresponding Status Bit
output low, whilst setting an Interrupt Mask Bit low al-
lows the corresponding Status Bit to be asserted. After
masking, the status bits are all OR'd together to produce
the INT output, which will pull low if any unmasked sta-
tus bit goes high, i.e. when any measured value goes out
of limit.
The INT output is enabled when Bit 1 of the Configuration
Register (INT_Enable) is high.
GENERAL PURPOSE LOGIC INPUT (GPI)
Pin 2 is used as a general purpose logic input with 12V
tolerance. The GPI input may be programmed to be
active high or active low by clearing or setting bit 6 of the
Configuration Register. The default value is active high.
Bit 4 of the Interrupt Status register follows the state (or
inverted state) of GPI and will generate an interrupt when
it is set to 1, like any other input to the Interrupt Status
Register. However, the GPI bit is not latched in the Status
Register and always reflects the current state (or inverted
state) of the GPI input. If it is 1 it will not be cleared by
reading the Status Register.
POWER-ON RESET
When the ADM1028 is powered up, it will initiate a
power-on reset sequence when the supply voltage V
CC3AUX
rises above the power-on reset threshold, with registers
being reset to their power-on values. Normal operation
will begin when the supply voltage rises above the reset
threshold. Registers whose power on values are not shown
have power on conditions that are indeterminate (this
includes the Value and Limit Registers). In most applica-
tions, usually the first action after power on would be to
write limits into the Limit Registers.
Power on reset clears or initializes the following registers
(the initialized values are shown in Table 4):
- Configuration Register
- Interrupt Status Register
- Interrupt Mask Register
- Analog Output Register
- Programmable Trip Point Registers
The ADM1028 can also be reset by taking AUXRST low
as an input. The above-mentioned registers will be reset
to their default values and the ADC will remain inactive
as long as AUXRST is below the reset threshold.
Taking the RST pin low will cause the following registers
to be reset.
- Bit 3 of the Configuration Register (Programmable
THERM Limit Lock Bit)
- DAC Output, Fan speed
Figure 17. ADM1028 Interrupt Register Structure
IN TERR UPT
STATUS
REGISTER
0
1
2
3
4
5
6
7
INT ENABLE
INT
CONFIGURATION
REGISTER
DAT A
DEM UL TI PL EX ER
HI GH AND
LO W LI MI T
CO MPA RATO RS
INT. TEMP
FLAG1
FLAG2
INT. THER M
GPI
EXT. TEM P
EXT. THER M
DIODE FAULT
HIGH
LIMIT
LOW
LIMIT
VALUE
FROM VALU E
AND LIMIT
REGISTERS
1 = OUT
OF LIMIT
MASK IN G DATA
FROM BUS
STATUS
BIT
MASK
BIT
MASK GATING X 8
INTERRUPT
MASK
REGISTER
8 MASK B ITS
(SAME BIT ORD ER AS
STATUS REGISTER)
ADM1028
–15–REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
INITIALIZATION (SOFT RESET)
Soft reset performs a similar, but not identical, function to
power on reset. The Limit Registers remain unchanged.
Soft reset is accomplished by setting Bit 4 of the Configu-
ration Register high. This Bit automatically clears after
being set.
Unlike clearing INT, where the temperature must fall
back within the set limits for three conversions before the
INT function is rearmed, the soft reset allows INT to be
pulled low immediatey after the soft reset.
NAND TREE TEST
A NAND tree is provided in the ADM1028 for Automated
Test Equipment (ATE) board level connectivity testing.
The device is placed into NAND tree test mode by
powering up with pin FAN_SPD/TEST_IN (pin 8) held
high. This pin is sampled and its state at power-up is
latched. If it is connected high, then the NAND tree test
mode is invoked. NAND tree test mode will only be ex-
ited once the ADM1028 is powered down.
In NAND tree test mode, all digital inputs may be tested
as illustrated in Table 3. THERMA/TEST_OUT will
become the NAND tree output pin.
The structure of the NAND Tree is shown in Figure 21.
To perform a NAND Tree test, all pins are initially
driven low. The test vectors set all inputs low, then one-
by-one toggles them high (keeping them high). Exercising
the test circuit with this “walking one” pattern, starting
with the input closest to the output of the tree, cycling
towards the farthest, causes the output of the tree to toggle
with each input change. Allow for a typical propagation
delay of 500ns.
Figure 21. NAND Tree
AUXRST
GPI
SDA
SCL
RST
LATCH Q
DClk
POWER-ON
RESET
ENABLE
FAN_SPD/
TEST_IN
THERMA/
TEST_OUT
TABLE 3. TEST VECTORS
RST AUXRST GPI SDA SCL THERMA
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 1 1
0 0 1 1 1 0
0 1 1 1 1 1
1 1 1 1 1 0
CONFIGURING THE INTERRUPT
On power-up, the Interrupt functionality of the device is
disabled. The Configuration register (0x40) must be writ-
ten to, in order to enable the Interrupt output. The
INT_Enable bit (bit 1) of the Register should be set to 1.
ADM1028
–16– REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
TABLE4. ADM1028 REGISTERS
Register Name Address A7 - A0 in hex Comments
Value Registers 0x14 – 0x38 See Table 5
Company ID 0x3E This location will contain the company identification
number. This register is read only.
Revision 0x3F This location will contain the revision number of the
part in the lower four bits of the register [3:0]. The
upper four bits reflect the ADM1028 Version Number
[7:4]. The first version is 1101. The next version of
ADM1028 would be 1110, etc. For instance, if the
stepping were A0 and this part is a ADM1028, then
this register would read 1101 0000. This register is
read only.
Configuration Register 0x40 See Table 6. Power on value = 0010 0001
Interrupt Status Register 0x41 See Table 7. Power on value = 0000 0000
Interrupt Mask Register 0x43 See Table 8. Power on value = 0000 0000
Manufacturer Test 0x44 - 0x4A Test Registers for manufacturer’s use only. Do not
write to these registers.
Remote function 0x4B See Table 9. Power on value = 0000 0000
Alert Status 0x4C See Table 10. Power on value = 0000 0000
TABLE 5. REGISTERS 0X13- 0X3A VALUE REGISTERS
Address Read/Write Description
0x13 Read/Write Programmable Internal Therm Automatic Trip Point - default 127 degrees C.
This register can only be written to if the write once bit in the configuration register
(0x40, bit 3) has not been set.
0x14 Read/Write Programmable Remote Thermal Diode Automatic Trip Point - default 100 degrees C.
This register can only be written to if the write once bit in the configuration register
(0x40, bit 3) has not been set.
0x15 Read/Write Test register for manufacturer’s use only. Do not write to this register
0x17 Read Only Default Internal Therm Automatic Trip Point - default 70 degrees C
Cannot be changed. Disabled when bit 3 of Config register is set
0x18 Read Only Default Remote Thermal Diode Automatic Trip Point - default 100 degrees C
Cannot be changed. Disabled when bit 3 of Config register is set
0x19 Read/Write Analog Output, FAN_SPD (defaults to 0x00h)
0x26 Read Only External Remote Temperature Value
0x27 Read Only Internal Temperature Value
0x37 Read/Write External Remote Temperature High Limit
0x38 Read/Write External Remote Temperature Low Limit
0x39 Read/Write Internal Temperature High Limit - default 127 degrees C.
0x3A Read/Write Internal Temperature Low Limit
ADM1028
–17–REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
TABLE 6. REGISTER 0X40 CONFIGURATION REGISTER POWER ON DEFAULT <7:0> = 21H
BIT Name R/W Description
0 START Read/Write Setting this bit to a “1” enables startup of ADM1028; clearing this bit
to “0” places ADM1028 in standby mode.
At startup temperature monitoring and limit checking functions begin.
Note, all limit values should be programmed into ADM1028 prior to
using the standard thermal interrupt mechanism based upon high and
low limits. (Powerup default=1)
1INT Enable Read/Write Setting this bit to a “1” enables the INT output.
1=Enabled 0=Disabled (Powerup Default = 0)
2 Reserved Read Only Reserved (default = 0)
3 Programmable Read/Write Once Setting this bit to a “1” will lock in the value set into the Programmable
Therm Remote Therm Limit Register (Value Register 0x14). Furthermore,
Limit Lock bit is set, the values in the Default Remote Therm Limit Register
Bit (Value Register 0x18) will no longer have an effect on the THERM,
FAN_SPD, or FAN-OFF outputs. This bit cannot be written again
until after RST has been asserted. (Power-up default = 0)
4 Soft Reset Read/Write Setting this bit to a “1”will restore powerup default values to the
Configuration Register, Interrupt Status Register and Interrupt Mask
Register. This also rearms INT structure but not the THERM
structure. This bit automatically clears itself since the power on default
is zero.
5FAN OFF Read/Write Setting this bit to a “1” will cause the FAN OFF pin to be floated.
Clearing this bit to “0” will cause the FAN OFF pin to be driven low
which requests that the fan be turned off. This bit will be
unconditionally set if the THERM pin is ever asserted; once THERM
is negated this bit must be returned to its prior state (prior to THERM
assertion). Reading this bit reflects the state of the FAN-OFF output
buffer. Due to the open-drain nature of this pin the value read does not
represent the actual state of the external circuit connected to it.
(Power up default =1)
6 GPI Invert Read/Write Setting this bit to a “1” will invert the GPI input for the purpose of
level detection and interrupt generation. Clearing this bit to “0” leaves
the GPI input unmodified. (Powerup default=0)
7 Reserved Read Only Reserved. (Powerup default = 0).
ADM1028
–18– REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
TABLE 7. REGISTER 0X41. INTERRUPT STATUS REGISTER. POWER ON DEFAULT <7:0> = 00H
BIT NAME READ/WRITE DESCRIPTION
0 Int. Temp Error Read/Write A one indicates that one of the limits for the internal
‘1’ to clear temperature sensor has been exceeded.
1 Flag 1 Read/Write This bit can be used as a general purpose flag with the capability of
generating an interrupt. Writing a ‘1’ to this bit causes it to be set to
‘1’. Writing a ‘0’ clears this bit.
2 Flag 2 Read/Write This bit can be used as a general purpose flag with the capability of
generating an interrupt. Writing a ‘1’ to this bit causes it to be set to
‘1’. Writing a ‘0’ clears this bit.
3 Int. THERM Read/Write A one indicates that the internal thermal overload (THERM) limit
‘1’ to clear has been exceeded.
4 GPI Input Read Only A “1” indicates that the GPI pin is asserted. The polarity of the GPI
pin is determined by GPI Invert (bit 6) in the Configuration
Register. For example, if GPI Invert is cleared then this bit will be
“1” when the GPI pin is high (“1”); this bit will be “0” when the
GPI pin is low (“0”). If GPI Invert is set then this bit will be “1”
when the GPI pin is low (“0”); this bit will be “0” when the GPI pin
is high (“1”). Note that the state of GPI is not latched; this bit
simply reflects the state or inverted state of the GPI pin. Note: if this
bit is “1” reading this register will NOT clear it to “0.”
5 Ext. Temp Error Read/Write A one indicates that one of the limits for the external
‘1’ to clear temperature sensor has been exceeded.
6 Ext. THERM Read/Write A one indicates that the external thermal overload (THERM) limit
‘1’ to clear has been exceeded.
7 Ext Diode Fault Read/Write A one indicates either a short- or open-circuit fault on the remote
‘1’ to clear sensor diode.
TABLE 8. REGISTER 0X43 INTERRUPT MASK REGISTER. POWER ON DEFAULT <7:0> = 00H
BIT Name Read/Write Description
0 Int Temp Error Read/Write A one disables the corresponding interrupt status bit for the INT
output.
1 Flag 1 Mask Read/Write A one disables the corresponding interrupt status bit for the INT
output.
2 Flag 2 Mask Read/Write A one disables the corresponding interrupt status bit for the INT
output.
3 Int THERM Read/Write A one disables the corresponding interrupt status bit for the INT
output.
4 GPI Mask Read/Write A one disables the corresponding interrupt status bit for the INT
output.
5 Ext Temp Error Read/Write A one disables the corresponding interrupt status bit for the INT
output.
6 Ext THERM Read/Write A one disables the corresponding interrupt status bit for the INT
output.
7 Ext Diode Fault Read/Write A one disables the corresponding interrupt status bit for the INT
output.
ADM1028
–19–REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
TABLE 9. REGISTER 0X4B REMOTE FUNCTION REGISTER. POWER ON DEFAULT <7:0> = 00 H
BIT Name Read/Write Description
0 R_RST Read/Write Writing a “1” to this bit causes the R_RST output to be pulsed low for
a minimum of 125µs. This bit will self-clear to 0 when the R_RST
pulse is complete. Writing a “0” to this bit has no effect. Reading this
bit reflects the state of this register bit and not the state of the pin. The
power-on default value is “0”.
1 R_OFF Read/Write Writing a “1” to this bit causes the R_OFF output to be driven high.
This bit will be cleared, and the output driven low, when RST is
asserted. Writing a “0” to this bit has no effect. The power-on default
value is “0”.
2 Reserved Read/Write Reserved (default = 0)
3 Reserved Read/Write Reserved (default = 0)
4 Reserved Read/Write Reserved (default = 0)
5 Reserved Read/Write Reserved (default = 0)
6 Reserved Read/Write Reserved (default = 0)
7 Reserved Read/Write Reserved (default = 0)
TABLE 10. REGISTER 0X4C ALERT STATUS REGISTER. POWER ON DEFAULT <7:0> = 00 H
BIT Name Read/Write Description
0 THERM Alert Read Only A one indicates that thee xternal thermal overload limit is currently
exceeded.
1 GPI Alert Read Only This bit represents the logic level of the GPI pin if bit 6 of the
Configuration Register is “0”, or the inverse logic level of the GPI pin
if bit 6 of the Configuration Register is “1”.
2 Reserved Read Only Undefined
3 Reserved Read Only Undefined
4 Reserved Read Only Undefined
5 Reserved Read Only Undefined
6 Reserved Read Only Undefined
7 Reserved Read Only Undefined
ADM1028
–20– REV. PrD
Preliminary Technical Data
PRELIMINARY
TECHNICAL
DATA
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin QSOP Package (RQ-16)
16 9
8
1
0.197 (5.00)
0.189 (4.80)
0.244 (6.20)
0.228 (5.79)
PIN 1
0.157 (3.99)
0.150 (3.81)
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025
(0.64)
BSC
0.059 (1.50)
MAX 0.069 (1.75)
0.053 (1.35)
0.010 (0.20 )
0.007 (0.18 )
0.050 (1.27)
0.016 (0.41)
88
88
8
08
88
8
REF: JEDEC 0.150” SSOP - DRAWING NUMBER MO-137
