MC68336376UMA - Motorola / Freescale Semiconductor

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 A-1
APPENDIX A
ELECTRICAL CHARACTERISTICS
This appendix contains electrical specification tables and reference timing diagrams
for MC68336 and MC68376 microcontroller units. 
Table A-1 Maximum Ratings
Num Rating Symbol Value Unit
1Supply Voltage1, 2, 7
NOTES:
1. Permanent damage can occur if maximum ratings are exceeded.  Exposure to voltages or currents in excess
of recommended values affects device reliability.  Device modules may not operate normally while being ex-
posed to electrical extremes.  
2. Although sections of the device contain circuitry to protect against damage from high static voltages or elec-
trical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages.
VDD – 0.3 to + 6.5 V
2Input Voltage11, 22, 3, 55, 77
3. All pins except TSTME/TSC.
Vin – 0.3 to + 6.5 V
3 Instantaneous Maximum Current
Single pin limit (applies to all pins)11, 55, 66, 
77
ID25 mA
4 Operating Maximum Current
Digital Input Disruptive Current 4, 5, 6, 7, 8
VNEGCLMAP  ≅ – 0.3  V
VPOSCLAMP  ≅ VDD + 0.3 
4. All functional non-supply pins are internally clamped to VSS.  All functional pins except EXTAL and XFC are
internally clamped to VDD.  Does not include QADC pins (refer to Table A-11).
5. Input must be current limited to the value specified.  To determine the value of the required current-limiting
resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two
values.
6. Power supply must maintain regulation within operating VDD range during instantaneous and operating max-
imum current conditions. 
7. This parameter is periodically sampled rather than 100% tested.
8. Total input current for all digital input-only and all digital input/output pins must not exceed 10 mA.  Exceeding
this limit can cause disruption of normal operation. 
IID
– 500 to 500 µA
5 Operating Temperature Range
MC68336/376 “C” Suffix
MC68336/376 “V” Suffix
MC68336/376 “M” Suffix
TA
TL to TH
– 40 to 85
– 40 to 105
– 40 to 125
°C
6 Storage Temperature Range Tstg – 55 to 150 °C

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-2

Table A-2 Typical Ratings

Num Rating Symbol Value Unit

1 Supply Voltage VDD 5.0 V

2 Operating Temperature TA25 °C

VDD Supply Current

RUN

LPSTOP, VCO off

LPSTOP, External clock, maxi fsys

IDD

113

125

3.75

µA

4 Clock Synthesizer Operating Voltage VDDSYN 5.0 V

VDDSYN Supply Current

VCO on, maximum fsys

External Clock, maximum fsys

LPSTOP, VCO off

VDD powered down

IDDSYN

1.0

5.0

100

µA

6 RAM Standby Voltage VSB 3.0 V

RAM Standby Current

Normal RAM operation

Standby operation

ISB 7.0

µA

8 Power Dissipation PD570 mW

Table A-3 Thermal Characteristics

Num Rating Symbol Value Unit

1Thermal Resistance

Plastic 160-Pin Surface Mount θJA 37 °C/W

The average chip-junction temperature (TJ) in C can be obtained from:

(1)

where:

TA= Ambient Temperature, °C

ΘJA = Package Thermal Resistance, Junction-to-Ambient, °C/W

PD= PINT + PI/O

PINT = IDD × VDD, Watts — Chip Internal Power

PI/O = Power Dissipation on Input and Output Pins — User Determined

For most applications PI/O < PINT and can be neglected. An approximate relationship between P

D and TJ (if PI/O is

neglected) is:

(2)

Solving equations 1 and 2 for K gives:

(3)

where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P

D (at

equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1)

and (2) iteratively for any value of TA.

TJTAPDΘJA

×()+=

PDKT

J273 °C+()÷=

KPDTA273°C+()Θ

JA PD

×++

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-3

Table A-4 Clock Control Timing

(VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH, 4.194 MHz reference)

Num Characteristic Symbol Min Max Unit

1 PLL Reference Frequency Range fref 4.194 5.243 MHz

2System Frequency1

On-Chip PLL System Frequency

External Clock Operation

NOTES:

1. All internal registers retain data at 0 Hz.

fsys

fref/32

20.97

MHz

3PLL Lock Time2, 3, 4, 5

2. This parameter is periodically sampled rather than 100% tested.

3. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total

external resistance from the XFC pin due to external leakage must be greater than 15 MΩ to guarantee this

specification. Filter network geometry can vary depending upon operating environment

4. Proper layout procedures must be followed to achieve specifications.

5. Assumes that stable VDDSYN is applied, and that the crystal oscillator is stable. Lock time is measured from the

time VDD and VDDSYN are valid until RESET is released. This specification also applies to the period required

for PLL lock after changing the W and Y frequency control bits in the synthesizer control register (SYNCR) while

the PLL is running, and to the period required for the clock to lock after LPSTOP.

tlpll —20ms

4VCO Frequency6

6. Internal VCO frequency (fVCO ) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a di-

vide-by-two circuit that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and f sys =

fVCO ÷ 4. When X = 1, the divider is disabled, and fsys = fVCO ÷ 2. X must equal one when operating at maximum

specified fsys.

fVCO —2 (f

sys max) MHz

5 Limp Mode Clock Frequency

SYNCR X bit = 0

SYNCR X bit = 1

flimp —

—

fsys max/2

fsys max

MHz

6CLKOUT Jitter2, 3, 4, 7

Short term (5 µs interval)

Long term (500 µs interval)

7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maxi-

mum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable exter-

nal clock signal. Noise injected into the PLL circuitry via VDDSYN and VSS and variation in crystal oscillator

frequency increase the Jclk percentage for a given interval. When jitter is a critical constraint on control system

operation, this parameter should be measured during functional testing of the final system.

Jclk –0.625

–0.0625

–0.625

–0.0625

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 A-4
Table A-5 DC Characteristic s
(VDD and VDDSYN = 5.0 Vdc ±5%, VSS = 0 Vdc, TA = TL to TH)
Num Characteristic Symbol Min Max Unit
1 Input High Voltage VIH 0.7 (VDD)V
DD + 0.3 V
2 Input Low Voltage VIL VSS – 0.3 0.2 (VDD)V
3Input Hysteresis1 VHYS 0.5 — V
4Input Leakage Current2
Vin = VDD or VSS Input-only pins Iin –2.5 2.5 µA
5High Impedance (Off-State) Leakage Current22
Vin = VDD or VSS All input/output and output pins   IOZ –2.5 2.5 µA
6CMOS Output High Voltage22, 3
IOH = –10.0 µA Group 1, 2, 4 input/output and all output pins VOH VDD – 0.2 — V
7CMOS Output Low Voltage22
IOL = 10.0 µA Group 1, 2, 4 input/output and all output pins VOL —0.2V
8Output High Voltage22, 33
IOH = –0.8 mA Group 1, 2, 4 input/output and all output pins  VOH VDD – 0.8 — V
9
Output Low Voltage22
IOL = 1.6 mA Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IP-
IPE
IOL = 5.3 mA Group 2 and Group 4 I/O Pins, CSBOOT, BG/CS 
IOL = 12 mA Group 3
VOL
—
—
—
0.4
0.4
0.4
V
10 Three State Control Input High Voltage VIHTSC 1.6 (VDD)9.1 V
11
Data Bus Mode Select Pull-up Current4
Vin = VIL DATA[15:0]
Vin = VIH DATA[15:0] IMSP
—
–15
–120
—µA
12A
MC68336 VDD Supply Current5
RUN 6
RUN, TPU emulation mode
LPSTOP, 4.194 MHz crystal, VCO Off (STSIM = 0)
LPSTOP (External clock input frequency = maximum fsys)
IDD
IDD
SIDD
SIDD
—
—
—
—
140
150
3
7
mA
mA
mA
mA
12B
MC68376 VDD Supply Current5
RUN6
RUN, TPU emulation mode
LPSTOP, 4.194 MHz crystal, VCO Off (STSIM = 0)
LPSTOP (External clock input frequency = maximum fsys)
IDD
IDD
SIDD
SIDD
—
—
—
—
150
160
3
7
mA
mA
mA
mA
13 Clock Synthesizer Operating Voltage VDDSYN 4.75 5.25 V
14
VDDSYN Supply Current55
4.194 MHz crystal, VCO on, maximum fsys 
External Clock, maximum fsys 
LPSTOP, 4.194 MHz crystal, VCO off (STSIM = 0)
4.194 MHz crystal, VDD powered down
IDDSYN
IDDSYN
SIDDSYN
IDDSYN
—
—
—
—
3
5
3
3
mA
mA
mA
mA

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-5

RAM Standby Voltage7

Specified VDD applied

VDD = VSS

VSB 0.0

3.0

5.25

RAM Standby Current55, 77, 8

Normal RAM operationVDD > VSB – 0.5 V

Transient condition VSB – 0.5 V ≥ VDD ≥ VSS + 0.5 V

Standby operation VDD < VSS + 0.5 V

ISB

—

100

µA

17A MC68336 Power Dissipation9PD— 756 mW

17B MC68376 Power Dissipation9PD— 809 mW

18 Input Capacitance22, 10All input-only pins

All input/output pins Cin

—

20 pF

Load Capacitance22

Group 1 I/O Pins and CLKOUT, FREEZE/QUOT, IPIPE

Group 2 I/O Pins and CSBOOT, BG/CS

Group 3 I/O pins

Group 4 I/O pins

—

100

130

200

NOTES:

1. Applies to :

Port E[7:4] — SIZ[1:0], AS, DS

Port F[7:0] — IRQ[7:1], MODCLK

Port QS[7:0] — TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO

TPUCH[15:0], T2CLK, CPWM[8:5], CTD[4:3], CTD[10:9], CTM2C

BKPT/DSCLK, IFETCH, RESET, RXD, TSTME/TSC

EXTAL (when PLL enabled)

2. Input-Only Pins: EXTAL, TSTME/TSC, BKPT, PAI, T2CLK, RXD, CTM2C

Output-Only Pins: CSBOOT, BG/CS, CLKOUT, FREEZE/QUOT, IPIPE

Input/Output Pins:

Group 1: DATA[15:0], IFETCH, TPUCH[15:0], CPWM[8:5], CTD[4:3], CTD[10:9]

Group 2: Port C[6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3]

Port E[7:0] — SIZ[1:0], AS, DS, AVEC, RMC, DSACK[1:0]

Port F[7:0] — IRQ[7:1], MODCLK

Port QS[7:3] — TXD, PCS[3:1], PCS0/SS

ADDR23/CS10/ECLK, ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2

Group 3: HALT, RESET

Group 4: MISO, MOSI, SCK

Pin groups do not include QADC pins. See Tables A-11 through A-14 for information concerning the QADC.

3. Does not apply to HALT and RESET because they are open drain pins. Does not apply to port QS[7:0] (TXD,

PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode.

4. Use of an active pulldown device is recommended.

5. Total operating current is the sum of the appropriate IDD, IDDSYN, and ISB values. IDD values include supply

currents for device modules powered by VDDE and VDDI pins.

6. Current measured at maximum system clock frequency, all modules active.

7. The SRAM module will not switch into standby mode as long as VSB does not exceed VDD by more than 0.5

volts. The SRAM array cannot be accessed while the module is in standby mode.

8. When VDD is transitioning during power-up or power down sequence, and VSB is applied, current flows between

the VSTBY and VDD pins, which causes standby current to increase toward the maximum transient condition

specification. System noise on the VDD and VSTBY pins can contribute to this condition.

9. Power dissipation measured at system clock frequency, all modules active. Power dissipation can be calculated

using the following expression:

PD = Maximum VDD (Run IDD + IDDSYN + ISB) + Maximum VDDA (IDDA)

10. This parameter is periodically sampled rather than 100% tested.

Table A-5 DC Characteristics (Continued)

(VDD and VDDSYN = 5.0 Vdc ±5%, VSS = 0 Vdc, TA = TL to TH)

Num Characteristic Symbol Min Max Unit

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-6

Table A-6 AC Timin g

(VDD and VDDSYN = 5.0 Vdc ±5%, VSS = 0 Vdc, TA = TL to TH)1

Num Characteristic Symbol Min Max Unit

F1 Frequency of Operation2 fsys — 20.97 MHz

1 Clock Period tcyc 47.7 — ns

1A ECLK Period tEcyc 381 — ns

1B External Clock Input Period3tXcyc 47.7 — ns

2, 3 Clock Pulse Width tCW 18.8 — ns

2A, 3A ECLK Pulse Width tECW 183 — ns

2B, 3B External Clock Input High/Low Time3tXCHL 23.8 — ns

3, 4 Clock Rise and Fall Time tCrf —5ns

4A, 5A Rise and Fall Time — All Outputs except CLKOUT trf —8ns

4B, 5B External Clock Rise and Fall Time4tXCrf —5ns

4 Clock High to Address, FC, SIZE, RMC Valid tCHAV 023ns

5 Clock High to Address, Data, FC, SIZE, RMC High Impedance tCHAZx 047ns

6Clock High to Address, FC, SIZE, RMC Invalid5tCHAZn 0—ns

7 Clock Low to AS, DS, CS Asserted tCLSA 023ns

8A AS to DS or CS Asserted (Read)6tSTSA –10 10 ns

8C Clock Low to IFETCH, IPIPE Asserted tCLIA 222ns

11 Address, FC, SIZE, RMC Valid to AS, CS Asserted tAVSA 10 — ns

12 Clock Low to AS, DS, CS Negated tCLSN 223ns

12A Clock Low to IFETCH, IPIPE Negated tCLIN 222ns

13 AS, DS, CS Negated to Address, FC, SIZE Invalid (Address Hold) tSNAI 10 — ns

14 AS, CS Width Asserted tSWA 80 — ns

14A DS, CS Width Asserted (Write) tSWAW 36 — ns

14B AS, CS Width Asserted (Fast Write Cycle) tSWDW 32 — ns

15 AS, DS, CS Width Negated7tSN 32 — ns

16 Clock High to AS, DS, R/W High Impedance tCHSZ —47ns

17 AS, DS, CS Negated to R/ W Negated tSNRN 10 — ns

18 Clock High to R/W High tCHRH 023ns

20 Clock High to R/W Low tCHRL 023ns

21 R/W Asserted to AS, CS Asserted tRAAA 10 — ns

22 R/W Low to DS, CS Asserted (Write) tRASA 54 — ns

23 Clock High to Data Out Valid tCHDO —23ns

24 Data Out Valid to Negating Edge of AS, CS t

DVASN 10 — ns

25 DS, CS Negated to Data Out Invalid (Data Out Hold) tSNDOI 10 — ns

26 Data Out Valid to DS, CS Asserted (Write) tDVSA 10 — ns

27 Data In Valid to Clock Low (Data Setup)5tDICL 5—ns

27A Late BERR, HALT Asserted to Clock Low (Setup Time) tBELCL 15 — ns

28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated tSNDN 060ns

29 DS, CS Negated to Data In Invalid (Data In Hold)

8tSNDI 0—ns

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-7

29A DS, CS Negated to Data In High Impedance

88, 9tSHDI —48ns

30 CLKOUT Low to Data In Invalid (Fast Cycle Hold)88 tCLDI 10 — ns

30A CLKOUT Low to Data In High Impedance88 tCLDH —72ns

31 DSACK[1:0] Asserted to Data In Valid10 tDADI —46ns

33 Clock Low to BG Asserted/Negated tCLBAN —23ns

35 BR Asserted to BG Asserted (RMC Not Asserted) 11 tBRAGA 1—t

cyc

37 BGACK Asserted to BG Negated tGAGN 12t

cyc

39 BG Width Negated tGH 2—t

cyc

39A BG Width Asserted tGA 1—t

cyc

46 R/W Width Asserted (Write or Read) tRWA 115 — ns

46A R/W Width Asserted (Fast Write or Read Cycle) tRWAS 70 — ns

47A Asynchronous Input Setup Time

BR, BGACK, DSACK[1:0], BERR, AVEC, HALT tAIST 5—ns

47B Asynchronous Input Hold Time tAIHT 12 — ns

48 DSACK[1:0] Asserted to BERR, HALT Asserted12 tDABA —30ns

53 Data Out Hold from Clock High tDOCH 0—ns

54 Clock High to Data Out High Impedance tCHDH —23ns

55 R/W Asserted to Data Bus Impedance Change tRADC 32 — ns

56 RESET Pulse Width (Reset Instruction) tHRPW 512 — tcyc

57 BERR Negated to HALT Negated (Rerun) tBNHN 0—ns

70 Clock Low to Data Bus Driven (Show) tSCLDD 023ns

71 Data Setup Time to Clock Low (Show) tSCLDS 10 — ns

72 Data Hold from Clock Low (Show) tSCLDH 10 — ns

73 BKPT Input Setup Time tBKST 10 — ns

74 BKPT Input Hold Time tBKHT 10 — ns

75 Mode Select Setup Time tMSS 20 — tcyc

76 Mode Select Hold Time tMSH 0—ns

77 RESET Assertion Time13 tRSTA 4—t

cyc

78 RESET Rise Time14, 15 tRSTR —10t

cyc

NOTES:

1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.

2. The base configuration of the MC68336/376 requires a 20.97 MHz crystal reference.

3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum

allowable tXcyc period is reduced when the duty cycle of the external clock signal varies. The relationship between

external clock input duty cycle and minimum tXcyc is expressed:

Minimum tXcyc period = minimum tXCHL / (50% –external clock input duty cycle tolerance).

4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during

reset). Does not pertain to an external VCO reference applied while the PLL is enabled (MODCLK pin held high

during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference

signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.

5. Address access time = (2.5 + WS) tcyc – tCHAV – tDICL

Chip select access time = (2 + WS) tcyc – tLSA – tDICL

Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.

Table A-6 AC Timing (Continued)

(VDD and VDDSYN = 5.0 Vdc ±5%, VSS = 0 Vdc, TA = TL to TH)1

Num Characteristic Symbol Min Max Unit

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-8

Figure A-1 CLKOUT Output Timing Diagram

Figure A-2 External Clock Input Timing Diagram

6. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative

loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside

the limits shown in specification 9.

7. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a

heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification

between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.

8. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast

cycle reads. The user is free to use either hold time.

9. Maximum value is equal to (tcyc / 2) + 25 ns.

10. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data setup

time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data

must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must

satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.

11. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after all cycles

of the current operand transfer are complete and RMC is negated.

12. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specification

47A).

13. After external RESET negation is detected, a short transition period (approximately 2 t

cyc) elapses, then the SIM

drives RESET low for 512 tcyc.

14. External assertion of the RESET input can overlap internally-generated resets. To insure that an external

reset is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.

15. External logic must pull RESET high during this period in order for normal MCU operation to begin.

68300 CLKOUT TI

CLKOUT

68300 EXT CLK INPUT

EXTAL

2B 3B

NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% VDD.

PULSE WIDTH SHOWN WITH RESPECT TO 50% VDD.

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-9

Figure A-3 ECLK Output Timing Diagram

68300 ECLK OUTPUT TI

ECLK

2A 3A

NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% VDD.

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-10

Figure A-4 Read Cycle Timing Diagram

68300 RD CYC TI

CLKOUT

S0 S1 S2 S3 S4 S5

27A

47A

ADDR[23:20]

FC[2:0]

SIZ[1:0]

R/W

DSACK0

DSACK1

DATA[15:0]

BERR

IFETCH

47B47A

ASYNCHRONOUS

INPUTS

HALT

12A12A

BKPT

14 15

29A

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USER’S MANUAL Rev. 15 Oct 2000 A-11

Figure A-5 Write Cycle Timing Diagram

68300 WR CYC TI

CLKOUT

S0 S1 S2 S3 S4 S5

27A

ADDR[23:20]

FC[2:0]

SIZ[1:0]

R/W

DSACK0

DSACK1

DATA[15:0]

BERR

HALT

BKPT

47A

2623

22 14A 17

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USER’S MANUAL Rev. 15 Oct 2000 A-12

Figure A-6 Fast Termination Read Cycle Timing Diagram

68300 FAST RD CYC TI

CLKOUT

S0 S1 S4 S5 S0

ADDR[23:0]

FC[2:0]

SIZ[1:0]

R/W

DATA[15:0]

14B

BKPT

46A

73 29A

30A

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-13

Figure A-7 Fast Termination Write Cycle Timing Diagram

68300 FAST WR CYC TI

CLKOUT

S0 S1 S4 S5 S0

ADDR[23:0]

FC[2:0]

SIZ[1:0]

R/W

DATA[15:0]

14B

BKPT

46A

24 18

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-14

Figure A-8 Bus Arbitration Timing Diagram — Active Bus Case

68300 BUS ARB TI

CLKOUT

S0 S1 S2 S3 S4

ADDR[23:0]

DATA[15:0]

S98A5A5A2

47A

39A

R/W

DSACK0

DSACK1

BGACK

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-15

Figure A-9 Bus Arbitration Timing Diagram — Idle Bus Case

68300 BUS ARB TIM ID

CLKOUT

A0 A5

ADDR[23:0]

DATA[15:0]

A2 A3 A0A5

BGACK

47A

33 33

47A

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USER’S MANUAL Rev. 15 Oct 2000 A-16

Figure A-10 Show Cycle Timing Diagram

CLKOUT

S0 S41 S42 S0 S1 S2

ADDR[23:0]

R/W

DATA[15:0]

BKPT

12915

SHOW CYCLE START OF EXTERNAL CYCLE

S43

68300 SHW CYC TIM

NOTE:

Show cycles can stretch during clock phase S42 when bus accesses take longer than two cycles

due to IMB module wait-state insertion.

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-17

Figure A-11 Chip-Select Timing Diagram

Figure A-12 Reset and Mode Select Timing Diagram

68300 CHIP SEL TI

66 8

11 11

29A

14A

18 20 18

S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5

CLKOUT

ADDR[23:0]

FC[2:0]

SIZ[1:0]

R/W

DATA[15:0]

21 21

17 17

68300 RST/MODE SEL

RESET

ATA[15:0]

77 78

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-18

Figure A-13 Background Debugging Mode Timing — Serial Communication

Figure A-14 Background Debugging Mode Timing — Freeze Assertion

Table A-7 Background Debug Mode Timing

(VDD = 5.0 Vdc ±5%, VSS = 0 Vdc, TA = TL to TH)1

NOTES:

1. All AC timing is shown with respect to 20% V

DD and 70% VDD levels unless otherwise noted.

Num Characteristic Symbol Min Max Unit

B0 DSI Input Setup Time tDSISU 15 — ns

B1 DSI Input Hold Time tDSIH 10 — ns

B2 DSCLK Setup Time tDSCSU 15 — ns

B3 DSCLK Hold Time tDSCH 10 — ns

B4 DSO Delay Time tDSOD —25ns

B5 DSCLK Cycle Time tDSCCYC 2 — tcyc

B6 CLKOUT Low to FREEZE Asserted/Negated tFRZAN —50ns

B7 CLKOUT High to IFETCH High Impedance tIPZ —TBDns

B8 CLKOUT High to IFETCH Valid tIP —TBDns

B9 DSCLK Low Time tDSCLO 1—t

cyc

68300 BKGD DBM SER COM

CLKOUT

FREEZE

BKPT/DSCLK

IFETCH/DSI

IPIPE/DSO

68300 BDM FRZ TIM

CLKOUT

FREEZE

IFETCH/DSI

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USER’S MANUAL Rev. 15 Oct 2000 A-19

Table A-8 ECLK Bus Timing

(VDD = 5.0 Vdc ±5%, VSS = 0 Vdc, TA = TL to TH)1

NOTES:

1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.

Num Characteristic Symbol Min Max Unit

E1 ECLK Low to Address Valid2

2. When the previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.

tEAD —48 ns

E2 ECLK Low to Address Hold tEAH 10 — ns

E3 ECLK Low to CS Valid (CS delay) tECSD — 120 ns

E4 ECLK Low to CS Hold tECSH 10 — ns

E5 CS Negated Width tECSN 25 — ns

E6 Read Data Setup Time tEDSR 25 — ns

E7 Read Data Hold Time tEDHR 5—ns

E8 ECLK Low to Data High Impedance tEDHZ —48 ns

E9 CS Negated to Data Hold (Read) tECDH 0—ns

E10 CS Negated to Data High Impedance tECDZ —1t

cyc

E11 ECLK Low to Data Valid (Write) tEDDW —2t

cyc

E12 ECLK Low to Data Hold (Write) tEDHW 10 — ns

E13 Address Access Time (Read)3

3. Address access time = tEcyc – tEAD – tEDSR.

tEACC 308 — ns

E14 Chip Select Access Time (Read)4

4. Chip select access time = tEcyc – tECSD – tEDSR.

tEACS 236 — ns

E15 Address Setup Time tEAS 1/2 — tcyc

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USER’S MANUAL Rev. 15 Oct 2000 A-20

Figure A-15 ECLK Timing Diagram

68300 E CYCLE TIM

CLKOUT

ADDR[23:0]

ECLK

DATA[15:0]

2A 3A

E10

E12

E14

E13

DATA[15:0]

E15

E11

WRITEREAD

WRITE

R/W

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USER’S MANUAL Rev. 15 Oct 2000 A-21

Table A-9 QSPI Timing

(VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH 200 pF load on all QSPI pins)1

NOTES:

1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.

Num Function Symbol Min Max Unit

Operating Frequency

Master

Slave

fQSPI DC

1/4

fsys

2 Cycle Time

Master

Slave

tqcyc 4

510

—

tcyc

3 Enable Lead Time

Master

Slave

tlead 2

128

—

tcyc

4 Enable Lag Time

Master

Slave

tlag —

1/2

—

SCK

tcyc

5 Clock (SCK) High or Low Time

Master

Slave2

2. For high time, n = External SCK rise time; for low time, n = External SCK fall time.

tsw 2 tcyc – 60

2 tcyc – n

255 tcyc

—

6 Sequential Transfer Delay

Master

Slave (Does Not Require Deselect)

ttd 17

8192

—

tcyc

7 Data Setup Time (Inputs)

Master

Slave

tsu 30

—

8 Data Hold Time (Inputs)

Master

Slave

thi 0

—

9 Slave Access Time ta—1 t

cyc

10 Slave MISO Disable Time tdis —2 t

cyc

11 Data Valid (after SCK Edge)

Master

Slave

tv—

—

12 Data Hold Time (Outputs)

Master

Slave

tho 0

—

13 Rise Time

Input

Output

tri

tro

—

µs

14 Fall Time

Input

Output

tfi

tfo

—

µs

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USER’S MANUAL Rev. 15 Oct 2000 A-22

Figure A-16 QSPI Timing — Master, CPHA = 0

Figure A-17 QSPI Timing — Master, CPHA = 1

QSPI MAST CPHA0

3 2

DATA LSB IN MSB IN

MSB OUT

MSB IN

MSB OUT DATA LSB OUT PORT DATA

1213

PCS[3:0]

OUTPUT

MISO

INPUT

MOSI

OUTPUT

SCK

CPOL=0

OUTPUT

SCK

CPOL=1

OUTPUT

QSPI MAST CPHA1

11 10

3 2

MSB

PCS[3:0]

OUTPUT

MISO

INPUT

MSBMSB OUT DATA LSB OUT PORT DATA

PORT DATA

MOSI

OUTPUT

DATA LSB IN

MSB IN

SCK

CPOL=0

OUTPUT

SCK

CPOL=1

OUTPUT

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-23

Figure A-18 QSPI Timing — Slave, CPHA = 0

Figure A-19 QSPI Timing — Slave, CPHA = 1

811 9

3 2

DATA LSB OUT PD MSB OUT

MSB IN

MSB OUT

MSB IN DATA LSB IN

INPUT

SCK

CPOL=0

INPUT

SCK

CPOL=1

INPUT

MISO

OUTPUT

MOSI

INPUT

QSPI SLV CPHA0

QSPI SLV CPHA1

INPUT

10 9

DATA SLAVE

LSB OUT PDMSB OUT

MSB IN DATA LSB IN

MISO

OUTPUT

SCK

CPOL=1

INPUT

MOSI

INPUT

SCK

CPOL=0

INPUT

MC68336/376 ELECTRICAL CHARACTERISTICS MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 A-24

Figure A-20 TPU Timing Diagram

Table A-10 Time Processor Unit Timing

(VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH, fsys = 20.97 MHz)1, 2

NOTES:

1. AC timing is shown with respect to 20% V

DD and 70% VDD levels.

2. Timing not valid for external T2CLK input.

Num Rating Symbol Min Max Unit

1CLKOUT High to TPU Output Channel Valid3, 4

3. Maximum load capacitance for CLKOUT pin is 90 pF.

4. Maximum load capacitance for TPU output pins is 100 pF.

tCHTOV 218ns

2 CLKOUT High to TPU Output Channel Hold tCHTOH 015ns

3 TPU Input Channel Pulse Width tTIPW 4—t

cyc

TPU I/O TIM

CLKOUT

TPU OUTPUT

TPU INPUT

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USER’S MANUAL Rev. 15 Oct 2000 A-25

Table A-11 QADC Maximum Ratings

Num Parameter Symbol Min Max Unit

1Analog Supply, with reference to VSSA VDDA – 0.3 6.5 V

2Internal Digital Supply, with reference to VSSI VDDI – 0.3 6.5 V

3Reference Supply, with reference to VRL VRH – 0.3 6.5 V

4VSS Differential Voltage VSSI – VSSA – 0.1 0.1 V

5VDD Differential Voltage VDDI – VDDA – 6.5 6.5 V

6VREF Differential Voltage VRH – VRL – 6.5 6.5 V

7VRH to VDDA Differential Voltage VRH – VDDA – 6.5 6.5 V

8VRL to VSSA Differential Voltage VRL – VSSA – 6.5 6.5 V

Disruptive Input Current1, 2, 3, 4, 5, 6, 7

VNEGCLAMP = – 0.3 V

VPOSCLAMP = 8 V

NOTES:

1. Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs

greater than VRH and $000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the

presence of the sample amplifier. Other channels are not affected by non-disruptive conditions.

2. Input signals with large slew rates or high frequency noise components cannot be converted accurately. These

signals also affect the conversion accuracy of other channels.

3. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions

within the limit do not affect device reliability or cause permanent damage.

4. Input must be current limited to the value specified. To determine the value of the required current-limiting re-

sistor, calculate resistance values using positive and negative clamp values, then use the larger of the calculated

values.

5. This parameter is periodically sampled rather 100% tested.

6. Condition applies to one pin at a time.

7. Determination of actual maximum disruptive input current, which can affect operation, is related to external sys-

tem component values.

INA – 500 500 µA

Positive Overvoltage Current Coupling Ratio1, 5, 6, 8

PQA

PQB

8. Current coupling is the ratio of the current induced from overvoltage (positive or negative, through an external

series coupling resistor), divided by the current induced on adjacent pins. A voltage drop may occur across the

external source impedances of the adjacent pins, impacting conversions on these adjacent pins.

KP2000

2000

——

Negative Overvoltage Current Coupling Ratio1, 5, 6, 8

PQA

PQB

KN125

500

——

Maximum Input Current3, 4, 6

VNEGCLAMP = – 0.3 V

VPOSCLAMP = 8 V

IMA – 25 25 mA

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USER’S MANUAL Rev. 15 Oct 2000 A-26

Table A-12 QADC DC Electrical Characteristics (Operating)

(VSSI and VSSA = 0Vdc, fQCLK = 2.1 MHz, TA = TL to TH)

Num Parameter Symbol Min Max Unit

1Analog Supply1

NOTES:

1. Refers to operation over full temperature and frequency range.

VDDA 4.5 5.5 V

2Internal Digital Supply1VDDI 4.5 5.5 V

3VSS Differential Voltage VSSI – VSSA – 1.0 1.0 mV

4VDD Differential Voltage VDDI – VDDA – 1.0 1.0 V

5Reference Voltage Low2

2. To obtain full-scale, full-range results, VSSA ≤ VRL ≤ VINDC ≤ VRH ≤ VDDA.

VRL VSSA —V

6Reference Voltage High2VRH —V

DDA V

7VREF Differential Voltage3

3. Accuracy tested and guaranteed at VRH – VRL = 5.0V ± 10%.

VRH – VRL 4.5 5.5 V

8 Mid-Analog Supply Voltage VDDA/2 2.25 2.75 V

9 Input Voltage VINDC VSSA VDDA V

10 Input High Voltage, PQA and PQB VIH 0.7 (VDDA)V

DDA + 0.3 V

11 Input Low Voltage, PQA and PQB VIL VSSA – 0.3 0.2 (VDDA)V

12 Input Hysteresis4

4. Parameter applies to the following pins:

Port A: PQA[7:0]/AN[59:58]/ETRIG[2:1]

Port B: PQB[7:0]/AN[3:0]/AN[51:48]/AN[Z:W]

VHYS 0.5 — V

Output Low Voltage, PQA5

IOL = 5.3 mA

IOL = 10.0 µA

5. Open drain only.

VOL —

—

0.4

0.2

Analog Supply Current

Normal Operation6

Low-Power Stop

6. Current measured at maximum system clock frequency with QADC active.

IDDA —

—

1.0

10.0

µA

15 Reference Supply Current IREF — 150 µA

16 Load Capacitance, PQA CL—90pF

Input Current, Channel Off7

PQA

PQB

7. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half

for each 10° C decrease from maximum temperature.

IOFF —

—

250

150

Total Input Capacitance8

PQA Not Sampling

PQA Sampling

PQB Not Sampling

PQB Sampling

8. This parameter is periodically sampled rather than 100% tested.

CIN

—

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USER’S MANUAL Rev. 15 Oct 2000 A-27

Table A-13 QADC AC Electrical Characteristics (Operating)

(VDDI and VDDA = 5.0 Vdc ± 5%, VSSI and VSSA = 0Vdc, TA = TL to TH)

Num Parameter Symbol Min Max Unit

1QADC Clock (QCLK) Frequency1

NOTES:

1. Conversion characteristics vary with fQCLK rate. Reduced conversion accuracy occurs at max fQCLK rate.

fQCLK 0.5 2.1 MHz

2QADC Clock Duty Cycle2, 3

High Phase Time (tPSL ≤ tPSH)

2. Duty cycle must be as close as possible to 75% to achieve optimum performance.

3. Minimum applies to 1.0 MHz operation.

tPSH 500 — ns

3Conversion Cycles4

4. Assumes that short input sample time has been selected (IST = 0).

CC 18 32 QCLK cycles

Conversion Time2,4,5

fQCLK = 0.999 MHz6

Min = CCW/IST = %00

Max = CCW/IST = %11

fQCLK = 2.097 MHz1, 7

Min = CCW/IST = %00

Max = CCW/IST = %11

5. Assumes that fsys = 20.97 MHz.

6. Assumes fQCLK = 0.999 MHz, with clock prescaler values of:

QACR0: PSH = %01111, PSA = %1, PSL = 100)

CCW: BYP = %0

7. Assumes fQCLK = 2.097 MHz, with clock prescaler values of:

QACR0: PSH = %00110, PSA = %1, PSL = 010)

CCW: BYP = %0

tCONV

18.0

8.58

15.24

µs

5 Stop Mode Recovery Time tSR —10 µs

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USER’S MANUAL Rev. 15 Oct 2000 A-28

Table A-14 QADC Conversion Characteristics (Operating)

(VDDI and VDDA = 5.0 Vdc ± 5%, VSSI and VSSA = 0 Vdc, TA = TL to TH,

0.5 MHz ≤ fQCLK ≤ 2.1 MHz, 2 clock input sample time)

Num Parameter Symbol Min Typ Max Unit

1Resolution1

NOTES:

1. At VRH – VRL = 5.12 V, one count = 5 mV.

1 Count — 5 — mV

2Differential nonlinearity2

2. This parameter is periodically sampled rather than 100% tested.

DNL — — ± 0.5 Counts

3Integral nonlinearity INL — — ± 2.0 Counts

4Absolute error2, 3, 4

fQCLK = 0.999 MHz5

PQA

PQB

fQCLK = 2.097 MHz6

PQA

PQB

3. Absolute error includes 1/2 count (2.5 mV) of inherent quantization error and circuit (differential, integral, and

offset) error. Specification assumes that adequate low-pass filtering is present on analog input pins — capacitive

filter with 0.01 µF to 0.1 µF capacitor between analog input and analog ground, typical source isolation

impedance of 20 kΩ.

4. Assumes fsys = 20.97 MHz.

5. Assumes clock prescaler values of:

QACR0: PSH = %01111, PSA = %1, PSL = 100)

CCW: BYP = %0

6. Assumes clock prescaler values of:

QACR0: PSH = %00110, PSA = %1, PSL = 010)

CCW: BYP = %0

—

± 2.5

± 4.0

Counts

5Source impedance at input7

7. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction

leakage into the pin and on leakage due to charge-sharing with internal capacitance.

Error from junction leakage is a function of external source impedance and input leakage current. In the following

expression, expected error in result value due to junction leakage is expressed in voltage (V

errj):

Verrj = RS X IOFF

where IOFF is a function of operating temperature. Refer to Table A-12.

Charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage between

successive conversions, and the size of the decoupling capacitor used. Error levels are best determined

empirically. In general, continuous conversion of the same channel may not be compatible with high source

impedance.

RS—20—k¾

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USER’S MANUAL Rev. 15 Oct 2000 A-29

Table A-15 FCSM Timing Characteristics

(VDD = 5.0 Vdc ± 5%, Vss = 0 Vdc, TA = TL to TH)

Num Parameter Symbol Min Max Unit

1Input pin frequency1

NOTES:

1. Value applies when using external clock.

fPCNTR 0f

sys/4 MHz

2Input pin low time1tPINL 2.0/fsys —µs

3Input pin high time1tPINH 2.0/fsys —µs

4 Clock pin to counter increment tPINC 4.5/fsys 6.5/fsys µs

5 Clock pin to new TBB value tPTBB 5.0/fsys 7.0/fsys µs

6 Clock pin to COF set ($FFFF) tPCOF 4.5/fsys 6.5/fsys µs

7 Pin to IN bit delay tPINB 1.5/fsys 2.5/fsys µs

8 Flag to IMB interrupt request tFIRQ 1.0/fsys 1.0/fsys µs

9Counter resolution2

2. Value applies when using internal clock. Minimum counter resolution depends on prescaler divide ra-

tio selection.

tCRES — 2.0/fsys µs

Table A-16 MCSM Timing Characteristics

(VDD = 5.0 Vdc ± 5%, VSS = 0Vdc, TA = TL to TH)

Num Parameter Symbol Min Max Unit

1Input pin frequency1

NOTES:

1. Value applies when using external clock.

fPCNTR 0f

sys/4 MHz

2Input pin low time1tPINL 2.0/fsys —µs

3Input pin high time1tPINH 2.0/fsys —µs

4 Clock pin to counter increment tPINC 4.5/fsys 6.5/fsys µs

5 Clock pin to new TBB value tPTBB 5.0/fsys 7.0/fsys µs

6 Clock pin to COF set ($FFFF) tPCOF 4.5/fsys 6.5/fsys µs

7 Load pin to new counter value tPLOAD 2.5/fsys 3.5/fsys µs

8 Pin to IN bit delay tPINB 1.5/fsys 2.5/fsys µs

9 Flag to IMB interrupt request tFIRQ 1.0/fsys 1.0/fsys µs

10 Counter resolution2

2. Value applies when using internal clock. Minimum counter resolution depends on prescaler divide ra-

tio selection.

tCRES — 2.0/fsys µs

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USER’S MANUAL Rev. 15 Oct 2000 A-30

Table A-17 SASM Timing Characteristics

(VDD = 5.0 Vdc ± 5%, VSS = 0Vdc, TA = TL to TH)

Num Parameter Symbol Min Max Unit

1 Input pin low time tPINL 2.0/fsys —µs

2 Input pin high time tPINH 2.0/fsys —µs

3Input capture resolution1

NOTES:

1. Minimum resolution depends on counter and prescaler divide ratio selection.

tRESCA — 2.0/fsys µs

4 Pin to input capture delay tPCAPT 2.5/fsys 4.5/fsys µs

5Pin to FLAG set t

PFLAG 2.5/fsys 4.5/fsys µs

6 Pin to IN bit delay tPINB 1.5/fsys 2.5/fsys µs

7 OCT output pulse tOCT 2.0/fsys —µs

8Compare resolution1tRESCM 2.0/fsys µs

9 TBB change to FLAG set tCFLAG 1.5/fsys 1.5/fsys µs

10 TBB change to pin change2

2. Time given from when new value is stable on time base bus.

tCPIN 1.5/fsys 1.5/fsys µs

11 FLAG to IMB interrupt request

2tFIRQ 1.0/fsys 1.0/fsys µs

Table A-18 DASM Timing Characteristics

(VDD = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)

Num Parameter Symbol Min Max Unit

1 Input pin low time tPINL 2.0/fsys —µs

2 Input pin high time tPINH 2.0/fsys —µs

3Input capture resolution1

NOTES:

1. Minimum resolution depends on counter and prescaler divide ratio selection.

tRESCA — 2.0/fsys µs

4 Pin to input capture delay tPCAPT 2.5/fsys 4.5/fsys µs

5Pin to FLAG set t

PFLAG 2.5/fsys 4.5/fsys µs

6 Pin to IN bit delay tPINB 1.5/fsys 2.5/fsys µs

7 OCT output pulse tOCT 2.0/fsys —µs

8Compare resolution1tRESCM — 2.0/fsys µs

9 TBB change to FLAG set tCFLAG 1.5/fsys 1.5/fsys µs

10 TBB change to pin change2

2. Time given from when new value is stable on time base bus.

tCPIN 1.5/fsys 1.5/fsys µs

11 FLAG to IMB interrupt request

2tFIRQ 1.0/fsys 1.0/fsys µs

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USER’S MANUAL Rev. 15 Oct 2000 A-31

Table A-19 PWMSM Timing Characteristics

(VDD = 5.0Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)

Num Parameter Symbol Min Max Unit

1PWMSM output resolution1

NOTES:

1. Minimum output resolution depends on counter and prescaler divide ratio selection.

tPWMR ——µs

2PWMSM output pulse2

2. Excluding the case where the output is always zero.

tPWMO 2.0/fsys —µs

3PWMSM output pulse3

3. Excluding the case where the output is always zero.

tPWMO 2.0/fsys 2.0/fsys µs

CPSM enable to output set

PWMSM enabled before CPSM , DIV23 = 0

PWMSM enabled before CPSM , DIV23 = 1

tPWMP 3.5/fsys

6.5/fsys

—µs

PWM enable to output set

PWMSM enabled before CPSM , DIV23 = 0

PWMSM enabled before CPSM , DIV23 = 1

tPWME 3.5/fsys

5.5/fsys

4.5/fsys

6.5/fsys

µs

6 FLAG to IMB interrupt request tFIRQ 1.5/fsys 2.5/fsys µs

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