General Description
The MAX8525 (VRM 10/VRD 10)/MAX8524 (VRM 9.1/
VRD 9.1) current-mode step-down controllers, the
MAX8523 high-speed, dual-phase MOSFET gate driver,
and the MAX8552 wide-input, single-phase MOSFET
gate driver provide flexible, low-cost, low-voltage CPU
core supplies. The MAX8523 and MAX8552 high-speed,
high-current gate drivers allow operation at high switch-
ing frequencies to reduce external component size and
cost for small-footprint, low-profile designs. Pin-selec-
table 2-, 3-, and 4-phase operation and master-slave 6-
and 8-phase operation provide output-current scalability
for servers, workstations, desktops, desk notes, and net-
working applications.
The switching frequency of the MAX8524/MAX8525 is
adjustable from 150kHz to 1.2MHz, permitting loop
bandwidths of up to 200kHz. Peak current-mode con-
trol provides fast transient response and reduces cost.
A proprietary current-sharing scheme reduces current
imbalance between phases to less than 5% at full load.
The MAX8524/MAX8525 offer 0.4% initial accuracy and
remote-sense functionality. Both controllers also feature
programmable no-load offset and output-voltage posi-
tioning to adjust the output voltage as a function of the
output current. The fast-active voltage positioning further
reduces bulk output capacitors and cost.
Current-mode control also simplifies compensation with
a variety of capacitors by eliminating the output-filter
double pole associated with voltage-mode controllers.
Both devices are compatible with electrolytic, tantalum,
polymer, and ceramic capacitors. Output current sens-
ing eliminates issues associated with controllers that
use high-side current sense and ensure stable and jit-
ter-free operation. Temperature-compensated, lossless
inductor current sense eliminates the need for a cur-
rent-sense resistor and further reduces cost, while
maintaining voltage-positioning accuracy and reducing
power dissipation.
The MAX8525 features control VID voltage transition for
dynamic VID changes and eliminate both undervoltage
and overvoltage overshoot. The PWRGD signal is accu-
rate during VID code changes for the MAX8525 to
avoid any false fault signal.
Adjustable foldback current-limit and overvoltage pro-
tection provide for a robust design.
Applications
Servers, Workstations
Desktop Computers
Desk Notes and LCD PCs
Voltage-Regulator Modules
High-End Switches and Routers
Features
♦VRD/VRM 10 (MAX8525)
♦VRD/VRM 9.1 (MAX8524)
♦Fastest Load-Transient Response
♦Rapid-Active Average Current Sensing
Better than 5% Current Balance
Fastest Voltage Positioning
♦±0.4% Initial Output-Voltage Accuracy
♦Pin-Selectable 2-/3-/4-Phase Operation
♦Master-Slave 6-/8-Phase Operation
♦Differential Remote Voltage Sensing
♦Dynamic VID Change (MAX8525)
♦Adjustable, Foldback Current Limit
♦Soft-Start and Soft-Stop
♦Power-Good Output
♦150kHz to 1.2MHz Switching Frequency per Phase
♦28-Lead QSOP Package
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
________________________________________________________________ Maxim Integrated Products 1
Pin Configurations
Ordering Information
19-2855; Rev 2; 4/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE
PIN-PACKAGE
MAX8524EEI -40°C to +85°C 28 QSOP
MAX8524EEI+ -40°C to +85°C 28 QSOP
MAX8525EEI -40°C to +85°C 28 QSOP
MAX8525EEI+ -40°C to +85°C 28 QSOP
Functional Diagram appears at end of data sheet.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PWM2
PWM4
CS4+
CS2_4-
CS2+
RS+
VID5
RS-
EN
VID4
VID3
VID2
VID1
VID0
CLKI
CLKO
PWRGD
OSC
ILIM
REF
COMP
GND
VCC
CS3+
CS1_3-
CS1+
PWM1
PWM3
QSOP
TOP VIEW
MAX8525
Pin Configurations continued at end of data sheet.
+Denotes lead-free package.
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
REF, COMP, VID0 to VID5, OSC, CLKI,
CLKO to GND ..........................................-0.3V to VCC + 0.3V
RS+, RS-, ILIM to GND .................................-0.3V to VCC + 0.3V
PWM_ to GND...............................................-0.3V to VCC + 0.3V
EN, PWRGD, VCC to GND........................................-0.3V to +6V
CS1_3-, CS2_4-, CS_+ to GND ....................-0.3V to VCC + 0.3V
Continuous Power Dissipation (TA= +70°C)
28-Pin QSOP (derate 10.8mW/°C above +70°C).........860mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩto GND, PWRGD =
100kΩto VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA= 0°C to +85°C, unless otherwise
noted.)
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
GENERAL
VCC Operating Range 4.5 5.5 V
Rising 4.0
4.25
4.5 V
VCC UVLO Trip Level Hysteresis
270
mV
VCC Shutdown Supply Current VCC < 3.75V, VID_ = GND 0.7 3 mA
VCC Standby Supply Current EN = 0V, VCC = 5.5V 13 20 mA
VCC Operating Supply Current RS+ = 1.2V (no switching), set VID code for 1.100V 13 20 mA
Thermal Shutdown Rising temperature, typical hysteresis = 15°C
165
°C
REFERENCE
Reference Voltage IREF = 200µA
2.0
- 0.4%
2.0 2.0
+ 0.4%
V
Reference Load Regulation 100µA < IREF < 500µA
-0.05
%
Reference Line Regulation 4.5V < VCC < 5.5V
-0.05 +0.05
%
Reference UVLO Trip Level Rising edge, has 80mV typical hysteresis
1.74 1.84 1.95
V
SOFT-START
Soft-Start Step Size
12.5
mV
Soft-Start Time per Step Soft-start counts from EN rising (Note 1) 17 20 23 µs
VOLTAGE REGULATION
RS+ Input Bias Current VRS+ = 1.1V 0.1 1 µA
RS- Input Bias Current VRS- = 0.2V 0.1 1 µA
VID_ = 1.1V, TA = +25°C
-0.4 +0.4
VOUT Initial Accuracy VID_ = 1.1V
-0.6 +0.6
%
VOUT Droop Accuracy (CS_+) = 1.125V ±5%
COMP Output Current (VO+) - (RS+) = 200mV
385
µA
GMV Amplifier Transconductance
2mS
GMV Amplifier Gain-Bandwidth
Product 5
MHz
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
_______________________________________________________________________________________ 3
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
CURRENT-SENSE AMPLIFIERS
CS_+, CS_- Input Bias Current CS_+ = CS_- = 2V, RS+ = 0V 0.2 5 µA
Average Current-Limit Trip Level
Accuracy VILIM = 1.5V, TA = +85°C
-10 +10
%
ILIM Input Bias Current VILIM = 1.5V
0.01
1µA
ILIM Default Program Level VILIM ≥ VCC - 0.2V 1 V
Peak Current-Limit Delay Time 20 ns
OSCILLATOR
Oscillator Frequency Accuracy 10 %
Switching Frequency Range
(per Phase)
150 1200
kHz
Slave-Mode CLKI/Set Frequency
Ratio 0.8 4.0
Maximum CLKO Duty-Cycle
Skew CLKO load < 50pF and ROSC = 40.2kΩ2%
LOGIC INPUTS (EN)
Input Low Level VCC = 4.5V to 5.5V 0.8 V
Input High Level VCC = 4.5V to 5.5V 2.8 V
Input Pullup Level Internal pullup
VCC
V
Input Pullup Resistance Internal pullup 50
100
200 kΩ
LOGIC INPUTS (CLKI)
Input Low Level VCC = 4.5V to 5.5V 1.2 V
Input High Level VCC = 4.5V to 5.5V 3.6 V
Input Pulldown Level Internal pulldown
GND
V
Input Pulldown Resistance Internal pulldown 50
100
200 kΩ
MAX8524 LOGIC INPUTS (VID0–VID4)
Input Low Level VCC = 4.5V to 5.5V 0.8 V
Input High Level VCC = 4.5V to 5.5V 1.6 V
Input Pullup Level
VCC
V
Input Pullup Resistance Internal pullup resistance 10 15 20 kΩ
MAX8525 LOGIC INPUTS (VID0–VID5)
Input Low Level VCC = 4.5V to 5.5V 0.4 V
Input High Level VCC = 4.5V to 5.5V 0.8 V
PWRGD OUTPUT
Output Low Level IPWRGD = 4mA 0.4 V
Output High Leakage VPWRGD = 5.5V 1 µA
PWRGD Blanking Time From EN rising, tracks CLKO 3 5 ms
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩto GND, PWRGD =
100kΩto VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA= 0°C to +85°C, unless otherwise
noted.)
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
4 _______________________________________________________________________________________
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
Output rising VID +
0.125
VID +
0.175
PWRGD Upper Threshold
Output falling VID +
0.075
VID +
0.125
V
Output falling VID -
0.250
VID -
0.200
PWRGD Lower Threshold
Output rising VID -
0.175
VID -
0.125
V
OVP PROTECTION
MAX8524 output rising VID +
0.20
VID +
0.25
Output Overvoltage Trip
Threshold, OVP Action
MAX8525 output rising VID +
0.175
VID +
0.225
V
PWM, CKLO OUTPUTS
Output Low Level IPWM_ = -5mA 0.1 0.4 V
Output High Level IPWM_ = +5mA 4.5 4.9 V
Source Current VPWM_ = VCC - 2V 84 mA
Sink Current VPWM_ = 2V 83 mA
Rise/Fall Times 10 ns
PWM Selection Threshold VCC = 4.5V to 5.5V 0.8 2.3 3.1 V
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩto GND, PWRGD =
100kΩto VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA= 0°C to +85°C, unless otherwise
noted.)
PARAMETER CONDITIONS MIN
TYP MAX
GENERAL
VCC Operating Range 4.5 5.5 V
VCC UVLO Trip Level Rising, typical hysteresis 270mV 4.0 4.5 V
VCC Shutdown Supply Current VCC < 3.75V, VID_ = high 3 mA
VCC Standby Supply Current EN = 0V, VCC = 5.5V 20 mA
VCC Operating Supply Current RS+ = 1.2V (no switching), set VID code for 1.100V 20 mA
REFERENCE
Reference Voltage IREF = 200µA 2.0 -
0.5%
2.0 +
0.4%
V
Reference Load Regulation 100µA < IREF < 500µA
-0.05
%
Reference Line Regulation 4.5V < VCC < 5.5V
-0.05 +0.05
%
Reference UVLO Trip Level Rising edge, has 80mV typical hysteresis 1.74
1.95
V
ELECTRICAL CHARACTERISTICS
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩto GND, PWRGD =
100kΩto VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA= -40°C to +85°C, unless otherwise
noted.) (Note 2)
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
_______________________________________________________________________________________ 5
PARAMETER CONDITIONS MIN
TYP MAX
SOFT-START
Soft-Start Time per Step Soft-start counts from EN rising (Note 1) 17 23 µs
VOLTAGE REGULATION
RS+ Input Bias Current VRS+ = 1.1V 1 µA
RS- Input Bias Current VRS- = 0.2V 1 µA
VOUT Initial Accuracy VID_ = 1.1V -1 +1 %
CURRENT-SENSE AMPLIFIERS
CS_+, CS_- Input Bias Current CS_+ = CS_- = 2V, RS+ = 0V 5 µA
ILIM Input Bias Current VILIM = 1.5V 1 µA
OSCILLATOR
Switching Frequency Range
(per Phase) 150
1200
kHz
Slave-Mode CLKI/Set Frequency
Ratio 0.8 4.0
LOGIC INPUTS (EN)
Input Low Level VCC = 4.5V to 5.5V 0.8 V
Input High Level VCC = 4.5V to 5.5V 2.8 V
Input Pullup Resistance Internal pullup 50 200 kΩ
LOGIC INPUTS (CLKI)
Input Low Level VCC = 4.5V to 5.5V 1.2 V
Input High Level VCC = 4.5V to 5.5V 3.6 V
Input Pulldown Resistance Internal pulldown 50 200 kΩ
MAX8524 LOGIC INPUTS (VID0–VID4)
Input Low Level VCC = 4.5V to 5.5V 0.8 V
Input High Level VCC = 4.5V to 5.5V 1.7 V
Input Pullup Resistance Internal pullup resistance 10 20 kΩ
MAX8525 LOGIC INPUTS (VID0–VID5)
Input Low Level VCC = 4.5V to 5.5V 0.4 V
Input High Level VCC = 4.5V to 5.5V 0.8 V
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩto GND, PWRGD =
100kΩto VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA= -40°C to +85°C, unless otherwise
noted.) (Note 2)
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
6 _______________________________________________________________________________________
PARAMETER CONDITIONS MIN
TYP MAX
UNITS
PWRGD OUTPUT
Output Low Level IPWRGD = 4mA 0.4 V
Output High Leakage VPWRGD = 5.5V 1 µA
PWRGD Blanking Time From EN rising, tracks CLKO 3 5 ms
Output rising VID +
0.125
VID +
0.175
PWRGD Upper Threshold
Output falling VID +
0.075
VID +
0.125
V
Output falling VID -
0.250
VID -
0.200
PWRGD Lower Threshold
Output rising VID -
0.175
VID -
0.125
V
OVP PROTECTION
MAX8524 output rising VID +
0.20
VID +
0.25
Output Overvoltage Trip
Threshold, OVP Action
MAX8525 output rising VID +
0.175
VID +
0.225
V
PWM, CLKO OUTPUTS
Output Low Level IPWM_ = -5mA 0.4 V
Output High Level IPWM_ = +5mA 4.5 V
PWM Selection Threshold VCC = 4.5V to 5.5V 0.8 3.1 V
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩto GND, PWRGD =
100kΩto VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA= -40°C to +85°C, unless otherwise
noted.) (Note 2)
Note 1: Total soft-start time equals the soft-start time per step times the VID voltage divided by 12.5mV.
Note 2: Specifications at -40°C are guaranteed by design.
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
_______________________________________________________________________________________ 7
EFFICIENCY vs. LOAD CURRENT
AT 1.45V OUTPUT
MAX8524 toc01
LOAD CURRENT (A)
EFFICIENCY
10
10
20
30
40
50
60
70
80
90
100
0
1100
VIN = 5V
VIN = 12V
OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX8524 toc02
LOAD CURRENT (A)
VOUT
908010 20 30 50 6040 70
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.000
0 100
VIN = 12V
OUTPUT LOAD TRANSIENT
MAX8524 toc03
10μs
IOUT
VOUT
50mV/div
POWER-
GOOD
OUTPUT
0A
80A
4-PHASE ACTIVE CURRENT SHARING
MAX8524 toc04
LOAD CURRENT (A)
INDUCTOR CURRENT (A)
908070605040302010
5
10
15
20
25
0
0 100
DYNAMIC VID RESPONSE,
250mV STEP VOLTAGE
MAX8524 toc05
40μs
POWER-GOOD
OUTPUT
PHASE 1
INDUCTOR
CURRENT
10A/div
OUTPUT
VOLTAGE
200mV/div
SOFT-START WAVEFORMS
AT 1.45V OUTPUT
MAX8524 toc06
1ms
ENABLE
INPUT
INPUT
CURRENT
0.5A/div
POWER-
GOOD
OUTPUT
OUTPUT
VOLTAGE
0.5V/div
SOFT-STOP WAVEFORMS
AT 1.45V OUTPUT
MAX8524 toc07
400μs
ENABLE
INPUT
INPUT
CURRENT
0.5A/div
POWER-
GOOD
OUTPUT
0A
OUTPUT
VOLTAGE
0.5V/div
IOUT = 0A
Typical Operating Characteristics
(VIN = 12V, VOUT = 1.2V, IOUT_MAX = 80A, fSW = 250kHz, TA= +25°C, unless otherwise noted.)
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN = 12V, VOUT = 1.2V, IOUT_MAX = 80A, fSW = 250kHz, TA= +25°C, unless otherwise noted.)
CURRENT-SENSE THRESHOLD vs. VILIM
MAX8524 toc10
OUTPUT CURRENT (A)
VILIM (V)
908070605040302010
0.200
0.400
0.600
0.800
1.000
1.200
1.400
0
0 100
REFERENCE VOLTAGE
vs. TEMPERATURE
MAX8524 toc11
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
100806040200-20
1.995
2.000
2.005
2.010
1.990
-40 120
REFERENCE VOLTAGE LOAD REGULATION
MAX8524 toc12
REFERENCE LOAD CURRENT (μA)
REFERENCE VOLTAGE (V)
100 200 300 400
2.001
2.002
2.000
0 500
CLOCK FREQUENCY vs. ROSC
MAX8524 toc13
ROSC RESISTOR (kΩ)
CLOCK FREQUENCY (kHz)
100
700
1000
1300
1600
1900
2200
2500
2800
3100
3400
3700
4000
4300
4600
4900
400
10 1000
CLOCK FREQUENCY vs. TEMPERATURE
MAX8524 toc14
TEMPERATURE (°C)
FREQUENCY (MHz)
100806040200-20
1
2
3
4
5
0
-40 120
ROSC = 43.2kΩ
ROSC = 105kΩ
ROSC = 294kΩ
CLKO RISE AND FALL TIME
vs. TEMPERATURE
MAX8524 toc15
TEMPERATURE (°C)
RISE (ns)
12010060 8002040-20
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
-40
FALL
RISE
SHORT-CIRCUIT AND
RECOVERY WAVEFORMS
MAX8524 toc09
1ms
POWER-
GOOD
OUTPUT
PHASE 1
INDUCTOR
CURRENT
10A/div
OUTPUT
VOLTAGE
0.5V/div
8-PHASE ACTIVE CURRENT SHARING
MAX8524 toc17
LOAD CURRENT (A)
INDUCTOR CURRENT (A)
150
126
101775226
5
10
15
20
25
0
0.193
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
_______________________________________________________________________________________ 9
8-PHASE OPERATION:
DYNAMIC VID RESPONSE
MAX8524 toc18
40μs
POWER-
GOOD
OUTPUT
PHASE 1
INDUCTOR
CURRENT
10A/div
OUTPUT
VOLTAGE
200mV/div
Typical Operating Characteristics (continued)
(VIN = 12V, VOUT = 1.2V, IOUT_MAX = 80A, fSW = 250kHz, TA= +25°C, unless otherwise noted.)
Pin Description
PIN
MAX8524 MAX8525
NAME FUNCTION
1 1 PWM3 PWM Signal Output for Phase 3. Logic low during shutdown.
2 2 PWM1 PWM Signal Output for Phase 1. Logic low during shutdown
3 3 CS1+ Positive Input of the Output Current Sense of Phase 1. Connect to the inductor side of the
output current-sense resistor.
4 4 CS1_3- Common Negative Input of the Output Current Sense of Phases 1 and 3. Connect to the load
side of the output current-sense resistors.
5 5 CS3+ Positive Input of the Output Current Sense of Phase 3. Connect to the inductor side of the
output current-sense resistor.
66V
CC IC Supply Input. Bypass to GND with a ceramic capacitor of at least 1µF.
7 7 GND IC Ground. Single connection to system ground.
8 8 COMP
Error-Amplifier Output. Connect to a tap in a resistor-divider from REF to GND to set the finite
DC gain for active voltage positioning. Add a series RC network from COMP to GND to
compensate the control loop. For 6- or 8-phase operation, connect COMP pins of two
controllers together for active current sharing.
9 9 REF 2.0V ±0.4% Reference Output. Bypass REF to GND with a ≤2.2µF low-ESR capacitor. REF
can source 0.5mA for external loads. REF is alive when EN is low if VCC is above UVLO.
10 10 ILIM
Output Current-Limit Set. Connect to a tap of a resistor-divider from REF to GND to set the
cycle-by-cycle average current-limit threshold. Current limit (per phase) = VILIM / (50 x
RSENSE). Connect to VCC to set the default 20mV current-limit threshold.
11 11 OSC
Internal Clock Oscillator Frequency-Set Input. Connect a resistor from OSC to GND to set the
switching frequency. OSC must be connected to an external resistor even if the IC is used in
slave mode. This pin is operational in shutdown if VCC is above UVLO.
12 12
PWRGD
Open-Drain Power-Good Indicator. PWRGD pulls low until the output voltage is in regulation.
PWRGD is low in shutdown and during UVLO.
INTERLEAVED 8-PHASE OPERATION:
LX WAVEFORMS
MAX8524 toc16
1μs
MASTER PH1
MASTER PH2
MASTER PH3
MASTER PH4
SLAVE PH1
SLAVE PH2
SLAVE PH3
SLAVE PH4
MAX8524/MAX8525
Detailed Description
The MAX8524/MAX8525 are synchronous, scalable 2-/
3-/4-phase, current-mode, step-down controllers. The
MAX8524/MAX8525 can be used to implement either
an embedded VRD design or a voltage regulator mod-
ule (VRM) design with external MOSFET driver, such as
the MAX8523.
The switching frequency of each phase can be set from
150kHz to 1.2MHz, permitting control bandwidth of up
to 200kHz. The 5MHz gain-bandwidth product of the
voltage-error amplifier ensures sufficient loop gain for
most applications. In VRM applications, current bal-
ance between modules is within 5% at full load, maxi-
mizing the benefits of multiphase operation. Lossless
inductor current sensing with temperature compensa-
tion can be used to reduce power dissipation while
maintaining droop accuracy.
The MAX8524/MAX8525 controllers can be configured
for 3-phase or 2-phase VRD or VRM applications by
connecting one or two PWM pin(s) to the logic-supply
pin (VCC). In these modes, internal phasing is automati-
cally adjusted for optimal ripple cancellation. The CLKI
(clock in) and CLKO (clock out) features provided by
the MAX8524/MAX8525 permit true 6- or 8-phase inter-
leaved operation when two MAX8524/MAX8525 con-
10 ______________________________________________________________________________________
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
Pin Description (continued)
PIN
MAX8524
MAX8525
NAME FUNCTION
13 13 CLKO
Clock Synchronization Output for Master-Mode Operation. Connect CLKO of the master
controller to CLKI of the slave controller. CLKO is active when EN is low, if VCC is above
UVLO to permit synchronized slave startup. CLKO is connected to the internal oscillator in
both master and slave mode.
14 14 CLKI
Clock Synchronization Input. Connect CLKI to CLKO of the master controller for interleaved
dual controller systems or to an external synchronization clock. Internal 100kΩ pulldown to
GND permits floating this pin. See the Paralleling Operation (CLKI and CLKO) section for
detailed clocking operation.
15–19 16–20
VID0–VID4
DAC Code Input. The MAX8524 has a 15kΩ internal pullup resistor to VCC. The MAX8525
requires an external pullup resistor.
— 15 VID5 DAC Code Input. The MAX8525 requires an external pullup resistor. Connect to VCC for the
MAX8524.
20 — N.C. No Connection
21 21 EN
Enable Input, Active High. Pulls up to VCC through an internal 100kΩ resistor when UVLO is
satisfied. Pull low with an external open-drain or open-collector input to shut down the
controller. For master/slave operation, the EN pins of the MAX8524/MAX8525 controllers
should be connected together.
22 22 RS- Output-Voltage Remote-Sense, Negative Input. Connect to GND directly at the load.
23 23 RS+ Output-Voltage Remote-Sense, Positive Input. Connect to VOUT+ directly at the load.
24 24 CS2+ Positive Input of the Output Current Sense of Phase 2. Connect to the inductor side of the
output current-sense resistor. Short CS4+ to CS2_4- for 2-phase operation.
25 25 CS2_4- Common Negative Input of the Output Current Sense of Phases 2 and 4. Connect to the load
side of the output current-sense resistors.
26 26 CS4+ Positive Input of the Output Current Sense of Phase 4. Connect to the inductor side of the
output current-sense resistor. Short CS4+ to CS2_4- for 2-, 3-, or 6-phase operation.
27 27 PWM4 PWM Signal Output for Phase 4. Connect this pin to VCC for 2-, 3-, or 6-phase operation.
Logic low during shutdown.
28 28 PWM2 PWM Signal Output for Phase 2. Connect this pin to VCC for 2-phase operation. Logic low
during shutdown.
trollers are utilized, further reducing input and output rip-
ple current. In 4-phase operation, the effective switching
frequency is 0.6MHz to 4.8MHz. For 8-phase operation,
the effective switching frequency is 1.2MHz to 9.6MHz.
The MAX8525 includes a 6-bit DAC (Intel VRM 10.0
compliant) and the MAX8524 includes a 5-bit DAC
(Intel VRM 9.1 compliant), both able to achieve ±0.4%
initial voltage accuracy. The power-good signal is
accurate during VID code changes for the MAX8525 to
avoid any fault signal due to the output voltage change
requested by the CPU.
The MAX8524/MAX8525 also include programmable
no-load offset and output-voltage positioning to adjust
the output voltage as a function of the output current.
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
______________________________________________________________________________________ 11
VID5 VID4 VID3 VID2 VID1 VID0
VOUT
011010 1.2125
111001 1.2250
011001 1.2375
111000 1.2500
011000 1.2625
110111 1.2750
010111 1.2875
110110 1.3000
010110 1.3125
110101 1.3250
010101 1.3375
110100 1.3500
010100 1.3625
110011 1.3750
010011 1.3875
110010 1.4000
010010 1.4125
110001 1.4250
010001 1.4375
110000 1.4500
010000 1.4625
101111 1.4750
001111 1.4875
101110 1.5000
001110 1.5125
101101 1.5250
001101 1.5375
101100 1.5500
001100 1.5625
101011 1.5750
001011 1.5875
101010 1.5875
VID5 VID4 VID3 VID2 VID1 VID0 VOUT
001010 0.8375
101001 0.8500
001001 0.8625
101000 0.8750
001000 0.8875
100111 0.9000
000111 0.9125
100110 0.9250
000110 0.9375
100101 0.9500
000101 0.9625
100100 0.9750
000100 0.9875
100011 1.0000
000011 1.0125
100010 1.0250
000010 1.0375
100001 1.0500
000001 1.0625
100000 1.0750
000000 1.0875
111111 OFF
011111 OFF
111110 1.1000
011110 1.1125
111101 1.1250
011101 1.1375
111100 1.1500
011100 1.1625
111011 1.1750
011011 1.1875
111010 1.2000
Table 1. VID Programmed Output Voltage (VRM 10.0)
MAX8524/MAX8525
Clock Frequency (OSC)
The clock frequency of the MAX8524/MAX8525 is set
by an external resistor from OSC to ground. After
selecting the switching frequency per phase, fSW, and
the number of phases, using Table 3, select the clock
frequency. For 6- or 8-phase operation, connect an
external resistor to OSC of both master and slave con-
trollers even if the MAX8524/MAX8525 is operated in
slave mode. A 1% resistor is recommended for the
ROSC to maintain good frequency accuracy, and ROSC
should be placed as close as possible to the OSC pin.
Voltage Reference (REF)
A precision 2V reference is provided by the
MAX8524/MAX8525 at the REF pin. REF is capable of
sourcing up to 500µA for external loads. REF stays
alive when EN is low and while VCC is above UVLO.
Connect a 0.22µF ceramic capacitor from REF to GND.
The capacitor should be placed as close to the REF pin
as possible.
An internal REFOK monitors the reference voltage. The
reference voltage must be above the REFOK threshold
of 1.85V to activate the controller. The controller is dis-
abled if the reference voltage falls below 1.81V.
Output Current Sensing (CS_+, CS_-)
The output current of each phase is sensed differential-
ly with a shared common return for each phase pair. A
low offset voltage and high-gain (50V/V) differential cur-
rent amplifier at each phase allow low-resistance cur-
rent-sense resistors to be used to minimize power
dissipation. Sensing the current at the output of each
phase offers advantages, including less noise sensitivi-
ty, more accurate current sharing between phases, and
the flexibility of using either a current-sense resistor or
the DC resistance of the output inductor.
Using the DC resistance, RDC, of the output inductor
allows higher efficiency. In this configuration, the initial
tolerance and temperature coefficient of RDC must be
accounted for in the output-voltage droop-error budget.
An RC filtering network is needed to extract the current
information from the output inductor, as shown in Figure
1. The time constant of the RC network is governed by
equation 1:
RC L
REq
DC
= ( )1
12 ______________________________________________________________________________________
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
VID4
VID3
VID2
VID1
VID0
VOUT
00000 1.850
00001 1.825
00010 1.800
00011 1.775
00100 1.750
00101 1.725
00110 1.700
00111 1.675
01000 1.650
01001 1.625
01010 1.600
01011 1.575
01100 1.550
01101 1.525
01110 1.500
01111 1.475
10000 1.450
10001 1.425
10010 1.400
10011 1.375
10100 1.350
10101 1.325
10110 1.300
10111 1.275
11000 1.250
11001 1.225
11010 1.200
11011 1.175
11100 1.150
11101 1.125
11110 1.100
11111Shutdown
Table 2. VID Programmed Output
Voltage (VRM 9.1)
NO. OF PHASES
PIN CONNECTIONS fCLKO
2 PWM2 = PWM4 = VCC 4 x fSW
3 PWM4 = VCC 3 x fSW
4 — 4 x fSW
6 PWM4 = VCC 3 x fSW
8 — 4 x fSW
Table 3. Clock Frequency Setting vs.
Switching Frequency and Number of
Phases
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
where L is the inductance of the output inductor. For
20A or higher current-per-phase applications, the DC
resistance of commercially available inductors is about
1mΩ, as shown in Table 4. To minimize current-sense
error due to the bias current at current-sense pins,
choose R less than 2kΩ(Figure 1). Determine the value
for C from equation 1. Choose the capacitor with 5%
tolerance and the resistor with 1% tolerance.
Temperature compensation is recommended for this
current-sense scheme. See the Loop Compensation
and Output-Voltage Positioning section for detailed
information.
When a current-sense resistor is used for more accu-
rate output-voltage positioning, similar RC filtering cir-
cuits should be used to cancel the equivalent series
inductance of the current-sense resistor, as shown in
Figure 2. Using criteria similar to that stated in the pre-
vious paragraph, the value of C can be determined by
equation 2:
where ESL is the equivalent series inductance of the
current-sense resistor, RSis the value of the current-
sense resistor, and C is the value of the compensation
capacitor. For example, a 1mΩ2025-package sense
resistor has an ESL of 1.6nH.
Output Current-Limit and Short-Circuit
Protection (ILIM)
The MAX8524/MAX8525 provide a cycle-by-cycle cur-
rent limit to control the average output current as pro-
grammed by the user at the ILIM pin. This approach is
insensitive to input-voltage variation and inductor toler-
ance. Once the current-limit threshold is exceeded, the
duty cycle is terminated immediately and the output
inductor current starts to ramp down. At the next
switching cycle, the PWM pulse is skipped if the output
inductor current is still above the current-limit threshold.
The current-limit threshold is adjustable over a wide
range by connecting a resistor-divider from the REF pin
to GND with the center tap connected to ILIM.
Connecting ILIM to VCC sets the default current thresh-
old to 20mV at the current-sense resistor.
The MAX8524/MAX8525 offer current foldback protec-
tion under soft-start and overload conditions. This fea-
ture allows the VRM to safely operate under
short-circuit conditions and to automatically recover
once the short-circuit condition is removed. Once the
output voltage falls below the low PWRGD threshold,
the foldback current threshold is set to half the current-
limit threshold.
Output Voltage Differential Sensing
(RS+, RS-)
The MAX8524/MAX8525 feature differential output-volt-
age sensing to achieve the highest possible output
accuracy. This allows the controllers to sense the actu-
al voltage at the load, so the controller can compensate
for losses in the power output and ground lines.
CESL
RR Eq
S
=× ( )2
MAX8524/MAX8525
______________________________________________________________________________________ 13
LRDC IOUT
VRDC = RDC x IOUT
R
RDC IS THE INDUCTOR DC RESISTANCE.
C
CS_+ CS_-
Figure 1. Inductor RDC Current Sense
ESL RSIOUT
VRS = RS x IOUT
RC
CS_+ CS_-
ESL IS THE PARASITIC INDUCTANCE OF PRECISION
CURRENT-SENSE RESISTOR.
Figure 2. Current-Sense Resistor
MANUFACTURER AND
PART NO.
BI Technologies
HM73-40R50
0.5µH/50A
Panasonic
ETQP1H0R6BFA
0.6µH/30A
Sumida
CDEP149(H)
0.45µH/32A
Coiltronics
HC2-0R68
0.68µH/50A
RDC (mΩ)0.78 (typ)
1.0 (max) 0.9 (max) 0.9 (typ)
1.1 (max) 0.6 (max)
Table 4. Output Inductor List
MAX8524/MAX8525
Traces from the load point back to RS+ and RS- should
be routed close to each other and as far away as possi-
ble from noise sources (such as inductors and high
di/dt traces). Use a ground plane to shield the remote-
sense traces from noise sources. To filter out common-
mode noise, RC filtering is recommended for these pins
as shown in Figure 3. For VRD applications, a 100Ω
resistor with a 470pF capacitor should be used. For
VRM applications, additional 50Ωresistors should be
connected from these pins to the local outputs of the
converter before the VRM connector. This avoids
excessive voltage at the CPU in case the remote-sense
connections get disconnected.
Loop Compensation (COMP)
During a load transient, the output voltage instantly
changes due to the ESR of the output capacitors by an
amount equal to their ESR times the change in load
current (ΔVOUT = -RESR_CO x ΔILOAD). The voltage-
positioning method allows better utilization of the output
regulation window, resulting in fewer output capacitors.
The MAX8524/MAX8525 employ rapid-active average
scheme, a proprietary current-mode architecture that
adjusts the output current based on instantaneous out-
put voltage, resulting in fast voltage positioning.
The voltage-error amplifier consists of a high bandwidth
and high-accuracy transconductance amplifier (GMV).
See the Functional Diagram. The negative input of the
transconductance amplifier is connected to the output
of the remote-voltage differential amplifier, and the pos-
itive input is connected to the output of an internal DAC
controlled by VID inputs. The DC gain of the transcon-
ductance amplifier is set to a finite value to achieve fast
output-voltage positioning by connecting an equivalent
resistor, RE, from the COMP pin to GND (RE= RU//RB).
The value of REis determined by the amount of droop
required at full load, which is specified as the output
impedance or the load line in Intel VRM specifications.
According to the Intel VRM specifications, the output
voltage at no load cannot exceed the voltage specified
by the VID code, including the initial set tolerance, rip-
ple voltage, and other errors. Therefore, the actual out-
put voltage should be biased lower to compensate for
these errors. Connect a resistor-divider, RUand RB,
from REF to GND, with the tap connected to COMP, to
set the offset voltage.
For 6- or 8-phase operations, connect COMP pins of
the two controllers together for active current sharing.
Dynamic VID Change (MAX8525 Only)
The MAX8525 offers the ability to dynamically change
the VID inputs while the controller is operating (on-the-
fly, or OTF). This feature allows the processor to adjust
its core voltage in a 250mV window. The MAX8525 out-
put voltage changes in 12.5mV steps when a VID
change is detected.
The VID inputs of the MAX8525 comply with Intel’s 400ns
logic-skew timing specifications to prevent false code
changes. Once the timer expires, the controller starts to
change the DAC output. Figure 4 shows the output volt-
age step during a VID OTF event. The MAX8525 con-
troller accepts both step-by-step changes of VID inputs
or all-at-once VID inputs changes. For all-at-once VID
input changes, the output-voltage slew rate is the same
as 12.5mV per step and 2µs duration.
Paralleling Operation (CLKI and CLKO)
Two MAX8524/MAX8525s can be connected together
to generate 6-phase or 8-phase core supplies. In this
configuration, one MAX8524/MAX8525 serves as a
master and the other serves as a slave. Connect the
CLKI pin of the slave controller to the CLKO pin of the
master controller. Interleaved operation is achieved by
synchronizing the master controller to the CLKO rising
edge and the slave controller to the CLKO falling edge.
Figure 5 shows the clock timing between the phases of
both master and slave controllers.
2-Phase and 3-Phase Operation Selection
(PWM3 and PWM4)
The MAX8524/MAX8525 can operate in 2-, 3-, and
4-phase operation. Connect PWM4 to VCC for 2-, 3-, or
6-phase operation. Also connect PWM2 to VCC for
2-phase operation. All PWM outputs are held low dur-
ing shutdown.
14 ______________________________________________________________________________________
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
MAX8524/
MAX8525
R3
100Ω
R1
50Ω
R4
100Ω
R2
50ΩC1
470pF
C1
470pF
TO POWER GROUND OF VRM
TO POSITIVE OUTPUT OF VRM
TO REMOTE-SENSE LOCATION
RS+
RS-
Figure 3. Recommended Filtering for Output-Voltage Remote
Sensing
Power-Good Output (PWRGD)
PWRGD is an open-drain output that is pulled low when
the output voltage rises above the PWRGD upper
threshold or falls below the PWRGD falling threshold.
PWRGD is held low in shutdown, VCC < UVLO, and
during soft-start conditions. For logic-level output volt-
ages, connect an external pullup resistor between
PWRGD and the logic power supply. A 100kΩresistor
works well in most applications.
UVLO, Output Enable (EN), and Soft-Start
When the IC supply voltage (VCC) is less than the
UVLO threshold, all PWM outputs are held low and
most internal circuitry is shut down to reduce the quies-
cent current. When EN is released and VCC > UVLO,
the internal 100kΩresistor pulls EN to VCC and soft-
start is initiated. During soft-start, the output of the inter-
nal DAC ramps up at 12.5mV per step. For 6- or
8-phase operation, connect EN of two MAX8524/
MAX8525s together and drive it by an open-drain sig-
nal, as shown in Figure 6.
Output Overvoltage Protection (OVP)
When the output voltage exceeds the regulation volt-
age by 225mV for the MAX8524 or 200mV for the
MAX8525, all PWM outputs are pulled low and the con-
troller is latched off. To discharge the output voltage,
the MOSFET drivers must keep the low-side MOSFETs
on and high-side MOSFETs off. The MAX8523 dual-
phase and the MAX8552 single-phase MOSFET drivers
fulfill this requirement. The latch condition can only be
cleared by cycling the input voltage (VCC).
Thermal Protection
The MAX8524/MAX8525 feature a thermal-fault-protec-
tion circuit. When the junction temperature rises above
+150°C, an internal thermal sensor activates the shut-
down circuit to hold all PWM outputs low to disable
switching. The thermal sensor reactivates the controller
after the junction temperature cools by 15°C.
Design Procedure
Setting the Switching Frequency
The switching frequency determines the switching loss
and the size of the power components. Higher switch-
ing frequency results in smaller external components
and more compact design. However, switching loss
and magnetic core loss are directly proportional to the
switching frequency. Select a switching frequency as a
tradeoff of the efficiency and size. The clock frequency
can be selected from Table 3.
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
______________________________________________________________________________________ 15
MAX8524 fig04
40μs
POWER-GOOD
OUTPUT
INDUCTOR
CURRENT
OF PH1
OUTPUT VOLTAGE
0.2V/div
Figure 4. Output-Voltage Waveform During VID On-the-Fly
Change with Load Transients
CLKOUT
PHASE 1
PHASE 2
PHASE 3
PHASE 4
PHASE 1
PHASE 2
PHASE 3
PHASE 4
CLKIN
EIGHT-PHASE OPERATION
MASTER IC PHASE CLOCK
SLAVE IC PHASE CLOCK
Figure 5. Clock Relationships Between the Master and Slave
Controllers
MAX8524/MAX8525
See the Clock Frequency vs. ROSC graph in the Typical
Operating Characteristics section for the relationship
between the clock frequency and the value of the fre-
quency-setting resistor, ROSC. The value of ROSC for a
given clock frequency can also be approximated from
equation 3:
Output Inductor Selection
Output inductance is set by the desired amount of
inductor current ripple (LIR) and the slew rate of the
inductor current during a load transient. A larger induc-
tance value minimizes output ripple current and increas-
es efficiency but slows down the current slew rate. For
the best tradeoff of size, cost, and efficiency, an LIR of
30% to 60% is recommended (LIR = 0.3 to 0.6). Choose
LIR close to the high end when more phases are used.
The inductor value is determined from:
where fSW is the switching frequency, IOUT_MAX is the
maximum-rated output current, D is the duty ratio, and
VOUT is the output voltage at a given VID code. Check
the output-inductance ripple current for the ripple volt-
age it produces across the output capacitor ESR. For
an n-phase VRM converter, the output ripple voltage,
VRIPPLE, can be calculated using:
For ripple voltage estimate, it is safe to replace
RESR_CO with RO, the VRM output impedance. If the
output ripple voltage is not satisfied, a larger value of
output inductance should be chosen. The selected
inductor should have the lowest possible DC resistance
and the saturation current should be greater than the
peak inductor current, IPEAK. IPEAK is found from:
When the DC resistance of the output inductor is used
for current sensing, the range of DC resistances is limit-
ed by the following constraints:
II LIR
NEq
PEAK OUT MAX
=+
×
()
( )
_
2
26
VVR ND
fL Eq
RIPPLE OUT ESR CO
SW
=×××
()
×
()
− ( )
_
15
LVDN
LIR f I HEq
OUT
SW OUT MAX
≥××
××
− ( )
( )
_
14
Rf Eq
OSC OSC MHz
=× . (
()
277 704 3
1- .197 k )Ω
16 ______________________________________________________________________________________
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
MAX8524/
MAX8525
MAX8524/
MAX8525
MASTER SLAVE
CLKO CLKI
COMP COMP
REF REF
RS+
RS-
RS+
RS-
REMOTE-SENSE
INPUT
VID0
VID5
VID4
VID3
VID2
VID1
VID0
VID5
VID4
VID3
VID2
VID1
EN EN
EN
INPUT
VID0 INPUT
VID1 INPUT
VID2 INPUT
VID3 INPUT
VID4 INPUT
VID5 INPUT
Figure 6. Master and Slave Controller Connections
and
Output Capacitor Selection
In most cases, selection of the output capacitor is dic-
tated by the ESR requirement to meet the core-supply
transient responses. The target equivalent series resis-
tance is RESR_CO = RO. The minimum output capaci-
tance, CO(min), based on the energy balance, is then
calculated from:
There is also an upper limit on the amount of output
capacitance to meet the OTF VID change requirement.
Too much output capacitance may prevent the output
voltage from reaching the new VID output voltage with-
in the OTF time window:
where tOTF is the time window to reach VOTF, the OTF
voltage steps. If CO(max) is less than CO(min), the sys-
tem does not meet the VID OTF specification.
Combinations of different types of capacitors, such as
SPCAPs, POSCAPs, or low-ESR aluminum electrolytic
capacitors may be needed to achieve the required
RESR_CO and the output capacitance simultaneously. If
the combination cannot be reached, the output induc-
tance must be adjusted.
Input Capacitor Selection
The input capacitor reduces the peak current drawn
from the power source and reduces the noise and volt-
age ripple on the input caused by the circuit’s switch-
ing. The input capacitors must meet the ripple current
requirement, IRMS, imposed by the switching currents
as defined by equation 11:
Use the minimum input voltage to calculate the input
ripple current. Low-ESR capacitors, such as low-ESR
aluminum electrolytic capacitors, polymer capacitors,
and ceramic capacitors, should be used to avoid large
voltage transients at the input during a large step load
change at the output. The capacitors’ ripple-current
specifications provided by the manufacturer should be
carefully reviewed. Additional small-value low-ESL
ceramic capacitors (1µF to 10µF/16V) can be used in
parallel to reduce the high-frequency ringing.
Power MOSFET Selection
MOSFET power dissipation depends on the gate-drive
voltage (VG), the on-resistance (RDSON), the total gate
charge (QGT), and the gate threshold voltage (VTH).
The supply voltage range for MOSFET drivers
(MAX8523) is from 4.5V to 6.5V. With VGATE < 10V,
logic-level threshold MOSFETs are recommended.
Power dissipation in the high-side MOSFET consists of
two parts: the conduction loss and the switching loss.
The conduction loss for each high-side switch can be
calculated from equation 12:
where MHS is the number of MOSFETs in parallel for each
high-side switch. Total high-side conduction loss equals
the number of phases times PCOND_HS. Switching loss is
the major contributor to the high-side MOSFET power
dissipation due to the hard switching transition every
time it turns on. The switching loss can be found from
the following:
where VDis the gate-drive voltage and RGis the total
gate resistance including the driver’s on-resistance
from the MAX8523 (0.8Ω) and the MOSFET’s gate
resistance. QMILLER is the MOSFET’s Miller charge,
which can be found in the MOSFET’s data sheet. For a
logic-level power MOSFET, the gate resistance is about
2Ω. Note that adding more MOSFETs in parallel at the
high-side switch increases the switching loss. Smaller
gate charge and lower gate resistance usually result in
lower switching loss.
The low-side MOSFET power dissipation is mostly
attributed to the conduction loss. Switching loss is neg-
ligible due to the zero voltage switching at turn-on and
body diode clamp at turn-off. Power dissipation in the
PVI
N
RQ
VV
fM Eq
SW HS IN OUT MAX GATE MILLER
DTH
SW HS
__
( )
=×× ××
−
××
2
13
PD
I
N
LIR
R
MEq
COND HS OUT MAX
DSON HS
HS
__
_
( )
=× ×+
⎛
⎝
⎜⎞
⎠
⎟
×
22
2
2
112
12
IDI ND Eq
RMS OUT MAX
=× × ×
( )
_
1111 -
CII t
VEq
OLIM OUT MAX OTF
OTF
(max)
() ( )
_
≤× - 2
10
CLI
NR V Eq
OOUT MAX
O OUT
(min)
( )
_
≥× ×
××
1
29
RN
I LIR Eq
DC OUT MAX
≥××+
()
50 2 8
( )
_
RN
I LIR Eq
DC OUT MAX
≤×
××+
()
5
50 2 7
( )
_
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
______________________________________________________________________________________ 17
MAX8524/MAX8525
low-side MOSFETs of each phase can be calculated
from the following equation:
where RDSON_LS is the on-resistance of the low-side
MOSFET and MLS is the number of MOSFETs in parallel
for the low-side switch. Total power dissipation for the
low-side switches equals the number of phases times
the low-side conduction loss of each phase. Even
though the switching loss is insignificant in the low-side
MOSFETs, RDSON is not the only parameter that should
be considered in selecting the low-side MOSFET. Large
Miller capacitance (CRSS) could turn on the low-side
MOSFETs momentarily when the drain-to-source volt-
age goes high at fast slewing rates if the driver cannot
hold the gate low. The ratio of CRSS/CISS should be
less than 1/10th for the low-side MOSFETs to avoid
shoot-through current due to momentary turn on of the
low-side switch.
The gate-driver power dissipation is also important. The
MAX8523 is a 0.8Ω/0.6Ωdual-channel driver, whereas
the MAX8552 is a 0.8Ω/0.6Ωsingle-channel driver.
Power dissipation in each driver is given by:
where ICC is the supply current of the MAX8523.
Ensure the power loss does not exceed the package
power dissipation.
Loop Compensation and
Output-Voltage Positioning
Once the current-sense resistance (RSENSE), the output
impedance (RO), and the output offset voltage (VOS)
are known, the values of RUand RBare calculated from
equations 16 and 17:
where GMis the transconductance (2mS). A capacitor,
CC, must be connected from COMP to ground to roll off
the gain at high frequency. The capacitor value can be
found from the following equation once the output
capacitor’s ESR zero frequency is known to obtain first-
order rolloff at zero across frequency:
where RESR_CO is the total equivalent series resistance
and COis the total capacitance of the output capaci-
tors, respectively. REis the parallel equivalent resis-
tance of RUand RB.
Setting the Current Limit
Current-limit threshold sets the maximum available out-
put DC current. To meet the OTF operation, the output
current limit, ILIM, should be set at least 15% higher
than the maximum rated output current, IOUT_MAX. The
voltage at ILIM and the value of the current-sense resis-
tor or the DC resistance of the output inductors set the
current-limit threshold:
for the resistor current sensing and:
for DC resistance of the output inductor current sensing.
In equation 20, the value of RDC at the high ambient
temperature must be used to guarantee the rated output
current. VILIM can be set by connecting ILIM to a resis-
tor-divider from REF to GND. Select resistors R26 and
R27 from the schematics in Figure 7 so the current
through the divider is at least 10µA:
A typical value for R27 is 100kΩ; then solve for R26
using:
RR V
VEq
ILIM
ILIM
26 27 222=× ( )
-
RR k Eq26 27 200 21+≤ ( )Ω
VR
I
NEq
ILIM DC LIM
( )=× ×50 20
VR
I
NEq
ILIM SENSE LIM
=× × ( )50 19
CRC
REq
CESR CO O
E
=×
_ ( )18
RGNR
RV
Eq
RGNR
RV
Eq
U
MO
SENSE OS
B
MO
SENSE OS
=
×
⎡
⎣
⎢⎤
⎦
⎥
=
×+
⎡
⎣
⎢⎤
⎦
⎥×
( )
( )
1
250
16
1
250
1
20 10
17
6
-
-
PVI
Vf M Q M Q
Eq
DRIVER D CC
D SW LS G LS HS G HS
( )
( )
_ _
=×
()
+
×× × × ×
()
+
2
15
PD
I
N
LIR
R
MEq
COND LS OUT MAX
DSON LS
LS
__
_
()
( )
=× ×+
⎛
⎝
⎜⎞
⎠
⎟
×
11
12
14
22
2
2
-
18 ______________________________________________________________________________________
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
______________________________________________________________________________________ 19
Applications Information
PC Board Layout Guidelines
A properly designed PC board layout is important in
any switching DC-DC converter circuit. If possible,
mount the MOSFETs, inductors, input/output capaci-
tors, and current-sense resistor on the top side of the
PC board. Connect the ground for these devices close
together on a power ground plane. Make all other
ground connections to a separate analog ground plane.
Connect the analog ground plane to power ground at a
single point.
To help dissipate heat, place high-power components
(MOSFETs and inductors) on a large PC board area, or
use a heat sink. Keep high-current traces short, wide,
and tightly coupled to reduce trace inductances and
resistances. Also, make the gate-drive connections (DH_
and DL_) short, wide, and tightly coupled to reduce EMI
and ringing induced by high-frequency gate currents.
Use Kelvin-sense connections for the current-sense
resistors. All signal traces of the current sense and the
remote-voltage sense should be tightly coupled and as
far away as possible from the inductors and other
switching noise sources. Use the ground plane to
shield the current-sense traces and the feedback from
noise sources.
Place the REF capacitor, the VCC capacitor, the current-
sense decoupling capacitors, and the remote-sense
decoupling capacitors as close to the MAX8524/
MAX8525 as possible.
For an example PC board layout, refer to the MAX8525
evaluation kit.
Chip Information
TRANSISTOR COUNT: 9021
PROCESS: BiCMOS
Pin Configurations (continued)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PWM2
PWM4
CS4+
CS2_4-
CS2+
RS+
VID0
RS-
EN
N.C.
VID4
VID3
VID2
VID1
CLKI
CLKO
PWRGD
OSC
ILIM
REF
COMP
GND
VCC
CS3+
CS1_3-
CS1+
PWM1
PWM3
QSOP
TOP VIEW
MAX8524
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
20 ______________________________________________________________________________________
VDD = 6.5V
VID4
PWM1
PWM3
RS+
PWM2
PWM4
KA317MR
U4
REF
EN
ILIM
COMP
AGND
PWRGD
VID0
VID1
VID2
VID3
D3
RS-
CLKI
CLKO
DLY
LX1
DH1
BST1
PV1
PWM2
INPUT
10V TO 13.2V
C18
0.1μFR15
OPEN
VCC
R12
10Ω
PWM1
VID5
VCC
DL1
PG1
PG2
BST2
DH2
LX2
DL2
C1
10μF
25V
C3
10μF
25V
C2
10μF
25V
C4
10μF
25V
L1
0.6μH
L2
0.6μH
N1
N3
D1
C13
0.22μF
R8
3.3Ω
C14
0.22μF
R9
3.3Ω
LX1
DH1
BST1
PWM2
PWM1
DL1
PG1
PG2
BST2
DH2
LX2
DL2
D2
C15
0.22μF
R10
3.3Ω
C16
0.22μF
R11
3.3Ω
CS2+
CS1_3-
CS1+
CS3+
CS2_4-
CS4+ CS4+
CS2+
CS2_4-
CS3+
CS1+
CS1_3-
OSC
CS1+
CS3+
CS1_3-
OUTPUT
0.8375V TO 1.6V,
80A
L1–L4: PANASONIC,
N1, N4, N7, N10, N13–N16: IRF7811W
N2, N3, N5, N6, N8, N9, N11, N12: IRF7822
NOTE: C30-C45 SELECTED FOR VRM 10 TRANSIENT RESPONSE SPECIFICATIONS AT 1.2V OR HIGHER OUTPUT.
C26
470pF
C24
0.22μF
C23
680pF
C22
1μF
10V
C21
2.2μF
16V
C20
2.2μF
C19
2.2μF
REF
R23
200kΩ
R18
50Ω
R20
100Ω
R19
50Ω
R21
100Ω
R22
348Ω
R28
6.81kΩ
R16
100kΩ
R13
10Ω
5%
R27
100kΩ
R26
28.3kΩ
R18
OPEN
J1–53
OUTEN
VOUT
J1–52
V0_SEN+
C30–C39
390μF/2V
SPCAPS
J1–11
V0_SEN-
7
21
12
8
9
R29
6.81kΩ
J1–10
VCC-PWRGD
PV2
N2
N13
N4
N6
N5
N14
C5
10μF
25V
C7
10μF
25V
C6
10μF
25V
C8
10μF
25V
L3
0.6μHRS1
1mΩ
RS2
1mΩ
R3
24Ω
R4
24Ω
C11
33nF
C12
33nF
N7
L4
0.6μH
CS2+
CS4+
N10
N12
N11
N16
DLY
PV1
C17
0.1μFR17
OPEN
VCC
R14
10Ω
PV2
C25
470pF
C27
470pF
VIN+
VIN+
VIN+
CS2_4-
VDD = 6.5V
C28
3.3nF
C29
3.3nF
R5
402Ω
R6
1.3kΩ
J1–54
J1–6
J1–7
J1–56
J1–8
J1–55
J1–1
J1–2
J1–3
VO+
VO-
C40–C45
470μF/6V
SPCAPS
6
10
2
1
15
20
19
18
17
16
14
13
26
24
25
5
3
4
28
27
23
22
11
4
13
7
8
9
10
12
14
15
16
6
11
3
5
2
1
4
13
7
8
9
10 12
14
15
16
6
11
3
5
2
1
12
3
21
3
3
2
1
2
1
35
67
8
4
123
5
67
8
4
123
5
67
8
4
123
5
67
8
4
123
5
67
8
4
123
5
67
8
4
12
3
5
67
8
4
12
3
5
67
8
4
123
567
8
12
3
4
567
8
12
3
4
567
8
12
3
4
N15
567
8
12
3
4
N8
567
8
12
3
4
567
8
12
3
4
567
8
12
3
4
N9
567
8
12
3
4
J1–13
J1–15
J1–17
J1–19
J1–21
J1–23
J1–25
J1–27
J1–29
J1–31
J1–32
J1–34
J1–36
J1–38
J1–40
J1–42
J1–44
J1–46
J1–48
J1–14
J1–16
J1–18
J1–20
J1–22
J1–24
J1–26
J1–28
J1–30
J1–33
J1–35
J1–37
J1–39
J1–41
J1–43
J1–45
J1–47
J1–49
J1–50
R25
5.11kΩR24
28.7kΩ
RS1
1mΩ
RS2
1mΩ
R1
24Ω
R2
24ΩC10
33nF
C9
33nF
MAX8525
U1
MAX8523
U2
MAX8523
U3
Figure 7. Typical Application Circuit for VRM 10 Using a Sense Resistor for Output Current Sensing and 8-Pin SO MOSFET Packages
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
______________________________________________________________________________________ 21
VDD = 6.5V
VID4
PWM1
PWM3
RS+
PWM2
PWM4
KA317MR
U4
REF
EN
ILIM
COMP
AGND
PWRGD
VID0
VID1
VID2
VID3
D3
RS-
CLKI
CLKO
DLY
LX1
DH1
BST1
PV1
PWM2
C18
0.1μF
VCC
R12
10Ω
PWM1
VID5
VCC
DL1
PG1
PG2
BST2
DH2
LX2
DL2
D1
C13
0.22μF
R8
0Ω
C14
0.22μF
R9
0Ω
LX1
DH1
BST1
PWM2
PWM1
DL1
PG1
PG2
BST2
DH2
LX2
DL2
D2
C15
0.22μF
R10
0Ω
C16
0.22μF
R11
0Ω
CS2+
CS1_3-
CS1+
CS3+
CS2_4-
CS4+ CS4+
CS2+
CS2_4-
CS3+
CS1+
CS1_3-
OSC
L1–L4: TDK, SPM12535T-R23M300
N1, N3, N5, N7: IRF7801
N2, N4, N6, N8: 2XIRF7822, EACH
C26
470pF
C24
0.22μF
C23
680pF
C22
1μF
10V
C21
2.2μF
16V
C20
2.2μF
C19
2.2μF
REF
R23
95kΩ
R18
50Ω
R19
50ΩR20
100Ω
R21
100Ω
R22
29kΩ
R15
11.9kΩ
R16
100kΩ
R13
10Ω
5%
R27
27kΩ
R26
10kΩ
R18
OPEN
OUTEN
VOUT
V0_SEN+
V0_SEN-
7
21
12
8
9
R24
6.8kΩ
J1–10
VCC-PWRGD
PV2
DLY
PV1
C17
0.1μF
VCC
R14
10Ω
PV2
C25
470pF
C27
470pF
VDD = 6.5V
C28
0.015μF
C29
0.015μF
R5
249Ω
R6
1.02kΩ
6
10
2
1
15
20
19
18
17
16
14
13
26
24
25
5
3
4
28
27
23
22
11
4
13
7
8
9
10
12
14
15
16
6
11
3
5
2
1
4
13
7
8
9
10 12
14
15
16
6
11
3
5
2
1
12
3
21
3
3
2
1
2
1
3
MAX8525
U1
MAX8523
U2
MAX8523
U3
N1
N2 R1
24Ω
C1
10μF
25V
C2
10μF
25V
L1
0.29μH
C9
0.033μF
RS1
1mΩ
VIN+
N3
N4 R2
24Ω
C3
10μF
25V
C4
10μF
25V
L2
0.29μH
C10
0.033μF
RS2
1mΩ
N5
N6 R3
24Ω
C5
10μF
25V
C6
10μF
25V
L3
0.29μH
C11
0.033μF
RS3
1mΩ
N7
N8 R4
24Ω
C7
10μF
25V
C8
10μF
25V
L4
0.29μH
C12
0.033μF
RS4
1mΩ
CS1+
CS3+
CS2+
CS4+ CS_4-
C30–C39
330μF/10mΩ
SPCAPS
VO+
VO-
CS1_3-
VOUT = 80A
VIN+
VIN+
VIN+
Figure 8. 600kHz Application Circuit with Direct MOSFETs for Compact VRM 10 Design
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
22 ______________________________________________________________________________________
7-BIT
COUNTER
LOAD
VID1
VID2
VID4
VID3
PWM1
REF
DAC
INTERNAL CLOCK
COMP
CS1+
RS+
RS-
PWM2
PWM3
PWM4
CS3+
GND
CS2+
CS4+
EN
OPERATION
MODE DETECT
VID0
225mV
UVLO
OVP
0.9MHz
TO 9.6MHz
OSCILLATOR
CURRENT FOLDBACK
AND FAULT LOGIC
PWRGD
PWRGD
VCC
OSC
CS2_4-
(MAX8525 ONLY) VID5
SYNC
DETECT
CLKI
CLKO
CS1_3-
ILIM
div 2
MUX
div 2/3/4
S/R
S/R
S/R
S/R
0.45MHz TO 4.8MHz
1
0
RSDA
GMV
RCS
EQUAL?
1μs
DELAY
NO
REF
SOFT-START
RSNS1
RU
RB
CC
REF
2V ±0.4%
REFOK
AND
100kΩ
RUN
ONE OF FOUR PHASES DEPICTED
OFFSET ROM
RAPID-
ACTIVE
AVERAGE
CURRENT
SENSE
GMC
PHASE 1
GMC
PHASE 2
GMC
PHASE 3
GMC
PHASE 4
BUF CLAMP
REF /2
PWM
PWM
PWM
PWM
S
S
S
S
MAX8524
MAX8525
Functional Diagram
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers
with Precise Current Sharing and Fast Voltage
Positioning
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
F
11
21-0055
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH