SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
1
WWW.TI.COM
D3.3-V Supply Operation
D10-Bit-Resolution A/D Converter
D11 Analog Input Channels
DThree Built-In Self-Test Modes
DInherent Sample and Hold
DTotal Unadjusted Error . . . ±1 LSB Max
DOn-Chip System Clock
DEnd-of-Conversion (EOC) Output
DPin Compatible With TLC1543
DCMOS Technology
description
The TLV1543C, TLV1543I, and TLV1543M are
CMOS 10-bit, switched-capacitor, successive-
approximation, analog-to-digital converters.
These devices have three inputs and a 3-state
output [chip select (CS), input-output clock (I/O
CLOCK), address input (ADDRESS), and data
output (DATA OUT)] that provide a direct 4-wire
interface to the serial port of a host processor. The
devices allow high-speed data transfers from the
host.
In addition to a high-speed A/D converter and
versatile control capability, these devices have a n
on-chip 14-channel multiplexer that can select
any one of 11 analog inputs or any one of three
internal self-test voltages. The sample-and-hold
function is automatic. At the end of A/D conversion, the end-of-conversion (EOC) output goes high to indicate
that conversion is complete. The converter incorporated in the devices features differential high-impedance
reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and
supply noise. A switched-capacitor design allows low-error conversion over the full operating free-air
temperature range.
The TLV1543C is characterized for operation from 0°C to 70°C. The TLV1543I is characterized for industrial
temperature range of −40°C to 85°C. The TLV1543M is characterized for operation over the full military
temperature range of −55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TASMALL
OUTLINE
(DB)
SMALL
OUTLINE
(DW)
CHIP CARRIER
(FK) CERAMIC DIP
(J) PLASTIC DIP
(N)
PLASTIC CHIP
CARRIER
(FN)
0°C to 70°C TLV1543CDB TLV1543CDW — — TLV1543CN TLV1543CFN
−40°C to 85°C TLV1543IDB — — — — —
−55°C to 125°C — — TLV1543MFK TLV1543MJ — —
Copyright 2000 − 2004, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+&#$ ,#$(
!,'&$% &!" $ %)(&&#$% )(! $-( $(!"% (.#% %$!'"($%
%$#,#!, /#!!#$0 !,'&$ )!&(%%1 ,(% $ (&(%%#!+0 &+',(
$(%$1 #++ )#!#"($(!%
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
EOC
I/O CLOCK
ADDRESS
DATA OUT
CS
REF+
REF−
A10
A9
DB, DW, FK, J, OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
I/O CLOCK
ADDRESS
DATA OUT
CS
REF+
A3
A4
A5
A6
A7
FN PACKAGE
(TOP VIEW)
A2
A1
A0
A10
REF − EOC
A8
GND
A9 CC
V
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
2WWW.TI.COM
functional block diagram
14-Channel
Analog
Multiplexer
Sample and
Hold
10-Bit
Analog-to-Digital
Converter
(switched capacitors)
Self-Test
Reference
Output
Data
Register
10-to-1 Data
Selector and
Driver
System Clock,
Control Logic,
and I/O
Counters
Input Address
Register
4
10
10
4
REF+ REF−
DATA
OUT
ADDRESS
I
/O CLOCK
CS
3
EOC
1
2
3
4
5
6
7
8
9
11
12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
14 13
16
19
17
18
15
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kΩ TYP
Ci = 60 pF MAX
(equivalent input
capacitance)
5 MΩ TYP
A0−A10 A0−A10
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
3
WWW.TI.COM
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
ADDRESS 17 I Serial address. A 4-bit serial address selects the desired analog input or test voltage that is to be converted
next. The address data is presented with the MSB first and is shifted in on the first four rising edges of I/O
CLOCK. After the four address bits have been read into the address register, ADDRESS is ignored for the
remainder of the current conversion period.
A0−A10 1−9, 11,
12 I Analog signal. The 1 1 analog inputs are applied to A0−A10 and are internally multiplexed. The driving source
impedance should be less than or equal to 1 kΩ.
CS 15 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DAT A O UT,
ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling edges
of the internal system clock.
DATA OUT 16 O The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS
is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance
state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The
next falling edge of I/O CLOCK drives DAT A OUT to the logic level corresponding to the next most significant
bit, and the remaining bits are shifted out in order with the LSB appearing on the ninth falling edge of I/O
CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial
interface data transfers of more than ten clocks produce zeroes as the unused LSBs.
EOC 19 O End of conversion. EOC goes from a high- to a low- logic level on the trailing edge of the tenth I/O CLOCK
and remains low until the conversion is complete and data are ready for transfer.
GND 10 I The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are
with respect to GND.
I/O CLOCK 18 I Input/output clock. I/O CLOCK receives the serial I/O CLOCK input and performs the following four functions:
1) It clocks the four input address bits into the address register on the first four rising edges of I/O
CLOCK with the multiplex address available after the fourth rising edge.
2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins
charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK.
3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.
4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.
REF+ 14 I The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range
is determined by the difference between the voltage applied to REF+ and the voltage applied to the REF−
terminal.
REF− 13 I The lower reference voltage value (nominally ground) is applied to REF−.
VCC 20 I Positive supply voltage
detailed description
With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT
is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins
with the enabling of I/O CLOCK and ADDRESS and the removal o f DATA OUT from the high-impedance state.
The host then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O CLOCK.
During this transfer, the host serial interface also receives the previous conversion result from DATA OUT. I/O
CLOCK receives an input sequence that is between 10 and 16 clocks long from the host. The first four I/O clocks
load the address register with the 4-bit address on ADDRESS selecting the desired analog channel and the next
six clocks providing the control timing for sampling the analog input.
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
4WWW.TI.COM
detailed description (continued)
There are six basic serial interface timing modes that can be used with the device. These modes are determined
by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with
a 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer
and C S active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between
conversion cycles, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with
an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow mode with a
16-clock transfer and CS active (low) continuously.
The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and
mode 5, o n the rising edge of EOC in mode 2 and mode 4, and following the 16th clock falling edge in mode 6.
The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data are
transmitted to the host through DATA OUT. The number of serial clock pulses used also depends on the mode
of operation, but a minimum of ten clock pulses is required for conversion to begin. On the 10th clock falling
edge, the EOC output goes low and returns to the high logic level when conversion is complete and the result
can be read by the host. On the 10th clock falling edge, the internal logic takes DATA OUT low to ensure that
the remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.
Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that
can be used, and the timing edge on which the MSB of the previous conversion appears at the output.
Table 1. Mode Operation
MODES CS NO. OF
I/O CLOCKS MSB AT DATA OUT†TIMING
DIAGRAM
Mode 1 High between conversion cycles 10 CS falling edge Figure 9
Fast Modes
Mode 2 Low continuously 10 EOC rising edge Figure 10
Fast Modes Mode 3 High between conversion cycles 11 to 16‡CS falling edge Figure 11
Mode 4 Low continuously 16‡EOC rising edge Figure 12
Slow Modes
Mode 5 High between conversion cycles 11 to 16‡CS falling edge Figure 13
Slow Modes
Mode 6 Low continuously 16‡16th clock falling edge Figure 14
†These edges also initiate serial-interface communication.
‡No more than 16 clocks should be used.
fast modes
The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is
completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not
begin until the falling edge of the 10th I/O CLOCK.
mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The
falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling
edges of the internal system clock.
mode 2: fast mode, CS active (low) continuously, 10-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then
begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous
conversion to appear immediately on this output.
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
5
WWW.TI.COM
mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 4: fast mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of
EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the
previous conversion to appear immediately on this output.
slow modes
In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow
mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must
occur before the conversion period is complete; otherwise, the device loses synchronization with the host serial
interface, and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must
occur within 9.5 µs after the tenth I/O clock falling edge.
mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 6: slow mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of
the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next
16-clock transfer initiated by the serial interface.
address bits
The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal
(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address
selects one of 14 inputs (11 analog inputs or 3 internal test inputs).
analog inputs and test modes
The 11 analog inputs and the 3 internal test inputs are selected by the 14-channel multiplexer according to the
input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce
input-to-input noise injection resulting from channel switching.
Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six
I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are
applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
6WWW.TI.COM
Table 2. Analog-Channel-Select Address
ANALOG INPUT
SELECTED
VALUE SHIFTED INTO
ADDRESS INPUT
SELECTED
BINARY HEX
A0 0000 0
A1 0001 1
A2 0010 2
A3 0011 3
A4 0100 4
A5 0101 5
A6 0110 6
A7 0111 7
A8 1000 8
A9 1001 9
A10 1010 A
Table 3. Test-Mode-Select Address
INTERNAL SELF-TEST
VOLTAGE SELECTED†
VALUE SHIFTED INTO
ADDRESS INPUT
OUTPUT RESULT (HEX)
‡
VOLTAGE SELECTED†
BINARY HEX
OUTPUT RESULT (HEX)‡
Vref)–V
ref–
1011
B
200
Vref
)
–V
ref–
2
1011 B 200
Vref− 1100 C 000
Vref+ 1101 D 3FF
†Vref+ is the voltage applied to the REF+ input, and V ref− is the voltage applied to the REF−
input.
‡The output results shown are the ideal values and vary with the reference stability and with
internal offsets.
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF−)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF−. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half the VCC voltage), a bit 0 is
placed in the output register and the 512-weight capacitor is switched to REF−. If the voltage at the summing
node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the 512-weight
capacitor remains connected to REF+ through the remainder of the successive-approximation process. The
process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all
bits are counted.
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
7
WWW.TI.COM
converter and analog input (continued) SC
Threshold
Detector
Node 512
REF−
REF+
ST
512
VI
To Output
Latches
REF−
ST
REF+
REF−
ST
REF+
REF−
ST
REF+
REF−
ST
REF+
REF−
ST
REF+
REF−
ST
REF+
REF−
ST
REF−
ST
1124816128256
Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS from being taken low close to completion of conversion because the output data
can be corrupted.
reference voltage inputs
There are two reference inputs used with these devices: REF+ and REF−. These voltage values establish the
upper and lower limits of the analog input to produce a full-scale and zero-scale reading respectively. The values
of REF+, REF−, and the analog input should not exceed the positive supply or be lower than GND consistent
with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal
to or higher than REF+ and at zero when the input signal is equal to or lower than REF−.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1): TLV1543C/TLV1543I −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
TLV1543M −0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input) −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive reference voltage, Vref+ V
CC + 0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative reference voltage, Vref− −0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak input current (any input), I(p-p) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak total input current (all inputs), Ip ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV1543C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV1543I −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV1543M −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF− and GND wired together (unless otherwise noted).
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
8WWW.TI.COM
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC
TLV1543C/TLV1543I 3 3.3 5.5 V
Supply voltage, VCC TLV1543M 3 3.3 3.6 V
Positive reference voltage, Vref+ (see Note 2) VCC V
Negative reference voltage, Vref− (see Note 2) 0 V
Differential reference voltage, Vref+ − Vref− (see Note 2) 2.5 VCC VCC+0.2 V
Analog input voltage (see Note 2) 0 VCC V
High-level control input voltage, VIH
TLV1543C/TLV1543I VCC = 3 V to 5.5 V 2 V
High-level control input voltage, VIH TLV1543M VCC = 3 V to 3.6 V 2 V
Low-level control input voltage, VIL
TLV1543C/TLV1543I VCC = 3 V to 5.5 V 0.6 V
Low-level control input voltage, VIL TLV1543M VCC = 3 V to 3.6 V 0.8 V
Setup time, address bits at data input before I/O CLOCK↑, tsu(A) (see Figure 4) 100 ns
Hold time, address bits after I/O CLOCK↑, th(A) (see Figure 4) 0 ns
Hold time, CS low after last I/O CLOCK↓, th(CS) 0 ns
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3) 1.425 µs
Clock frequency at I/O CLOCK (see Note 4)
TLV1543C/TLV1543I 0 1.1
MHz
Clock frequency at I/O CLOCK (see Note 4) TLV1543M 0 2.1 MHz
Pulse duration, I/O CLOCK high, tw(H_I/O) 190 ns
Pulse duration, I/O CLOCK low, tw(L_I/O) 190 ns
Transition time, I/O CLOCK, tt(I/O) (see Note 5) 1µs
Transition time, ADDRESS and CS, tt(CS) 10 µs
TLV1543C 0 70
°C
Operating free-air temperature, T
A
TLV1543I −40 85 °
C
Operating free-air temperature, TA
TLV1543M −55 125 °C
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF− convert as all zeros (0000000000).
3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS
setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V), at least one I/O clock rising edge (≥ 2 V) must occur within
9.5 µs.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
9
WWW.TI.COM
electrical characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C, and TLV1543I
VCC = Vref+ = 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
TLV1543C/TLV1543I
VCC = 3 V, IOH = −1.6 mA 2.4 V
VOH
High-level output voltage
TLV1543C/TLV1543I VCC = 3 V to 5.5 V, IOH = 20 µA VCC−0.1 V
VOH High-level output voltage
TLV1543M
VCC = 3 V, IOH = −1.6 mA 2.4 V
TLV1543M VCC = 3 V to 3.6 V, IOH = 20 µA VCC−0.1 V
TLV1543C/TLV1543I
VCC = 3 V, IOL = 1.6 mA 0.4 V
VOL
Low-level output voltage
TLV1543C/TLV1543I VCC = 3 V to 5.5 V, IOL = 20 µA 0.1 V
VOL Low-level output voltage
TLV1543M
VCC = 3 V, IOL = 1.6 mA 0.4 V
TLV1543M VCC = 3 V to 3.6 V, IOL = 20 µA 0.1 V
IOZ
Off-state (high-impedance-state) output current
VO = VCC, CS at VCC 10
A
IOZ Off-state (high-impedance-state) output current VO = 0, CS at VCC −10 µA
IIH High-level input current VI = VCC 0.005 2.5 µA
IIL Low-level input current VI = 0 −0.005 −2.5 µA
ICC Operating supply current CS at 0 V 0.8 2.5 mA
Selected channel leakage current
Selected channel at VCC,
Unselected channel at 0 V 1
A
Selected channel leakage current Selected channel at 0 V,
Unselected channel at VCC −1 µA
Maximum static analog reference current into REF+ Vref+ = VCC, Vref− = GND 10 µA
Input capacitance, Analog
TLV1543C/TLV1543I 7 60
pF
Ci
Input capacitance, Analog
inputs TLV1543M 7 60 pF
C
i
Input capacitance, Control
TLV1543C/TLV1543I 5 60
pF
Input capacitance, Control
inputs TLV1543M 5 60
pF
†All typical values are at VCC = 5 V, TA = 25°C.
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
10 WWW.TI.COM
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C, and TLV1543I
VCC = Vref+ = 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
Linearity error (see Note 6) ±1 LSB
Zero error (see Note 7) ±1 LSB
Full-scale error (see Note 7) ±1 LSB
Total unadjusted error (see Note 8) ±1 LSB
ADDRESS = 1011 512
Self-test output code (see Table 3 and Note 9) ADDRESS = 1100 0
Self-test output code (see Table 3 and Note 9)
ADDRESS = 1101 1023
tc(1) Conversion time See Figures 9−14 21 µs
tc(2) Total cycle time (access, sample, and conversion) See Figures 9−14
and Note 10
21
+10 I/O
CLOCK
periods
µs
t(acq) Channel acquisition time (sample) See Figures 9−14
and Note 10 6 I/O
CLOCK
periods
tvValid time, DATA OUT remains valid after I/O CLOCK↓See Figure 6 10 ns
td(I/O-DATA) Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 6 240 ns
td(I/O-EOC) Delay time, tenth I/O CLOCK↓ to EOC↓See Figure 7 70 240 ns
td(EOC-DATA) Delay time, EOC↑ to DATA OUT (MSB) See Figure 8 100 ns
tPZH, tPZL Enable time, CS↓ to DATA OUT (MSB driven) See Figure 3 1.3 µs
tPHZ, tPLZ Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 150 ns
tr(EOC) Rise time, EOC See Figure 8 300 ns
tf(EOC) Fall time, EOC See Figure 7 300 ns
tr(bus) Rise time, data bus See Figure 6 300 ns
tf(bus) Fall time, data bus See Figure 6 300 ns
td(I/O-CS) Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion
(see Note 11) 9µs
†All typical values are at TA = 25°C.
NOTES: 6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6).
11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425 µs) after the transition.
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
11
WWW.TI.COM
PARAMETER MEASUREMENT INFORMATION
EOC
CL = 50 pF 12 kΩ
DATA OUT
Test Point VCC
RL = 2.18 kΩ
CL = 100 pF 12 kΩ
Test Point VCC
RL = 2.18 kΩ
Figure 2. Load Circuits
CS
DATA
OUT
2.4 V
0.4 V
90%
10%
tPZH, tPZL tPHZ, tPLZ
VIL
2 V
Figure 3. DATA OUT to Hi-Z Voltage Waveforms
ADDRESS
th(A)
VIL
2 V
I/O CLOCK
Address
Valid
tsu(A)
VIL
Figure 4. ADDRESS Setup Voltage Waveforms
Last
Clock
CS VIL
2 V
VIL
tsu(CS)
VIL
I/O CLOCK
th(CS)
First
Clock
Figure 5. CS and I/O CLOCK Voltage Waveforms
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
12 WWW.TI.COM
PARAMETER MEASUREMENT INFORMATION
0.4 V
2.4 V 0.4 V
2.4 V
2 V VIL
I/O CLOCK
DATA OUT
tt(I/O)
VIL
2 V
tr(bus), tf(bus)
td(I/O-DATA)
tv
I/O CLOCK Period
tt(I/O)
VIL
Figure 6. DATA OUT and I/O CLOCK Voltage Waveforms
10th
Clock VIL
2.4 V 0.4 V
tf(EOC)
td(I/O-EOC)
I/O CLOCK
EOC
Figure 7. I/O CLOCK and EOC Voltage Waveforms
0.4 V
2.4 V
EOC
td(EOC-DATA)
Valid MSB
DATA OUT
0.4 V 2.4 V
tr(EOC)
Figure 8. EOC and DATA OUT Voltage Waveforms
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
13
WWW.TI.COM
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval InitializeInitialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Hi-Z State
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
(see Note A)
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system cloc
k
after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup
time has elapsed. Figure 9. Timing for 10-Clock Transfer Using CS
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Low Level
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
(see Note A)
Must be High on Power Up
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system cloc
k
after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup
time has elapsed. Figure 10. Timing for 10-Clock Transfer Not Using CS
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
14 WWW.TI.COM
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal syste
m
clock after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum C
S
setup time has elapsed.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges
of
the internal system clock.
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
ÏÏÏ
ÏÏÏ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Low
Level Hi-Z
See Note B
11 16
(see Note A)(see Note A)
Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion
)
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Low Level
12345678910 1
I/O
CLOCK
DATA
OUT
A
DDRESS
CS
EOC
Initialize
Must be High on Power Up
14 15 16
See Note B
(see Note A)
ÎÎÎ
ÎÎÎ
NOTES: A. The first I/O CLOCK must occur after the rising edge of EOC.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges o
f
the internal system clock.
Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
15
WWW.TI.COM
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum
chip CS setup time has elapsed.
B. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial
interface synchronization.
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
11
ÏÏÏ
ÏÏÏ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Hi-Z State
16
See Note B
ÏÏÏ
ÏÏÏ
Low
Level
(see Note A)
Figure 13. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion
)
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Must be High on Power Up
14 15 16
See Note B
See Note A
Low Level
Access Cycle B
(
see Note A)
Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion
)
NOTES: A. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing seria
l
interface synchronization.
B. The I/O CLOCK sequence is exactly 16 clock pulses long.
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
16 WWW.TI.COM
APPLICATION INFORMATION
1000000000
0111111111
0000000010
0000000001
0000000000
1111111110
0 0.0096 2.4528 2.4576 2.4624
Digital Output Code
1000000001
1111111101
1111111111
4.9056 4.9104 4.9152
512
511
2
1
0
1022
Step
513
1021
1023
0.0024
VI − Analog Input Voltage − V
VZT = VZS + 1/2 LSB
VZS
See Notes A and B
4.9080
0.0048
VFT = VFS − 1/2 LSB
VFS
NOTES: A. This curve is based on the assumption that Vref+ and V ref− have been adjusted so that the voltage at the transition from digital
0 to 1 (VZT) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB = 4.8 mV.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS)
is the step whose nominal midstep value equals zero.
Figure 15. Ideal Conversion Characteristics
Processor Control
Circuit
Analog
Inputs
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
I/O CLOCK
CS
ADDRESS
DATA OUT
EOC
REF+
REF−
GND
TLV1543
To Source
Ground
3-V DC Regulated
1
2
3
4
5
6
7
8
9
11
12
15
18
17
16
19
14
13
10
Figure 16. Serial Interface
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
17
WWW.TI.COM
APPLICATION INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
VC = VS 1−e
−t
c
/R
t
C
i
( )
(
1)
Where:R
t
= R
s
+ r
i
The final voltage to 1/2 LSB is given by
(2)VC (1/2 LSB) = VS − (VS/2048)
Equating equation 1 to equation 2 and solving for time tc gives
VS −(VS/2048) = VS 1−e
( )
(
3)
−t
c
/R
t
C
i
and t
c
(1/2 LSB) = R
t
× C
i
× ln(2048) (
4)
Therefore, with the values given the time for the analog input signal to settle is
(5)
tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(2048)
This time must be less than the converter sample time shown in the timing diagrams.
Rsri
VSVC
1 kΩ MAX
Driving Source†TLV1543
Ci
VI
VI= Input Voltage at A0−A10
VS= External Driving Source Voltage
Rs= Source Resistance
ri= Input Resistance
Ci= Input Capacitance
†Driving source requirements:
•Noise and distortion for the source must be equivalent to the
resolution of the converter.
•Rs must be real at the input frequency.
Figure 17. Equivalent Input Circuit Including the Driving Source
60 pF MAX
PACKAGE OPTION ADDENDUM
www.ti.com 29-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9689401Q2A OBSOLETE LCCC FK 20 TBD Call TI Call TI
TLV1543CDB ACTIVE SSOP DB 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1543CDBG4 ACTIVE SSOP DB 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1543CDBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI
TLV1543CDBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1543CDBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1543CDW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1543CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1543CDWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1543CDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1543CFN ACTIVE PLCC FN 20 46 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
TLV1543CFNG3 ACTIVE PLCC FN 20 46 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
TLV1543CN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV1543CNE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV1543IDB ACTIVE SSOP DB 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1543IDBG4 ACTIVE SSOP DB 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1543IDBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI
TLV1543IDBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1543IDBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 29-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV1543MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TLV1543MJ OBSOLETE CDIP J 20 TBD Call TI Call TI
TLV1543MJB OBSOLETE CDIP J 20 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV1543CDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
TLV1543IDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV1543CDBR SSOP DB 20 2000 367.0 367.0 38.0
TLV1543IDBR SSOP DB 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
