=~. a: Ps SBP Cypress Features e High speed taa = Dns e CMOS for optimum speed/power e Lew active power 1020 mW Low standby power 250 mW 2.0V data retention (optional) 100 uw Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE), CE, and OE options PRELIMINARY CY7C109A Functional Description The CY7C109A is a high-performance CMOS static RAM organized as 131,072 words hy 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE,), an active HIGH chip enable (CE3), an active LOW output enable (OE), and three-state drivers. This device has an au- tomatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by tkingerp enable one (CE)) and write en- able (WE) inputs LOW and chip enable two (CE>) input HIGH. Data on the eight 1/O pins (1/Og through 1/07) is then written into the location specified on the address pins (Ap through A4_). 128K x 8 Static RAM Reading from the device is accomplished by taking chip enable one (CE)) and out- put enable ) LOW while forcing write enable (WE) and chip enable two (CE) HIGH. Under these conditions, the con- tents of the memory location specified by the address pins will appear on the 1/O pins. The eight input/output pins (I/O through 1/O7) are placed in a high-impedance state when the device is deselected (CE, HIGH or CE; LOW), the outputs are disabled (OE HIGH), or during a write operation (CE, LOW, CE; HIGH, and WE LOW). The CY7C109A is available in standard 400-mil-wide DIPs and SOJs anda leadless chip carrier. Logic Block Diagram die aN | [c {> Og INPUT BUFFER La NS . U rf . Ay & | wa 103 eal! oy 8 V0 me) mate BY ge A; 8 re Vg Ag x | > Os L POWER] > VOg cb sexsi, | festa] tT we vo FERTERTS r sraesee OE Li had Ie 1094-1 Pin Configurations DIP/SOJ Top View Lcc Top View 1 2 3 4 5 6 7 8 Selection Guide ns} Maximum Operating | Comme Current (mA} Maximum Standby Current (mA) TCLO9A 12 TC1LO9A 15 Nw 36 7C109A20 7C109A25 7C109A35CYPRESS PRELIMINARY CY7C109A Maximum Ratings (Above which the useful life may be impaired. For user guidelines, Static Discharge Voltage ............0..0....0000- >2001V not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ......0...00e eee -~65Cto 159C Latch-Up Current... 6.0.6.0. eee eee >200 mA Ambient Temperature with : Power Applied... 00.00. .0ccceeceeeees -55Cto +125C Operating Range Supply Voltage on Vcc to Relative GND] |, -0.5V to +7.0V Ambient {2} c DC Voltage Applied to Outputs Range Temperature Vee in High ZStatel) 26 -0.5V to Vec +0.5V Commercial 0C to +70C 5V + 10% DC Input Voltage!) 2... -0,5V to Vcc +0.5V Military 55C to +125C SV + 10% Current into Outputs (LOW) .......6.. 0.0 cece eee 20 mA Electrical Characteristics Over the Operating Rangel] TC1O9A12 TIC1IOIA15 7C109A20 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Unit Vou Output HIGH Vec = Min., [oy = 4.0mA 2.4 2.4 2.4 v Voltage Vo. Output LOW Vec = Min., Io, = 8.0 mA 0.4 0.4 0.4 v Voltage Vin Input HIGH 2.2 Veco + 2.2 Vec + 2.2 Vecot+ Vv Voltage 0.3 0.3 0.3 Vin Input LOW -03 0.8 -0.3 0.8 -03 0.8 v Voltagel!] hix Input Load GND < Vi < Vcc ~1 +1 I +1 ~t +1 pA Current loz Output Leakage GND < Vi < Vcc, ~5 +5 -5 +5 ~5 +5 wA Current Output Disabled los Output Short Vcc = Max., Vout = GND ~300 ~ 300 -300 | mA Circuit Currentl4l loc Vec Operating Veco = Max., Com! 185 170 155 mA Supply Current Tout = OMA, Py fo thaax = Lipe Mil 180 170 Isnt Automatic CE Max. Voc, CE; > Vip | Com 45 40 30 mA Power-Down or CE? < Vir. Current Vin > Vin or 7 3 TTL Inputs Vin < Vit f = fMax Mil 40 30 Isp2 Automatic CE Max. Voc, Com 2 2 2 mA Power-Down CE, > Vec - 03V, Current or CE, < 03V, , CMOS Inputs | Vin > Vcc - 03V, Mil 2 2 or Vin < 0.3V, f=0 Notes: 1. Vyz. (min.) = 2.0 for pulse durations of less than 20 ns, 2. Ty is the instant on case temperature.PRELIMINARY _CY7C109A CYPRESS Electrical Characteristics Over the Operating Rangel?! (continued) TC109A25 7C109A~35 Parameter Description Test Conditions Min. Max. Min. Max. Unit Von Output HIGH Voltage | Vcc = Min, log = 4.0 mA 24 24 V VoL Output LOW Voltage | Vcc = Min., Jo. = 8.0 mA 0.4 0.4 Vv Ving Input HIGH Voltage 2.2 Veco + 2.2 Voc + Vv 0.3 0.3 Vit Input LOW Voltagel!] ~03 0.8 -0.3 0.8 v lix Input Load Current GND < Vi < Vcc -1 +1 -l +1 pA loz Output Leakage GND < Vi < Veco. - +5 - +5 pA Current Output Disabled los Output Short Vcc = Max., Vour = GND ~300 300 mA Circuit Currentl4l Icc Vcc Operating Voc = Max. Com'l 145 140 mA Supply Current I =OmA, pPy f= tuax = Wtee Mil T60 150 Isp1 Automatic CE Max. Vcc, CE; > Vin Com! 30 25 mA Power-Down or CE? < Vit, Current Vin = Vin or * TTL Inputs Vin < Vin, f = fMax Mil 30 Isp? Automatic CE Max. Voc. Com'l 2 2 mA Power-Down CE, > Vcc ~ 03V, Current or CE; < 0.3V, - = 5 CMOS Inputs Vin = Voc ~ 0.3V, Mil 2 2 or Vin < 0.3V, f=0 Capacitancel*| Parameter Description Test Conditions Max. Unit Cin: Addresses Input Capacitance Ta = 25C, f = 1 MHz, 7 pF Cin: Controls Veo = 10 pF Cout Output Capacitance 10 pF AC Test Loads and Waveforms R1 4802 Ri 48022 ALL INPUT PULSES 3.0V OUTPUT OUTPUT GND 30 rT 25st) 8 rT 2550 INCLUDING i = INCLUDING i = <3ns 10BA-5 JIG AN Score (a) Normal Load = SCOP (b) High-Z Load 1094-4 Equivalent to: THEVENIN EQUIVALENT 167Q OUTPUT Owwr_9_s'1.73V Notes: 3, See the last page of this specification for Group A subgroup testing information. 4, Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters.j CYPRESS PRELIMINARY _CY7C109A Switching Characteristics!'. ] Over the Operating Range TCLO9A12 | 7CIO9A-15 | 7C109A--20 | 7C109A~25 | 7C109A35 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Min. | Unit READ CYCLE tre Read Cycle Time 12 15 20 25 35 ns tAA Address to Data Valid 12 15 20 25 35 ns {OHA Data Hold from Address Change 3 3 3 3 3 ns tace CE, LOW to Data Valid, CE; HIGH 12 15 20 25 35 | ns to Data Valid tpoE OE LOW to Data Valid 6 7 8 10 10 ns tLZOE OE LOW to Low Z 0 0 0 0 0 ns tHZ0E OE HIGH to High Z!7- 8) 6 7 8 10 10 | ns th 2zcE CE, LOW to Low Z, CE? HIGH to 3 3 3 3 3 ns Low za) tHZ2cE CE, HIGH to High Z, CE2 LOW to 6 7 8 10 10 ns High ZI7. 8} tpu CE, LOW to Power-Up, CE7HIGH | 0 0 0 0 0 ns to Power-Up tpp CE, HIGH to Power-Down, 12 15 20 25 35 ns CE; LOW to Power-Down WRITE CYCLE! '9J twc Write Cycle Time 12 15 20 25 35 ns sce CE; LOW to Write End, CE, HIGH | 10 12 15 20 25 ns to Write End taw Address Set-Up to Write End 10 12 15 20 25 ns tHA Address Hold from Write End 0 0 0 0 ns tsa Address Set-Up to Write Start 0 0 0 0 0 ns tewE WE Pulse Width 10 12 15 20 25 ns tsp Data Set-Up to Write End 8 10 15 20 ns typ Data Hold from Write End 0 0 0 0 0 ns tLZWE WE HIGH to Low ZI&I 3 3 3 3 ns tuzwe | WE LOW to High Z/7.4] 6 7 8 10 10 | ns Notes: 6, Test conditions assume signal transition time of 3 nsor less, timing ref- 9. The internal write time of the memory is defined by the overlap of CE; erence levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified lor/lon and 30-pF load capacitance, tyzoe tuzce. and tyzwe are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured +500 mV from steady-state voltage. At any given temperature and voltage condition, tyzce is less than tLzce, tHzok is less than t_zog, and tyzwe is less than ty wk for any given device. 10, LOW, CE; HIGH, and WE LOW. CE, and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write, The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tyizwe and tsp.CYPRESS PRELIMINARY _CY7C109A Data Retention Characteristics Over the Operating Range (L Version Only) Commercial Military Parameter Description Conditions|!!! Min. | Max. | Min. | Max. ] Unit VpR Voc for Retention Data 2.0 2.0 v Iccpr Data Retention Current Voc = Vor = 2.0V, 50 70 pA 12 Vee 0.3V or tcpRbl Chip Deselect to Data Retention Time CE? < 0.3V, 0 0 ns - Vin > Vcc 0.3V or tril Operation Recovery Time Vin < 0.3V tre tre ns Data Retention Waveform DATA RETENTION MODE Voc 4.5V e ty } fo 8 VLLLLLLLI S C& SX Z YOSA-6 Switching Waveforms Read Cycle No, 1!!2, 13) ADDRESS K taa C toHa *} DATA OUT PREVIOUS DATA VALID x DATA VALID 100A-7 Read Cycle No. 2 (OE Controlled)|!3 '41 ADDRESS cE, CE DATA OUT tpoe tLz0e HIGH IMPEDANCE tizce DATA VALID HIGH IMPEDANCE | tpp - Voc teu NJ (cc SUPPLY / 50% 50% K CURRENT ISB 109A-8 Notes: 1, No input may exceed Voc +0.5V. 12. Device is continuously selected. OF, CEy = Vy, CE? = Vin. 13. WE is HIGH for read cycle. 14. Address valid prior lo or coincident with CE, transition LOW and CE2 transition HIGH. 2-40J CYPRESS PRELIMINARY _ CY7C109A Switching Waveforms (continued) Write Cycle No. 1 (CE, or CE; Controlled)(!5. 16] two ADDRESS CE. tpwe WE 1+___ tso tHo DATA I/O DATA VALID 1OSA-9 Write Cycle No. 2 (WE Controlled, OF HIGH During Write)!!5. !] twe ADDRESS CE, CE2 WE OE tsp DATA 1/0 DATAiy VALID Notes: 15. Data I/O is high impedance if OF = Vint. 16. If CE, goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. CYPRESS PRELIMINARY CY7C109A Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)!!. !6] ADDRESS CE, CE WE tsp DATA I/O DATA VALID Truth Table CE, | CE; | OE | WE | Input/Output Mode Power H Xx X | X | HighZ Power-Down Standby (Isp) XxX L x X | HighZ Power-Down Standby (Isp) L H L H | Data Out Read Active (lcc) L H xX L | Data In Write Active (icc) L H H H High Z Selected, Outputs Disabled Active (Ic) Ordering Information Speed Package Package Type Operating (ns) Ordering Code Name Range 12 CY7C1O9A 12PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7CLOVA - 12VC V33 32-Lead (400-Mil) Molded SOJ {5 CY7ICIO9A15PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7C109A-15VC V33 32-Lead (400-Mil) Molded SOJ CY7C109A15DMB D44 32-Lead (400-Mil) CerDIP Military CY7C109A15LMB L75 32-Pin Leadless Chip Carrier 20 CY7C1O9A 20PC P43 32-Lead (400-Mil} Molded DIP | Commercial CY7C1IN9A 20VC V33 32-Lead (400-Mil) Molded SOJ CY7C109A 20DMB D44 32-Lead (400-Mil) CerDIP Military CY7C109A20LMB L75 32-Pin Leadless Chip Carrier Contact factory for L" version availability. 1094-114PRELIMINARY _CY7C109A CYPRESS Ordering Information (continued) Speed Package Operating (ms) Ordering Code Name Package Type Range 25 CY7C109A~25PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7C109A -25VC V33 32-Lead (400-Mil) Molded SOJ CY7C109A -25DMB D44 32-Lead (400-Mil) CerDIP Military CY7C109A25LMB L75 32-Pin Leadless Chip Carrier 35 CY7C109A~35PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7C109A-35VC v33 32-Lead (400-Mil) Molded SOJ CY7C109A-35DMB D44 32-Lead (400-Mil) CerDIP Military CY7C109A35LMB L75 32-Pin Leadless Chip Carrier Contact factory for L version availability. MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups Vou 1,2,3 VoL 1, 2,3 Vin 1, 2,3 Vit Max. 1, 2,3 Tix 1, 2,3 loz 1, 2,3 lec 1, 2,3 TsB1 1,2,3 Isp2 1, 2,3 Switching Characteristics Parameter | Subgroups READ CYCLE trc 7, 8,9, 10, 11 tAA 7,8, 9,10, 11 tOHA 7, 8,9, 10, 11 tace 7, 8,9, 10, 11 (DoE 7, 8,9, 10, 11 WRITE CYCLE twc 7, 8,9, 10, 11 tscE 7, 8,9, 10, 11 taw 7, 8,9, 10,11 {HA 7, 8,9, 10,11 tsa 7, 8,9, 10, 11 (pWE 7, 8,9, 10, 11 tsp 7, 8,9, 10, 11 tub 7, 8.9, 10, 11 Document #: 38-00233-A