2 PRELIMINARY W223-02 SDRAM Buffer -2 DIMM Features Key Specifications * Ten skew controlled CMOS outputs (SDRAM0:9) * Supports two SDRAM DIMMs * Ideal for high performance systems designed around Intel's latest Mobile chip set * I2C Serial configuration interface * Skew between any two outputs is less than 250 ps * 4 to 8 ns propagation delay * DC to 133 MHz operation * Single 3.3V supply voltage * Low power CMOS design packaged in a 28-pin, 0.209 inch SSOP (Shrink Small Outline Package) Supply Voltages:........................................... VDD = 3.3V5% Operating Temperature: ................................... 0C to +70C Input Threshold: .................................................. 1.5V typical Maximum Input Voltage:.......................................VDD + 0.5V Input Frequency: ............................................... 0 to 133MHz BUF_IN to SDRAM0:9 Propagation Delay: ..............4 to 8 ns Output Edge Rate:................................................. >1.5 V/ns Output Skew:............................................................ 250 ps Output Duty Cycle: .................................. 45/55% worst case Output Impedance:...............................................15 typical Output Type:................................................ CMOS rail-to-rail Simplified Block Diagram Pin Configuration [1] SSOP SDATA SCLOCK Serial Port Device Control OE SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 BUF_IN SDRAM9 VDD SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 GND BUF_IN VDD SDRAM8 GND VDD SDATA 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDD SDRAM7 SDRAM6 GND VDD SDRAM5 SDRAM4 GND OE VDD SDRAM9 GND GND SCLK Note: 1. Internal pull-up resistor of 250K on SDATA, SCLK and OE inputs (should not be relied upon for pulling up to VDD). I2C is a trademark of Philips Corporation. Intel is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07243 Rev. ** * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised September 17, 2001 PRELIMINARY W223-02 Pin Definitions Pin Name SDRAM0:9 Pin No. Pin Type Pin Description 2, 3, 6, 7, 22, 23, 26, 27, 11, 18 O SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within 250 ps of each other. BUF_IN 9 I Clock Input: This clock input has an input threshold voltage of 1.5V (typ). SDATA 14 I/O I2C Data Input: Data should be presented to this input as described in the I2C section of this data sheet. Internal 250-k pull-up resistor. SCLOCK 15 I I2C Clock Input: The I2C Data clock should be presented to this input as described in the I2C section of this data sheet. Internal 250-k pull-up resistor. VDD 1, 5, 10, 13, 19, 24, 28 P Power Connection: Power supply for core logic and output buffers, connected to 3.3V supply. GND 4, 8, 12,16, 17, 21, 25 G Ground Connection: Connect all ground pins to the common system ground plane. Document #: 38-07243 Rev. ** Page 2 of 11 PRELIMINARY W223-02 Overview Output Drivers The Cypress W223-02 is a low-voltage, ten-output clock buffer. Output buffer impedance is approximately 15 which is ideal for driving SDRAM DIMMs. The W223-02 output buffers are CMOS type which deliver a rail-to-rail (GND to VDD) output voltage swing into a nominal capacitive load. Thus, output signaling is both TTL and CMOS level compatible. Nominal output buffer impedance is 15. Functional Description Operation Output Control Pins Data is written to the W223-02 in eleven bytes of eight bits each. Bytes are written in the order shown in Table 1. Outputs three-stated when OE = 0, and toggle when OE = 1. Outputs are in phase with BUF_IN but are phase delayed by 3 to 7ns. Outputs can also be controlled via the I2C interface. Table 1. Byte Writing Sequence Byte Sequence Byte Name Bit Sequence Byte Description 1 Slave Address 11010010 Commands the W223-02 to accept the bits in Data Bytes 0-7 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W223-02 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). 2 Command Code "Don't Care" Unused by the W223-02, therefore bit values are ignored ("Don't Care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count "Don't Care" Unused by the W223-02, therefore bit values are ignored ("Don't Care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 Data Byte 0 "Don't Care" Refer to Cypress clock drivers. 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 Refer to Table 2 10 Data Byte 6 11 Data Byte 7 The data bits in these bytes set internal W223-02 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 2, Data Byte Serial Configuration Map. Document #: 38-07243 Rev. ** Page 3 of 11 PRELIMINARY W223-02 Writing Data Bytes Each bit in the data bytes control a particular device function. Bits are written MSB (most significant bit) first, which is bit 7. Table 2 gives the bit formats for registers located in Data Bytes 5-7. Table 2. Data Bytes 5-7 Serial Configuration Map[2] Affected Pin Bit(s) Pin No. Pin Name Bit Control Control Function 0 1 Data Byte 5 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) 7 N/A Reserved (Reserved) -- -- 6 N/A Reserved (Reserved) -- -- 5 N/A Reserved (Reserved) -- -- 4 N/A Reserved (Reserved) -- -- 3 7 SDRAM3 Clock Output Disable Low Active 2 6 SDRAM2 Clock Output Disable Low Active 1 3 SDRAM1 Clock Output Disable Low Active 0 2 SDRAM0 Clock Output Disable Low Active Data Byte 6 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) 7 27 SDRAM7 Clock Output Disable Low Active 6 26 SDRAM6 Clock Output Disable Low Active 5 23 SDRAM5 Clock Output Disable Low Active 4 22 SDRAM4 Clock Output Disable Low Active 3 N/A Reserved (Reserved) -- -- 2 N/A Reserved (Reserved) -- -- 1 N/A Reserved (Reserved) -- -- 0 N/A Reserved (Reserved) -- -- Data Byte 7 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) 7 18 SDRAM9 Clock Output Disable Low Active 6 11 SDRAM8 Clock Output Disable Low Active 5 N/A Reserved (Reserved) -- -- 4 N/A Reserved (Reserved) -- -- 3 N/A Reserved (Reserved) -- -- 2 N/A Reserved (Reserved) -- -- 1 N/A Reserved (Reserved) -- -- 0 N/A Reserved (Reserved) -- -- Note: 2. At power up all SDRAM outputs are enabled and active. It is recommended to program Bits 4-7 of Byte 5 and Bits 0-3 of Byte 6 to a "0" to save power and reduce noise. Document #: 38-07243 Rev. ** Page 4 of 11 PRELIMINARY W223-02 How To Use the Serial Data Interface Electrical Requirements Figure 1 illustrates electrical characteristics for the serial interface bus used with the W223-02. Devices send data over the bus with an open drain logic output that can (a) pull the bus line low, or (b) let the bus default to logic 1. The pull-up resistor on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data. Although the W223-02 is a receive-only device (no data write-back capability), it does transmit an "acknowledge" data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance. VDD VDD ~ 2k ~ 2k SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE SDCLK CLOCK IN CLOCK OUT DATA IN N DATA OUT CHIP SET (SERIAL BUS MASTER TRANSMITTER) SCLOCK SDATA CLOCK IN N SDATA DATA IN DATA OUT N CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER) Figure 1. Serial Interface Bus Electrical Characteristics Document #: 38-07243 Rev. ** Page 5 of 11 PRELIMINARY W223-02 Signaling Requirements Sending Data to the W223-02 As shown in Figure 2 valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock high (logic 1) pulse. A transitioning data line during a clock high pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition). A write sequence is initiated by a "start bit" as shown in Figure 3. A "stop bit" signifies that a transmission has ended. As stated previously, the W223-02 sends an "acknowledge" pulse after receiving eight data bits in each byte as shown in Figure 4. t SDATA SCLOCK Valid Data Bit Change of Data Allowed Figure 2. Serial Data Bus Valid Data Bit SDATA SCLOCK Start Bit Stop Bit Figure 3. Serial Data Bus Start and Stop Bit Document #: 38-07243 Rev. ** Page 6 of 11 PRELIMINARY W223-02 SDATA tSPF tLOW SCLOCK tDSU tSTHD tDHD tSP tHIGH tR tSPSU tSTHD tSPSU tF Figure 4.4 Serial Data Bus Write Sequence Signaling from System Core Logic Start Condition Stop Condition Slave Address (First Byte) SDATA Command Code (Second Byte) MSB 1 1 0 1 0 0 1 LSB 0 1 2 3 4 5 6 7 8 SCLOCK Byte Count (Third Byte) MSB A 1 LSB 2 3 4 5 6 7 8 Last Data Byte (Last Byte) MSB A 1 MSB 2 3 4 1 LSB 2 3 SDATA Signaling by Clock Device Acknowledgment Bit from Clock Device Figure 5.5 Serial Data Bus Timing Diagram Document #: 38-07243 Rev. ** Page 7 of 11 4 5 6 7 8 A PRELIMINARY Absolute Maximum Ratings only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating Parameter W223-02 Description Rating Unit VDD, VIN Voltage on any pin with respect to GND -0.5 to +7.0 V TSTG Storage Temperature -65 to +150 C TB Ambient Temperature under Bias -55 to +125 C TA Operating Temperature 0 to +70 C DC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V5% Parameter IDD Description 3.3V Supply Current IDD 3.3V Supply Current IDD Tristate 3.3V Supply Current in Three-state Test Condition/ Notes Min. [1] 66 MHz 100 MHz [1] Typ. Max. Unit 120 160 mA 185 220 mA 5 10 mA V Logic Inputs VIL Input Low Voltage VSS-0.3 0.8 VIH Input High Voltage 2.0 VDD+0.5 V IILEAK Input Leakage Current, BUF_IN -5 +5 A IILEAK Input Leakage Current -20 +5 A 50 mV Logic Outputs (SDRAM0:9) VOL Output Low Voltage IOL = 1mA VOH Output High Voltage IOH = -1mA 3.1 IOL Output Low Current VOL = 1.5V 70 110 185 mA IOH Output High Current VOH = 1.5V 65 100 160 mA V Pin Capacitance/Inductance CIN Input Pin Capacitance (Except BUF_IN) 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH Note: 1. OE, SDATA, and SCLOCK logic pins have a 250-k internal pull-up resistor (VDD - 0.8V). Document #: 38-07243 Rev. ** Page 8 of 11 PRELIMINARY W223-02 AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V5% (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition Min. Typ. Max. Unit 0 133 MHz 4.0 V/ns fIN Input Frequency tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1.5 tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1.5 4.0 V/ns tSR Output Skew, Rising Edges 250 ps tSF Output Skew, Falling Edges 250 ps tEN Output Enable Time 1.0 8.0 ns tDIS Output Disable Time 1.0 8.0 ns tPR Rising Edge Propagation Delay 6 ns tPF Falling Edge Propagation Delay 6 ns tD Duty Cycle Zo AC Output Impedance Measured at 1.5V 45 55 15 % Ordering Information Ordering Code Package Name W223-02 Document #: 38-07243 Rev. ** G Package Type 28-Pin Plastic SSOP (209-mil) Page 9 of 11 PRELIMINARY W223-02 Package Diagram 28-Pin Shrink Small Outline Package (SSOP, 209-mil) Document #: 38-07243 Rev. ** Page 10 of 11 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY W223-02 Document Title: W223-03 SDRAM Buffer-2 DIMM Document Number: 38-07243 REV. ECN NO. Issue Date Orig. of Change ** 110508 10/31/01 SZV Document #: 38-07243 Rev. ** Description of Change Change from Spec number: 38-00980 to 38-07243 Page 11 of 11