PRELIMINARY
SDRAM Buffer -2 DIMM
W223-02
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07243 Rev. ** Revised September 17, 2001
2
Features
• Ten skew controlled CMOS outputs (SDRAM0:9)
• Supports two SDRAM DIMMs
• Ideal for high performance systems designed around
Intel’s latest Mobile chip set
•I
2C Serial configuration interface
• Skew between any two outputs is less than 250 ps
• 4 to 8 ns propagation delay
• DC to 133 MHz operation
• Single 3.3 V supply volta ge
• Low power CMOS design packaged in a 28-pin, 0.209
inch SSOP (Shrink Small Outline Package)
Key Specificati ons
Supply Voltages:...........................................VDD = 3.3V±5%
Operating Temperature: ................................... 0°C to +70°C
Input Threshold: ..................................................1.5V typical
Maximum Input Voltage:.......................................VDD + 0.5V
Input Frequency: ...............................................0 to 133MHz
BUF_IN to SDRAM0:9 Propagation Delay:..............4 to 8 ns
Output Edge Rate:................................................. >1.5 V/ns
Output Skew:............................................................ ±250 ps
Output Duty Cycle:..................................45/55% worst case
Output Impedance:...............................................15Ω typical
Output Type:................................................CMOS rail-to-rail
I2C is a trademark of Philips Corporation.
Intel is a registered trademark of Intel Corporation.
Simplified Block Diagram Pin Configuration
SSOP
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM0
Serial Port
SCLOCK
SDATA Device Control
BUF_IN
OE VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
VDD
SDRAM8
GND
VDD
SDATA
VDD
SDRAM7
SDRAM6
GND
VDD
SDRAM5
SDRAM4
GND
OE
VDD
SDRAM9
GND
GND
SCLK
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Note:
1. Internal pull-up resistor of 250K on SDATA, SCLK
and OE inputs (should not be relied upon for pulling
up to VDD).
[1]
W223-02
PRELIMINARY
Document #: 38-07243 Rev. ** Page 2 of 11
Pin Definitions
Pin Name Pin No. Pin
Type Pin Description
SDRAM0:9 2, 3, 6, 7, 2 2,
23, 26, 27,
11, 18
OSDRAM Outputs: Provid es buf fered co py of BUF_IN . The pro pagation de lay
from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are
skew controlled to within ± 250 ps of each other.
BUF_IN 9 I Clock Input: This clock input has an input threshold voltage of 1.5V (typ).
SDATA 14 I/O I2C Data Input: Data should b e presente d to this in put as describ ed in the I 2C
section of this data sheet. Internal 250-kΩ pull- up resistor.
SCLOCK 15 I I2C Clock Input: The I2C Data clock should be presented to this input as
describ ed in the I2C section of this data sheet. Internal 250-kΩ pull-up resistor .
VDD 1, 5, 10, 13,
19, 24, 28 PPower Connection: Power supply for core logic and output buffers, connected
to 3.3V supply.
GND 4, 8, 12,16,
17, 21, 25 GGround Conn ection: Conne ct all ground pins to the common sy stem ground
plane.
W223-02
PRELIMINARY
Document #: 38-07243 Rev. ** Page 3 of 11
Overview
The Cypress W223-02 is a low-voltage, ten-output clock buff-
er. Output buffer impedance is approximately 15Ω which is
ideal for driving SDRAM DIMMs.
Functional Description
Output Control Pins
Outputs three-stated when OE = 0, and toggle when OE = 1.
Outputs are in phase with BUF_IN but are phase delayed by
3 to 7ns. Outputs can also be controlled via the I2C interface.
Output Drivers
The W223-02 output buffers are CMOS type which deliver a
rail-to-rail (GND to VDD) output voltage swing into a nominal
capaci tive load. Thus , outp ut signaling is both TTL and CMOS
level compatible. Nominal output buffer impedance is 15Ω.
Operation
Data is written to the W223-02 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 1.
Table 1. Byte Writing Sequence
Byte
Sequence Byte Name Bit Sequence Byte Description
1 Sl ave Addres s 11010010 Command s the W223-02 to accept th e bits in Data By tes 0–7 fo r int er-
nal regis ter c onfi gu ration. Since other devic es may exist on the sam e
common serial data bus, it is necessary to have a specific slave address
for each potential receiver . The slave receiver address for the W223-02
is 11010010. Re gis ter sett ing w ill not b e ma de if the Slav e Ad dres s i s
not correct (or is for an alternate slave receiver).
2 Command Code “Don’t Care”Unused by the W223-02, therefore bit values are ignored (“Don’t Care).
This byte must be included in the data write sequence to maintain prop-
er byte allocation. The Command Code Byte is part of the standard
serial c ommunicat ion protocol and may be u sed when writ ing to anot h-
er addressed slave receiver on the serial data bus.
3 By te Count “Don’t Care”Unused by the W223-02, therefore bit values are ignored (“Don’t
Care”). This b yte must be inc luded in the data write sequ ence to main-
tain proper byte allocati on. The Byte Count Byte is part of the standard
serial c ommunicat ion protocol and may be u sed when writ ing to anot h-
er addressed slave receiver on the serial data bus.
4 Data Byte 0 “Don’t Care”Refer to Cypress clock drivers.
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4
9 Data Byte 5 Refer to Table 2 The data bits in thes e bytes set inte rnal W223-02 re gisters t hat control
device operation. The data bits are only accepted when the Address
Byte bit se quence is 11010010, a s note d a bo ve. Fo r description of bi t
control fu nctions, ref er to Table 2, Data B yte Serial Co nfigura tion Map.
10 Data Byte 6
11 Data Byte 7
W223-02
PRELIMINARY
Document #: 38-07243 Rev. ** Page 4 of 11
Writing Data Bytes
Each bit in the data bytes control a particular device function.
Bits are written MSB (most significant bit) first, which is bit 7. Table 2 gives the bit formats for registers located in Data Bytes
5–7.
Note:
2. At power up all SDRAM outputs are enabled and active. It is recommended to program Bits 4–7 of Byte 5 and Bits 0–3 of By te 6 to a “0” to save power and
reduce noise .
Table 2. Data Bytes 5–7 Serial Configuration Map[2]
Bit(s)
Affected Pin
Control Function
Bit Control
Pin No. Pin Name 0 1
Data Byte 5 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
7 N/A Reserved (Reserved) -- --
6 N/A Reserved (Reserved) -- --
5 N/A Reserved (Reserved) -- --
4 N/A Reserved (Reserved) -- --
3 7 SDRAM3 Clock Output Disable Low Active
2 6 SDRAM2 Clock Output Disable Low Active
1 3 SDRAM1 Clock Output Disable Low Active
0 2 SDRAM0 Clock Output Disable Low Active
Data Byte 6 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
7 27 SDRAM7 Clock Output Disabl e Low Active
6 26 SDRAM6 Clock Output Disabl e Low Active
5 23 SDRAM5 Clock Output Disabl e Low Active
4 22 SDRAM4 Clock Output Disabl e Low Active
3 N/A Reserved (Reserved) -- --
2 N/A Reserved (Reserved) -- --
1 N/A Reserved (Reserved) -- --
0 N/A Reserved (Reserved) -- --
Data Byte 7 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
7 18 SDRAM9 Clock Output Disabl e Low Active
6 11 SDRAM8 Clock Output Disable Low Active
5 N/A Reserved (Reserved) -- --
4 N/A Reserved (Reserved) -- --
3 N/A Reserved (Reserved) -- --
2 N/A Reserved (Reserved) -- --
1 N/A Reserved (Reserved) -- --
0 N/A Reserved (Reserved) -- --
W223-02
PRELIMINARY
Document #: 38-07243 Rev. ** Page 5 of 11
How To Use the Serial Data Interface
Electric al Requ irem en ts
Figure 1 ill ustrates ele ctrical char acteristic s for the serial int er-
face bus used with the W223-02. Devices send data over the
bus with an open drain logic output that can (a) pull the bus
line low , or (b) let the bus default to logic 1. The pull-up resistor
on the bus (both c lock a nd data lines) est ablish a de fau lt logi c
1. All bus devices generally have logic inputs to receive data.
Although the W223-02 is a receive-only device (no data
write-back capability), it does transmit an “acknowledge” data
pulse after each byte is received. Thus, the SDATA line can
both transm it and rec eiv e data .
The pu ll-up re sistor sh ould be si zed to mee t the rise and fall
times specified in AC parameters, taking into consideration
total bus line capacitance.
DATA IN
DATA OUT
N
CLOCK IN
CLOCK OUT
CHIP SET
(SERIAL BUS MASTER TRANSMITTER)
SDCLK SDATA
SERIAL BUS CLOCK LINE
SERIAL BUS DATA LINE
N
DATA IN
DATA OUT
CLOCK IN
CLOCK DEVICE
(SERIAL BUS SLAVE RECEIVER)
SCLOCK SDATA
N
~ 2k
Ω
~ 2k
Ω
VDD VDD
Figure 1. Serial Interface Bus Electrical Characteristics
W223-02
PRELIMINARY
Document #: 38-07243 Rev. ** Page 6 of 11
Signaling Requirements
As show n in Figure 2 valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock high (logic 1)
pulse. A transitioning data line during a clock high pulse may
be interpre ted as a s tart or s top puls e (it will be inte rpre ted as
a start or stop pulse if the start/stop timing parameters are
met).
A write se quence is initiated by a “start bit” as shown in Figure
3. A “stop bit” signifies that a transmission has ended.
As stated previously, the W223-02 sends an “acknowledge”
pulse after receiving eight data bits in each byte as shown in
Figure 4.
Sending Data to the W223-02
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon th e receipt of each da ta bit (regis ters are not double buf f-
ered). Partial transmission is allowed meaning that a transmis -
sion can be truncated as soon as the desired data bits are
transmitted (remaining registers will be unmodified). Trans-
mission is truncated with either a stop bit or new start bit (re-
start condi tio n).
t
SDATA
SCLOCK
Valid
Data
Bit
Change
of Data Allowed
Figure 2. Serial Data Bus Valid Data Bit
SDATA
SCLOCK
Start
Bit Stop
Bit
Figure 3. Serial Data Bus Start and Stop Bit
PRELIMINARY W223-02
Document #: 38-07243 Rev. ** Page 7 of 11
tSTHD
tLOW
tR
tHIGH
tF
tDSU tDHD tSP tSPSU tSTHD
tSPSU
tSPF
SDATA
SCLOCK
Figure 4.4 Serial Data Bus Write Sequence
MSB
12345678A12345678A1234SCLOCK 12345678A
11010010LSB MSB MSB LSBSDATA
SDATA
Signaling from System Core Logic
Start Condition
MSB LSB
Slave Address
(First Byte) Command Code
(Second Byte) Last Data Byte
(Last Byte)
Byte Count
(Third Byte)
Stop Condition
Signaling by Clock Device Acknowledgment Bit
from Clock Device
Figure 5.5 Serial Data Bus T imi ng Dia gram
W223-02
PRELIMINARY
Document #: 38-07243 Rev. ** Page 8 of 11
Absolute Maximum Ratings
Stresses greater than those lis ted in this ta ble may c ause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those speci fie d i n the operating se ct ion s of this specif i-
cation is not implied. Maximum conditions for extended peri-
ods ma y af fe ct r eli abi li ty.
Note:
1. OE, SDATA, and SCLOCK logic pins have a 250-kΩ internal pull-up resistor (VDD – 0.8V).
Parameter Description Rating Unit
VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V
TSTG Storage Temperature –65 to +150 °C
TBAmbient Temperature under Bias –55 to +125 °C
TAOperating Temperature 0 to +70 °C
DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5%
Parameter Description Test Condition/
Notes Min. Typ. Max. Unit
IDD 3.3V Supply Current 66 MHz[1] 120 160 mA
IDD 3.3V Supply Current 100 MHz[1] 185 220 mA
IDD Tristate 3.3V Supply Current in Three-state 5 10 mA
Logic Inputs
VIL Input Low Voltage VSS–0.3 0.8 V
VIH Input High Voltage 2.0 VDD+0.5 V
IILEAK Input Leakage Current, BUF_IN –5+5µA
IILEAK Input Leakage Current –20 +5 µA
Logic Outputs (SDRAM0:9)
VOL Output Low Voltage IOL = 1mA 50 mV
VOH Output High Voltage IOH = –1mA 3.1 V
IOL Output Low Current VOL = 1.5V 70 110 185 mA
IOH Output High Current VOH = 1.5V 65 100 160 mA
Pin Capacitance/Inductance
CIN Input Pin Capacitance (Except BUF_IN) 5 pF
COUT Output Pin Capacitance 6pF
LIN Input Pin Inducta nc e 7nH
W223-02
PRELIMINARY
Document #: 38-07243 Rev. ** Page 9 of 11
AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% (Lump Capacitance Test Load = 30 pF)
Parameter Description Test Condition Min. Typ. Max. Unit
fIN Input Frequency 0 133 MHz
tROutput Rise Edge Rate Measu red from 0.4V to 2.4V 1.5 4.0 V/ns
tFOutput Fall Edge Rate Measu red from 2.4V to 0.4V 1.5 4.0 V/ns
tSR Output Skew, Rising Edges 250 ps
tSF Output Skew, Falling Edges 250 ps
tEN Output Enable Time 1.0 8.0 ns
tDIS Output Disable Time 1.0 8.0 ns
tPR Rising Edge Propagation Delay 6 ns
tPF Falling Edge Propagation Delay 6 ns
tDDuty Cycle Measured at 1.5V 45 55 %
ZoAC Output Imped an ce 15 Ω
Ordering Information
Ordering Code Package
Name Package Type
W223-02 G28-Pin Plastic SSOP (209-mil )
W223-02
PRELIMINARY
Document #: 38-07243 Rev. ** Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypr ess Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. C ypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expe cted to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
28-Pin Shrink Small Outline Package (SSOP, 209-mil)
W223-02
PRELIMINARY
Document #: 38-07243 Rev. ** Page 11 of 11
Document Title: W223-03 SDRAM Buffer-2 DIMM
Document Number: 38-07243
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 110508 10/31/01 SZV Change from Spec number: 38-00980 to 38-07243
