Enpirion® Power Datasheet
EN5364QI 6A Pow er SoC
Volt age M ode Synchr onous
Bu ck PWM DC-DC Convert er
Wi th In tegrated Inductor
Description
The EN5364QI is a Power Supply on a Chip
(PwrSoC) DC to DC converter with integrated
inductor, PWM controller, MOSFETS, and
compensation providing the smallest possible
solution size in a 68 pin QFN module. The
switching frequency can be synchronized to an
external clock or other EN5364QIs with the
added capability of phasing multiple EN5364QIs
as desired. Other features include precision
ENABLE threshold, pre-bias monotonic start-up,
margining, and parallel operation.
EN5364QI is specifically designed to meet the
precise voltage and fast transient requirements
of present and future high-performance
applications such as set-top boxes/HD DVRs,
LAN/SAN adapter cards, audio/video equipment,
optical networking, multi-function printers, test
and measurement, embedded computing,
storage, and servers. Advanced circuit
techniques, ultra high switching frequency, and
very advanced, high-density, integrated circuit
and proprietary inductor technology deliver high-
quality, ultra compact, non-isolated DC-DC
conversion. Operating this converter requires
very few external components.
The Altera Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity
by offering greatly simplified board design, layout
and m anufac turing r equirem ents .
All Altera Enpirion products are RoHS compliant
and lead-free manufacturing environment
compatible.
Typical Application Circuit
V
OUT
V
IN
VFB
47µF
47µF
15nF
VOUT
ENABLE
AGND
SS
PVIN
AVIN
PGND
PGND
Figure 1: Typica l Appl i cation S che m atic
Features
• Integrated Inductor, MOSFETS, Controller in
a 8 x 11 x 1.85mm package
• Wide input voltage range of 2.375V to 6.6V.
• > 20W continuous output power.
• High efficiency, up to 93%.
• O utput voltage m argining
• Monotonic output voltage ramp during start-
up with pre-biased loads.
• Prec is ion Enable pin for ac c urate sequencing
of pow er c onverter s and Pow er O K s ignal.
• Programmable soft-start time.
• Soft Shutdow n.
• 4 MHz operating frequency w ith ability to
synchronize to an external system clock or
other E N5364’s.
• Program m able phas e delays between
synchronized units to allow reduction of
input ripple.
• Master/slave configuration for paralleling
multiple EN5364’s for greater power output.
• Under Voltage Lockout, Over-c urrent, Short
Cir c uit, and Ther m al Protec tion
• RoHS compliant, MSL level 3, 260C reflow.
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03544 October 11, 2013 Rev E
EN5364QI
Applications
•Point of load r egulation for low -power
processors, network processors, DSPs,
FPGAs , and ASIC s
•Low voltage, dis tributed pow er ar c hitec tures
with 2.5V, 3.3V or 5V, 6V rails
•Computing, broadband, networking,
LAN/WAN, optical, tes t & m eas urem ent
•A/V, high density cards, storage, DSL, STB,
DVR , DTV, Indus trial PC
•Beat frequency sensitive applications
•Applications requiring m onotonic s tart-up w ith
pre-bias
•Ripple voltage sensitive applications
•Nois e s ens itive applic ations
•Pin compatible with EN 5394QI (9A)
Ordering Information
Part Num ber
Te m p Ra ting
(°C)
Package
EN5364QI
-40 to +85
68-pi n QF N T&R
EVB-EN5364QI
QF N E valuati on B oard
Pin Configuration
PGND
PGND
PGND
PGND
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
NC
NC
PGND
PGND
PGND
PGND
PGND
VSENSE
MAR2
MAR1
S_DELAY
SS
OCP_ADJ
EAOUT
VFB
AGND
POK
AVIN
ENABLE
EN_PB
M/S
EN5364QI
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC(SW)
NC(SW)
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PVIN
66
68
67
63
65
64
60
62
61
57
59
58
54
56
55
53
52
50
51
18
16
17
21
19
20
24
22
23
27
25
26
30
28
29
31
32
34
33
S_IN
S_OUT
NC
NC
NC
NC
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
1
4
3
6
5
8
7
10
9
12
11
14
13
15
2
49
46
47
44
45
42
43
40
41
38
39
36
37
35
48
69
PGND
Thermal Pads
70
PGND
Figure 2: P inout Diagra m (Top V i ew). All perim eter pi ns m ust be soldere d to PCB.
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03544 October 11, 2013 Rev E
EN5364QI
Pin Descriptions
PIN
FUNCTION
1-4,
27-33,
64-68
PGND
I nput/Output power ground. Connect these pi ns to the groun d electr ode of the input
and output fi lter capacitor s. S ee VOU T and PVI N descriptions for m ore details.
5-13 VOUT
Regulated converte r outp ut. Conn ect to the load, and place output filter capacitor (s)
between these pins and PGN D pins 1-4 and 64-68.
14-24,
44-47 NC
NO CON NECT: These pins m ust be soldered to P CB but not be electrically connecte d
to each other or to any external signal, vol tage, or grou nd. These pins m ay be
connected interna lly. Failur e to follow this guideline m ay result in device dam age.
25-26 NC(SW)
NO CON NECT: These pins are internall y conne cte d to the com m on switching node of
the internal M OS FETs. They must be soldered to PCB but not be electrically
connected to any external signal, grou nd, or voltage. Fa il ure to follow this guideline
m ay result in devi ce dam age.
34-43 PVIN
I nput power supply. Connect to input power supply, place input filter capacitor(s)
between these pins and PGND pins 27-33.
48 S_OUT
Clock Output. Depending on the m ode, either a clock signal or the PWM signal is
output on thi s pin. These signals are delaye d by a tim e that i s related to the resistor
connected between S_DELAY and AGND. Leave this pin floating if not needed.
49 S_IN
Clock I nput. Depending on the m ode, this pin accepts either an input clock to
synchronize the internal switching freque ncy or the S_OUT signal from anothe r
EN5364QI. Leave this pin floating if it is not used.
50 M/S
This i s a Ternary I nput. Floating the pin disables par all el oper atio n. A low level
confi gures the device as M aster and a H igh level configures the device as a slave.
51 EN_PB
This i s the E nable P re-Bias I nput. W hen this pin is pulled high, the Device will support
m onotonic start-up unde r a pre-biased load. The re is a 150k
Ω
pull-d own on this pin.
52 ENABLE
This i s the Device Enable pin. A high level enables the device while a low level
disables the devi ce.
53
I nput power supply for the controller. Needs to be connected to VIN at a quiet poi nt.
54 POK
Power OK is an open drain transistor for pow er system state indicat ion. POK is a
logic hi gh w hen VOU T is with -10% to +20% of VOU T nom inal. B eing an open drain
output allows several devices to be w ired to logically AND the function. Size pull-up
resistor to lim it current to 4m A w hen POK is low.
55
Ground return for the contro ller. Needs to be connecte d to a quiet groun d.
56 VFB
External Feedback i nput. The feed ba ck loop is closed throug h this pin. A voltage
divider at V OUT is used to set the output voltage. The m id-point of the divider is
connected to VFB. The control loop reg ulates to m ake the VFB node voltage 0.6V .
57
Optional E rror Am plifier output. A llows for custom ization of the control loop.
58 OCP_ADJ
When this pin i s pull ed to AGND, the overcurrent pro tect ion trip poin t is increased by
approx im ately 30% . Leave floating for defau lt OCP thresho ld (see E lectrical
Characteristics table) . Tie this pin to A GND for pin com patibility with the EN5394.
59 SS
A soft-start capacitor is connected betw een this pin to A GND. The value of the
capacitor controls the soft-star t interval and startup tim e.
60 S_DELAY
A resistor is connected between this pin and AGN D . The value of the resistor contr ols
the delay in S_OUT. This pin can be left floating if the S _OUT function is not used.
61-62 MAR1,
MAR2
These are 2 ternary input pins. Each pin can be a logical Lo, Logical Hi or Float
condition. 7 of the 9 states are used to m odulate the output volta ge by 0%, ±2.5%,
±5% or ±10%. The 8th state is used to by-pass the delay in S_OUT. See Functional
Description section.
63
This pi n senses VOUT when the device is placed in the Back-feed (or P re-bias) m ode.
69, 70 PGND
Device therm al pads to be connected to the system gnd plane. See Layou t
Recom m endations section.
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03544 October 11, 2013 Rev E
EN5364QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond
recommended operating conditions is not implied. Stress beyond absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended per iods m ay affec t devic e reliability.
PARAMETER
MIN
MAX
UNITS
Voltages on PVIN , AVIN , VO U T
-0.5
7.0
V
Voltages on VSENSE, ENABLE, EN_PB, POK,
-0.5
VIN + 0.3
V
Voltages on VFB, EAOUT, SS, S_IN, S_OUT, OCP_ADJ
-0.5
2.7
V
Voltages on MAR1, MAR 2, M/S
-0.5
3.6
V
Storage T emperature Range
-65
150
°C
Maximum Operating Junc tion T emperature
150
°C
Ref low T emp, 10 Sec, MSL3 JEDEC J -STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MAX
UNITS
I nput Voltage Range
VIN
6.6
V
Output Voltage Range
VOUT
VIN – VDO†
V
Output Current
ILOAD
6
A
Operating Ambient T emperature
TA
+85
°C
Operating Junction T emperature
TJ
+125
°C
† VDO (drop-out voltage) is defined as (ILOAD x Dropout Resistance). Pl ease see Elect rical Characteri stics table.
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
T hermal Resistance: Junction to A mbie nt (0 LFM)††
θJA
16
°C/W
T hermal Resistance: Junction to Cas e
θJC
1
°C/W
Thermal Shutdown T rip Point
TSD
+150
°C
Thermal Shutdown T rip Point Hysteresi s
TSDH
20
°C
†† Based on a f our-layer board and proper thermal design in line with JEDEC EI J/JESD 51 Standards.
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03544 October 11, 2013 Rev E
EN5364QI
Electrical Characteristics
NO TE: VIN=5.5V over operating tem perature r ange unles s otherw is e noted.
Typic al values are at TA = 25°C.
PARAMETER
SYMBOL
COMMENTS
MIN
TYP
MAX
UNITS
I nput V oltage
VIN
2.375
6.6
V
Under Voltage Lock out
threshold
V
UVLOR
VUVLOF
V
IN
Increasing
VIN Decreasing
2.2
2.1
V
Shut-Dow n S upply
Current
IS ENABLE=0V 250 µA
Feedback Pin Voltage VFB
2.375V ≤ VIN ≤ 6.6V,
ILOAD = 1A; TA = 2 5°C
0.588 0.600 0.612 V
Feedback Pin I nput Leaka ge
Current
1
IFB -5 5 nA
Line Regulation
∆VOUT_LINE
2.375V ≤ VIN ≤ 6.6V
0.035
%/V
Load Regulation
∆VOUT_LOAD
0A ≤ ILOAD ≤ 6A
−0.04
%/A
Tem perature Regulation
∆VOUT_TEMP
-40°C ≤ TEMP ≤ 85°C
0.001
%/°C
VOUT Rise Time TRISE
Measured from w hen V
IN
≥ V
UVLOR
& E N A BLE pin crosses logic high
threshold. (4.7nF ≤ CSS ≤ 100nF)
CSS x
65kΩ
Rise Tim e Accuracy1
∆TRISE
4.7nF ≤ CSS ≤ 100nF
-25
+25
%
Output D ropout
Voltage1
Resistance
1
VDO
RDO
VINMIN – VOUT at Full Load
I nput to Output Resistance
240
40
480
80
mV
mΩ
Maximum Continuous
Output C urrent
2
IOUT_MAX_CONT 6 A
Current Lim it Threshold
IOCP
OCP_ ADJ floating
10.5
A
ENABLE pin :
Disabl e Threshold
Enable Threshold
VDISABLE
VENABLE
2.375V ≤ V
IN
≤ 6.6V
ENABLE pin logic low
ENABLE pin logic high
1.00
1.0
1.30
V
ENABLE Lock-out tim e tENLO
Tim e for device to re-enable after
a falling edge on ENAB LE pin
2 ms
ENABLE Pin Input
Current
IENABLE VIN = 5.5V 50 µA
Switching Frequency
FSWITCH
Free Runni ng frequ ency
4
MHz
External S_I N Clock
Frequency Lock Range
FPLL_LOCK
Frequency Range of S_I N
I nput C lock
3.6 4.4 MHz
S_IN Threshold – Low
VS_IN_LO
S_IN Clock low level
0.8
V
S_IN Threshold – High
VS_IN_HI
S_I N Clock high level
1.8
2.5
V
S_OUT Threshold – Low
VS_OUT_LO
S_OUT Clock low level
0.5
V
S_OUT Threshold – High
VS_OUT_HI
S_OUT Clock high l evel
1.8
V
S_I N Duty Cycle for
External Synchroniz ation
1
SYDC_SYNC M /S Pi n Float or Low 20 80 %
S_I N Duty Cycle for
Parallel Operation
1
SYDC_PWM M/ S Pin High 10 90 %
Phase Delay vs. S_Delay
Resistor value ΦDEL
Delay i n ns / kΩ
Delay i n phase angle / kΩ -
@ 4MHz switching frequency
2
3
ns
°
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03544 October 11, 2013 Rev E
EN5364QI
Phase Delay between
S_I N and S_OU T1 ΦDEL
Phase delay program m able via
resistor connected from S _Delay
to AGN D.
20 150 ns
Phase Delay between
S_I N and S_OU T
1
ΦDEL
Delay By-Pass M ode
(M AR1 floating, M A R2 high)
10 ns
Phase Delay Accuracy1
-20
20
%
Pre-Bi as Level VPB
Allowable Pr e-Bi as as a fraction
of program m ed output voltage
(subject to a m inim um of 300m V)
20 85 %
Non-Monotonicity
VPB_NM
Allowable non m onotonicity
50
mV
POK Low er Threshold as
a percent of V OUT
3
POKLT
V
OUT
rising
VOUT falling
92
90
%
POK U pper Threshold as
a percent of V OUT
3
POKUT
V
OUT
rising
VOUT falling
120
115
%
POK Falling Edge
Deglitch Delay
4
60 µs
POK Output Low Voltage
VPOKL
With 4m A current sink into P OK
0.4
V
POK Output High V oltage
VPOKH
2.375V ≤ VIN ≤ 6.6V
VIN
V
Ternary P in Logic Low5
VT-Low
Tie pin to GND
0
V
Ternary P in Logic High5 VT-High Pull up to VIN through an ex ternal
resistor REXT – see Figure 5.
see Input
Current
below
Ternary P in I nput Current
(see Figure 5)5 ITERN
V
IN
= 2.375V, R
EXT
= 3.32kΩ
VIN = 3.3V, REXT = 15kΩ
VIN = 5.0V, REXT = 24.9kΩ
VIN = 6.6V, REXT = 49.9k
Ω
50
70
100
85 µA
Binary Input Logic Low
Threshold
6
VB-Low 0.8
Binary Input Logic High
Threshold
6
VB-High 1.8
NOTES:
1. Param eter guarant eed by design.
2. Maxi m um output current m ay need t o be de-rat ed, based on operat i ng condi ti on, to m eet TJ requirements.
3. POK threshold when VOUT is rising is nominally 92%. This thresh old is 90% when VOUT is falling. After crossing the
90% level, there is a 256 clock cycle (~50us) delay bef ore POK is de-as sert ed. The 90%, 92%, 115%, and 120%
l evel s are nom i nal values. Expect these threshol ds to vary by ± 3%.
4. O n t he fall i ng edge of VOUT bel ow 90% of program m ed value, POK response i s del ayed for t he durati on of the
degl itch del ay ti m e. Any VOUT gli tch s horter t han the degl i tch ti m e i s i gnored.
5. M/S, MAR1, and MAR2 are ternary. T ernary pins have three logic levels: high, float, and low. These pi ns are onl y
meant to be strapped to VIN through an external res i stor, strapped to GND, or l eft fl oat i ng. Thei r s tate cannot be
changed whil e the devi c e i s on.
6. Bi nary i nput pi ns are E N_P B and O CP _A DJ.
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03544 October 11, 2013 Rev E
EN5364QI
Typical Performance Characteristics
Effi cien cy V IN = 3.3V
VOUT (From top to bottom ) = 2.5, 1.8, 1.2, 1.0V
Effi cien cy V IN = 5.0V
VOUT (F ro m to p to b o ttom) = 3.3, 2.5, 1.8, 1.2, 1.0V
Output Ri ppl e: VIN = 3.3V, VOUT = 1.2V, I out = 6A
CIN = 2 x 22
µ
F/1206, COUT = 47
µ
F/1206 + 10u F / 0805
Output Ri ppl e: VIN = 3.3V, VOUT = 1.2V, I out = 6A
CIN = 2 x 22
µ
F/1206, COUT = 47
µ
F/1206 + 10u F / 0805
Output Ri ppl e: VIN = 5.0V, VOUT = 1. 2V, I out = 6A
CIN = 2 x 22
µ
F/1206, COUT = 47
µ
F/1206 + 10u F / 0805
Output Ri ppl e: VIN = 5.0V, VOUT = 1. 2V, I out = 6A
CIN = 2 x 22
µ
F/1206, COUT = 47
µ
F/1206 + 10u F / 0805
V
IN
= 3.3V
30
40
50
60
70
80
90
0123456
Load (Amps)
Efficiency (%)
VIN = 5V
20
30
40
50
60
70
80
90
0 1 2 3 4 5 6
Load (Amps)
Efficiency (%)
20 MHz BW limit
500 MHz BW
20 MHz BW limit
500 MHz BW
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03544 October 11, 2013 Rev E
EN5364QI
Loa d Transient: VIN = 5.0V , VOUT = 1.2V
Ch .1 : VOUT, Ch .4: ILOAD 0
↔
6A (slew rate ≥ 10A/µS)
CIN
≈
50
µ
F, COUT
≈
50
µ
F
RA = 150k
Ω
, CA = 27pF (see Fi gure 4)
Loa d Transient: VIN = 3.3V, VOUT = 1.2V
Ch .1 : VOUT, Ch .4: ILOAD 0
↔
6A (slew rate ≥ 10A/µS)
CIN
≈
50
µ
F, COUT
≈
50
µ
F
RA = 100k
Ω
, CA = 47p F (se e Fi gure 4)
Power Up/ Down at No Load: VIN/VOUT = 5.0V/1.2V,
15nF soft-star t cap acito r ,
Ch.1: ENABL E, Ch .2: V OUT, Ch .3; POK
Power U p/ D own into 0 . 2
Ω
load: VIN/VOUT = 5.0V/1.2V,
15nF soft-star t cap acito r ,
Ch.1: ENABL E, Ch .2: V OUT, Ch .3; P O K
Delay vs . S_Delay R es istance
ENABLE Lockout Ope ration
Ch .1 : ENABLE, Ch2: V OUT
Delay vs. S_Delay Resi stance
0
20
40
60
80
100
120
140
160
180
020 40 60 80 100
S _ Delar R ( ko h m)
Del ay (ns)
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03544 October 11, 2013 Rev E
EN5364QI
Block Diagram
(+)
(-)
Error
Amp
V
OUT
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
PLL / Sawtooth
Generator
(+)
(-)PWM
Comp
PVIN
ENABLE
Compensation
Network
Bandgap
Reference
PGND
VFB
EAOUT
S_OUT
SS Reference
Voltage
selector
Over Voltage
power
Good
Logic POK
S_IN
MAR1 MAR2
EAOUT
EN_PB
Digital I/O
M_S To PLL
MAR1/2
NC(SW)
Figure 3. Syste m B lock Diagram
Functional Description
Synchr onous Buck Conver ter
The EN5364QI is a synchronous, programmable
power supply with integrated power MOSFET
switches and integrated inductor. The nominal
input voltage range is 2.375-6.6V. The output
voltage is programmed using an external resistor
divider network. The feedback control loop is a
type III, voltage-mode, and the device uses a
low-noise PWM topology. Up to 6A of continuous
output current can be drawn from this converter.
The 4MHz operating frequency enables the use
of s m all-s iz e input and output c apac itors .
The power supply has the following protection
features:
• Over-c urrent pr otec tion w ith hic c up m ode.
• Short C irc uit protection.
• Thermal shutdown with hysteresis.
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03544 October 11, 2013 Rev E
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• Under-voltage lockout circuit to disable the
converter output when the input voltage is
less than approximately 2.2V
En able Operation
The ENABLE pin provides a means to start
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted
(high) the device will undergo a normal soft start.
A logic low will disable the converter. A logic low
will power down the device in a controlled
manner and the device is subsequently shut
down. The device will remain shut-down for the
duration of the ENABLE lockout time (see
Electrical Characteristics Table). If the ENABLE
signal is re-asserted during this time, the device
will power up with a normal soft-start at the end
of the ENABLE loc kout tim e.
The Enable threshold is a precision Analog
voltage rather than a digital logic threshold.
Precision threshold along with choice of soft-start
capacitor helps to accurately sequence multiple
power s upplies in a s ys tem .
Frequency Synchroniz ation
The switching frequency of the DC/DC converter
can be phase-locked to an external clock source
to move unwanted beat frequencies out of band.
To avail this feature, the ternary input M/S pin
should be floating or pulled low. The internal
switching clock of the DC/DC converter can then
be phase locked to a clock signal applied to S_IN
pin. An activity detector recognizes the presence
of an external clock signal and automatically
phase-locks the internal oscillator to this external
clock. Phase-lock will occur as long as the input
clock frequency is within ±10% of the free
running frequency (see Electrical Characteristics
table). When no clock signal is present, the
device reverts to the free running frequency of
the internal oscillator. The external clock input
may be swept between 3.6 MHz and 4.4 MHz at
repetition r ates of up to 10 kHz in or der to r educ e
EMI frequency components.
Master / Slave Parallel Operation
Multiple EN5364QI devices may be connected in
parallel in a Master/Slave configuration to handle
load currents greater than device maximum
rating. The device is set in Master mode by
pulling the ternary M/S pin low or in Slave mode
by pulling M/S pin high to VIN through an external
resistor. When this pin is in Float state, parallel
operation is not possible. In master mode, the
internal PWM signal is output on the S_OUT pin.
This PWM signal from the Master can be fed to
one or more Slave devices at its S_IN input. The
Slave device acts like an extension of the power
FETs in the Master. As a practical matter,
paralleling more than 4 devices may be very
difficult from the view point of maintaining very
low im pedanc e in VIN and VOUT lines.
The table below summarizes the different
configurations for the S_IN and S_OUT pins
depending on the c ondition of the M/S pin:
When M/S
pin is:
High (Slave)
Low (Master)
Float
S_IN input
should be:
S_OUT f rom
Master
External Sync input if
needed (NC for internal
clock)
S_OUT is
equal to
(s ubject to
S_DELAY):
Same duty
cycl e a s
S_IN
Same duty
cycl e a s
internal PWM
S_IN or
internal
clock
Pleas e c ontac t Altera Power Applications support
for m or e inform ation on Mas ter / Slave operation.
Phase Del ay
In all cases, S_OUT can be delayed with respect
to internal switching clock or the clock applied to
S_IN. Multiple EN5364QI devices on a system
board may be daisy chained to reduce or
eliminate input ripple as well as avoiding beat
frequency components. The EN5364QIs can all
be phase locked by feeding S_OUT of one
device into S_IN of the next device in a daisy
chain. All the switchers now run at a common
frequency. The delay is controlled by the value of
a resistor connected between S_DELAY and
AGND pins. The magnitude of this delay as a
function of S_DELAY resistor is shown in the
Electrical Characteristics table. See Figures 6
and 7 for an exam ple of us ing phas e delay.
Margining
Using MAR1 and MAR2 pins, the nominal output
10 www.altera.com/enpirion
03544 October 11, 2013 Rev E
EN5364QI
voltage can be increased / decreased by 2.5, 5
or 10% for system compliance, reliability or other
tes ts . The PO K thres hold voltages s c ale w ith the
margined output voltages. The following table
provides the pos s ible c om binations :
MAR1
MAR2
Output Modulation
Float
Float
0%
Low
Low
-2.5%
High
Low
+2.5%
Low
High
-5%
High
High
+5%
Low
Float
-10%
High
Float
+10%
Float
High
0%, Delay Bypass
Float
Low
Reserved
N ote: Low mea ns t ie to GND. Hig h means tie to VIN
as shown in Figure 5.
As shown above, when MAR1 is floating, and
MAR2 is high, the devic e enter s the delay
bypas s m ode. In this m ode, the delay fr om the
internal clock or S_IN to S_OU T is almost
eliminated (see Electrical Characteristics table).
Soft-Start Operation
The SS pin in conjunction with a small external
capacitor between this pin and AGND provides
the soft start function to limit the in-rush current
during start-up. During start-up of the converter
the reference voltage to the error amplifier is
gradually increased to its final level as an internal
current source of typically 10uA charges the soft
start capacitor. The typical soft-start time for the
output to reach regulation voltage, from when
AVIN > VUVLO and ENABLE c ros s es its logic high
threshold, is given by:
TSS = (CSS * 65KΩ) ± 25%
Where the soft-start time TSS is in seconds and
the soft-start capacitance CSS is in Farads.
Typically, around 15nF is recommended. The
soft-start capacitor should be between 4.7nF and
100nF. A proper choice of SS capacitance can
be used advantageously for power supply
s equenc ing us ing the prec is ion Enable thres hold.
During a soft-start cycle, when the soft-start
capacitor voltage reaches 0.60V, the output has
reached its programmed regulation range. Note
that the soft-start current source will continue to
charge the SS capacitor beyond 0.6V. During
normal operation, the soft-start capacitor will
c harge to a final value of ~ 1.5V.
Soft-Shutdown Operation
When the Enable signal is de-asserted, the soft-
start capacitor is discharged in a controlled
manner. Thus the output voltage ramps down
gradually. The internal circuits are kept active for
the duration of soft-shutdown, thereafter they are
deactivated.
Pre-Bias Operation
When EN_PB is asserted, the device will support
a monotonic output voltage ramp if the output
capacitor is charged to a pre-bias level.
Proprietary circuit ensures the output voltage
ramps monotonically from pre-bias voltage to the
programmed output voltage. Monotonic start-up
is guaranteed by design for pre-bias voltages
between 20% and 85% of the programmed
output voltage. This feature is not supported
when EN ABLE is tied to VIN.
P OK Op e r a tio n
The POK signal indicates if the output voltage is
within a specified range. The POK signal is
asserted when the rising output voltage crosses
92% (nominal) of the programmed output
voltage. POK is de-asserted ~50us (256 clock
cycles) after the falling output voltage crosses
90% (nominal) of the programmed voltage. POK
is also de-asserted if the output voltage exceeds
120% of the programmed output. If the feedback
loop is broken, POK will remain de-asserted
(output < 92% of programmed value), and the
output voltage will equal the input voltage. If
however, there is a short across the PFET, and
the feedbac k is in plac e, PO K w ill be de-asserted
as an over voltage condition. The power NFET is
also turned on, resulting in a large input supply
current. This in turn is expected to trip the OCP
of the EN5364QI input pow er s upply.
POK is an open drain output. It requires an
external pull up. Multiple EN5364QI’s POK pins
may be connected to a single pull up. The open
drain NFET is designed to sink up to 4mA. The
11 www.altera.com/enpirion
03544 October 11, 2013 Rev E
EN5364QI
pull-up resistor value should be chosen
accordingly for when POK is logic low.
Input Under-Voltage Lock-Out (UVLO)
When the input voltage is below a required
voltage level (VUVLO) for normal operation, the
converter switching is inhibited. The lock-out
threshold has hysteresis to prevent chatter.
UVLO is implemented to ensure that operation
does not begin before there is adequate voltage
to proper ly bias all internal c irc uitry.
Over-Current Protection (OCP)
The current limit and short-circuit protection is
achieved by sensing the current flowing through
a sense P-FET. When the sensed current
exceeds the current limit, both NFET and PFET
switches are turned off. If the over-current
condition is removed, the over-current protection
circuit will re-enable the PWM operation. If the
over-current condition persists, the circuit will
c ontinue to pr otec t the devic e.
The OCP trip point is nominally set to 175% of
maximum rated load. In the event the O C P c irc uit
trips, the device enters a hiccup mode. The
device is disabled for ~10msec and restarted
with a normal soft-start. This cycle can continue
indefinitely as long as the over current condition
persists. During soft-start at power up or fault
recovery, the hiccup mode is disabled and the
device has cycle-by-c yc le c urrent lim iting.
Thermal Overload Protection
Thermal shutdown will disable operation when
the Junction temperature exceeds approximately
150ºC. Once the junction temperature drops by
approximately 20ºC, the converter will re-start
with a norm al s oft-start.
Compensation
The EN5364 uses of a type III compensation
network. Most of this network is integrated.
However a phase lead capacitor is required in
parallel with upper resistor of the external divider
network (see Figure 4). This network results in a
wide loop bandwidth and excellent load transient
performance. It is optimized for around 50μF of
output filter capacitance at the voltage sensing
point. Additional decoupling capacitance may be
placed beyond the voltage sensing point outside
the control loop. Voltage-mode operation
provides high noise immunity at light load.
Further, voltage-mode control provides superior
impedance matching to ICs processed in sub
90nm technologies.
In exceptional cases modifications to the
compensation may be required. The EN5364QI
provides the capability to modify the control loop
response to allow for customization for specific
applications. For more information, contact Altera
Power Applications support.
Application Information
Output Voltage Programming
The EN5364 output voltage is determined by the
voltage presented at the VFB pin. This voltage is
s et by w ay of a res is tor divider between VOUT and
AGND with the midpoint going to VFB. A phase
lead capacitor CA is also required for stabilizing
the loop. Figure 4 shows the required
components and the equations to calculate their
values. Please note the equations below are
written to optimize the control loop as a function
of input voltage.
Figure 4: Out put v olt age resist or divid e r an d ph ase-
lead capacit or calcul atio n. The equations need t o be
f ollowe d in t he or der w ri t ten ab ov e.
VOUT
RACA
RBVFB
−
×
=
Ω
×
=
Ω×=
−
nominal
0.6V is
value. calculated than lower value standard closest to down C Round
)F/ in /R(C
) in (value
A
AA
FB
FBOUT
AFB
B
A
A
A
V
VV RV
R
R
C
VinR
)(
1072.4
000,30
6
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03544 October 11, 2013 Rev E
EN5364QI
Inpu t Cap acitor S electio n
The EN5364QI requires between 20-40uF of
input capacitance. Low ESR ceramic capacitors
are required with X5R or X7R dielectric
formulation. Y5V or equivalent dielectric
formulations must not be used as these lose
capacitance with frequency, temperature and
bias voltage.
In some applications, lower value ceramic
capacitors may be needed in parallel with the
larger capacitors in order to provide high
frequency decoupling.
Recommended Input C apacitors
Description
MFG
P/N
10uF , 10V, 10%
X7R , 1206
(2-4 capac itor s needed )
Murata
GRM31CR71A106KA01L
Taiyo Yud e n
LMK316B7106KL-T
22uF , 10V, 20%
X5R , 1206
(1-2 capac itor s needed )
Murata
GRM31CR61A226ME19L
Taiyo Yud e n
LMK316BJ226ML-T
47uF , 6.3V, 20%
X5R , 1206
( 1 c apacitor need ed)
Murata
GRM31CR60J476ME19L
Taiyo Yud e n JMK212BJ476ML-T
Output C apacitor Selection
The EN5364 has been optimized for use with
about 50µF of output filter capacitance. Up to
100µF can be placed at the voltage sensing
point. Additional capacitance may be placed
beyond the voltage sensing point outside the
control loop. For the output filter, low ESR X5R or
X7R ceramic capacitors are required. Y5V or
equivalent dielectric formulations must not be
used as these lose capacitance with frequency,
tem per ature and bias voltage.
Recommended Output C apacitors
Description
MFG
P/N
47uF , 6.3V, 20%
X5R , 1206
( 1 c apacitor need ed)
Murata
GRM31CR60J476ME19L
T aiyo Yuden
JMK212BJ476ML-T
10uF , 6.3V, 10%
X5R , 0805
( Optional 1 capacit or in
par allel w ith 47u F above )
Murata
GRM21BR60J106KE19L
T aiyo Yuden JMK212BJ106KG-T
Output ripple voltage is primarily determined by
the aggregate output capacitor impedance. At
the 4MHz switching frequency, the capacitor
impedance, denoted as Z, is comprised mainly of
effective series resistance, ESR, and effective
series inductance, ESL:
Z = ESR + ESL.
Placing multiple capacitors in parallel reduces
the impedance and hence will result in lower
ripple voltage.
nTotal
ZZZZ 1
...
111
21
+++=
Typical ripple versus capacitor arrangement is
given below:
Out put Capaci t or
Configuration
Typical Out pu t R ippl e ( mVp-p)
(as mea sure d on EN5364QI
Eva l uation Boa rd)
†
1x47uF
30mV
1x47uF + 1x10uF
15mV
† 20 MHz bandwidth limit
Ternary Pin Inputs
The three ternary pins MAR1, MAR2, and M/S
have three possible states. In the Low state, the
pins are to be tied to GND. In the floating state,
nothing is to be connected to the pins. In the
High state, they are to be tied to VIN through an
external resistor REXT in order to limit the input
current to the pin (see Figure 5). The Electrical
Characteristics table lists, as a function of VIN,
some recommended values for REXT, and the
resulting input currents.
Frequency Sync & Phase Del ay
The EN5364 can be synchronized to an external
clock source or to another EN5364 in order to
eliminate unwanted beat frequencies.
Furthermore, two or more synchronized
EN5364’s can have a programmable phase
delay with res pec t to eac h other to m inim iz e input
voltage ripple and noise. An example of
synchronizing three EN5364’s with approximately
equal phase delay between them is shown in
Figures 6 and 7. The lowest allowable value for
the S_DELAY resistor is 10kΩ.
Power Up/Down Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
be powered when AVIN is off. During power
13 www.altera.com/enpirion
03544 October 11, 2013 Rev E
EN5364QI
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements.
Figure 6: E xamp le of synchronizing mu lti ple E N5364QIs in a daisy chain with phas e delay.
Figure 7: E xamp le of a possible way to sy nchroni z e an d use delays adv ant age o usly t o minim i ze input rippl e .
R1 ~ 39k
Ω
, R 2 ~ 33k
Ω
. ( Re f er t o Figur e 6 f or R 1 and R2.) R3 does not mat te r in this case.
Rext
R1
100k
R2
100k
R3
3k
D1
2.5V
VIN
AGND
To Gat es
IC Package
Vf ~ 2V
250
X1
EN5364
P/AVIN
P/AGND
VFB
S_IN
VOUT
S_OUT
S_DELAY
X1_1
EN5364
P/AVINP/AGND
VFB
S_IN
VOUT
S_OUT
S_DELAY
X1_2
EN5364
P/AVINP/AGND
VFB
S_IN
VOUT
S_OUT
S_DELAY
VIN
R1 R2 R3
GND
R4
R5
C1
OUT1
R6
R7
C2
OUT2
R8
R9
C3
OUT3
EXT_CLK
VDRAIN- 1
VDRAIN- 2
VDRAIN- 3
Delay ~ 140°
Delay ~ 120°
Figure 5: Equivalen t circuit of a tern ary pin
( MA R1 , MA R2 , or M/S) inp ut buf fe r. To get a
logic H igh on a te rnary inpu t , pul l the pi n t o VIN
t hrough an ext ernal resist or REXT. See E lectrical
Characteris tics t able for s ome rec omm ended
REXT values as a func tion of VIN and t he re sulti ng
input curr ent s.
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03544 October 11, 2013 Rev E
EN5364QI
Layout Recommendations
Fi gure 8: Critica l Com ponents and Laye r 1 Coppe r for Mi ni m um Footpri nt
Figure 8 above shows critical components and
layer 1 traces of the recommended EN5364
layout for minimum footprint with ENABLE tied
to VIN. Alternate ENABLE configurations, and
other small signal pins need to be connected
and routed according to specific customer
application. Please see the Gerber files at
www.altera.com/enpirion for exact dimensions
and other layers .
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EN5364QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EN5364QI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the c apac itors .
Recommendation 2: The system ground
plane referred to in recommendations 2 and 3
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the
converter and the input/output c apac itor s .
Recommendation 3: The large and small
thermal pads underneath the component must
be connected to the system ground plane
through as many vias as possible. The drill
diameter of the vias should be 0.33mm, and
the vias must have at leas t 1 oz . c opper plating
on the inside wall, making the finished hole
size around 0.20-0.26mm. Do not use thermal
reliefs or spokes to connect the vias to the
ground plane. This connection provides the
path for heat dissipation from the converter.
Pleas e s ee figures : 8, 9, and 10.
Recommendation 4: Multiple small vias (the
same size as the thermal vias discussed in
recommendation 3) should be used to connect
ground terminal of the input capacitor and
output capacitors to the system ground plane.
It is preferred to put these vias along the edge
of the GND copper closest to the +V copper.
These vias connect the input/output filter
capacitors to the GND plane, and help reduce
parasitic inductances in the input and output
c urrent loops .
Recommendation 5: AVIN is the power supply
for the small-signal control circuits. It s hould be
connected to the input voltage at a quiet point.
In Figure 8 this connection is made at the input
capacitor.
Recommendation 6: The layer 1 metal under
− RA and R B are voltage
programming resistors.
− CA is used for loop
compensation.
− CSS is the soft-start
capacitor.
− AGND via is also a test point.
− Test point added for EAOUT.
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03544 October 11, 2013 Rev E
EN5364QI
the device must not be more than shown in
Figure 8. See the section regarding exposed
metal on bottom of package. As with any
switch-mode DC/DC converter, try not to run
sensitive signal or control lines underneath the
converter package on other layers.
Recommendation 7: The VOUT sense point
should be just after the last output filter
capacitor. Keep the sense trace short in order
to avoid nois e c oupling into the node.
Recommendation 8: Keep R A, CA, and RB
c los e to the VFB pin (s ee Figures 4 and 8).
The VFB pin is a high-impedance, sensitive
node. Keep the trac e to this pin as short as
possible. Whenever pos s ible, c onnec t R B
directly to the A GND pin instead of going
through the GND plane.
Thermal Considerations
The Altera Enpirion EN5364QI DC-DC
converter is packaged in an 11 x 8 x 1.85mm
68-pin QFN package. The QFN package is
constructed with copper lead frames that have
exposed thermal pads. The recommended
maximum junction temperature for continuous
operation is 125°C. Continuous operation
above 125°C will reduce long-term reliability.
The device has a thermal overload protection
circuit designed to shut it off at an approximate
junction temperature value of 150°C.
The silicon is mounted on a copper thermal
pad that is exposed at the bottom of the
package. There is an additional thermal pad in
the corner of the package which provides
another path for heat flow out from the
package. The thermal resistance from the
s ilic on to the expos ed therm al pads is ver y low .
In order to take advantage of this low
resistance, the exposed thermal pads on the
package should be soldered directly on to a
copper ground pad on layer 1 of the PCB. The
PCB then acts as a heat sink. In order for the
PCB to be an effective heat sink, the device
thermal pads should be coupled to copper
ground planes using multiple vias (refer to
Layout Recommendations section).
The junction temperature, TJ, is c alc ulated from
the ambient temperature, TA, the device power
dissipation, PD, and the device junction-to-
ambient thermal resistance, θJA in °C/W:
TJ = TA + (PD)(θJA)
The junction temperature, TJ, can also be
expressed in terms of the device case
temperature, TC, and the device junction-to-
case thermal resistance, θJC in °C/W, as
follows: TJ = TC + (PD)(θJC)
The device case temperature, TC, is the
temperature at the center of the larger exposed
therm al pad at the bottom of the pac kage.
The device junction-to-ambient and junction-to-
case thermal resistances, θJA and θJC, are
shown in the Thermal Characteristics table.
The θJC is a function of the device and the 68-
pin QFN package design. The θJA is a function
of θJC and the user’s system design
parameters that include the thermal
effectiveness of the customer PCB and airflow.
The θJA value shown in the Thermal
Characteristics table is for free convection with
the device heat sunk (through the thermal
pads) to a copper plated four-layer PC board
with a full ground and a full power plane
following JEDEC EIJ/JESD 51 Standards. The
θJA can be reduced with the use of forced air
convection. Because of the strong dependence
on the thermal effectiveness of the PCB and
the system design, the actual θJA value will be
a func tion of the s pec ific applic ation.
When operating on a board with the θJA of the
thermal characteristics table, no thermal
deratings are needed to operate all the way up
to maximum output current.
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03544 October 11, 2013 Rev E
EN5364QI
Design Considerations for Lead-Frame Based Modules
Exposed Met al on Bot t om of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance,
and in overall foot print. How ever, they do require s om e s pec ial c ons iderations .
In the assembly process lead frame construction requires that, for mechanical support, some of the
lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached.
This r es ults in s everal s m all pads being expos ed on the bottom of the pac kage, as s how n in Figure 9.
Only the two thermal pads and the perimeter pads are to be m ec hanic ally or elec tric ally c onnec ted to
the PC board. The PCB top layer under the EN5364QI should be clear of any metal (copper pours,
traces, or vias) except for the two thermal pads. The “grayed-out” area in Figure 9 represents the
area that should be clear of any metal on the top layer of the PCB. Any layer 1 metal under the
grayed-out area runs the risk of undesirable shorted connections even if it is c overed by s olderm as k.
O ne expos ed pad in the gr ayed-out area can have VIN m etal under it as noted in Figure 9.
Figure 10 demonstrates the recommended PCB footprint for the EN5364QI. Figure 11 shows the
package dimensions.
Figure 9: Lead-Frame exposed metal. Grey area high lights expo s ed metal t hat is not to be mechan ically or
electrically con nected to the PCB.
V
IN
copper covered by
soldermask acceptable
under this exposed pad.
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03544 October 11, 2013 Rev E
EN5364QI
PCB Footprint and Package Dimensions
Fi gure 10: EN5364QI P CB F ootpri nt (Top View)
T he solder stencil aperture for the therm al pad i s shown i n bl ue and i s based on Enpi rion power produc t m anufac turi ng
specifications.
18 www.altera.com/enpirion
03544 October 11, 2013 Rev E
EN5364QI
Figure 11. Package Dimensions
Contact Information
Altera Corporation
101 Innovation D rive
San Jos e, C A 95134
Phone: 408-544-7000
www.altera.com
© 2013 Alter a C or por ati on —C onf id en tial. All r igh ts r es er ved. ALTERA, ARRIA, CYCLONE, ENPIRION , HARDCOPY, MAX, MEGACOR E , N IOS,
QU AR TU S and STR ATIX w or ds and logos ar e tr ademar ks of Alter a C or por atio n and r egister ed in the U.S. Patent and Trade ma r k Office and in other
countr ies. All other w or ds and logos identi fi ed as tr ademar ks or ser v ice mar ks ar e the pr oper ty of their r espect ive hold er s as descr ibed at
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standar d w ar r anty , but r eser ves the r ight to make changes to any pr oduc ts and ser vices at any time w ithout notice . Alt er a assumes no r esponsibili ty or
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Alter a customer s ar e adv ised to obtain the latest ver sion of device spec ifi catio ns befor e r elyi ng on any pub l ished informatio n and bef o r e pla c in g or de r s
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19 www.altera.com/enpirion
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