Integrated
Circuit
Systems, Inc.
ICS91857
0494C—08/15/05
Block Diagram
Value SSTL_2 Clock Driver (60MHz - 220MHz)
Pin Configuration
48-Pin TSSOP
Recommended Application:
Zero delay board fan-out memory modules
Product Description/Features:
• Meets PC3200 specification for DDRI-400 support
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum tolerant inputs
• Auto PD when input signal removed
Switching Characteristics:
• CYCLE - CYCLE jitter (>100MHz):<75ps
• OUTPUT - OUTPUT skew: <100ps
STUPNISTUPTUO
etatSLLP
DDVA#DPTNI_KLCCNI_KLCTKLCCKLCTTUO_BFCTUO_BF
DNGH L H LH L H ffo/dessapyB
DNGH H L HL H L ffo/dessapyB
V5.2
)mon( LL HZZZ Z ffo
V5.2
)
mon( LH LZZZ Z ffo
V5.2
)mon( HL HLHL H no
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ZZ Z Z ffo
Functionality
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
PD#
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
6.10 mm. Body, 0.50 mm. pitch TSSOP
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
ICS91857
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
ICS91857
0494C—08/15/05
Pin Descriptions
REBMUNNIPEMANNIPEPYTNOITPIRCSED
,12,51,21,11,4
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,52,42,81,8,7,1
84,24,14,13 DNGRWPdnuorG
61DDVARWP .333RDDotpuV5.2,ylppusrewopgolanA
.zHM004ta
I-RDDrofV6.2ylppusrewoP
71DNGARWP.dnuorggolanA
,64,44,93,92,72
3,5,01,02,22 )0:9(TKLCTUO.stuptuoriaplaitnereff
idfokcolC"eurT"
,74,34,04,03,62
2,6,9,91,32 )0:9(CKLCTUO.stuptuoriaplaitnereffidfoskcolc"yratnemelpmoC"
41CN
I_KLCNItupnikcolcecnerefer"yratnemelpmoC"
31TNI_KLCNItupnikcolcecnerefer"eurT"
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rofdetacided,tuptuokcabdeeF"yratnemelpmoC"
deriwebtsumtuptuosihT.KLCehtsaycneuqerfemasehttasehctiws
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I_BFot
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.TNI_BFotderiwebtsumtup
tuosihT.KLCehtsaycneuqerfemaseht
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This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
ICS91857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten differential
pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The
clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT, FB_INC) the 2.5-
V LVCMOS input (PD#) and the Analog Power input (AVDD). When input (PD#) is low while power is applied, the receivers
are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AVDD is grounded, the PLL
is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will
enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input
buffers, will detect the low frequency condition and perform the same low power features as when the (PD#) input
is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on,
the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT,
FB_INC) and the input clock pair (CLK_INC, CLK_INT).
The PLL in the ICS91857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]). The
ICS91857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS91857 is characterized for operation from 0°C to 70°C and will meet JEDEC Standard 82-1 and 82-1A for Registered
DDR Clock Driver.
3
ICS91857
0494C—08/15/05
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above
those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Electrical Characteristics for DDR200/266/333 - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Current IIH VI = VDD or GND 5 µA
Input Low Current IIL VI = VDD or GND 5 µA
IDD2 . 5 CL = 0pf @ 200MHz 260 mA
IDDPD CL = 0pf 100 mA
Output High Current IOH VDD = 2.3V, VOUT = 1V -18 -32 mA
Output Low Current IOL VDD = 2.3V, VOUT = 1.2V 26 35 mA
High Impedance
Out
p
ut Current IOZ VDD=2.7V, Vout=VDD or GND ±10 mA
Input Clamp Voltage VIK VDDQ = 2.3V Iin = -18mA -1.2 V
VDD = min to max,
IOH = -1 mA VDDQ - 0.1 V
VDDQ = 2.3V,
IOH = -12 mA 1.7 V
VDD = min to max
IOL=1 mA 0.1 V
VDDQ = 2.3V
IOH=12 mA 0.6 V
Input Capacitance1CIN VI = GND or VDD 3pF
Output Capacitance1COUT VOUT = GND or VDD 3pF
1Guaranteed by design at 170MHz, not 100% tested in production.
Operating Supply
Current
High-level output
voltage VOH
Low-level output voltage VOL
4
ICS91857
0494C—08/15/05
Electrical Characteristics for DDRI-400 - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.6V ± 0.1V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Current IIH VI = VDD or GND 5 µA
Input Low Current IIL VI = VDD or GND 5 µA
IDD2.5 CL = 0pf @ 200MHz 260 mA
IDDPD CL = 0pf 100 mA
Output High Current IOH VDD = 2.3V, VOUT = 1V -18 -32 mA
Output Low Current IOL VDD = 2.3V, VOUT = 1.2V 26 35 mA
High Impedance
Out
p
ut Current IOZ VDD=2.7V, Vout=VDD or GND ±10 mA
Input Clamp Voltage VIK VDDQ = 2.3V Iin = -18mA -1.2 V
VDD = min to max,
IOH = -1 mA VDDQ - 0.1 V
VDDQ = 2.3V,
IOH = -12 mA 1.7 V
VDD = min to max
IOL=1 mA 0.1 V
VDDQ = 2.3V
IOH=12 mA 0.6 V
Input Capacitance1CIN VI = GND or VDD 3pF
Output Capacitance1COUT VOUT = GND or VDD 3pF
1Guaranteed by design at 220MHz, not 100% tested in production.
Operating Supply
Current
High-level output
voltage VOH
Low-level output voltage VOL
5
ICS91857
0494C—08/15/05
Recommended O
p
eratin
g
Condition for DDR200/266/333
(
see note1
)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VDDQ, AVDD 2.3 2.7 V
CLKT, CLKC, FB_INC VDDQ/2 - 0.18 V
PD# -0.3 0.7 V
CLKT, CLKC, FB_INC VDDQ/2 + 0.18 V
PD# 1.7 VDDQ + 0.6 V
DC input signal voltage
(
note 2
)
-0.3 VDDQ V
DC - CLKT, FB_INT 0.36 VDDQ + 0.6 V
AC - CLKT, FB_INT 0.7 VDDQ + 0.6 V
Output differential cross
-
volta
g
e
(
note 4
)
VOX VDDQ/2 - 0.15 VDDQ/2 + 0.15 V
Input differential cross-
voltage (note 4) VIX VDDQ/2 - 0.2 VDDQ/2 + 0.2 V
High level output
current IOH 0.12 mA
Low level output current IOL 12 mA
Input slew rate SR14V/ns
Operating free-air
temperature TA070°C
Differential input signal
voltage (note 3) VID
Low level input voltage VIL
High level input voltage VIH
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VCC and is the
voltage at which the differential signal must be crossing.
6
ICS91857
0494C—08/15/05
Recommended O
p
eratin
g
Condition for DDRI-400
(
see note1
)
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.6V ± 0.1V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VDDQ, AVDD 2.5 2.6 2.7 V
CLKT, CLKC, FB_INC VDDQ/2 - 0.18 V
PD# -0.3 0.7 V
CLKT, CLKC, FB_INC VDDQ/2 + 0.18 V
PD# 1.7 VDDQ + 0.3 V
DC input signal voltage
(
note 2
)
-0.3 VDDQ V
DC - CLKT, FB_INT 0.36 VDDQ + 0.6 V
AC - CLKT, FB_INT 0.7 VDDQ + 0.6 V
Output differential cross
-
volta
g
e
(
note 4
)
VOX VDDQ/2 - 0.15 VDDQ/2 + 0.15 V
Input differential cross-
voltage (note 4) VIX VDDQ/2 - 0.2 VDDQ/2 + 0.2 V
High level output
current IOH 12 mA
Low level output current IOL -12 mA
Input slew rate SR14V/ns
Operating free-air
temperature TA070°C
Differential input signal
voltage (note 3) VID
Low level input voltage VIL
High level input voltage VIH
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VCC and is the
voltage at which the differential signal must be crossing.
7
ICS91857
0494C—08/15/05
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. Switching characteristics guaranteed for application frequency range.
3. Static phase offset shifted by design.
Timin
g
Re
q
uirements for DDRI-400
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.6V ± 0.1V
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
Max clock frequency freqop 2.6V ± 0.1V 60 230 MHz
Application Frequency
Range freqApp 2.6V ± 0.1V 95 220 MHz
Input clock duty cycle dtin 40 60 %
CLK stabilization TSTAB 100 µs
Switching Characteristics for DDR200/266/333
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Low-to high level
propagation delay time tPLH1CLK_IN to any output 3.5 ns
High-to low level propagation
dela
time tPLL1CLK_IN to any output 3.5 ns
Output enable time tEN PD# to any output 3 ns
Output disable time tdis PD# to any output 3 ns
Period jitter Tjit (per) 100 - 200 MHz -75 75 ps
Half-period jitter t
(j
it_h
p
er
)
100 - 200 MHz -75 75
Input clock slew rate t
(
sir_I
)
14V/ns
Output clock slew rate t(sl_o) 12V/ns
Cycle to Cycle Jitter1Tc
y
c-Tc
y
c100 - 200 MHz -75 75 ps
Static Phase Offset t
(
s
p
o
)
3-50 0 50 ps
Output to Output Skew Tskew 100 ps
Pulse skew Tskewp 100 ps
Timing Requirements for DDR200/266/333
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
Max clock frequency freqop 2.5V ± 0.2V @ 25°C 60 170 MHz
Application Frequency
Range freqApp 2.5V ± 0.2V @ 25°C 95 170 MHz
Input clock duty cycle dtin 40 60 %
CLK stabilization TSTAB 100 µs
8
ICS91857
0494C—08/15/05
Switching Characteristics for DDRI-400
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Low-to high level
propagation delay time tPLH1CLK_IN to any output 3.5 ns
High-to low level propagation
dela
time tPLL1CLK_IN to any output 3.5 ns
Output enable time tEN PD# to any output 3 ns
Output disable time tdis PD# to any output 3 ns
Period jitter Tjit (per) 100 - 200 MHz -50 50 ps
Half-period jitter t
(j
it_h
p
er
)
100 - 200 MHz -75 75
Input clock slew rate t
(
sir_I
)
14V/ns
Output clock slew rate t(sl_o) 12V/ns
Cycle to Cycle Jitter1Tc
y
c-Tc
y
c100 - 200 MHz -75 75 ps
Static Phase Offset t
(
s
p
o
)
3-50 0 50 ps
Output to Output Skew Tskew 75 ps
Pulse skew Tskewp 100 ps
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. Switching characteristics guaranteed for application frequency range.
3. Static phase offset shifted by design.
9
ICS91857
0494C—08/15/05
GND
ICS91857
V
DD
VDD
/2
V(CLKC)
V(CLKC)
SCOPE
C=14pF
-VDD/2
-VDD/2
-VDD/2
VDD/2
Z=60Ω
Z=60Ω
Z=50Ω
Z=50Ω
R=10Ω
R=10Ω
R=50Ω
R=60Ω
R=60Ω
R=50Ω
V(TT)
V(TT)
C=14pF
NOTE: V(TT) =GND
tc(n) tc(n+1)
tjit(cc) =t
c(n) ±t
c(n+1)
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
Y , FBOUTC
X
Y , FBOUTT
X
Parameter Measurement Information
ICS91857
Figure 3. Cycle-to-Cycle Jitter
10
ICS91857
0494C—08/15/05
(N is a large number of samples)
t
( ) n+1
t
()n
t
()
=
1
n=N
t
()n
N
CLK_INC
CLK_INT
å
FB_INC
FB_INT
t(SK_O)
Y#
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
YX
Parameter Measurement Information
Figure 4. Static Phase Offset
Figure 5. Output Skew
1
fO
t=t-
(jit_per) C(n)
1
fO
Figure 6. Period Jitter
11
ICS91857
0494C—08/15/05
Clock Inputs
and Outputs
80%
20%
80%
20%
tslrr(i) tslrf(i) slrf(o)
VID,V
OD
Figure 8. Input and Output Slew Rates
Parameter Measurement Information
t(hper_n) t(hper_n+1)
1
fo
Y , FB_OUTC
X
Y , FB_OUTT
X
Figure 7. Half-Period Jitter
t=-
(jit_Hper)
t
(jit_Hper_n)
1
2xf
O
12
ICS91857
0494C—08/15/05
Ordering Information
ICS91857yGLFT
Designation for tape and reel packaging
RoHS Compliant (Optional)
Pattern Number
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
Example:
ICS XXXX y G - PPP - LF - T
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil) (20 mil)
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
a0°8°0°8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
48 12.40 12.60 .488 .496
10 - 0 0 3 9
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS SEE VARIATIONS
8.10 BASIC 0.319 BASIC
0.50 BASIC 0.020 BASIC
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
Refere nce Doc.: JEDE C Publication 95, MO-153
13
ICS91857
0494C—08/15/05
Designation for tape and reel packaging
RoHS Compliant (Optional)
Pattern Number
Package Type
L = TSSOP (TVSOP)
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
Example:
ICS XXXX y L - PPP - LF -T
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa C
Ordering Information
ICS91857yLLFT
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.13 0.23 .005 .009
c 0.09 0.20 .0035 .008
D
E
E1 4.30 4.50 .169 .177
e
L 0.45 0.75 .018 .030
N
a0° 8° 0° 8°
aaa -- 0.08 -- .003
VARIATIONS
MIN MAX MIN MAX
48 9.60 9.80 .378 .386
10 -00 3 7
ND mm. D
(
inch
)
Reference Doc. : JEDEC Publication 95, MO-153
0.40 BASIC 0.016 BASIC
SEE VARIATIONS SEE VARIATIONS
SEE VARIATIONS SEE VARIATIONS
6.40 BASIC 0.252 BASIC
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
4.40 mm. Body, 0.40 mm. pitch TSSOP (TVSOP)
(173 mil) (16 mil)
14
ICS91857
0494C—08/15/05
Revision History
Rev. Issue Date Description Page #
C 8/15/2005 Added LF Ordering Information. 12-13