DS04-27226-2Ea
FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©2002-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2002.9
ASSP For Power Management Applications
2-channel DC/DC Converter IC
with Synchronous Rectifier
MB3882
■DESCRIPTION
The MB38 82 is a 2-cha nnel DC/DC co nver te r IC using pulse wid th modul ation (PW M) and sy nchrono us recti fi-
cation, designed for do wn conversion applications.
This device is a power supply with high output drive capacity. Synchronous rectification also provides for high
efficiency.
In addition, a 5 V regulator is built in to reduce the number of system components. The result is an ideal built-in
power supply for driving products with high speed CPU’s such as home TV game devices and notebook PC’s.
This product is covered by US Patent Number 6,147,477.
■FEATURES
• Synchronous rectification for high efficiency
• Supply voltage range : 5.5 V to 18 V
• High-precision reference voltage : 2.5 V ± 1%
• Error Amp. threshold v oltage : 1.25 V ± 1% (0 °C to 85 °C)
• Oscillator frequency range : 10 kHz to 500 kHz
• Built-in soft-start circuit with error Amp. input control
• Totem pole type output for N-ch MOSFET
■PACKAGE
24-pin Plastic SSOP
(FPT-24P-M03)
MB3882
2
■PIN ASSIGNMENTS
(TOP VIE W)
(FPT-24P-M03)
1
2
3
4
5
6
7
8
9
10
11
12
CT :
RT :
SGND :
CS1 :
−INE1 :
FB1 :
+INC1 :
OUT1-1 :
VS1 :
CB1 :
OUT2-1 :
PGND :
24
23
22
21
20
19
18
17
16
15
14
13
: VREF
: VCC
: CSCP
: CS2
: −INE2
: FB2
: +INC2
: OUT1-2
: VS2
: CB2
: OUT2-2
: VB
MB3882
3
■PIN DESCRIPTIONS
Pin No. Symbol I/O Description
1CTTriangular wave oscillator frequency setting capacitor connection terminal
2RTTriangular wave oscillator frequency setting resistor connection terminal
3SGNDGround terminal
4CS1CH1 soft-start capacitor connection terminal. (Also used as channel control)
5−INE1 I CH1 error Amp. inverted input terminal
6 FB1 O CH1 error Amp. output terminal
7+INC1 I CH1 overvoltage comparator non-inverted input terminal
8 OUT1-1 O CH1 totem pole output terminal. (External main side FET gate drive)
9VS1CH1 external main side FET source connection terminal
10 CB1 CH1 boot capacitor connection terminal. Connect capacitor between the
CB1 terminal and VS1 terminal.
11 OUT2-1 O CH1 totem pole output terminal. (External synchronous rectifier side FET
gate drive)
12 PGND Ground terminal
13 VB O Output circuit bias output terminal
14 OUT2-2 O CH2 totem pole output terminal. (External synchronous rectifier side FET
gate drive)
15 CB2 CH2 boot capacitor connection terminal. Connect capacitor between the
CB2 terminal and VS2 terminal.
16 VS2 CH2 external main side FET source connection terminal.
17 OUT1-2 O CH2 totem pole output terminal. (External main side FET gate drive)
18 +INC2 I CH2 overvoltage comparator non-inverted input terminal
19 FB2 O CH2 error Amp. ou tput terminal
20 −INE2 I CH2 error Amp. inverted input terminal
21 CS2 CH2 soft-start capacitor connection terminal. (Also used as channel control)
22 CSCP Timer latch short protection capacitor connection terminal
23 VCC Reference voltage, control circuit power supply terminal
24 VREF O Reference voltage output terminal
MB3882
4
■BLO C K DIAGR AM
−
+
+
−
+
−
+
−
+
6
23
13
10
8
9
11
5
4
7
FB1
CS1
−INE1
+INC1
10 µA
Error Amp.1
OVP Comp.1 PWM Comp.2-1
PWM Comp.1-1
Drive1-1
Drive2-1
1.25 V
1.47 V VCC R
SQ
Latch1
< CH1 >
5 V Reg.
VCC
VB
CB1
OUT1-1
OUT2-1
VS1
−
+
+
−
+
−
−
+
−
+
−
+
19 15
17
16
14
12
1 2
20
21
18
FB2
CS2
−INE2
+INC2
10 µA
Error Amp.2
SCP Comp.
OVP Comp.2 PWM Comp.2-2
PWM Comp.1-2
Drive1-2
Drive2-2
1.25 V
1.47 V
2.1 V
VCC R
SQ
Latch1
< CH2 > CB2
OUT1-2
OUT2-2
PGND
VS2
22
CSCP
1 µA
bias
SR
Latch UVLO OSC Power
Ref
(2.5 V)
24 3
CT RT VREF SGND
bias VCC
1.9 V
1.3 V
MB3882
5
■ABSOLUTE MAXIMUM RATINGS
* : The packages are mounted on the dual-sided epoxy board (10cm × 10cm).
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Conditions Rating Unit
Min Max
Supply voltage VCC 20 V
Boot voltage VCB CB terminal 25 V
Output current IO120 mA
Peak output current IOP Duty ≤ 5%
(t = 1 / fOSC × Duty) 800 mA
Power dissipation PDTa ≤ +25 °C740* mW
Storage temperature Tstg −55 +125 °C
MB3882
6
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
Parameter Symbol Conditions Value Unit
Min Typ Max
Supply voltage VCC 5.5 12 18 V
Boot voltage VCB CB terminal 23 V
Reference voltage output current IOR VREF terminal −10mA
Bias output current IOB VB terminal −10mA
Input vo lta ge VIN −INE term inal 0 VCC − 1.8 V
VINC +INC terminal 0 VCC V
Output current IO−100 100 mA
Peak output current IOP Duty ≤ 5%
(t = 1 / fosc × Duty) −700 700 mA
Oscillator frequency fOSC 10 200 500 kHz
Timing resistor RT6.8 10 12 kΩ
Timing capacitor CT150 470 15000 pF
Boot capacitor CB0.1 1.0 µF
Referenc e vo ltag e
output capacitor CREF VREF terminal 0.1 1.0 µF
Bias output capacitor CVB VB terminal 1.0 4.7 10 µF
Soft-start capacitor CS0.1 1 µF
Short detection capacitor CSCP 0.01 0.1 µF
Operating ambient temperature Ta −30 +25 +85 °C
MB3882
7
■ELECTRICAL CHARACTERISTICS (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C)
* : Typical setting value (Continued)
Parameter Symbol Pin No. Conditions Value Unit
Min Typ Max
1.
Reference
Voltage Block
[Ref]
Out p ut v ol t ag e VREF 24 Ta = +25 °C 2.475 2.500 2.525 V
∆VREF/
VREF 24 Ta = 0 °C to +85 °C0.5* %
Input stability Line 24 VCC = 5.5 V to 18 V 110mV
Load stability Load 24 VREF = 0 mA to −1 mA 310mV
Short output
current Ios 24 VREF = 2 V −28 −14 −7mA
2.
Bias Voltage
Block
[VB]
Out p ut v ol t ag e VB 13 4.95 5.05 5.15 V
3.
Undervoltage
Lockout
Circuit Block
[UVLO]
Threshold
voltage VTH 23 VCC = 2.6 2.9 3.2 V
Hysteresis
width VH23 0.2* V
Reset voltage VRST 23 1.7 2.1 2.5 V
4.
Soft-start
Block
[CS]
Charge
current ICS 4, 21 −14 −10 −6µA
5.
Short
Detection
Comparator
Block
[SCP]
Threshold
voltage VTH 22 0.63 0.68 0.73 V
Input source
current ICSCP 22 −1.4 −1.0 −0.6 µA
Short
detection time tSCP 22 CSCP = 0.01 µF 4.5 6.8 12.2 ms
6.
Triangular
Wave
Oscillator
Block
[OSC]
Oscillator
frequency fOSC 1RT = 10 kΩ, CT = 470 pF 170 190 210 kHz
Frequency
temperature
variation rate
∆fOSC/
fOSC 1Ta = 0 °C to +85 °C 1* %
7.
Error Amp
Block
[Error Am p.]
Threshold
voltage
VTH1 5, 20 FB = 1.6 V,
Ta = +25 °C1.241 1.2500 1.259 V
VTH2 5, 20 FB = 1.6 V,
Ta = 0 °C to +85 °C1.2375 1.2500 1.2625 V
Input bias
current IB5, 20 −INE = 0 V −200 −20 nA
Voltage gain AV6, 19 DC 60 100 dB
MB3882
8
(VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C)
* : Typical setting value (Continued)
Parameter Symbol Pin No. Conditions Value Unit
Min Typ Max
7.
Error Amp
Block
[Error Am p.]
Frequency
band width BW 6, 19 AV = 0 dB 800* kHz
Out p ut v ol t ag e VFBH 6, 19 2.2 2.5 V
VFBL 6, 19 0.8 1.0 V
Output source
current ISOURCE 6, 19 F B = 1.6 V −100 −45 µA
Output sink
current ISINK 6, 19 FB = 1.6 V 1.5 9.0 mA
8.
PWM
Comparator
Block
[PWM Comp.]
Threshold
voltage
VTL 6, 19 Duty cycle = 0%1.2 1.3 V
VTH 6, 19 Duty cycle = Dtr 1.81 2.0 V
9.
Dead time
Adjustment
Block
[DTC]
Maximum
duty cycle Dtr 8, 17 RT = 10 kΩ,
CT = 470 pF 85 90 95 %
10. Output
Block
[Drive]
Output current
(main side)
ISOURCE1 8, 17 Duty ≤ 5%
(t = 1 / fOSC × Duty) −700* mA
ISINK1 8, 17 Duty ≤ 5%
(t = 1 / fOSC × Duty) 900* mA
Out p ut v ol t ag e
(main side)
VOH1 8, 17 OUT1 = −100 mA,
CB = 17 V, VS = 12 V CB −
2.5 CB −
0.9 V
VOL1 8, 17 OUT1 = 100 mA,
CB = 17 V, VS = 12 V VS +
0.9 VS +
1.4 V
Output current
(synch ronous
rectifier side)
ISOURCE2 11, 14 Duty ≤ 5%
(t = 1 / fOSC × Duty) −750* mA
ISINK2 11, 14 Duty ≤ 5%
(t = 1 / fOSC × Duty) 900* mA
Out p ut v ol t ag e
(synch ronous
rectifier side)
VOH2 11, 14 OUT2 = −100 mA 2.5 4.1 V
VOL2 11, 14 OUT2 = 100 mA 1.0 1.4 V
Diode voltage VD10, 15 VB = 10 mA 0.9 1.1 V
MB3882
9
(Continued) (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C)
Parameter Symbol Pin No. Conditions Value Unit
Min Typ Max
10. Output
Block
[Drive] Dead time
tD1
8, 11,
17, 14
RT = 10 kΩ, CT = 470 pF
OUT1 = OUT2 = OPEN,
VS = 0 V
OUT2 : − OUT1 :
100 200 ns
tD2
RT = 10 kΩ, CT = 470 pF
OUT1 = OUT2 = OPEN,
VS = 0 V
OUT1 : − OUT2 :
100 250 ns
11.
Overvoltage
Detection
Comparator
Block
[OVP]
Threshold
voltage VTH 7, 18 +INC = 1.44 1.47 1.50 V
Input bias
current IB7, 18 +INC = 0 V −200 −30 nA
12.
General Power supply
current ICC 23 11 16.5 mA
MB3882
10
■TYPICAL CHARACTERISTICS
(Continued)
15.0
12.5
10.0
7.5
5.0
2.5
0.00510
Supply current ICC (mA)
Supply voltage VCC (V)
Supply Current vs. Supply Voltage
15 20
Ta = +25 °CTa = +25 °C
VREF = 0 mA
5
4
3
2
1
00 5 10 15 20
Reference voltage VREF (V)
Supply voltage VCC (V)
Reference Voltage vs. Supply Voltage
VCC = 12 V
VREF = 0 mA
2.0
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−40 −20 0 604020 80 100
Reference voltage ∆V
REF
(%)
Ambient temperature Ta (°C)
Reference Voltage vs. Ambient Temperature
Ta = +25 °C
VCC = 12 V
CTL = 5 V
2.5
2.0
1.5
1.0
0.51 k 10 k 100 k 1 M
Triangular wave upper/lower limit voltage V
CT
(V)
Triangular wave oscillator frequency fosc (Hz)
Triangular Wave Upper/Lower Limit Voltage vs.
Triangular Wave Oscillator Frequency
Upper
limit
Lower
limit
VCC = 12 V
RT = 10 kΩ
CT = 470 pF
2.5
2.0
1.5
1.0
0.5 020−20 40−40 60 80 100
Triangular wave upper/lower limit voltage VCT (V)
Ambient temperature Ta (°C)
Triangular Wave Upper/Lower Limit Voltage vs.
Ambient Temperature
Upper
limit
Lower
limit
MB3882
11
(Continued)
Ta = +25 °C
VCC = 12 V
CTL = 5 V
RT = 10 kΩ
10 M
1 M
100 k
10 k
1 k10 100 1000 10000 100000
Triangular wave frequency fOSC (Hz)
Timing capacitor CT (pF)
Triangular Wave Oscillator Frequency vs.
Timing Capacitor
Ta = +25 °C
VCC = 12 V
CTL = 5 V
10 M
1 M
100 k
10 k
1 k
1001 k 10 k 100 k
CTL = 150 pF
CTL = 470 pF
CTL = 15000 pF
Triangular wave frequency f
OSC
(Hz)
Timing resistor R
T
(Ω)
Triangular Wave Oscillator Frequency vs.
Timing Resistor
Ta = +25 °C
RT = 10 kΩ
CT = 470 pF
250
240
230
220
210
200
190
180
170
160
1500 5 10 15 20
Triangular wave frequency fOSC (Hz)
Supply voltage VCC (V)
Triangular Wave Oscillator Frequency vs.
Supply Voltage
VCC = 12 V
RT = 10 kΩ
CT = 470 pF
250
240
230
220
210
200
190
180
170
160
150 0−20−40 20 40 60 80 100
Triangular wave frequency fOSC (Hz)
Ambient temperature Ta (°C)
Triangular Wave Oscillator Frequency vs.
Ambient Temperature
Ta = +25 °C
40
20
0
−20
−40
180
90
0
−90
−180
1 k 10 k 100 k 1 M 10 M
A
V
φ
−
+
+
− +
56
4OUT(19)
(21)
(20)
IN 10 µF
4.7 kΩ
4.7 kΩ
2.4 kΩ
240 kΩ
1.5 V 1.25 V
VCC = 12 V
Error Amp.1
(Error Amp.2)
Gain A
V
(dB)
Phase φ (deg.)
Frequency f (Hz)
Error Amp Gain, Phase vs. Frequency
MB3882
12
(Continued)
800
700
600
500
400
300
200
100
0020 −20 40−40 60 80 100
740
Power dissipation PD (mW)
Ambient temperature Ta (°C)
Power Dissipation vs. Ambient Temperature
MB3882
13
■FUNCTION DESCRIPTION
1. DC/DC Converter Function
(1) Reference Voltage Block
The reference voltage c ircuit takes the voltage feed from the power suppl y termi nal (pin 23) a nd generates a
temperature compensated reference voltage (2.5 V Typ) , for use as the reference voltage for the power supply
control un it.
Also, an external load cur rent can be obtain ed from the power suppl y at the VREF ter mi nal (pin 24) , up to a
maximum of 1 mA.
(2) Triangular Wave Oscillator Block
A triangular waveform with amplitude 1.3 V to 1.9 V can be generated by connecting a timing capacitor and
resistor to the CT terminal (pin 1) and RT terminal (pin 2) , respectively.
The triangular oscillator waveform can be input to the IC’s internal PWM comparator, as well as supplied externally
from the CT terminal.
(3) Error Amp Block (Error Amp.)
The erro r Amp. is an amplifi er that detects the o utput voltage fr om the DC/DC converter an d outputs a PWM
control signal. The error Amp. has a broad in-phase input voltage range of 0 to Vcc−1.8 V that can be easily set
by the external power supply.
In additio n, an arbitrar y loop gain can be set up by connec ting a feedba ck resistor and capacitor between the
error Amp. output terminal and inv erter input terminal, providing stable phase compensation to the system.
Also, power-on rush current can be prev ented by connecting a soft-start capacitor between the error Amp . non-
inv erted input terminals CS1 terminal (pin 4) and CS2 terminal (pin 21) . The soft-start function operates with a
stable soft-start time that is not dependent on the output load of the DC/DC converter.
(4) PWM Comparator Block (PWM Comp.)
This is a voltage - pulse width modulator that controls the output duty according to the input voltage.
(5) Output Block
The out put block has totem pole configu ration on both the main side and synchrono us rectifier side, a nd can
drive an external N-ch MOSFET.
Also, the high output drive capability (700 mA max : duty ≤ 5%) pr ovides h ig h g ate -s ou rce ca pac it or , e nabling
the use of low on-resistor FET devices.
Main side : Turns the output transistor on in the intervals in which the error Amp. output
voltage is higher than the triangular wave voltage.
Synchronous rectifier side : Turns the output transistor on in the intervals in which the triangular wave volt-
age the is lower than error Amp. voltage.
MB3882
14
2. Channel Control Functions
Channel ON/OFF control is provided by using the CS1 terminal (pin 4) and CS2 terminal (pin 21) setting functions.
Channel On/Off Setting Functions
3. Protective Functions
(1) Timer Latch Short Circuit Protection (SCP)
The sh ort c ircuit pro tectio n compa rators re ad the outp ut voltage levels. If the output voltage on ei ther ch annel
falls below the short detection voltage, the timer circuit is activated to start charging the external capacitor Cscp
connected to the CSCP terminal (pin 22) .
When capacitor voltage reaches approximately 0.68 V the output FET turns off, setting the idle interval to 100%.
Once the protection circuit is activated, it can be reset by turning the power supply off and on again. (See “Setting
the Timer Latch Short Circuit Protector Time Constant.”)
(2) Undervoltage Lockout Circuit Block (UVLO)
Transient status during normal power-on or momentary drops in supply voltage can cause abnormal operation
in an control IC, leading to damage or degradation of system components. The undervoltage lockout circuit
prevents such abnormal operations by reading the internal reference voltage level and switching the output
transistor off, setting the idle interval to 100% and holding the CSCP terminal (pin 22) to “L” level.
System operation is restored when the supply voltage rises back about the undervoltage lockout circuit threshold
voltage.
(3) Overvoltage Protection Block (OVP)
The overvoltage protec tion c ircuit uses a n overvoltage c omparator (OVP Comp.) on each channel to re ad the
output voltage levels from the DC/DC conver ter. If the output voltage exceeds the thres hold voltage a latc h is
set, turning off the main side FET on the corresponding channel.
CS terminal voltage level Channel output state
CS1 CS2 CH1 CH2
GND GND OFF OFF
GND Hi-Z OFF ON
Hi-Z GND ON OFF
Hi-Z Hi-Z ON ON
MB3882
15
■SETTING THE TIMER LATCH SHORT CIRCUIT PROTECTOR TIME CONSTA NT
Each channel has a short circuit protection comparator (SCP Comp.) which constantly compares the error Amp.
output level to the reference voltage.
When the DC/DC comparator load conditions are stable on all channels, the short circuit protection comparator
output is at “H” level, transistor Q1 is on, and the CSCP terminal (pin 22) is held at input standby voltage
(VSTB : = 50 mV) .
If load condi tions cha nge rapidly, such as dur ing a load sho rt, cau sing output voltage to dr op, the short circuit
protection comparator output goes to “L” level. This causes the transistor Q1 to shut off, charging the short circuit
protection capacitor Cscp (connected to the CSCP terminal) at 1 µA.
Short detection time
tscp (s) := 0.68 × Cscp (µF)
When the capacitor Cscp is charted to the threshold voltage (VTH : = 0.68 V) a latch is set, turning the e xternal
FET off (sett ing the idle i nte rval to 100%) . At th is ti me th e l atc h inpu t is c lo sed and the CS CP t ermi nal is he ld
at the i npu t l atc h voltage (V I : = 50 mV) . (When a short circuit is d etec ted on ei the r of the two ch annels, b oth
channels are shut off.)
MB3882
16
−
+
+
8
6
5
4
11
FB1
CS1
CS1
−INE1
Error
Amp.1
1.25 V
Q2
OUT1-1
Drive
Drive OUT2-1
−
+
+
−
+
−
17
19
20
21
14
FB2
CS2
CS2
22
CSCP
−INE2
Error
Amp.2
SCP
Comp.
1.25 V
2.1 V
Q3
OUT1-2
OUT2-2
10 µA 10 µA
1 µA
CSCP
Q1 Q4
SR
Latch
bias
UVLO
Drive
Drive
< Timer Latch Short Circuit Protection Circuit >
MB3882
17
■PROCESSING WITHOUT USING THE CSCP TERMINAL
When the timer latch short circuit pr otecti on circui t is no t used, the CSCP ter mina l (pin 22 ) sho uld be sho rted
to GND using the shortest possible connection.
223 GND CSCP
< Operation Without Using the CSCP Terminal >
MB3882
18
■SOFT-START TIME SETTING
The soft-star t func tion prevents ru sh current events when the IC power is tur ned o n, by co nnecting s oft-star t
capacitors (Cs1, Cs2) to the CS1 terminal (pin 4) for channel 1, and the CS2 terminal (pin 21) for channel 2.
When the IC i s acti vated (Vcc ≥ UVLO thr esh ol d voltage) , Q2 and Q3 ar e off and the CS1 an d CS 2 termi nals
begin charging the externally connected soft-start capacitors (Cs1, Cs2) at 10 µA.
Because the error Amp. output (FB1, FB2) is determined by the ratio of the lower of the two non-inverted input
terminals (1.25 V, CS terminal voltage) to the inverted input terminal voltage (−INE) , the soft-start interval (when
CS terminal voltage < 1.25 V) FB is determined by the ratio of the −INE terminal voltage and CS terminal voltage.
Thus the DC/DC co nverte r outp ut voltage rises i n p roportion to the rise in th e CS te rmin al voltage as the s of t-
start capacitor connected to the CS terminal charges. The soft-start time is determined b y the following formula.
Soft-start time (time to output 100%)
ts (s) := 0.125 × Cs (µF)
CS terminal voltage
2.3 V
1.25 V
0 V
Error Amp. block comparison voltage
to −INE voltage
Soft start time ts
t
MB3882
19
−
+
+
UVLO
1.25 V
Q2
(Q3)
6
19
5
20
4
21
Error
Amp.
CS1
(CS2)
(CS2)
CS1
(FB2)
FB1
(−INE2)
−INE1
10 µA 10 µA
VREF
< Soft-start Block >
MB3882
20
■PROCESSING WITHOUT USING THE CS TERIMNALS
When the soft-start function is not used, the CS1 terminal (pin 4) and CS2 terminal (pin 22) should be left open.
■OSCILLATOR FREQUENCY SETTING
The oscillator frequency can be set by connecting a timing capacitor (CT) to the CT terminal (pin 1) and a timing
resistor (RT) to the RT terminal (pin 2) .
Oscillator frequency
■OUTPUT VOLTAGE SETTING
214 CS1 CS2
"Open" "Open"
< Operation Without Soft-start Setting >
fosc (kH z) := 893000
CT (pF) •RT (kΩ)
−
+
+
6
5
4
VO
R1
R2
FB1
CS1
−INE1
Error
Amp.
1.25 V
VO = (R1 + R2)
R2
1.25 V
< CH1, 2 >
MB3882
21
■OVERVOLTAGE PROTECTION CIRCUIT VOTAGE SETTING
Overvoltage conditions in the DC/DC converter output voltage can be detected by connecting external resistance
from the DC/DC converter output voltage to the +INC1 terminal (pin 7) and +INC2 terminal (pin 18) on the
respectiv e overvoltage protection comparator circuits (OVP comp. 1, 2) .
When the o utpu t voltage of the DC/DC c onver ter rises above the detection voltage, the overvoltage prote ction
comparator (OVP Comp. 1, 2) output goes to “H” level, setting a latch and shutting off the corresponding channel.
Each of the overvoltage protection circuit latches operates independently.
Detection voltage
VOVP (V) := 1.47 × (R3 + R4) /R4
Once the protection circuit has been activated, it can be reset by lowering the VCC voltage below the reset
voltage (1.7 V Min) .
+
−
18
7
VO
R3
R4
(+INC2)
+INC1
OVP
Comp.
1.47 V
RQ
S
VCC
MB3882
22
■PRECAUTIONS RELATED TO INTERNAL IC POWER CONSUMPTION
The internal power dissipation in the IC is greatly affected by the oscillator frequency and the FET total gate
charge. When using the MB3882 in an application, caution must be taken in relation to internal IC power
consumption.
As shown below, IB (average current) can be determined from the total gate charge Qg1, Qg2, charged from the
gate capacitance (Ciss1, Ciss2, Crss1, Crss2) of the external FET Q1, Q2, by the following formula.
Per individual channel :
Because IC current consumption other than IB is 11 mA, power consumption can be determined from the following
formula.
Power consumption : Pc
Pc (W) = 0.011 × VCC + 2 × VCC × IB − VB × IB
IB (A) = I1 + I2
:= I bias1 × T1
T + Qg1
T + Ibias2 × T2
T + Qg2
T (Ibi a s1 = Ibias2 := 2 mA)
MB3882
23
Using the above formulas to determine power consumption, settings should be made with reference to the “Power
Consumption vs. Input Voltage” on the following page, as well as the “Power dissipation vs. Ambient Tempera-
ture.”
Drive
1-1
Drive
2-1
23
13
10
8
A
9
11
12
L1 VO1
Vin VCC
5 V IBVB
CB1
VS1
PGND
OUT1-1
OUT2-1
CVB
I1
I2
Crss1Crss2
Ciss1
Ciss2
Q1
Q2
t
T2
T1
T
VOUT1-1
VOUT2-1
I1
I2
Bias current
Ibias1 2 mA
Bias current
Ibias2 2 mA
MB3882
24
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.0056789101112
Input voltage Vin (V)
Power consumption PC (W)
Power Consumption vs. Input Voltage (Qg Parameters)
13 14 15 16 17 18 19 20
Qg1 = Qg2 = 70 nC Qg1 = Qg2 = 50 nC
Qg1 = Qg2 = 30 nC
Qg1 = Qg2 = 20 nC
Qg1 = Qg2 = 10 nC
Ta = +25 °C
fOSC = 200 kHz
SW1 = OFF
SW2 = OFF
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.005 6 7 8 9 10111213
Power Consumption vs. Input Voltage (fosc Parameters)
Input voltage Vin (V)
Power consumption PC (W)
14 15 16 17 18 19 20
fOSC = 500 kHz
fOSC = 300 kHz
fOSC = 200 kHz
fOSC = 100 kHz
fOSC = 10 kHz
Ta = +25 °C
Qg1 = Qg2 = 20 nC
SW1 = OFF
SW2 = OFF
MB3882
25
■APPLICATION CIRCUIT
A
B
13
10
8
9
11
15
17
16
14
12
32421
22
−
−
+
+
−
−
+
18
21
20
19
B
A
+
−
+
−
+
−
+
−
−
+
+
23
+
−
7
4
5
6<CH1>
<CH2>
Vo1 (2 V)
+C8
68 µF × 3
C20
D1
Q2
2.2 µF
L1
2.7 µH
C6 0.1 µF
Q1
C7
0.1 µF22 µF
+C10
C5
4.7 µF
D3
VB
CB1
OUT1-1
OUT2-2
VS1
D4
CB2
OUT1-2
VS2
OUT2-2
PGND
C9 Vo2 (2 V)
L2
2.7 µH
+C11
68 µF × 3
C21
2.2 µF
D2Q4
0.1 µF
Q3
C18+C19
0.1 µF22 µF
C17
VCC 0.1 µF
5 V Reg
Drive
1-1
Drive
2-1
Drive
1-2
Drive
2-2
PWM Comp.1-1
PWM Comp.1-2
PWM Comp.2-1
PWM Comp.2-2
Error Amp.1
Error Amp.2
OVP Comp.1
OVP Comp.2
Latch1
Latch2
R
SQ
R
SQ
1.25 V
1.25 V
VCC
VCC
1.47 V
1.47 V
10 µA
10 µA
FB1
FB2
C1
C3
0.022 µF
0.022 µF
R1
2.7 kΩ
R5
2.7 kΩ
R9
Channel
On/Off
signal
Channel
On/Off
signal
2 kΩ
R11 2 kΩ
Vin C14
0.1 µF 22 µF
+C15
SW1
6.2 kΩ
6.2 kΩ
R21
10 kΩ
R23
10 kΩ
+INC1
−INE1
+INC2
−INE2
R2
R6
10 kΩ
R10
3.3 kΩ
R20
10 kΩ
R12
3.3 kΩ
R22
C2
0.1 µF
C4
0.1 µF
CS1
CS2
1.9 V
1.3 V
OSC
bias VCC
Ref
(2.5 V) Power
SGND
VREF
C16
0.1 µF
RT
R13
10 kΩ
CT
C13
470 pF
UVLO
SR
Latch
bias
2.1 V
1 µA
SCP Comp.
CSCP
C12
0.01 µF
SW2
+
MB3882
26
■COMPONENT LIST
Notes : IR : International Rectifier Corp.
ROHM : Rohm, Ltd.
TDK : TDK, Ltd.
COMPONENT ITEM SPECIFICATION VENDOR PARTS No.
Q1 to Q4 FET VDS = 30 V IR IRF7811
D1, D2
D3, D4 Diode
Diode VF=0.35V(Max),at IF=1 A
VF=0.30V(Max),at IF=10mA ROHM
ROHM RB051L-40
RB495D
L1, L2 Coil 2.7 µH 12 A, 4.5 mΩTDK RLF12545T
-2R7N8R7
C1
C2
C3
C4
C5
C6, C7
C8
C9
C10
C11
C12
C13
C14
C15
C16 to C18
C19
C20, C21
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Electrolytic Condenser
Ceramics Condenser
OS Condenser
Electrolytic Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
OS Condenser
Ceramics Condenser
OS Condenser
Ceramics Condenser
0.022 µF
0.1 µF
0.022 µF
0.1 µF
4.7 µF
0.1 µF
68 µF
0.1 µF
22 µF
68 µF
0.01 µF
470 pF
0.1 µF
22 µF
0.1 µF
22 µF
2.2 µF
6.3 V
25 V
6.3 V
25 V
25 V

R1
R2
R5
R6
R9
R10
R11
R12
R13
R20
R21
R22
R23
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
2.7 kΩ
10 kΩ
2.7 kΩ
10 kΩ
2 kΩ
3.3 kΩ
2 kΩ
3.3 kΩ
10 kΩ
6.2 kΩ
10 kΩ
6.2 kΩ
10 kΩ
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W

MB3882
27
■REFERENCE DATA
100
95
90
85
80
75
70 012345
Load current IL (A)
Conversion efficiency η (%)
Ta = +25 °C
2 V output
SW1 = OFF
SW2 = ON
Conversion Efficiency vs. Load Current Characteristics (Channel 1)
678910
Vin = 6 V
Vin = 8.5 V
Vin = 10 V
MB3882
28
■PRECAUTIONARY INFORMATION
• Printed circuit board ground lines should be designed with consideration for common impedance.
• Take sufficient countermeasures should be taken to protect against static electricity.
• Always place semiconductors in containers that have anti-static provisions, or are conductive.
• After mounting, PC boards should be placed in conductive bags or containers for storage and handling.
• Working surfaces, tools, and measurement equipment should be grounded.
• Persons handling semiconductors should be grounded directly with resistance of 250 kΩ to 1 MΩ.
• Do not apply negative voltages.
• Applic ation of negative voltage of −0.3 V or greater can create parasitic transistor effects on an LSI device,
leading to abnormal operation.
■ORDERING INFORMATION
Part Number Package Remarks
MB3882PFV 24-p in Pl as tic SSO P
(FP T -2 4 P -M03)
MB3882
29
■PACKAGE DIMENSION
24-pin, Plastic SSOP
(FPT-24P-M03) Note1 : Pins width and pins thickness include plating thickness.
Note2 : *This dimension does not include resin protrusion.
Dimensions in mm (inches) .
C
2001 FUJITSU LIMITED F24018S-c-3-4
7.75±0.10(.305±.004)
5.60±0.10 7.60±0.20
(.220±.004) (.299±.008)
*
0.10(.004)
112
1324
0.65(.026)
–0.07
+0.08
0.24
.009
+.003
–.003
M
0.13(.005)
INDEX
0.17±0.03
(.007±.001)
"A"
0.25(.010)
0.10±0.10
(.004±.004)
(Stand off)
Details of "A" part
(Mounting height)
1.25
+0.20
–0.10
–.004
+.008
.049
0~8°
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10(.004)
MB3882
30
MEMO
MB3882
31
MEMO
FUJITSU MICROELECTRONICS LIMITED
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