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Inc.” products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made
are the result of normal document improvements and are noted in the document history page, where supported. Future
revisions will occur when appropriate, and changes will be noted in a document history page.
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Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-00719 Rev. *J Revised September 24, 2015
S25FL216K
16-Mbit 3.0 V Serial Flash Memory
with Uniform 4 kB Sectors
Distinctive Features
Single power supply operation
– Full voltage range: 2.7 to 3.6V
16-Mbit Serial Flash
– 16-Mbit/2048 kbyte/9192 pages
– 256 bytes per programmable page
– Uniform 4-kbyte Sectors/64-kbyte Blocks
Standard and Dual
– Standard SPI: SCK, CS#, SI, SO, WP#, HOLD#
– Dual SPI: SCK, CS#, SI/IO0, SO, WP#, HOLD#
– Fast Read Dual Output instruction
– Auto-increment Read capability
High Performance
– FAST READ (Serial): 65 MHz clock rate
– DUAL OUTPUT READ: 65 MHz clock rate
Low Power Consumption
– 12 mA typical active current
– 15 µA typical standby current
Flexible Architecture with 4 kB Sectors
– Sector Erase (4 kB)
– Block Erase (64 kB)
– Page Program up to 256 bytes
– 100k erase/program cycles typical
– 20-year data retention typical
Software and Hardware Write Protection
– Write Protect all or portion of memory via software
– Enable/Disable protection with WP# pin
High Performance Program/Erase Speed
– Page program time: 1.6 ms typical
– Sector erase time (4 kB): 45 ms typical
– Block erase time (64 kB): 450 ms typical
– C hip erase time: 12 seconds typical
Package Options
– 8-pin SOIC 150/208-mil
– All Pb-free packages are RoHS compliant
General Description
The S25FL216K device is a 16-Mbit, 2048-kbyte Serial Flash memory, with advanced write protection mechanisms. The
S25FL216K supports the standard Serial Peripheral Interface (SPI), and a high performance Dual output using SPI pins: Serial
Clock, Chip Select, Serial SI/IO0, SO, WP#, and HOLD#. SPI clock frequencies of up to 65 MHz are supported.
The S25FL216K array is organized into 8,192 programmable pages of 256 bytes each. Up to 256 bytes can be programmed at a
time. Pages can be erased in groups of 16 (4-kB Sector Erase), groups of 256 (64-kB Block Erase) or the entire chip (Chip Erase).
The S25FL216K has 512 erasable sectors and 32 erasable blocks. The small 4 kB sectors allow for greater flexibility in applications
that require data and parameter storage.
A Hold pin, Write Protect Pin and programmable write protection provi de further control flexibility. Additionally, the S25FL216K
device supports JEDEC standard manufacturer and device identification.
Document Number: 002-00719 Rev. *J Page 3 of 35
S25FL216K
Contents
Distincti ve Fe atures ............................................................. 2
General Description ............................................................. 2
1. Block Diagram.............................................................. 4
2. Connection Diagrams.................................................. 4
3. Signal Descriptions ..................................................... 5
4. Ordering Information................................................... 6
4.1 Valid Combinations........................................................ 6
5. Memory Organizations................................................ 7
6. Functional Des c ri pti on................................................ 8
6.1 SPI Modes ......... ... ............................ ... ... .............. ... ... ... 8
6.2 Dual Output SPI............................................................. 8
6.3 Hold Function................................................................. 8
6.4 Status Register .............................................................. 9
7. Write Protection......................................................... 10
7.1 Page Programming...................................................... 11
7.2 Sector Erase, Block Erase, and Chip Erase................ 11
7.3 Polling During a Write, Program, or Erase Cycle......... 11
7.4 Active Power, Stand-by Power, and Deep Power-Do wn
Modes .......................................................................... 11
8. Commands ................................................................. 11
8.1 Write Enable (06h)....................... ................. ............... 12
8.2 Write Disable (04h)............. ... ................. ................. .... 13
8.3 Read Status Register (05h) ......................................... 13
8.4 Write Status Register (01h).......................................... 14
8.5 Read Data (03h) .......................................................... 15
8.6 Fast Read (0Bh)........................................................... 15
8.7 Fast Read Dual Output (3Bh) ...................................... 16
8.8 Page Program (PP) (02h)............................................ 17
8.9 Sector Erase (SE) (20h)............................................... 18
8.10 Block Erase (BE) (D8h)........................... ... ................. . 19
8.11 Chip Erase (CE) (C7h)................................................. 19
8.12 Deep Power-d own (DP) (B9h)..................................... 20
8.13 Release Deep Powe r-down / Device ID (ABh) ............ 21
8.14 Read Manufacturer / Device ID (90h).......................... 22
8.15 Read Identification (R DID) (9Fh) ................................. 23
9. Electrical Specifications............................................ 25
9.1 Power-up Timing.......................................................... 25
9.2 Absolute Maximum Ratings......................................... 26
9.3 Recommended Operating Ranges .............................. 26
9.4 DC Characteristics...... ... ... .............................. ............. 27
9.5 AC Measurement Conditi ons....................................... 27
9.6 AC Characteristics....................................................... 28
10. Package Material........................................................ 31
10.1 8-Pin SOIC 150-mil Package (SOA 008)..................... 31
10.2 8-Pin SOIC 208-mil Package (SOC 008)..................... 32
11. Revision History......................................................... 33
Document Number: 002-00719 Rev. *J Page 4 of 35
S25FL216K
1. Block Diagram
2. Connection Diagrams
Address
Buffers
and
Latches
X-Decoder Flash
Memory
Y-Decoder
Control Logic
I/O Buffers
and Data
Latches
Serial Interface
CS # SCK SI/IO0 SO W P# HO LD #
1
2
3
4
CS#
SO
WP#
GND SI/IO0
SCK
HOLD#
VCC
5
6
7
8
Figure 2.1 8-pin SOIC (150/208 mil)
Document Number: 002-00719 Rev. *J Page 5 of 35
S25FL216K
3. Signal Descriptions
Serial Data Input / Output (SI/IO0)
The SPI Serial Data Input/Output (SI/IO0) pin provides a means for instructions, addresses and data to be serially written to (shifted
into) the device. Data is latched on the rising edge of the Serial Clock (SCK) input pin. The SI/IO0 pin is also used as an output pin
when the Fast Read Dual Output instruction is executed.
Serial Data Output (SO)
The SPI Serial Data Output (SO) pin provides a means for data and status to be serially read from (shifted out of) the device. Data is
shifted out on the falling edge of the Serial Clock (SCK) input pin.
Serial Clock (SCK)
The SPI Serial Clock Input (SCK) pin provides the timing for serial input and output operations. See SPI Modes on page 8.
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is dese lected and the Serial
Data Output pins are at high impedance.
When deselected, the device’s power consumption will be at standby levels unless an internal erase, program or status register
cycle is in progress. When CS# is brought low the device will be selected, po wer consumption will increase to active levels and
instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new
instruction will be accepted.
HOLD (HOLD#)
The HOLD# pin allows the device to be paused while it is actively sele cted. When HOLD# is brought low, while CS# is low, the SO
pin will be at high impedance and signals on the SI and SCK pins will be ignored (don’t care). The HOLD# function can be useful
when multiple devices are sharing the same SPI signals.
Write Protec t (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status
Register’s Block Protect (BP0, BP1 and BP2, BP3) bits and Status Register Protect (SRP) bits, a portion or the entire memory array
can be hardware protected.
Note:
1. SI/IO0 output is used for Dual Output Read instruction.
Table 3.1 Pin Descriptions
Symbol Pin Name
SCK Serial Clock Input
SI/IO0 Serial Data Input / Output (1)
SO Serial Data Output
CS# Chip Enable
WP# Write Protect
HOLD# Hold Input
VCC Supply Voltage (2.7-3.6V)
GND Ground
Document Number: 002-00719 Rev. *J Page 6 of 35
S25FL216K
4. Ordering Information
The ordering part number is formed by a valid combination of the follo wing:
4.1 Valid Combinations
Table 4.1 lists the valid combinations co nfigurations planned to be supported in volume for this device.
S25FL 216 K 0P M F I 01 1 Packing Type
0 = Tray
1 = Tube
3 = 13” Tape and Reel
Model Number (Additional Ordering Options)
04 = 8-pin SO package (150 mil)
01 = 8-pin SO package (208 mil)
Temperature Range
I = Industrial (–40°C to +85°C)
Package Materials
F = Lead (Pb)-free
Package Type
M = 8-pin SO p ackage
Speed
0P = 65 MHz
Device Technology
K = 0.09 µm process technology
Density
216= 16 Mbit
Device Family
S25FL
Spansion Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory
Table 4.1 S25FL216K Valid Combinations
S25FL216K Valid Combinations
Package Marking
Base Ordering
Part Number Speed Option Package and
Temperature Model
Number Packing Type
S25FL216K 0P MFI 01, 04 0, 1, 3 FL216KIF
Document Number: 002-00719 Rev. *J Page 7 of 35
S25FL216K
5. Memory Organizations
The memory is organized as:
2,097,152 bytes
Uniform Sector Architecture
– 32 blocks of 64 kB
– 512 sectors of 4 kB
8,192 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, Block or Chip Erasable but not
Page Erasable.
Figure 5.1 Memory Organization
xxFF00h xxFFFFh 1FFF00h 1FFFFFh
....
xxF000h xxF0FFh 1F0000h 1F0FFFh
xxEF00h xxEFFFh
..
xxE000h xxE0FFh
08FF00h 08FFFFh
..
080000h 0800FFh
07FF00h 07FFFFh
..
070000h 0700FFh
xx1F00h xx1FFFh
..
xx1000h xx10FFh
xx0F00h xx0FFFh 00FF00h 00FFFFh
....
xx0000h xx00FFh 000000h 0000FFh
...
…
...
Sector 15 (4 kB) Block 31 (64 kB)
Sector 14 (4 kB)
Sector 0 (4 kB)
Sector 1 (4 kB)
Block 7 (64 kB)
Block 8 (64 kB)
Block 0 (64 kB)
Document Number: 002-00719 Rev. *J Page 8 of 35
S25FL216K
6. Functional Description
6.1 SPI Modes
The S25FL216K device can be driven by an embedde d microcontroller (bus master) in either of the two following clocking modes.
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the output data is
always available from the falling edge of the SCK clock signal. The difference between the two modes is the clock polarity when the
bus master is in standby mode and not transferring any data.
SCK will stay at logic low state with CPOL = 0, CPHA = 0
SCK will stay at logic high state with CPOL = 1, CPHA = 1
Figure 6.1 SPI Modes
6.2 Dual Output SPI
The S25FL216K supports Dual Output Operation when using the “Fast Read with Dual Output” (3B hex) command. This feature
allows data to be transferred from the Serial Flash at twice the rate possible with the standard SPI. Thi s command can be used to
quickly download code from Flash to RAM upon Power-up (Code-shadowing) or for applications that cache code-segments to RAM
for execution.
The Dual Output feature simply allows the SPI data input pin (SI) to also serve as an output during this command. All other
operations use the standard SPI interface with single signal. The host keeps CS# low and HOLD# high. The Write Protect (WP#)
signal is ignored. The memory drives data on the SI/IO0 and SO signals during the dual output cycles. The next interface state
continues to be Dual Output Cycle until the host returns CS# to high ending the command.
6.3 Hold Function
The Hold (HOLD#) signal is used to pause any serial communications with the S25FL216K device without deselecting the device or
stopping the serial clock. To enter the Hold condition, the device must be selected by driving the CS# input to the logic low state. It is
recommended that the user keep the CS# input low state during the entire duration of the Hold condition. This is to ensure that the
state of the interface logic remains unchanged from the moment of entering the Hold condition. If the CS# input is driven to the logic
high state while the device is in the Hold condition, the interface logic of the devi ce will be reset. To restart communication with the
device, it is necessary to drive HOLD# to the logic high state while driving the CS# signal into the logi c low state. This prevents the
device from going back into the Hold condition.
The Hold condition starts on the falling edge of the Hold (HOLD#) signal, pr ovided t hat thi s coincid es with SCK bein g at the logic low
state. If the falling edge does not coincide with the SCK signal being at the logic low state, the Hold condition starts whenever the
SCK signal reaches the logic low state. Taking the HOLD# signal to the logic low state does not terminate any Write, Program or
Erase operation that is currently in progress.
CS#
Mode3
Mode 0
Mode 3
SI/IO0
DONT CARE
SO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
MSB
High Impedance
SCK
Mode0
Document Number: 002-00719 Rev. *J Page 9 of 35
S25FL216K
During the Hold condition, SO is in high impedance and both the SI and SCK input are Don't Care. The Hold condition ends on the
rising edge of the Hold (HOLD#) signal, provided that this coincides with the SCK signal being at the logic low state. If the rising
edge does not coincide with the SCK signal being at the logic low state, the Hold condition ends whenever the SCK signal reaches
the logic low state.
Figure 6.2 Hold Condition Waveform
6.4 Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions
WIP (Write In Progress) is a read only bit in the status register (R0) which indicates whether the device is performing a
program, write, erase operation, or any other operation, during which a new operation command will be ignored. When the
WIP bit is set to 1, the device is busy performing an operation. When the bit is cleared to 0, no operation is in progress.
Write Enable Latch (WEL) is a read only bit in the status register (R1) that must be set to 1 to enable program, write, or
erase operations as a means to provide protection against inadvertent changes to memory or register values. The Write
Enable (WREN) command execution sets the W rite Enable Latch to a 1 to allow any program, erase, or write commands to
execute afterwards. The Write Disable (WRDI) command can be used to set the Write Enable Latch to a 0 to prevent all
program, erase, and write commands from executio n. The WEL bit is cleared to 0 at the end of any successful program,
write, or erase operation. After a power down/power up sequence, hardware reset, or software reset, the Write Enable
Latch is set to a 0.
Block Protect Bits (BP3, BP2, BP1, BP0) are non-volatile read/write bits in the status register (R5, R4, R3, and R2) that
define the main flash array area to be software protected against program and erase commands. When one or more of the
BP bits is set to 1, the relevant memory area is protected against program and erase. The Chip Erase (CE) command can
be executed only when the BP bits are cleared to 0’s. See Table 7.1 on page 10 for a description of how the BP bit values
select the memory array area protected. The factory default setting for all the BP bits is 0, which implies that none of array
is protected.
Reserved Bits (REV), Status register bit location R6 is reserved for future use. Current devices will read 0 for this bit
location. It is recommended to mask out the reserved bit when testing the Status Register. Doing this will ensure
compatibility with future devices.
The St atus Register Protect (SRP) bit is a non-volatile read/write bit in status register (R7) that can be used in conjunction
with the Write Protect (WP#) pin to disable writes to st atus register . When the SRP bit is set to a 0 state (factory default) the
WP# pin has no control over status register. When the SRP pin is set to a 1, the Write Status Register instruction is locked
out while the WP# pin is low. When the WP# pin is high the Write Status Register instruction is allowed.
Table 6.1 Status Register Bit Locations
R7 R6 R5 R4 R3 R2 R1 R0
SRP REV BP3 BP2 BP1 BP0 WEL WIP
SCK
HOLD#
Active Hold Active Hold Active
Document Number: 002-00719 Rev. *J Page 10 of 35
S25FL216K
7. Write Protection
Some basic protection against unintended changes to stored data is provided and controlled purely by the hardware design. These
protection mechanisms in the S25FL216K device are described below:
Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is
outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a
multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Regi ster (WRSR) instruction completion or Page Program
(PP) instruction completion or Sector Erase (SE) instruction completion or Block Erase (BE) instruction completion or Chip
Erase (CE) instruction completion
The Block Protect (BP3, BP2, BP1, and BP0) bits allow part of the memory to be configured as read-only. Thi s is the
Software Protected Mode (SPM).
The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and S tatus Register Protect (SRP) bit to
be protected. This is the Hardware Protected Mode (HPM).
In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from
inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the
Release from Deep Power-down instruction).
Table 7.1 Protected Area Sizes Block Organization — S25FL216K
Status Bit Protect Blocks
BP3 BP2 BP1 BP0
0000 0 (None)
0001 1 (1 block, block 31th)
0010 2 (2 blocks, block 30th~31th)
0011 3 (4 blocks, block 28th~31th)
0100 4 (8 blocks, block 24th~31th)
0101 5 (16 blocks, block 16th~31th)
0110 6 (32 blocks, all)
0111 7 (32 blocks, all)
1000 8 (32 blocks, all)
1001 9 (32 blocks, all)
1010 10 (16 blocks, block 0th~15th)
1011 11 (24 blocks, block 0th~23th)
1100 12 (28 blocks, block 0th~27th)
1101 13 (30 blocks, block 0th~29th)
1110 14 (31 blocks, block 0th~30th)
1111 15 (32 blocks, all)
Document Number: 002-00719 Rev. *J Page 11 of 35
S25FL216K
7.1 Page Programming
To program one data byte, two instructions are required: Write Enab le (WREN), which is one byte, and a Page Program (PP)
sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this
overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0),
provided that they lie in consecutive addresses on th e same page of memory.
7.2 Sector Erase, Block Erase, and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have
been erased to all 1s (FFh). This can be achieved a sector at a time, using the Sector Erase (SE) instruction, a block at a time using
the Block Erase (BE) instruction or throughout the entire memory, using the Chi p Erase (CE) instruction. This starts an internal
Erase cycle (of duration tSE, tBE, or tCE). The Erase instruction must be preceded by a Write Enable (WREN) instruction.
7.3 Polling During a Write, Program, or Erase Cycle
A further improve ment in th e time to Write St atus Regi ster (WR SR), Program (PP) or Erase (SE, BE, or CE) can be achieved by not
waiting for the worst case delay (tW, tPP, tSE, tBE, or tCE). The Write In Progress (WIP) bit is provided in the Status Register so that
the application program can monitor its value, po lling it to establish when the previous Write cycle, Program cycle or Erase cycle is
complete.
7.4 Active Power, Stand-by Power, and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device
is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status
Register). The device then goes into the Standby Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the speci fic in struction (the Enter Deep Power-down Mode (DP) instruction) is
executed, with the device consumption at ICC2. The device remains in this mode until another specific instruction (the Release from
Deep Power-down Mode and Rea d Device ID (RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software
protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase
instructions.
8. Commands
The command set of the S25FL216K consists of fifteen basic instructions that are fully controlled through the SPI bus (see
Table 8.1). The host system must shift all commands, addresses, and data in and out of the device, beginning with the most
significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte co mmand on SI (all
commands are one byte long), most significant bit first. Each successive bit is latched on the rising edge of SCK.
Every command sequence begins with a one-byte co mmand code. The comma nd may be followed by address, data, both, or
nothing, depending on the command. CS# must be driven high after the last bit of the command sequence has been written. All
commands that write, program or erase require that CS# be driven high at a byte boundary, otherwise the command is not executed.
Since a byte is composed of eight bits, CS# must therefore be driven high when the number of clock pulses after CS# is driven low
is an exact multiple of eight. The device ignores any attempt to access the memory array during a Write Registers, program, or erase
operation, and continues the operation uninterrupted.
Table 8.1 Command Set (Sheet 1 of 2)
Command
Name Byte1 Code Byte2 Byte3 Byte4 Byte5 Byte6 N-bytes
Write Enable 06h
write Disable 04h
Read Status
Register 05h (S7-S0) (1) (Note 2)
Document Number: 002-00719 Rev. *J Page 12 of 35
S25FL216K
Notes:
1. Data bytes are shifted with Most Signif i cant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the device on the SO pin.
2. The Status Register conten ts will repeat continuously until CS# terminates the instruction.
3. See Table 8.2, Manufacturer and Device Identification on page 12 for Device ID information.
4. The Device ID will repeat continuously until CS# terminates the instruction.
8.1 Write Enable (06h)
The Write Enable command (Figure 8.1) sets the Write Enable Latch (WEL) bit in the Status Register to a 1, which enables the
device to accept a Write Status Register, program, or erase command.
The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase, and Write Status Register command.
The host system must first drive CS# low, write the WREN command, and then drive CS# high.
Write Status
Register 01h S7-S0
Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) continuous
Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0) (Next byte)
continuous
Fast Read
Dual Output 3Bh A23-A16 A15-A8 A7-A0 dummy
I/O=
(D6,D4,D2,D0)
O=
(D7,D5,D3,D1)
(One byte per 4
clocks,
continuous)
Page Program 02h A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) Up to 256
bytes
Block Erase
(64 kB) D8h A23-A16 A15-A8 A7-A0
Sector Erase
(4 kB) 20h A23-A16 A15-A8 A7-A0
Chip Erase C7h/60h
Power-down B9h
Release
Power-down /
Device ID ABh dummy dummy dummy (ID7-ID0) (4)
Manufacturer /
Device ID (3) 90h dummy dummy 00h (M7-M0) (ID7-ID0)
JEDEC ID 9Fh (M7-M0)
manufacturer (ID15-ID8)
Memory Type (ID7-ID0)
Capacity
Table 8.2 Manufacturer and Device Identification
OP Code (M7-M0) (ID15-ID0) (ID7-ID0)
ABh 14h
90h 01h 14h
9Fh 01h 4015h
Table 8.1 Command Set (Sheet 2 of 2)
Command
Name Byte1 Code Byte2 Byte3 Byte4 Byte5 Byte6 N-bytes
Document Number: 002-00719 Rev. *J Page 13 of 35
S25FL216K
Figure 8. 1 Write Enable Command Sequence
8.2 Write Disable (04h)
The Write Disable command (Figure 8.2) resets the Write Enable Latch (WEL) bit to a 0, which disables the device from accepting a
write, program or erase command. The host system must first drive CS# low, write the WRDI command, and then drive CS# high.
The WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,
Block Erase, and Chip Erase commands.
Figure 8.2 Write Disable Command Sequence
8.3 Read Status Register (05h)
The Read Status Register (RDSR) command outputs the state of the Status Register bits. The RDSR command may be written at
any time, even while a program, erase, or Write Registers operation is in progress. The host system shoul d check the Write In
Progress (WIP) bit before sending a new command to the device if an operation is already in progress. Figure 8.3 shows the RDSR
command sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven high. (See
Section 6.4, Status Register on page 9).
CS
SCK
05431 276
Mode0 Mode0
Mode3 Mode3
SI/IO0
SO High Impedance
Instruction(06H)
CS
SCK
05431 276
Mode0 Mode0
Mode3 Mode3
SI/IO0
SO
High Impedance
Instruction(04H)
Document Number: 002-00719 Rev. *J Page 14 of 35
S25FL216K
Figure 8.3 Read Status Register Command Seque nce
8.4 Write Status Register (01h)
The Write Status Register command allows the Status Reg ister to be written. A Write Enable command must previously have been
executed for the device to accept the Write Status Register command (Status Register bit WEL must equal 1). Once write enabled,
the command is entered by driving CS# low, sendin g the instruction code “01h”, and then writing the status register data byte as
illustrated in Figure 8.4. The Status Register bits are shown in Table 6.1 on page 9 and described in Section 6.4, Status Register
on page 9.
Only non-volatile Status Register bits SRP, BP3, BP2, BP1, and BP0 (bits 7, 5, 4, 3, and 2) can be written to. All other Status
Register bit locations are read-only and will not be affected by the Write Status Register command.
The CS# chip select input pin must be driven to the logic high state after the eighth bit of data has been latched in. If not, the Write
Status Register command is not executed. As soon as the CS# chip select input pin is driven to the logic high sta te, the self-timed
Write Status Register cycle is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is a 1 during the self-timed Write Status Register
cycle, and is a 0 when it is completed. When the Write Status Register cycle is completed, the Write Enable Latch (WEL) is set to a
0.
The Write Status Register command allows the Block Protect bits (BP3, BP2, BP1, and BP0) to be set for protecting all, a portion, or
none of the memory from erase and program commands. Protected areas become read-only (see Table 7.1 on page 10). The Write
Status Register command also allows the Status Register Protect bit (SRP) to be set. This bit is used in conjunction with the Write
Protect (WP#) pin to disable writes to the status register. When the SRP bit is set to a 0 state (factory default) the WP# pin has no
control over the status register. When the SRP pin is set to a 1, the Write Status Register command is locked out while the WP# pin
is low. When the WP# pin is high the Write Status Register comma nd is allowed.
CS#
SCK Mode0
Mode3 01 1514
13
121110987
6
5432 21
20
19181716 2322
SI/IO0
Instruction (05H)
SO
*=M SB
Status Register Out Status Register Out
**
High Impedance 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Document Number: 002-00719 Rev. *J Page 15 of 35
S25FL216K
Figure 8.4 Write Status Register Command Sequence
8.5 Read Data (03h)
The Read Data command allows one more data bytes to be sequentially read from the memory. The command is initiated by driving
the CS# pin low and then shifting the instruction code “03h” followed by a 24-bit address (A23-A0) into the SI/IO0 pin. The code and
address bits are latched on the rising edge of the SCK pin. After the address is received, the data byte of the addressed memory
location will be shifted out on the SO pin at the falling edge of SCK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after ea ch byte of data is shifted out allowing for a continuous stream of data. This means
that the entire memory can be accessed with a single command as lo ng as the clock continues. The command is completed by
driving CS# high.
The Read Data command sequence is shown in Figure 8.5. If a Read Data command is issued while an Erase, Program or Write
cycle is in process (WIP=1) the command is ignored and will not have any effects on the current cycle. The Read Data command
allows clock rates from D.C. to a maximum of fR. See AC Characteristics on page 28.
Figure 8.5 Read Data Command Sequence
8.6 Fast Read (0Bh)
The Fast Read command is similar to the Read Da ta command except that it can operate at higher frequency than the traditional
Read Data command. See AC Characteristics on page 28. This is accomplished by adding eight “dummy” clocks after the 24-bit
address as shown in Figure 8.6. The dummy clocks allow the device’s internal circuits additional time for setting up the initial
address. During the dummy clocks the data value on the SI pin is a “don’t care”.
CS#
SCK
Mode0
Mode3
01 1514
13
121110987
6
5432
Mode3
Mode0
SI/IO0
Instruction (01H)
SO High Im pedance
*
*= M SB
7 6 5 4 3 2 1 0
CS#
SCK Mode0
Mode3 01 10987
6
5432 30 39383736
35
34333231
28 29
SI/IO0
Instruction (03 H)
SO High Impedance
23 2
3
2122 01
6
75 2
31
40
*
*
*=M SB
24-Bit Address
Data O ut 1 Data O ut 2
7
Document Number: 002-00719 Rev. *J Page 16 of 35
S25FL216K
Figure 8.6 Fast Read Command Sequence
8.7 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) command is similar to the standard Fast Read (0Bh) command except that data is output on two
pins, SO and SI/IO0, instead of just SO. This allows data to be transferred from the S25FL216K at twice the rate of standard SPI
devices. The Fast Read Dual Output command is ideal for quickly downloading code from the SPI flash to RAM upon power-up or
for applications that cache code-segments to RAM for execution.
Similar to the Fast Read command, the Fast Read Dual Output command can operate at higher frequencies than the traditional
Read Data command. See AC Characteristics on page 28. This is accomplished by adding eight “dummy” clocks after the 24-bit
address as shown in Figure 8.7. The dummy clocks allow the device's internal circuits additional time for setting up the initial
address. The input data during the dummy clocks is “don’ t care”. However, the SI/IO0 pin should be high-impedance prior to the
falling edge of the first data out clock.
CS#
SCK
32 33 4241
4039
38
37363534 45 5453
5151
50
49484746
43 44
SI/IO0
Dummy Clocks
6
75 2
31
40
*
*=M SB
Data O ut 1
7
CS#
SCK
Mode0
Mode3
01 109
87
6
5432 30 31
28 29
SI/IO0
Instruction (0BH)
SO High Impedance
23 2
3
2122 01
*
24-Bit Address
6
75 2
3140
*
6
75 2
31
40
Data O ut 1
55
*
SO
Document Number: 002-00719 Rev. *J Page 17 of 35
S25FL216K
Figure 8.7 Fast Read Dual Ou tput Command Sequence
8.8 Page Program (PP) (02h)
The Page Program command allows up to 256 bytes of data to be programmed at previously erased to all 1s (FFh) memory
locations. A Write Enable command must be executed before th e device will accept the Page Program command (Status Register
bit WEL must equal 1). The command is initiated by driving the CS# pin low then shifting the command code “02h” followed by a 24-
bit address (A23-A0) and at least one data byte, into the SI/IO0 pi n. The CS# pin must be held low for the entire length of the
command while data is being sent to the device. The Page Program command sequence is shown in Figure 8.8.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. If the
last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning
of the page. In some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within
the same page. One condition to perform a partial page program is that the number of clocks can not exceed the remaining page
length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously
sent data.
As with the write and erase commands, the CS# pin must be driven high after the eighth bit of the last byte has been latched. If this
is not done the Page Program command will not be executed. After CS# is driven high, the self-timed Page Program command will
commence for a time du ra ti o n of tPP. See AC Characteristics on page 28. While the Page Program cycle is in progress, the Read
Status Register command may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Page Program
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again. After the Page Program
cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program command will not be
executed if the addressed page is protected by th e Block Protect (BP3, BP2, BP1, and BP0) bits (see Table 7.1 on page 10).
CS#
SCK Mode0
Mode3 01 109
87
6
5432 30 31
28 29
SI/IO0
Instruction (3BH)
SO
High Im pedance
23 2
3
2122 01
*
24-Bit Address
CS#
SCK
32 33 4241
4039
38
37363534 45 5453
5151
50
49484746
43 44
SI/IO0
Dummy Clocks
SO 5
73 5
73
11
*
*=M SB
75
73 5
7311
*
55
*
4
62 4
62
004
62 4
62
00 6
* *
SI/IO0 switches from input to output
D ata ou t 1 Data out 2 D ata o ut 3 Data out 4
Document Number: 002-00719 Rev. *J Page 18 of 35
S25FL216K
Figure 8.8 Page Program Command Sequence
8.9 Sector Erase (SE) (20h)
The Sector Erase command sets all bits in the addressed 4-kB sector to 1 (all bytes are FFh). Before the Sector Erase command
can be accepted by the device, a Write Enable command must be issued and decoded by the device, whic h sets the Write Enable
Latch bit in the Status Register to enable any write operations. The command is initiated by driving the CS# pin low and shifting the
command code “20h” followed by a 24-bit sector address (A23-A0). The Sector Erase command sequence is shown in Figure 8.9.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector Erase command
will not be executed. After CS# is driven high, the self-timed Sector Erase command will commence for a time duration of tSE.
See AC Characteristics on page 28. While the Sector Erase cycle is in progress, the Read Status Register command may still be
accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other commands again. After the Sector Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Sect or Erase comm an d w ill not be executed if the addressed page is protected
by the Block Protect (BP3, BP2, BP1, and BP0) bits (see Table 7.1 on page 10).
CS#
SCK
40 41 5049
4847
46
45444341 53
2072
5554
51 52
SI/IO0
Data Byte 2
SO
6
75 2
31
40
*
*=M SB
Data Byte 256
CS#
SCK
Mode0
Mode3
01 109
87
6
5432 30 31
28 29
SI/IO0
Instruction (02H)
SO High Impedance
23 2
3
2122 01
*
24-Bit Address
6
75 2
3140
*
6
75 2
31
40
Data Byte 3
34 35
32 33 38 39
37
36
6
75 2
31
40
*
2078
2077
2076
2075
2074
2073
2079
Mode0
Mode3
*
Data Byte 1
High Impedance
Document Number: 002-00719 Rev. *J Page 19 of 35
S25FL216K
Figure 8.9 Sector Erase Command Sequence
8.10 Block Erase (BE) (D8h)
The Block Erase command sets all bits in the addressed 64-kB block to 1 (all bytes are FFh). Before the BE command can be
accepted by the device, a Write Enable command must be issued and decoded by the device, which sets the Write Enable Latch in
the Status Register to enable any write operations. The command is initiated by driving the CS# pin low and shifting the command
code “D8h” followed a 24-bit block address (A23-A0). The Block Erase command sequence is shown in Figure 8.10.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase command
will not be executed. After CS# is driven high, the self-timed Block Erase command will commence for a time duration of tBE. See AC
Characteristics on page 28. While the Block Erase cycle is in progress, the Read Status Register command may still be accessed
for checking the status of the WIP bit. The WIP bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished
and the device is ready to accept other commands again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Block Erase command will not be executed if the addressed page is protected by the
Block Protect (BP3, BP2, BP1, and BP0) bits (see Table 7.1 on page 10).
Figure 8.10 Block Erase Command Sequence
8.11 Chip Erase (CE) (C7h)
The Chip Erase command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. Before the CE command can be
accepted by the device, a Write Enable command must be issued and decoded by the device, which sets the Write Enable Latch in
the Status Register to enable any write operations. The command is initiated by driving the CS# pin low and shifting the command
code “C7h”. The Chip Erase command sequence is shown in Figure 8.11.
CS#
SCK
Mode0
Mode3
01 3130
29
987
6
5432
Mode3
Mode0
SI/IO0
Instruction(20H)
SO High Impedance
*
*=M SB
23 22 2 1 0
24-Bit Address
CS#
SCK
Mode 0
Mode 3
01 3130
29
987
6
5432
Mode3
Mode0
SI/IO0
In s tru c tio n (D8)
SO High Impedance
*
*=M SB
23 22 210
24-Bit Address
Document Number: 002-00719 Rev. *J Page 20 of 35
S25FL216K
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase command will not be
executed. After CS# is driven high, the self-timed Chip Erase command will commence for a time duration of tCE. See AC
Characteristics on page 28. While the Chip Erase cycle is in progress, the Read Status Register command may still be accessed to
check the status of the WIP bit. The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other commands again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Chip Erase command will not be executed if any page is protected by the Block Protect (BP3,BP2, BP1,
and BP0) bits (see Table 7.1 on page 10).
Figure 8.11 Chip Erase Command Sequence
8.12 Deep Power-down (DP) (B9h)
The Deep Power-Down (DP) command provides the lowest power consumption mode of the device. It is intended for periods when
the device is not in active use, and ignores all commands except for the Release from Deep Power-Down (RES) command. The
lower power consumption makes the Deep Power-down command especially useful for battery powered applications (See ICC1 and
ICC2 in DC Characteristics on page 27.) The command is initiated by driving the CS# pin low and shifti ng the command code “B9h”
as shown in Figure 8.12.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power-down command will not be
executed. After CS# is driven high, the power-down state will enter within the time duration of tDP (See AC Characteristics
on page 28.) While in the power-down state only the Release from Power-down / Device ID command, which restores the device to
normal operation, will be recognized. All other commands are ignored. This incl udes the Read Status Register command, which is
always available during normal operation. The Deep Power-down mode therefore provides the maximum data protection against
unintended write operations. Deep Power-down mode automatically terminates when power is removed, and the device always
powers up in the standard standby mode. The device rejects any Deep Po wer-down command issued while it is executing a
program, erase, or Write Registers operation, and continues the operation uninterrupted.
CS#
SCK
05431 276
Mode0 Mode0
Mode3 Mode3
SI/IO0
SO
High Impedance
Instruction(C7H)
Document Number: 002-00719 Rev. *J Page 21 of 35
S25FL216K
Figure 8. 12 Deep Power-down Command Sequence
8.13 Release Deep Power-down / Device ID (ABh)
The Release from Deep Power-down / Device ID command is a multi-p urpose command. The device requires the Release from
Deep Power-down command to exit the Deep Power-down mode. When the device is in the Deep Power-down mode, all commands
except Release from Deep Power-down command are ignored. In addition, the ABh command can also be used to read the device's
8-bit electronic Device ID.
When used only to release the device from the power-down state, the command is issued by driving the CS# pin low, shifting the
command code “ABh” and driving CS# high as shown in Figure 8.13. After the time duration of tRES1 (See AC Characteristics
on page 28.) the device will resume normal operation and other command s will be accepted. The CS# pin must remain high during
the tRES1 time duration.
When used only to obtain the Device ID while not in the Deep power-down state, the command is initiated by driving the CS# pin low
and shifting the command code “ABh” followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of SCK
with most significant bit (MSB) first as shown in Figure 8.14. The Device ID value for the S25FL216K is listed in Manufacture r and
Device Identification table. The Device ID can be read c ontinuously. The command is completed by driving CS# high.
When used to release the device from the Deep power-down state and obtain the Device ID, the command is the same as
previously described, and shown in Figure 8.14, except that after CS# is driven high it must re main high for a time duration of tRES2
(See AC Characteristics on page 28.). After this time duration the device will resume normal operation and other commands will be
accepted. If the Release from Deep Power-down / Device ID command is issued while an Erase, Program or Write cycle is in
process (when WIP equals 1) the command is ignored and will not have any effects on the current cycle.
Figure 8.13 Release Deep Power-down Command
CS#
SCK
05431 276
Mode0
Mode3
SI/IO0
SO High Impedance
Instruction (B9H)
Mode3
tDP
Standard Current Power-down Current
Mode0
CS#
SCK
05431 276
Mode0
Mode3
SI/IO0
SO High Impedance
Instruction(ABH)
Mode3
tRES1
Deep P ow e r-d o w n C u rre n t
High Performance Current
Stand-by Current
Mode0
Document Number: 002-00719 Rev. *J Page 22 of 35
S25FL216K
Figure 8.14 Release Deep Power-down / Device ID Command Sequence
8.14 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID command is an alternative to the Release from Deep Power-down /Device ID comma nd that
provides both the JEDEC assigned manufac turer ID and the specific device ID.
The Read Manufacturer/Device ID command is very similar to the Release from Deep Powe r-down / Device ID command. The
command is initiated by driving the CS# pin low and shifting the command code “90h” followed by a 24-bit address (A23-A0) of
000000h. After which, the Manufacturer ID for Spansion (01h) and the Device ID are shifted out on the falling edge of SCK with most
significant bit (MSB) first as shown in Figure 8.15. The Device ID values for the S25FL216K are listed in Table 8.2 on page 12. If the
24-bit address is initially set to 000001h the Device ID will be read first, followed by the Manufacturer ID.
*=M SB
CS#
SCK
Mode0
Mode3
01 109
87
6
5432 30 31
28 29
SI/IO0
Instruction (ABH )
SO High Impedance
23 2
3
2122 01
*
3 Dummy Bytes
34 35
32 33 383736
6
75 2
31
40
*
Mode3
Mode0
Device ID **
t
RES2
Power down Current
High Performance Mode Current
Stand-by
Current
Document Number: 002-00719 Rev. *J Page 23 of 35
S25FL216K
Figure 8. 15 Read Manufacturer / Device ID Command Sequence
8.15 Read Identification (RDID) (9Fh)
For compatibility reasons, the S25FL216K provides several commands to electronically determine the identity of the device. The
Read JEDEC ID command is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003.
The command is initiated by driving the CS# pin low and shifting the command code “9Fh”. The JEDEC assigned Manu facturer ID
byte for Spansion (01h) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling
edge of SCK with most significant bit (MSB) first as shown in Figure 8.16. For memory type and capacity values refer to Table 8.2,
Manufacturer and Device Identification on page 12.
CS#
SCK
32 33 4241
4039
38
37363534 45 46
43 44
SI/IO0
62
*=MSB
CS#
SCK Mode0
Mode3 01 109
87
6
5432 30 31
28 29
SI/IO0
Instruction (90H)
SO High Impedance
23 2
3
2122 01
*
Address᧤000000 H᧥
6
75 2
3140
* *
Manufacturer ID Device ID**
Mode0
Mode3
Document Number: 002-00719 Rev. *J Page 24 of 35
S25FL216K
Figure 8. 16 Read JEDEC ID Command Sequence
CS#
SCK Mode0
Mode3 01 1514
13
121110987
6
5432
SI/IO0
Instruction (9FH )
SO
Manufacturer ID
*
High Im pedance
CS#
SCK
16 17 313029282726252423
22
21201918 Mode3
Mode0
SI/IO0
Memory Type ID 15-ID8
SO
*
*=M SB
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 07 6 5 4 3 2 1 0
C apacity ID 7 -ID 0
*
Document Number: 002-00719 Rev. *J Page 25 of 35
S25FL216K
9. Electrical Specifications
9.1 Power-up Timing
Figure 9.1 Power-up Timing
Notes:
1. The parameters are characterized only.
2. VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 9.1 Power-up Voltage and Timing
Parameter Symbol Type Unit
Min Max
VCC (min) to CS# Low tVSL (1) 10 µs
Time Delay Before Write Instruction tPUW (1) 110ms
Write Inhibit Threshold Volt age VWI (1) 12V
Vcc (max)
Vcc (min)
VWI
Reset
Stast
tVSL
CS# Must Track Vcc
Program, E ra s e, and Write Instruction are Ignored
Read Instructions
Allow ed
Device is Fully
Accessible
tPUW
Vcc
Time
Document Number: 002-00719 Rev. *J Page 26 of 35
S25FL216K
9.2 Absolute Maximum Ratings
Stresses above the values so mentioned above may cause permanen t damage to the device. These values are for a stress rating
only and do not imply that the device should be operated at conditions up to or above these values.
Notes:
1. This device has been designed and t ested for the specified operation ranges. Proper operation outside of these levels is not guaranteed . Exposure to absolute
maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damag e.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances
(RoHS) 2002/95/EU.
9.3 Recommended Operating Ranges
Note:
1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Table 9.2 Absolute Maximum Ratings
Parameters Symbol Conditions Range Unit
Supply Voltage VCC -0.6 to +4.0 V
Voltage applied on any pin VIO Relative to Ground -0.6 to VCC+0.4 V
Transient Voltage on any Pin VIOT <20 ns T ransient Relati ve
to Ground -2.0 to VCC+2.0 V
Storage Temperature TSTG -65 to +150 °C
Lead Temperature TLEAD (Note 2) °C
Table 9.3 Recommended Operating Ranges
Parameter Symbol Conditions Spec Unit
Min Max
Supply Voltage VCC FR = 65 MHz, fR = 44 MHz 2.7 3.6 V
Ambient Temperature, Operating TAIndustrial -40 +85 °C
Document Number: 002-00719 Rev. *J Page 27 of 35
S25FL216K
9.4 DC Characteristics
This section summarizes the DC Characteristics of the device. Designers should check that the opera ti ng conditions in their circuit
match the measurement condition s spe cified in the AC Measurement Con ditions in Table 9.6 on page 28, when relying on the
quoted parameters.
Notes:
1. Tested on sample basis and specified through design and characterization data. TA=25°C, VCC 3V.
2. Checker Board Pattern.
9.5 AC Measurement Conditions
Table 9.4 DC Characteristics
Symbol
(Notes) Parameter
(Notes) Conditions
(Notes) Spec Unit
Min Typ Max
CIN (1) Input Capacitance VIN = 0V (2) 6pF
COUT (1) Output Capacitance VOUT = 0V (2) 8pF
ILI Input Leakage ±2 µA
ILO I/O Leakage ±2 µA
ICC1 Standby Curren t CS# = VCC, VIN = GND or
VCC 15 35 µA
ICC2 Power-down Current CS# = VCC, VIN = GND or
VCC 15 32 µA
ICC3 Current Read Data / Dual Out put Read
33 MHz (2) C = 0.1 VCC / 0.9 VCC SO
= Open 10/12 15/18 mA
ICC3 Current Read Data / Dual Out put Read
65 MHz (2) C = 0.1 VCC / 0.9 VCC SO
= Open 25 mA
ICC4 Current Page Program CS# = VCC 15 20 mA
ICC5 Current Write Status Register CS# = VCC 10 18 mA
ICC6 Current Sector/Block Erase CS# = VCC 20 25 mA
ICC7 Current Chip Erase CS# = VCC 20 25 mA
VIL Input Low Voltage -0.5 VCC x 0.3 V
VIH Input High Voltage VCC x0.7 VCC +0.4 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = -100 µA VCC -0.2 V
Table 9.5 AC Measurement Conditions
Symbol Parameter Min Max Unit
CLLoad C apacitance 30 pF
TR, TFInput Rise and Fall Times 5 ns
VIN Input Pulse Voltages 0.2 VCC to 0.8 VCC V
VtIN Input Timing Reference Voltages 0.3 VCC to 0.7 VCC V
VtON Output Timing Reference Voltages 0.5 VCC to 0.5 VCC V
Document Number: 002-00719 Rev. *J Page 28 of 35
S25FL216K
Figure 9.2 AC Measurement I/O Waveform
9.6 AC Characteristics
Table 9.6 AC Characteristics (Sheet 1 of 2)
Symbol
(Notes) Alt Parameter
(Notes) Spec Unit
Min Typ Max
FRfCClock frequency
For all instructions, except Read Data (03h) D.C. 65 MHz
fRClock freq. Read Data instruction (03h) D.C. 44 MHz
tCLH, tCLL (1) Clock High, Low Time for all instructions except
Read Data (03h) 4ns
tCRLH, tCRLL (1) Clock High, Low Time for Read Data (03h)
instruction 4ns
tCLCH (2) Clock Rise Time peak to peak 0.1 V/ns
tCHCL (2) Clock Fall Time peak to peak 0.1 V/ns
tSLCH tCSS CS# Active Setup Time relative to SCK 5 ns
tCHSL CS# Not Active Hold Time relative to SCK 5 ns
tDVCH tDSU Data In Setup Time 4 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH CS# Active Hold Time relative to SCK 3 ns
tSHCH CS# Not Active Setup Time relative to SCK 5 ns
tSHSL tCSH CS# Deselect Time (for Array Read 'Array Read /
Erase or Program ' Read Status Register) 50/100 ns
tSHQZ (2) tDIS Output Disable Time 6 ns
tCLQV tVClock Low to Output Valid 11 14 ns
tCLQX tHO Output Hold Time 0 ns
tHLCH HOLD# Active Setup Time relative to SCK 5 ns
tCHHH HOLD# Active Hold Time relative to SCK 5 ns
tHHCH HOLD# Not Active Setup Time relative to SCK 5 ns
tCHHL HOLD# Not Active Hold Time relative to SCK 5 ns
tHHQX (2) tLZ HOLD# to Output Low-Z 7 ns
tHLQZ (2) tHZ HOLD# to Output High-Z 12 ns
tWHSL (3) Write Protect Setup Time Before CS# Low 20 ns
tSHWL (3) Write Protect Hold Time After CS# High 100 ns
tDP (2) CS# High to Power-down Mode 3 µs
tRES1 (2) CS# High to Standby Mode without Electronic
Signature Read 3µs
tRES2 (2) CS# High to Standby Mode with Electronic
Signature Read 1.8 µs
tWWrite Status Register Time 3 5 ms
Input Levels
0.8 Vcc
0.2 Vcc 0.3 Vcc
0.7 Vcc
Input and Output
Timing Reference Levels
Document Number: 002-00719 Rev. *J Page 29 of 35
S25FL216K
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.
4. For multiple bytes after first byte within a pa ge, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed.
5. Max value shown is for less than 10k cycles. For greater than 10k cycle s, max value is 4.0s.
6. Max value shown is for less than 10k cycles. For greater than 10k cycle s, max value is 30s.
Figure 9.3 Serial Output Timing
Figure 9.4 Input Timing
tBP1 Byte Program Time (First Byte) (4) 30 50 µs
tBP2 Additional Byte Program Time (After First Byte) (4) 612µs
tPP Page Program Time 1.6 5 ms
tSE Sector Erase Time (4 kB) 50 200 ms
tBE (5) Block Erase Time (64 kB) 0.45 1.5 s
tCE (6) Chip Erase Time 12 25 s
Table 9.6 AC Characteristics (Sheet 2 of 2)
Symbol
(Notes) Alt Parameter
(Notes) Spec Unit
Min Typ Max
CS#
SCK
SO / SI(IO0)
LSB Out
tCLQX
tCLQV
tCLQX
tCLQV tCL
tCH
tCLQL
tCLQH
tSHQZ
SI(IO0) is an O utput O NLY for the Fast Read Dual Output command (3Bh)
Note
Note:
CS#
SCK
tCHSL
tSLCH
tCLCH
tSHSL
tSHCH
tCHSH
tCHCL
SI/IO0
tDVCH tCHDX
MSB IN LSB IN
SO High Impedance
Document Number: 002-00719 Rev. *J Page 30 of 35
S25FL216K
Figure 9.5 Hold Timing
CS#
SCK
SI/IO0
tHLQZ
tCHHL
SO
tHLCH
HOLD#
tHHCH
tHHQ H
tCHHH
Document Number: 002-00719 Rev. *J Page 31 of 35
S25FL216K
10. Package Material
10.1 8-Pin SOIC 150-mi l Package (SOA 008)
g1019 \ 16-038.3f \ 10.06.11
NOTES:
1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
Document Number: 002-00719 Rev. *J Page 32 of 35
S25FL216K
10.2 8-Pin SOIC 208-mi l Package (SOC 008)
3602 \ 16-038.03 \ 9.1.6
NOTES:
1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
PACKAGE SOC 008 (inches) SOC 008 (mm)
JEDEC
SYMBOL MIN MAX MIN MAX
A 0.069 0.085 1.753 2.159
A1 0.002 0.0098 0.051 0.249
A2 0.067 0.075 1.70 1.91
b 0.014 0.019 0.356 0.483
b1 0.013 0.018 0.330 0.457
c 0.0075 0.0095 0.191 0.241
c1 0.006 0.008 0.152 0.203
D 0.208 BSC 5.283 BSC
E 0.315 BSC 8.001 BSC
E1 0.208 BSC 5.283 BSC
e .050 BSC 1.27 BSC
L 0.020 0.030 0.508 0.762
L1 .049 REF 1.25 REF
L2 .010 BSC 0.25 BSC
N 8 8
θ0˚ 8˚ 0˚ 8˚
θ1 5˚ 15˚ 5˚ 15˚
θ2 0˚ 0˚
Document Number: 002-00719 Rev. *J Page 33 of 35
S25FL216K
11. Revision History
Section Description
Revision 01 (October 7, 2011)
Initial release
Revision 02 (October 31, 2011)
Global Removed USON package offering
Revision 03 (December 21, 2011)
DC Characteristics Updated ICC2 values
Revision 04 (January 6, 2012)
Distinctive Features Updated Standby Current value
Revision 05 (May 7, 2012)
Global Promoted data sheet from Advance Information to Preliminary
Distinctive Features Updated SPI clock frequencies: Fast Read and Dual Output Read
Updated Sector erase time
Recommended Operating Rang es Updated Supply Voltage Conditions
DC Characteristics DC Characteristics table: updated Max values for ICC1 and ICC2
AC Characteristics AC Characteristics table: Updated Max values for FR, updated Max value for fR, updated values for
tCLQV, updated values for tW
Revision 06 (July 18, 2012)
AC Characteristics AC Characteristics table: added note 5 and 6
Revision 07 (August 9, 2012)
Status Register Changed status register bit R0 from ‘BUSY’ to ‘WIP’
Global Changed ‘BUSY’ to ‘WIP’
Revision 08 (November 16, 2012)
AC Characteristics AC Characteristics table: changed Sector Erase Time (4 kB) Typ value
Revision 09 (January 17, 2013)
Cover Sheet Added Nantronics logo to cover sheet
Revision 10 (September 16, 2013)
Global Changed data sheet designation to “Full Production”
Document Number: 002-00719 Rev. *J Page 34 of 35
S25FL216K
Document History Page
Document Title: S25FL216K 16-Mbit 3.0 V Serial Flash Memory with Uniform 4 kB Sectors
Document Number: 002-00719
Revision ECN Orig. of
Change Submission
Date Description of Change
** – BWHA 10/07/2011 Initial release
*A – BWHA 10/31/2011 Global:
Removed USON package offering
*B – BWHA 12/21/2011 DC Characteristics:
Updated ICC2 values
*C – BWHA 01/06/2012 Distinctive Features:
Updated Standby Current value
*D – BWHA 05/07/2012 Global:
Promoted data sheet from Advance Information to Preliminary
Distinctive Features:
Updated SPI clock frequencies: Fast Read and Dual Output Read
Updated Sector erase time
Recommended Operating Ranges:
Updated Supply Voltage Conditions
DC Characteristics:
DC Characteristics table: updated Max values for ICC1 and ICC2
AC Characteristics:
AC Characteristics table: Updated Max values for FR, updated Max value for fR, updated
values for tCLQV, updated values for tW
*E – BWHA 07/18/2012 AC Characteristics:
AC Characteristics table: added note 5 and 6
*F – BWHA 08/09/2012 Status Register:
Changed status register bit R0 from ‘BUSY’ to ‘WIP’
Global:
Changed ‘BUSY’ to ‘WIP’
*G – BWHA 11/16/2012 AC Characteristics:
AC Characteristics table: changed Sector Erase Time (4 kB) Typ value
*H – BWHA 01/17/2013 Cover Sheet:
Added Nantronics logo to cover sheet
*I – BWHA 09/16/2013 Global:
Changed data sheet designation to “Full Production”
*J 4925867 BWHA 09/24/2015 Updated to Cypress template
Document Number: 002-00719 Rev. *J Revised September 24, 2015 Page 35 of 35
Cypress®, Spa nsion®, Mirr orBit®, MirrorBit® Eclipse™ , ORNAND™, HyperBus™, Hyp erFlash™ and combinations th ereof, are tr ademarks an d registe red trademar ks of Cypress Sem iconduct or Co rp .
All products and company names mentioned in this document may be the trademarks of their respective holders.
© Cypress Semico nducto r Co rpor ation , 2011-2015. The i nfor mation cont ai ned he rein is subj ect to chang e with out no tice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or safety ap pl i cations, unless pur suan t to an express written ag re em en t w it h C ypr ess. Fu rth erm ore, Cyp ress doe s not auth ori ze i t s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress pr oducts in life-su pport systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protecti on (United States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee pr oduct to be used only in conjunction with a Cyp ress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials de scribed herei n. Cypress d oes not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
S25FL216K
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