MC14007UBFELG - ON Semiconductor

June, 2011 − Rev. 9

1Publication Order Number:

MC14007UB/D

MC14007UB

Dual Complementary Pair

Plus Inverter

The MC14007UB multipurpose device consists of three N−Channel

and three P−Channel enhancement mode devices packaged to provide

access to each device. These versatile parts are useful in inverter

circuits, pulse−shapers, linear amplifiers, high input impedance

amplifiers, threshold detectors, transmission gating, and functional

gating.

Features

•Diode Protection on All Inputs

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range

•Pin−for−Pin Replacement for CD4007A or CD4007UB

•This device has 2 outputs without ESD Protection. Antistatic

precautions must be taken.

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD +0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

±10 mA

PDPower Dissipation, per Package

(Note 1)

500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8 second Soldering)

260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/°C from 65°C 5o 125°C.

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

11

12

13

14

8

9

105

4

3

2

1

7

6

GATEC

S−PC

OUTC

D−PA

VDD

D−NA

S−NC

S−NB

GATEB

S−PB

D−PB

VSS

GATEA

D−NB

PIN ASSIGNMENT

D = DRAIN

S = SOURCE

MARKING

DIAGRAMS

1

14

PDIP−14

P SUFFIX

CASE 646

MC14007UBCP

AWLYYWWG

SOIC−14

D SUFFIX

CASE 751A

1

14

14007UG

AWLYWW

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G = Pb−Free Indicator

SOEIAJ−14

F SUFFIX

CASE 965

1

14

MC14007UB

ALYWG

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MC14007UB

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2

Figure 1. Typical Application: 2−Input Analog Multiplexer

A

B

C

INPUT

A

B

C

12

1

3

5

9

2

4

11

10

14

VDD

6

7V

SS

8

13

INPUT

1

0

OUTPUT CONDITION

A = C, B = OPEN

A = B, C = OPEN

Substrates of P−Channel devices internally

connected to VDD; substrates of N−Channel

devices internally connected to VSS.

Figure 2. Schematic

14 13 2 1 11

126

78 3 4 510 9

VDD = PIN 14

VSS = PIN 7

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎÎ

−55°C

ÎÎÎÎÎÎÎÎ

25°C

ÎÎÎÎÎÎ

125°C

ÎÎ

Unit

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 2)

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

Vin = 0 or VDD “1” Level

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎÎ

0

ÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎÎ

0.05

ÎÎ

Vdc

ÎÎÎÎ

VOH

ÎÎÎ

5.0

10

15

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

−

ÎÎ

Vdc

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 Vdc)

(VO = 9.0 Vdc)

(VO = 13.5 Vdc)

(VO = 0.5 Vdc) “1” Level

(VO = 1.0 Vdc)

(VO = 1.5 Vdc)

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

1.0

2.0

2.5

ÎÎÎ

−

ÎÎÎÎ

2.25

4.50

6.75

ÎÎÎ

1.0

2.0

2.5

ÎÎÎ

−

ÎÎÎÎ

1.0

2.0

2.5

ÎÎ

Vdc

ÎÎÎÎ

VIH

ÎÎÎ

5.0

10

15

ÎÎÎÎ

4.0

8.0

12.5

ÎÎÎ

−

ÎÎÎ

4.0

8.0

12.5

ÎÎÎÎ

2.75

5.50

8.25

ÎÎÎ

−

ÎÎÎ

4.0

8.0

12.5

ÎÎÎÎ

−

ÎÎ

Vdc

ÎÎÎÎ

IOH

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎ

5.0

10

15

ÎÎÎÎ

–3.0

–0.64

–1.6

–4.2

ÎÎÎ

−

ÎÎÎ

–2.4

–0.51

−1.3

−3.4

ÎÎÎÎ

–5.0

–1.0

–2.5

–10

ÎÎÎ

−

ÎÎÎ

–1.7

−0.36

–0.9

−2.4

ÎÎÎÎ

−

ÎÎ

mAdc

ÎÎÎÎ

IOL

ÎÎÎ

5.0

10

15

ÎÎÎÎ

0.64

1.6

4.2

ÎÎÎ

−

ÎÎÎ

0.51

1.3

3.4

ÎÎÎÎ

1.0

2.5

10

ÎÎÎ

−

ÎÎÎ

0.36

0.9

2.4

ÎÎÎÎ

−

ÎÎ

mAdc

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎ

15

ÎÎÎÎ

−

ÎÎÎ

±0.1

ÎÎÎ

−

ÎÎÎÎ

±0.00001

ÎÎÎ

±0.1

ÎÎÎ

−

ÎÎÎÎ

±1.0

ÎÎ

mAdc

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

5.0

ÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎ

pF

ÎÎÎÎ

IDD

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

0.25

0.5

1.0

ÎÎÎ

−

ÎÎÎÎ

0.0005

0.0010

0.0015

ÎÎÎ

0.25

0.5

1.0

ÎÎÎ

−

ÎÎÎÎ

7.5

15

30

ÎÎ

mAdc

ÎÎÎÎ

IT

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (Notes 3 and 4)

(Dynamic plus Quiescent,

Per Gate) (CL = 50 pF)

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.7 mA/kHz) f + IDD/6

IT = (1.4 mA/kHz) f + IDD/6

IT = (2.2 mA/kHz) f + IDD/6

ÎÎ

mAdc

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25°C.

4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.003.

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25°C)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

VDD

Vdc

ÎÎÎÎÎ

Min

ÎÎÎÎÎ

Typ

(Note 6)

ÎÎÎÎÎ

Max

ÎÎ

Unit

ÎÎÎÎ

tTLH

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise Time

tTLH = (1.2 ns/pF) CL + 30 ns

tTLH = (0.5 ns/pF) CL + 20 ns

tTLH = (0.4 ns/pF) CL + 15 ns

ÎÎÎÎÎ

5.0

10

15

ÎÎÎÎÎ

−

ÎÎÎÎÎ

90

45

35

ÎÎÎÎÎ

180

90

70

ÎÎ

ns

ÎÎÎÎ

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Fall Time

tTHL = (1.2 ns/pF) CL + 15 ns

tTHL = (0.5 ns/pF) CL + 15 ns

tTHL = (0.4 ns/pF) CL + 10 ns

ÎÎÎÎÎ

5.0

10

15

ÎÎÎÎÎ

−

ÎÎÎÎÎ

75

40

30

ÎÎÎÎÎ

150

80

60

ÎÎ

ns

ÎÎÎÎ

tPLH

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Turn−Off Delay Time

tPLH = (1.5 ns/pF) CL + 35 ns

tPLH = (0.2 ns/pF) CL + 20 ns

tPLH = (0.15 ns/pF) CL + 17.5 ns

ÎÎÎÎÎ

5.0

10

15

ÎÎÎÎÎ

−

ÎÎÎÎÎ

60

30

25

ÎÎÎÎÎ

125

75

55

ÎÎ

ns

ÎÎÎÎ

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Turn−On Delay Time

tPHL = (1.0 ns/pF) CL + 10 ns

tPHL = (0.3 ns/pF) CL + 15 ns

tPHL = (0.2 ns/pF) CL + 15 ns

ÎÎÎÎÎ

5.0

10

15

ÎÎÎÎÎ

−

ÎÎÎÎÎ

60

30

25

ÎÎÎÎÎ

125

75

55

ÎÎ

ns

5. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 3. Typical Output Source Characteristics Figure 4. Typical Output Sink Characteristics

VDD = -VGS VDD = VGS

14

VDS = VOH - VDD VDS = VOL

VSS VSS

7

IOH IOL

IOH, DRAIN CURRENT (mAdc)

IOL , DRAIN CURRENT (mAdc)

0

-4.0

-8.0

-12

-16

-20

-8.0-10 -6.0 -4.0 -2.0 -0

VDS, DRAIN VOLTAGE (Vdc)

20

16

12

8.0

4.0

0

0 2.0 4.0 6.0 8.0 10

VDS, DRAIN VOLTAGE (Vdc)

TA = -55°C

TA = +25°C

TA = +125°C

a

b

c

VGS = -5.0 Vdc b

c

a

-10 Vdc -15 Vdc

c

bc

b

a

b

c

a

bc

a

b

c

5.0 Vdc

TA = -55°C

TA = +25°C

TA = +125°C

a

b

c

VGS = 15 Vdc

10 Vdc

All unused inputs connected to ground. All unused inputs connected to ground.

These typical curves are not guarantees, but are design aids.

Caution: The maximum current rating is 10 mA per pin.

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5

Figure 5. Switching Time and Power Dissipation Test Circuit and Waveforms

PULSE

GENERATOR

VDD

500mF0.01 mF

CERAMIC

14

CL

Vout

VSS

7

Vin

IDVin

Vout

90%

50%

10%

90%

50%

10%

20 ns 20 ns

VDD

VSS

VOH

VOL

tTHL tTLH

tPHL tPLH

APPLICATIONS

The MC14007UB dual pair plus inverter, which has access to all its elements offers a number of unique circuit applications.

Figures 1, 6, and 7 are a few examples of the device flexibility.

Figure 6. 3−State Buffer

+VDD

DISABLE3

INPUT10

DISABLE6

12OUTPUT

11

1

2

9

8

7

INPUT DISABLE OUTPUT

1

0

X

0

1

0

1

OPEN

X = Don’t Care

Figure 7. AOI Functions Using Tree Logic

VDD

14

13

11

10

3

6

B

C

A

9

5

4

8

7

1

2

OUTPUT

OUT = A+B•C

Substrates of P−Channel devices internally connected to VDD;

Substrates of N−Channel devices internally connected to VSS.

12

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ORDERING INFORMATION

Device Package Shipping†

MC14007UBCPG PDIP−14

(Pb−Free) 25 Units / Rail

MC14007UBDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14007UBDR2G SOIC−14

(Pb−Free) 2500 / Tape & Reel

MC14007UBFELG SOEIAJ−14

(Pb−Free) 2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE P

17

14 8

B

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L

M−−− 10 −−− 10

N0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG D

K

C

SEATING

PLANE

N

−T−

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

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PACKAGE DIMENSIONS

SOIC−14 NB

CASE 751A−03

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.

H

14 8

71

M

0.25 B M

C

h

X 45

SEATING

PLANE

A1

A

M

_

S

A

M

0.25 B S

C

b

13X

B

A

E

D

e

DETAIL A

L

A3

DETAIL A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

D8.55 8.75 0.337 0.344

E3.80 4.00 0.150 0.157

A1.35 1.75 0.054 0.068

b0.35 0.49 0.014 0.019

L0.40 1.25 0.016 0.049

e1.27 BSC 0.050 BSC

A3 0.19 0.25 0.008 0.010

A1 0.10 0.25 0.004 0.010

M0 7 0 7

H5.80 6.20 0.228 0.244

h0.25 0.50 0.010 0.019

__ __

6.50

14X

0.58

14X

1.18

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

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PACKAGE DIMENSIONS

SOEIAJ−14

CASE 965−01

ISSUE B

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.004 0.008

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 1.42 --- 0.056

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH OR PROTRUSIONS AND ARE MEASURED

AT THE PARTING LINE. MOLD FLASH OR

PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)

PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

0.13 (0.005) M0.10 (0.004)

D

Z

E

1

14 8

7

eA

b

VIEW P

c

L

DETAIL P

M

A

b

c

D

E

e

L

M

Z

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

MC14007UB/D

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