W83194R-39/-39A
100MHZ 3-DIMM CLOCK
Publication Release Date: May 27, 2005
- 1 - Revision A1
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. PRODUCT FEATURES .............................................................................................................. 3
3. BLOCK DIAGRAM ...................................................................................................................... 4
4. PIN CONFIGURATION...............................................................................................................4
5. PIN DESCRIPTION..................................................................................................................... 5
5.1 Crystal I/O ....................................................................................................................... 5
5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs................................................................. 5
5.3 I2C Control Interface ....................................................................................................... 6
5.4 Fixed Frequency Outputs ............................................................................................... 6
5.5 Power Pins......................................................................................................................6
6. FREQUENCY SELECTION ........................................................................................................ 7
6.1 Frequency table of W83194R-39.................................................................................... 7
6.2 Frequency table of W83194R-39A ................................................................................. 7
7. MODE PIN -POWER MANAGEMENT INPUT CONTROL......................................................... 8
8. FUNTION DESCRIPTION .......................................................................................................... 8
8.1 POWER MANAGEMENT FUNCTIONS ......................................................................... 8
8.2 2-WIRE I2C CONTROL INTERFACE ............................................................................. 8
8.3 SERIAL CONTROL REGISTERS .................................................................................. 9
8.3.1 Register 0: CPU Frequency Select Register (default = 0)..............................................9
8.3.2 Register 1 : CPU , 48/24 MHz Clock Register (1 = enable, 0 = Stopped) ....................10
8.3.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped) .............................................10
8.3.4 Register 3: SDRAM Clock Register ( 1 = enable, 0 = Stopped ).....................................10
8.3.5 Register 4: Reserved Register (1 = enable, 0 = Stopped) ..............................................11
8.3.6 Register 5: Peripheral Control (1 = enable, 0 = Stopped)...............................................11
9. SPECIFICATIONS .................................................................................................................... 11
9.1 ABSOLUTE MAXIMUM RATINGS ............................................................................... 11
9.2 AC CHARACTERISTICS.............................................................................................. 12
9.3 DC CHARACTERISTICS.............................................................................................. 12
9.4 BUFFER CHARACTERISTICS .................................................................................... 13
9.4.1 TYPE 1 BUFFER FOR CPU CLOCK...........................................................................13
9.4.2 TYPE 2 BUFFER FOR IOAPIC ...................................................................................14
9.4.3 TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ ...........................................................14
9.4.4 TYPE 4 BUFFER FOR SDRAM (0:12)......................................................................14
9.4.5 TYPE 5 BUFFER FOR PCICLK(0:4,F) ........................................................................15
W83194R-39/-39A
- 2 -
10. POWER MANAGEMENT TIMING ............................................................................................ 15
10.1 CPU_STOP# Timing Diagram...................................................................................... 15
10.2 PCI_STOP# Timing Diagram........................................................................................ 16
11. OPERATION OF DUAL FUCTION PINS.................................................................................. 16
12. ORDERING INFORMATION .................................................................................................... 18
13. HOW TO READ THE TOP MARKING...................................................................................... 18
14. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 19
15. REVISION HISTORY ................................................................................................................20
W83194R-39/-39A
Publication Release Date: May 27, 2005
- 3 - Revision A1
1. GENERAL DESCRIPTION
The W83194R-39/-39A is a Clock Synthesizer which provides all clocks required for high-speed RISC
or CISC microprocessor such as Intel Pentium II. W83194R-39 provides eight different frequencies
CPU and PCI clocks; W83194R-39A provides sixteen CPU/PCI frequencies which are externally
selectable with smooth transitions. W83194R-39/-39A also provides 13 SDRAM clocks controlled by
the none-delay buffer_in pin.
The W83194R-39/-39A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable stopping
individual clock outputs and frequency selection through I2C interface. The device meets the
Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-
up. Using dual function pin for the slots (ISA, PCI, CPU, DIMM) is not recommend. The add on cards
may have a pull up or pull down.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into
20 pF loads, when maintaining 50± 5% duty cycle. The fixed frequency outputs, such as REF,
24MHz, and 48 MHz provide better than 0.5V /ns slew rate.
2. PRODUCT FEATURES
• Supports Pentium II CPU with I2C.
• 2 CPU clocks (one free-running CPU clock)
• 13 SDRAM clocks for 3 DIMs
• 6 PCI synchronous clocks
• One IOAPIC clock for multiprocessor support
• Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
• < 250ps skew among CPU and SDRAM clocks
• < 250ps skew among PCI clocks
• < 5ns propagation delay SDRAM from buffer input
• Skew from CPU (earlier) to PCI clock -1 to 4ns, center 2.6ns.
• Smooth frequency switch with selections from 50 MHz to 133 MHz CPU
• I
2C 2-Wire serial interface and I2C read back
• ±0.25% or ±0.5% spread spectrum function to reduce EMI
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• MODE pin for power Management
• One 48 MHz for USB & one 24 MHz for super I/O
• 48-pin SSOP package
W83194R-39/-39A
- 4 -
3. BLOCK DIAGRAM
W83194R-39 W83194R-39A
PLL2
XTAL
OSC
Spread
Spectrum
PLL1
LATCH
POR STOP
1/2
Control
Logic
Config.
Reg.
STOP
STOP
STOP
PCI
Clock
Divider
a
a
4
2
13
5
48MHz
24MHz
IOAPIC
REF(0:1)
CPUCLK_
F
CPUCLK1
SDRAM(0:1
PCICLK(0:
4
PCICLK_F
Xin
Xout
BUFFER IN
FS(0:2)*
3
MODE*
CPU_STOP#
PCI_STOP#
SDATA*
SDCLK*
PLL2
XTAL
OSC
Spread
Spectrum
PLL1
LATCH
POR STOP
1/2
Control
Logic
Config.
Reg.
STOP
STOP
STOP
PCI
Clock
Divider
a
a
4
2
12
5
48MHz
24MHz
IOAPIC
REF(0:1)
CPUCLK_F
CPUCLK1
SDRAM(0:1
1
PCICLK(0:4
)
PCICLK_F
Xin
Xout
BUFFER IN
FS(0:3)*4
MODE*
CPU_STOP#
PCI_STOP#
SDATA*
SDCLK*
SDRAM12
4. PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vddq1
PCI_STOP#/REF0
Vss
Xin
Xout
Vddq2
PCICLK_F/MODE*
PCICLK0/FS3*
Vss
PCICLK1
PCICLK2
PCICLK3
PCICLK4
Vddq2
BUFFER IN
Vss
SDRAM11
SDRAM10
Vddq3
SDRAM 9
SDRAM 8
Vss
SDATA
SDCLK
VddL1
IOAPIC
REF1/FS2*
Vss
CPUCLK_F
CPUCLK1
VddL2
CPU_STOP#
SDRAM12
Vss
SDRAM 0
SDRAM 1
SDRAM 2
Vddq3
SDRAM 3
Vss
SDRAM 4
SDRAM 5
SDRAM 6
SDRAM 7
Vddq4
Vddq3
48MHz/FS0*
24MHz/FS1*
(W83194R-39A )
W83194R-39/-39A
Publication Release Date: May 27, 2005
- 5 - Revision A1
5. PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kΩ pull-up
5.1 Crystal I/O
SYMBOL PIN I/O FUNCTION
Xin 4 IN
Crystal input with internal loading capacitors and
feedback resistors.
Xout 5 OUT Crystal output at 14.318MHz nominally.
5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL PIN I/O FUNCTION
CPUCLK_F 44 OUT
Free running CPU clock. Not affected by
CPU_STOP#
CPUCLK1 43 OUT
Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
Powered by VddL2. Low if CPU_STOP# is low.
CPU_STOP# 41 IN
This asynchronous input halts CPUCLK1,IOAPIC &
SDRAM(0:12) at logic “0” level when driven low.
IOAPIC 47 OUT
High drive buffered output of the crystal, and is
powered by VddL1.
SDRAM [ 0:12]
17,18,20,21,2
8,29,31,32,34,
35,37,38,40
OUT SDRAM clock outputs. Fanout buffer outputs from
BUFFER IN pin.(Controlled by chipset)
PCICLK_F/
*MODE 7 I/O
Free running PCI clock during normal operation.
Latched Input. Mode=1, Pin 2 is REF0; Mode=0,
Pin2 is PCI_STOP#
PCICLK0/*FS3
(W83194R-39A) 8 I/O
Low skew (< 250ps) PCI clock outputs.
Latched input for FS3 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
PCICLK [ 0:4 ]
(W83194R-39) 8,10,11,12,13 OUT
Low skew (< 250ps) PCI clock outputs.
Synchronous to CPU clocks with 1-48ns skew(CPU
early).
BUFFER IN 15 IN Inputs to fanout for SDRAM outputs.
SDRAM [ 0: 11 ]
17,18,20,21,
28,29,31,32,
34,35,37,38
O Synchronous DRAM DIMs clocks which have the
same frequency as CPU clocks
W83194R-39/-39A
- 6 -
5.3 I2C Control Interface
SYMBOL PIN I/O FUNCTION
*SDATA 23 I/O
Serial data of I2C 2-wire control interface with
internal pull-up resistor.
*SDCLK 24 IN
Serial clock of I2C 2-wire control interface with
internal pull-up resistor.
5.4 Fixed Frequency Outputs
SYMBOL PIN I/O FUNCTION
REF0 / PCI_STOP# 2 I/O
14.318MHz reference clock. This REF output is the
stronger buffer for ISA bus loads.
Halt PCICLK(0:4) clocks at logic 0 level, when input
low (In mobile mode. MODE=0)
REF1 / *FS2 46 I/O
14.318MHz reference clock.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
24MHz / *FS1 25 I/O
24MHz output clock.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
48MHz / *FS0 26 I/O
48MHz output for USB during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
5.5 Power Pins
SYMBOL PIN FUNCTION
Vddq1 1 Power supply for Ref [0:1] crystal and core logic.
VddL1 48 Power supply for IOAPIC output, either 2.5V or 3.3V.
VddL2 42 Power supply for CPUCLK[0:3], either 2.5V or 3.3V.
Vddq2 6, 14 Power supply for PCICLK_F, PCICLK[0:4], 3.3V.
Vddq3 19, 30, 36 Power supply for SDRAM[0:12], and CPU PLL core,
nominal 3.3V.
Vddq4 27
Power for 24 & 48MHz output buffers and fixed PLL
core.
Vss 3,9,16,22,33,39,45 Circuit Ground.
W83194R-39/-39A
Publication Release Date: May 27, 2005
- 7 - Revision A1
6. FREQUENCY SELECTION
6.1 Frequency table of W83194R-39
FS2 FS1 FS0 CPU,SDRAM (MHZ) PCI (MHZ) REF,IOAPIC (MHZ)
0 0 0 50 25(CPU/2) 14.318
0 0 1 75 37.5(CPU/2) 14.318
0 1 0 83.3 41.65(CPU/2) 14.318
0 1 1 66.8 33.4(CPU/2) 14.318
1 0 0 103 34.3(CPU/3) 14.318
1 0 1 112 37.33(CPU/3) 14.318
1 1 0 133 33.25(CPU/4) 14.318
1 1 1 100.2 33.3(CPU/3) 14.318
6.2 Frequency table of W83194R-39A
FS3=0 CPU,SDRAM (MHZ) PCI (MHZ) REF,IOAPIC
FS2 FS1 FS0 (MHZ)
0 0 0 124 41.33(CPU/3) 14.318
0 0 1 75 37.5(CPU/2) 14.318
0 1 0 83.3 41.65(CPU/2) 14.318
0 1 1 66.8 33.4(CPU/2) 14.318
1 0 0 103 34.3(CPU/3) 14.318
1 0 1 112 37.33(CPU/3) 14.318
1 1 0 133 44.33(CPU/3) 14.318
1 1 1 100.3 33.3(CPU/3) 14.318
FS3=1 CPU,SDRAM (MHZ) PCI (MHZ) REF,IOAPIC
FS2 FS1 FS0 (MHZ)
0 0 0 120 40.00(CPU/3) 14.318
0 0 1 115 38.33(CPU/3) 14.318
0 1 0 110 36.67(CPU/3) 14.318
0 1 1 105 35.00(CPU/3) 14.318
1 0 0 140 35.00(CPU/4) 14.318
1 0 1 150 37.50(CPU/4) 14.318
1 1 0 124 31.00(CPU/4) 14.318
1 1 1 133 33.25(CPU/4) 14.318
W83194R-39/-39A
- 8 -
7. MODE PIN -POWER MANAGEMENT INPUT CONTROL
MODE, PIN7 (LATCHED INPUT) PIN 2
0 PCI_STOP# (Input)
1 REF0 (Output)
8. FUNTION DESCRIPTION
8.1 POWER MANAGEMENT FUNCTIONS
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCO to stabilize prior to enabling clock outputs to
assure correct pulse widths. When MODE=0, pins 15 and 46 are inputs (PCI_STOP#),
(CPU_STOP#), when MODE=1, these functions are not available. A particular clock can be enabled
as both the 2-wire serial control interface and one of these pins indicate that it should be enable.
The W83194R-39/-39A may be disabled in the low state according to the following table in order to
reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period
on transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
CPU_STOP# PCI_STOP# CPUCLK1, IOAPIC &
SDRAM 0:12 PCI OTHER CLKS XTAL & VCOS
0 0 LOW LOW RUNNING RUNNING
0 1 LOW RUNNING RUNNING RUNNING
1 0 RUNNING LOW RUNNING RUNNING
1 1 RUNNING RUNNING RUNNING RUNNING
8.2 2-WIRE I2C CONTROL INTERFACE
The clock generator is a slave I2C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83194R-39/-39A initializes with default register settings. Use of the 2-wire control interface is then
optional.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle.
Data is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address and a write command bit [1101
0010], command code checking [0000 0000], and byte count checking. After successful reception of
each byte, an “acknowledge“(low) on the SDATA wire will be generated by the clock chip. Controller
can start to write to internal I2C registers after the string of data. The sequence order is as follows:
W83194R-39/-39A
Publication Release Date: May 27, 2005
- 9 - Revision A1
Bytes sequence order for I2C controller:
Clock Address
A(6:0) & R/W Ack 8 bits dummy
Command code Ack 8 bits dummy
Byte count Ack Byte0,1,2...
until Stop
Set R/W to 1 when “read back”, the data sequence is as follows :
Clock Address
A(6:0) & R/W Ack Byte 0 Ack Ack Byte2, 3, 4...
until Stop
Byte 1
8.3 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the default state at
true power up. "Command Code" byte and "Byte Count" byte must be sent following the
acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't
care", they must be sent and will be acknowledge. After that, the sequence described below
(Register 0, Register 1, Register 2, ....) will be valid and acknowledged.
8.3.1 Register 0: CPU Frequency Select Register (default = 0)
BIT @POWERUP PIN DESCRIPTION
7 0 -
0 = ±0.25% Spread Spectrum Modulation
1 = ±0.5% Spread Spectrum Modulation
6 0 - SSEL2 (for frequency table selection by software via I2C)
5 0 - SSEL1 (for frequency table selection by software via I2C)
4 0 - SSEL0 (for frequency table selection by software via I2C)
3 0 -
0 = Selection by hardware
1 = Selection by software I2C - Bit 6:4
2 0 - SSEL3 (for frequency table selection by software via I2C)
1 0 -
0 = Normal
1 = Spread Spectrum enabled
0 0 -
0 = Running
1 = Tristate all outputs
Note : The frequency table selected by software via I2C is the same as the hardware setting frequency table.
W83194R-39/-39A
- 10 -
8.3.2 Register 1: CPU, 48/24 MHz Clock Register (1 = enable, 0 = Stopped)
BIT @POWERUP PIN DESCRIPTION
7 x - Latched FS2#
6 1 - Reserved
5 1 - Reserved
4 1 - Reserved
3 1 40 SDRAM12 (Active / Inactive)
2 1 - Reserved
1 1 43 CPUCLK1 (Active / Inactive)
0 1 44 CPUCLK_F (Active / Inactive)
8.3.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped)
BIT @POWERUP PIN DESCRIPTION
7 1 - Reserved
6 1 7 PCICLK_F (Active / Inactive)
5 1 - Reserved
4 1 14 PCICLK4 (Active / Inactive)
3 1 12 PCICLK3 (Active / Inactive)
2 1 11 PCICLK2 (Active / Inactive)
1 1 10 PCICLk1 (Active / Inactive)
0 1 8 PCICLK0 (Active / Inactive)
8.3.4 Register 3: SDRAM Clock Register (1 = enable, 0 = Stopped)
BIT @POWERUP PIN DESCRIPTION
7 1 - Reserved
6 x - Latched FS0#
5 1 26 48MHz (Active / Inactive)
4 1 25 24MHz (Active / Inactive)
3 1 - Reserved
2 1
21,20,18,1
7 SDRAM(8:11) (Active / Inactive)
1 1
32,31,29,2
8 SDRAM(4:7) (Active / Inactive)
0 1
38,37,35,3
4 SDRAM(0:3) (Active / Inactive)
W83194R-39/-39A
Publication Release Date: May 27, 2005
- 11 - Revision A1
8.3.5 Register 4: Reserved Register (1 = enable, 0 = Stopped)
BIT @POWERUP PIN DESCRIPTION
7 1 - Reserved
6 1 - Reserved
5 1 - Reserved
4 1 - Reserved
3 x - Latched FS1#
2 1 - Reserved
1 x - Latched FS3#
0 1 - Reserved
8.3.6 Register 5: Peripheral Control (1 = enable, 0 = Stopped)
BIT @POWERUP PIN DESCRIPTION
7 1 - Reserved
6 1 - Reserved
5 1 - Reserved
4 1 47 IOAPIC (Active / Inactive)
3 1 - Reserved
2 1 - Reserved
1 1 46 REF1 (Active / Inactive)
0 1 2 REF0 (Active / Inactive)
9. SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.
Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).
SYMBOL PARAMETER RATING
Vdd , VIN Voltage on any pin with respect to GND - 0.5 V to + 7.0 V
TSTG Storage Temperature - 65°C to + 150°C
TB Ambient Temperature - 55°C to + 125°C
TA Operating Temperature 0°C to + 70°C
W83194R-39/-39A
- 12 -
9.2 AC CHARACTERISTICS
Vdd = Vddq3 = 3.3V
±
5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V , TA = 0
°
C to +70
°
C
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Output Duty Cycle 45 50 55 % Measured at 1.5V
CPU/SDRAM to PCI
Offset tOFF 1 4 ns
15 pF Load Measured at
1.5V
Skew (CPU-CPU), (PCI-
PCI), (SDRAM-SDRAM) tSKEW 250 ps
15 pF Load Measured at
1.5V
CPU/SDRAM
Cycle to Cycle Jitter tCCJ ±250 ps
CPU/SDRAM
Absolute Jitter tJA 500 ps
Jitter Spectrum 20 dB
Bandwidth from Center BWJ 500 KHz
Output Rise (0.4V ~
2.0V)
& Fall (2.0V ~0.4V) Time
tTLH
tTHL
0.4 1.6 ns 15 pF Load on CPU and
PCI outputs
Overshoot/Undershoot
Beyond Power Rails Vover 0.7 1.5 V 22 Ω at source of 8 inch
PCB run to 15 pF load
Ring Back Exclusion VRBE 0.7 2.1 V Ring Back must not enter
this range.
9.3 DC CHARACTERISTICS
Vdd = Vddq3 = 3.3V
±
5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V , TA = 0
°
C to +70
°
C
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Input Low Voltage VIL 0.8
Vdc
Input High Voltage VIH 2.0
Vdc
Input Low Current IIL -66
µA
Input High Current IIH 5
µA
Output Low Voltage
IOL = 4 mA VOL 0.4
Vdc All outputs
Output High Voltage
IOH = 4mA VOH 2.4
Vdc All outputs using 3.3V
power
Tri-State leakage Current Ioz 10
µA
W83194R-39/-39A
Publication Release Date: May 27, 2005
- 13 - Revision A1
DC CHARACTERISTICS, continued
Vdd = Vddq3 = 3.3V
±
5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V , TA = 0
°
C to +70
°
C
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Dynamic Supply Current
for Vdd + Vddq3 Idd3 mA
CPU = 66.6 MHz
PCI = 33.3 Mhz with load
Dynamic Supply Current
for Vddq2 + Vddq2b Idd2 mA
Same as above
CPU Stop Current
for Vdd + Vddq3 ICPUS3 mA
Same as above
CPU Stop Current
for Vddq2 + Vddq2b ICPUS2 mA
Same as above
PCI Stop Current
for Vdd + Vddq3 IPD3 mA
9.4 BUFFER CHARACTERISTICS
9.4.1 TYPE 1 BUFFER FOR CPU CLOCK
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Pull-Up Current Min IOH(min) -27 mA Vout = 1.0 V
Pull-Up Current Max IOH(max) -27 mA Vout = 2.0V
Pull-Down Current Min IOL(min) mA Vout = 1.2 V
Pull-Down Current Max IOL(max) 27 mA Vout = 0.3 V
Rise/Fall Time Min
Between 0.4 V and 2.0 V TRF(min) 0.4 ns 10pF Load
Rise/Fall Time Max
Between 0.4 V and 2.0 V TRF(max) 1.6 ns 20pF Load
W83194R-39/-39A
- 14 -
9.4.2 TYPE 2 BUFFER FOR IOAPIC
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Pull-Up Current Min IOH(min) mA Vout = 1.4 V
Pull-Up Current Max IOH(max) -29 mA Vout = 2.7 V
Pull-Down Current Min IOL(min) mA Vout = 1.0 V
Pull-Down Current Max IOL(max) 28 mA Vout = 0.2 V
Rise/Fall Time Min
Between 0.7 V and 1.7 V TRF(min) 0.4 ns 10pF Load
Rise/Fall Time Max
Between 0.7 V and 1.7 V TRF(max) 1.8 ns 20pF Load
9.4.3 TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Pull-Up Current Min IOH(min) -29 mA Vout = 1.0 V
Pull-Up Current Max IOH(max) -23 mA Vout = 3.135V
Pull-Down Current Min IOL(min) 29 mA Vout = 1.95 V
Pull-Down Current Max IOL(max) mA Vout = 0.4 V
Rise/Fall Time Min
Between 0.8 V and 2.0 V TRF(min) 1.0 ns 10pF Load
Rise/Fall Time Max
Between 0.8 V and 2.0 V TRF(max) 4.0 ns 20pF Load
9.4.4 TYPE 4 BUFFER FOR SDRAM (0:12)
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Pull-Up Current Min IOH(min) mA Vout = 1.65 V
Pull-Up Current Max IOH(max) -46 mA Vout = 3.135 V
Pull-Down Current Min IOL(min) mA Vout = 1.65 V
Pull-Down Current Max IOL(max) 53 mA Vout = 0.4 V
Rise/Fall Time Min
Between 0.8 V and 2.0 V TRF(min) 0.5 ns 20pF Load
Rise/Fall Time Max
Between 0.8 V and 2.0 V TRF(max) 1.3 ns 30pF Load
W83194R-39/-39A
Publication Release Date: May 27, 2005
- 15 - Revision A1
9.4.5 TYPE 5 BUFFER FOR PCICLK (0:4,F)
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Pull-Up Current Min IOH(min) -33 mA Vout = 1.0 V
Pull-Up Current Max IOH(max) -33 mA Vout = 3.135 V
Pull-Down Current Min IOL(min) 30 mA Vout = 1.95 V
Pull-Down Current Max IOL(max) 38 mA Vout = 0.4 V
Rise/Fall Time Min
Between 0.8 V and 2.0 V TRF(min) 0.5 ns 15pF Load
Rise/Fall Time Max
Between 0.8 V and 2.0 V TRF(max) 2.0 ns 30pF Load
10. POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
CPU_STOP#
CPUCLK[0:3]
SDRAM
34
1234 12
For synchronous Chipset, CPU_STOP# pin is an asynchronous “ active low ” input pin used to stop
the CPU clocks for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock (PCICLK_F). All other clocks will continue to run
while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and
resume output with full pulse width. In this case, CPU locks on latency “is less than 4 CPU clocks
and locks off latency” is less then 4 CPU clocks.
W83194R-39/-39A
- 16 -
10.2 PCI_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
PCI_STOP#
PCICLK[0:5]
1212
For synchronous Chipset, PCI_STOP# pin is an asynchronous “active low” input pin used to stop the
PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run
while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume
output with full pulse width. In this case, PCI locks on latency “is less than 2 PCI clocks and locks off
latency” is less then 2 PCI clocks.
11. OPERATION OF DUAL FUCTION PINS
Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore,
and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on
these pins is latched into their appropriate internal registers. Once the correct information is properly
latched, these pins will change into output pins and will be pulled low by default. At the end of the
power up timer (within 3 ms) outputs starts to toggle at the specified frequency.
Within 3ms
Input Output
Output tri-state Output pull-low
2.5V
Output tri-state Output pull-low
#7 PCICLK_F/MODE
#46 REF1/FS2
#25 24/FS1
#26 48/FS0
All other clocks
Vdd
W83194R-39/-39A
Publication Release Date: May 27, 2005
- 17 - Revision A1
Each of these pins has a large pull-up resistor (250 kΩ @3.3V) inside. The default state will be logic
1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these
dual function pins. Under these conditions, an external 10 kΩ resistor is recommended to be
connected to Vdd if logic 1 is expected. Otherwise, there should be direct connection to ground if a
logic 0 is desired. The 10 kΩ resistor should be placed before the serious terminating resistor.
Note that these logic will only be latched at initial power on.
If optional EMI reducing capacitor are needed, they should be placed as close to the series
terminating resistor as possible and after the series terminating resistor. These capacitors have
typical values ranging from 4.7pF to 22pF.
Device
Pin
Vdd
Ground Ground
10k Series
Terminating
Resistor Clock
Trace
EMI
Reducing
Cap
10k
Ω
Ω
Optional
Device
Pin
Vdd Pad Ground Pad
Programming Header
Series
Terminating
Resistor Clock
Trace
EMI
Reducing
Cap
Ground
10kΩ
Optional
W83194R-39/-39A
- 18 -
12. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83194R-39/-39A 48 PIN SSOP Commercial, 0°C to +70°C
13. HOW TO READ THE TOP MARKING
W83194R-39
28051234
814GBB
W83194R-39A
28051234
814GBB
1st line: Winbond logo and the type number: W83194R-39/-39A
2nd line: Tracking code 2 8051234
2
: wafers manufactured in Winbond FAB 2
8051234: wafer production series lot number
3rd line: Tracking code 814 G B B
814: packages made in '98, week 14
G: assembly house ID; A means ASE, S means SPIL, G means GR
BB: IC revision
All the trade marks of products and companies mentioned in this data sheet
belong to their respective owners.
W83194R-39/-39A
Publication Release Date: May 27, 2005
- 19 - Revision A1
14. PACKAGE DRAWING AND DIMENSIONS
W83194R-39/-39A
- 20 -
15. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 May 27, 2005 20 ADD Important Notice
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
