CY7C1339 PSSLIMINASY 128K x 32 Synchronous-Pipelined Cache RAM Features + Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states * Fully registered inputs and outputs for pipelined oper- ation + 128K by 32 common I/O architecture * 3.3V core power supply 2.5V /3.3V I/O operation + Fast clock-to-output times 3.5 ns (for 166-MHz device) 4.0 ns (for 133-MHz device) 5.5ns (for 100-MHz device) + User-selectable burst counter supporting Intel@ Pen- tium interleaved or linear burst sequences Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable JEDEC-standard 100 TQFP pinout + ZZ Sleep Mode option and Stop Clock option Functional Description The CY7C1339 is a 3.3V 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. Logic Block Diagram BURST COUNTER ADDRESS CE REGISTER 1 DB SBME ENABLE REGISTER CLK SLEEP CONTROL Intel and Pentium are trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. Cypress Semiconductor Corporation + 3901 North First Street + The CY7C1339 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3 tolerant when Vopq=2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 3.5 ns (166-MHz device}. The GY7C1339 supports either the interleaved burst se- quence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the processor_address strobe (ADSP) or the controller address strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select (BW73-p)) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write cir- cuitry. Three synchronous chip selects (CE,, CE, CE) and an asyn- chronous output enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state. 128K X32 MEMORY ARRAY OUTPUT. INPUT REGISTERS REGISTERS CLK CLK SanJose -* CA95134 + 408-943-2600Pin Configuration i HSE E 2S 2s5e Bae Lu eed EERE 22a8 eWeek 2 2 HHOODAHAOONAOAHOUOONOOOo 8 Oo ky OW C9 ~~ OD Om WW a KT OOoaamnoondriananwo nd wo wo co co oO 0 NC CS { s0 [I NG DQig a 79 | DO, DQ, C4 3 78 fF] DQy, Vope C44 77 [2 VYppe Vssq [4 5 76 F Vesq bat? Cc 6 75 fo DQ, 19 G47 74 Fo BO BYTE2 DQ. 4 3 3 Da, BYTE1 DQ>s, co 9g 72 fH DQi4 Vssq 4 io 71 FS] Veso ppg [4 11 70 |) Vppa BQ, CS t2 69 Fo DO, DQe3 TH 4g 68 Fo DQ, NC C4 144 67 [1 Veg Vop Ef i5 66 FNC NC CS i6 65 F Vpp Veg CS 17 64 [9 ZZ DQs4 TS ig 63 ) COQ, DQs, C] ig 62 [2 DO, Vopo 20 61 Fo Vopa Vesa cS 21 60 Fo Vesq ba CC 22 59 fF DO, BYTE3 a7 TS ag 58 Fo DQ, DQsg CS 24 57 || DQ; BYTEO D@rg ED 25 56 fF] DQ, Vssq CO 26 55 [ Veso ppa 4 27 54 [) Vppq DQ3) CS 28 53 1 DQ, DQ3, ES 2g 52 fF] DQ, NC C4 30 51 fA nc ~-A OrwooOoOMr-OoOoOor-nA YMTwHowoOMnM. OD Oo YOM AOHMONMNMNNOMNTtTTttt T+ + +O UUUUUUUUUUUUUUUUUUUo 4 EZ ELL ELI HBV ZESZIZE = Selection Guide 7C1339-166 7C1339-133 7C1339-100 7C1339L-166 7C1339L-133 7C1339L-100 Maximum Access Time (ns) 4.0 5.5 7.0 Maximum Operating Current (mA) Commercial 420 375 325 L 378 340 293 Maximum CMOS Standby Current (mA) Commercial 10 10 10a Pin Definitions PRSCIAINARY CY7C1339 Pin Number | Name Vo Description 50-44, 81, Are-o] Input- Address Inputs used to select one of the 64K address locations. Sampled atthe 82, 99, 100, Synchronous | rising edge of the CLK if ADSP or ADSC is active LOW, and CE,, CE, and CE, 32-37 are sampled active. Aj,.q) feed the 2-bit counter. 96-93 BWi3:9] Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes Synchronous | to the SRAM. Sampled on the rising edge of GLK. 88 Gw Input- Global Write Enable Input, active LOW. When asserted LOW on the rising edge Synchronous | of GLK, aglobal write is conducted (ALL bytes are written, regardless of the values on BWi3.9) anid BWE). 87 BWE Input- Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This Synchronous | signal must be asserted LOW to conduct a byte write. 89 CLK Input-Glock | Glock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. 98 CE, Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge_of CLK. Used in Synchronous | conjunction with CE, and CE, to select/deselect the device. ADSP is ignored if GE, is HIGH. 97 CEs Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of GLK. Used in Synchronous | conjunction with CE, and CE; to select/deselect the device. 92 CE3 Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous | conjunction with CE, and CE; to select/deselect the device. 86 OE Input- Output Enable, asynchronous input, active LOW. Controls the direction of the I/O Asynchronous | pins. When LOW, the I/O pins behave as outputs_When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. 83 ADV Input- Advance Input signal, sampled on the rising edge of CLK. When asserted, it auto- Synchronous | matically increments the address in a burst cycle. 84 ADSP Input- Address Strobe from Processor, sampled on the rising edge of CLK. When as- Synchronous | serted LOW, Ajig.9 is captured in the address registers. Ay, 9) are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog- nized. ASDP is ignored when CE, is deasserted HIGH. 85 ADSG Input- Address Strobe from Controller, sampled on the rising edge of CLK. When assert- Synchronous | ed LOW, Ar.9] is captured in the address registers. Aj1.p) are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog- nized. 64 ZZ Input- #7 sleep Input. This active HIGH input places the device in a non-time-critical Asynchronous | sleep condition with data integrity preserved. 29,28, 25-22, | DQ/31-0) fO- Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that 19, 18,13,12, Synchronous | is triggered by the rising edge of CLK. As outputs, they deliver the data contained 9-6, 3,2, 79, in the memory location specified by Ar; .o) during the previous clock rise of the 78, 75-72, 69, read cycle. The direction of the pins is controlled by OE. When E is asserted 68, 63, 62 LOW, the pins behave as outputs. When HIGH, DQj3; 9) are placed in a three-state 59-56, 53, 52 condition. 15,41, 65,91 | Vpp Power Supply | Power supply inputs to the core of the device. Should be connected to 3.3V power supply. 17,40, 67,90 | Vss Ground Ground for the core of the device. Should be connected to ground of the system. 4,11,20,27, | Vong Power Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power 54, 61, 70, 77 Supply supply. 5,10, 21,26, | Vesa Ground | Ground for the I/O circuitry. Should be connected to ground of the system. 55, 60, 71, 76 31 MODE Input- Selects burst order. When tied to GND selects linear burst sequence. When tied Static to VDDQ or lef floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. 1,14, 16,30, | NG - No Connects 38,39, 42,43, 51, 66, 80PRSCIAINARY CY7C1339 === Introduction Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (teo) is 3.5ns (166-MHz device). The GCY7C1 339 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is de- termined by sampling the MODE input. Accesses can be ini- tiated with either the processor address strobe (ADSP) or the controller address strobe (ADSG}. Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first ad- dress in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW/3.9)) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchro- nous self-timed write circuitry. Three synchroncus chip selects (CE, , CEs, CE;) and an asyn- chronous output enable (CE) provide for easy bank selection and output three-state control. ADSP is ignored if CE, is HIGH. Single Read Accesses This access is initiated when the following conditions are sat- isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) GE,, CEs, GE, are all asserted active, and _(3) the write sig- nals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE, is HIGH. The address presented to the address inputs (Arig:o)) is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3.5 ns (166-MHz device} if OE is active low. The only exception occurs when the SRAM is emerging from a deselected state tc a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the E signal. Consecutive single read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Single Write Accesses initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) GE,, CEg, CE3 are all asserted active. The address presented to Arie:o] (5 loaded into the address register and the address advancement logic while being delivered to the RAM ccre. The write signals (GW, BWE, and BW)3-9)) and ADV inputs are ignored during this first cycle. ADSP-triggered_ write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQ)31.q) inputs is written into the corresponding address location in the RAM core._lf GW is HIGH, then the write operation is controlled by BWE and BWi3.9] Signals. The CY7C1339 provides byte write capability that is described in the write cycle description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW/3.9)) input will selectively write to only the desired bytes. Byles not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1339 is a common I/O device, the Gutput Enable (CE) must be deasserted HIGH before presenting data to the DQi31.9) inputs. Doing so will three-state the output driv- ers. As a safety precaution, DQjz1.9 are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Wrife Accesses initiated by ADSC ADSC write accesses are initiated when the following condi- tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE,, CEs, CE; are all asserted active, and (4) the_appropriate combination of the write inputs (GW, BWE, and BW)3.9)) are asserted active to conduct a write to the desired byte(s). ADSC- triggered write accesses require a single clock cycle to complete. The address presented to Arte-o] 'S loaded into the address register and the address ad- vancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is con- ducted, the data presented to the DQ)3;.9 is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1339 is a common I/O device, the Cutput Enable (CE) must be deasserted HIGH before presenting data to the DQ)31.p) inputs. Doing so will three-state the output driv- ers. As a safety precaution, DQ)31.9 are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The GY7C1339 provides a two-bit wraparound counter, fed by Ato). that implements either an interleaved or linear burst se- quence. The interleaved burst sequence is designed specifi- cally to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a lin- ear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Interleaved Burst Sequence rst n u Address Address Address Address 1: 1: 1: 1: 00 0 0 0 00 0 00 0PASUAINARY CY7C1339 === Linear Burst Sequence Sleep Mode - - The 27 input pin is an asynchronous input. Asserting 27 plac- First Second Third Fourth es the SRAM in apower conservation sleep mode. Two clock Address Address Address Address cycles are required to enter into or exit from this sleep mode. A A, A A While in this mode, data integrity is guaranteed. Accesses [1-0] [1-0] [1:0] [1:0] pending when entering the sleep mode are not considered 00 Ot 10 14 valid nor is the completion of the operation guaranteed. The device must_be deselected prior to entering the sleep mode. 01 10 11 00 CE,, CEs, CEz ADSP and ADSC must remain inactive for the 10 11 00 01 duration of tz7Rec after the ZZ input returns LOW. 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit lppzz Snooze mode 2Z 2 Vpp-0.2V 3 mA standby current tzz5 Device operationto | 7Z>Vpj0.2V 2toyc ns ZZ tz7REC 22 recovery time 27 <0.2V 2Zteve nsPRSCIAINARY CY7C1339 au oN aig My, Bathe ee Cycle Descriptions!" 2 I Next Cycle | Add.Used | ZZ | CE; | CE, | CE, | ADSP | ADSC | ADV | OE | DQ | write Unselected None L x 1 x 0 x x Hi-Z x Unselected None L 1 x 0 0 Xx x x Hi-Z x Unselected None L Xx 0 0 0 X X X Hi-Z x Unselected None L 4 x 0 1 0 x x Hi-Z x Unselected None L x 0 0 1 0 X X Hi-Z x Begin Read External L 0 1 0 0 x x x Hi-Z x Begin Read External L 0 1 0 1 0 Xx Xx Hi-7 Read Continue Read | Next L x x x 1 1 0 1 Hi-Z Read Continue Read | Next L Xx Xx Xx 1 1 0 0 DQ Read Continue Read | Next L x x 1 X 1 0 1 Hi-2 Read Continue Read | Next L x x 1 Xx 1 0 0 DQ Read Suspend Read | Current L x x x 1 1 1 1 Hi-Z Read Suspend Read | Current L x x x 1 1 1 0 DQ Read Suspend Read | Current L x x 1 x 1 1 1 Hi-2 Read Suspend Read | Current L x x 1 x 1 1 0 DQ Read Begin Write Current L x x x 1 1 1 x Hi-Z Write Begin Write Current L x x 1 x 1 1 x Hi-Z Write Begin Write External L 0 1 0 1 0 x x Hi-7 Write Continue Write | Next L x x x 1 1 0 X Hi-Z Write Continue Write | Next L x x 1 x 1 0 x Hi-Z Write Suspend Write | Current L x x x 1 1 1 X Hi-2 Write Suspend Write | Current L x x 1 x 1 1 X Hi-Z Write 22 Sleep None H X X X x X x x Hi-Z X Note: 1. X=Dont Care, 1=HIGH 0=LOW. _ 2. Write is defined by BWE, BW, 9), and GW. See Write Cycle Descriptions Table. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.PRSCIAINARY CY7C1339 Write Cycle Descriptions!* > Function Gw BWE BW, BW, BW, BW, Read 1 1 X X X X Read 1 0 1 1 1 1 Write Byte 0-DQrz.9) 1 0 1 1 1 0 Write Byte 1-DQr5-3) 1 0 1 1 0 1 Write Bytes 1,0 1 0 1 1 0 0 Write Byte 2 - DQ)53.14] 1 0 1 0 1 1 Write Bytes 2, 0 1 0 1 0 1 0 Write Bytes 2, 1 1 0 1 0 0 1 Write Bytes 2, 1,0 1 0 1 0 0 0 Write Byte 3 - DQy31-24) 1 0 0 1 1 1 Write Bytes 3, 0 1 0 0 1 1 0 Write Bytes 3, 1 1 0 0 1 0 1 Write Bytes 3, 1, 0 1 0 0 1 0 0 Write Bytes 3, 2 1 0 0 0 4 1 Write Bytes 3, 2, 0 1 0 0 0 1 0 Write Bytes 3, 2, 1 1 0 0 0 0 1 Write All Bytes 1 0 0 0 0 0 Write All Bytes 0 x x x x x Maximum Ratings Current into Outputs (LOW)... eee 20 mA Static Discharge Voltage ...0..... eee >2001V tree. rat tested useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) Storage Temperature sssussususmannennaneun 65C to +150C Latch-Up Current 0.0 cece cece teeeeeeeeeenees >200 mA Ambient Temperature with Operating Range Power Applied... srestreretseiensentiesenernen ~OO tO +125C Ambient Supply Voltage on Voo Relative to GND......... 0.5V to +4.6V Range | Temperature!! Vop Vopa DC Voltage Applied to Outputs in High ZS vere ww O.5V10Vpp +0.5V | Com! | OC to +70C 3.3V 2.5V 5% 7 5%/4+10% 3.3V /+10% DC Input Voltage!) esses 0.5 tO Vpn + 0.5V Note: 4. X=Don't Care, 1=Logic HIGH, 0=Logic LOW. 5. The SRAM always initiates a read cycle when ADSP. asserted, regardless of the state of GW, BWE, or BWi3 g) Writes may occur only on subsequent clocks _ after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE isa don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DO=HIGHZ when GE is inactive or when the device is de-selected, and DQ=data when OE is active. Minimum voltage equals 2.0 Yor pulse durations of less than 20 ns. Ty is the instant on" case temperature. aPRSCIAINARY CY7C1339 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit Vop Power Supply Voltage | 3.3V 5%/+10% 3.135 3.6 Vopa I/O Supply Voltage 2.5V 5% to 3.3V +10% 2.375 36 V Vou Output HIGH Voltage | Vop = Min., loy =-4.0 mA 24 Vv VoL Output LOW Vollage =| Vpp = Min., Ip, = 8.0 mA 0.4 V Vin Input HIGH Voltage 2.0 | Vppt+0.3 ] V Vib Input LOW Voltagel] 0.3 0.8 Vv ly Input Load Current GND <V)<Vppe - 5 LA except 77 and MODE Input Current of MODE | Input = Vgs 30 LA Input = Vope 5 LA Input Current of 27 Input = Veg -8 LA Input = Vppa 30 LA loz Output Leakage GND < V, < Vppq, Output Disabled 5 5 LA Current Ipp Vpp Operating Supply | Vpp = Max., loyt =O mA, 6 ns cycle, 166 MHz 420 mA Current f= fMax = TMteve 7.5 ns cycle, 133 MHz 375 mA 10 ns cycle, 100 MHz 325 mA Ipp (L) Vpp Operating Supply | Vop = Max., Igy = 0 mA, 6 ns cycle, 166 MHz 378 mA Current for Low Power | f= fyyax = I4teye Version 7.5 ns cycle, 133 MHz 340 mA 10 ns cycle, 100 MHz 293 mA Ispt Automatic CS Max. Vpp, Device Deselected, 6 ns cycle, 166 MHz 35 mA Power-Down Vin = Vin of Vin = Vie CurrentTTL Inputs =| f = fax = TAcyc 7.9 ns cycle, 133 MHz 30 mA 10 ns cycle, 100 MHz 25 mA Ispe Automatic CS Max. Vpp, Device Deselected, Vjy 10 mA Power-Down = 0.3V or Vin = Vppg 0.3V, f =0 Gurrent GMOS Inputs Isp3 Automatic CS Max. Vpp, Device Deselected, or | 6 ns cycle, 166 MHz 10 mA Power-Down Vin <0.3V or Vin = Vppe 0.3V CurrentCMOS Inputs | f = fax = THeve 7.5 ns cycle, 133 MAz 10 mA 10 ns cycle, 100 MHz 10 mA lop Automatic CS Max. Vpp, Device Deselected, 18 mA Power-Down Vin = Vin or Vin = Vi, f =O GurrentTTL Inputs Shaded area contains preliminary information.CY7C1339 PRSCIAINARY Capacitance! Parameter Description Test Conditions Max. Unit Cn Input Gapacitance Ta = 25C, f = 1 MHz, 6 pF - Vpp = 3.3V. Cok Clock Input Capacitance Vopa = 3.3V 8 pF Cro Input/Output Capacitance a pF AC Test Loads and Waveforms R=3172 OUTPUT $.3V gw OUTPUT , R, =502 | 5 pF + R=3519 VL = 1.5V INCLUDING => + JIGAND ~ ~ ta) SCOPE (b) Note: 9. Tested initially and after any design or process changes that may affect these parameters. 10. Input waveform should have a slew rate of 1V/ns. ALL INPUT PULSES!"2) 2.5V 90% 10%, 10% GND < 2.50 = 2.5ns (c)PRSCIAINARY CY7C1339 Switching Characteristics Over the Operating Range!!1.12-191 -166 -133 -100 Parameter Description Min. Max. Min. Max. Min. Max. | Unit teye Clock Cycle Time 6.0 75 10 ns tou Glock HIGH 17 1.9 3.5 ns toL Clock LOW 1.7 19 3.5 ns tas Address Set-Up Before CLK Rise 2.0 2.5 2.5 ns tay Address Hold After CLK Rise 0.5 05 0.5 ns tco Data Output Valid After CLK Rise 3.5 4.0 55 ns tpou Data Output Hold After CLK Rise 156 2.0 2.0 ns taps ADSP, ADSC Set-Up Before CLK Rise 2.0 2.5 2.5 ns tapy ADSP ADSC Hold After CLK Rise 05 0.5 0.5 ns twes BWE, GW, BW[3:0] Set-Up Before CLK Rise | 2.0 2.5 2.5 ns tweH BWE, GW, BW[3:0] Hold After GLK Rise 05 0.5 0.5 ns tapys ADV Set-Up Before GLK Rise 2.0 25 2.5 ns taDVH ADV Hold After CLK Rise 05 0.5 0.5 ns tos Data Input Set-Up Before CLK Rise 2.0 2.5 2.5 ns toH Data Input Hold After CLK Rise 0.5 0.5 0.5 ns tcEs Chip Select Set-Up 2.0 2.5 2.5 ns teeny Chip Select Hold After CLK Rise 0.5 05 0.5 ns tonz Glock to High-z!"4l 35 3.5 35 ns teLz Clock to Low-z!"4] 0 0 0 ns teouz OE HIGH to Output High-Z!'2: 13] 35 35 55 ns teoz OE LOW to Output Low-Z!!2:15] 0 0 0 ns teoy OE LOW to Output Valid!'2] 35 4.0 55 ns Notes: 11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0, and output loading of the specified Ip) /lgy and load capacitance. Shown in (a) and (b) of AC test loads. 12. touz. terz. toey tea uz, and tegyz are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured + 200 mV from steady-state voltage. 13. At any given voltage and temperature, teoyz is less than teg_z and toyz is less than to, z. 10PRSCIAINARY CY7C1339 Switching Waveforms Write Cycle Timing!'*: 15) | | | | | toy ! | | | | | os ast .PRSCIAINARY CY7C1339 Switching Waveforms (continued) Read Cycle Timingl'* 14 E&]= DON'T CARE [S$ = UNDEFINED 12PRSCIAINARY CY7C1339 Switching Waveforms (continued) Read/Write Cycle Timing!'* '5: '6 a 13CY7C1339 . ni : | | | \ | | i | HIGH igndred ADSP ic with CE, | | | | I PRSCIAINARY [17, 18] | | | | | | | | EV oa \f FS f 5 H | | - ~S Switching Waveforms (continued) Pipeline Timing (Using ADSP}!': Data In/Ou UNDEFINED order to select the device. DON'T CARE BS 14 a ally deselected. igin 18. CE is the combination of CE, and CE;. All chip selects need to be active in Notes: 17. Device oriCY7C1339 PRSCIAINARY ade Switching Waveforms (continued) Pipeline Timing (Using ADSC)I" 1) CLK ES o P ignbred ith CE, HIGH gS RS ADSP with UNDEFINED DONT CARE 8 = - 15CY7C1339 PRSCIAINARY Switching Waveforms (continued) 19. Device must be deselected when entering 22 mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. ZZ Mode Timing !'9: 2 Note: Os are in three-state when exiting 22 sleep mode. 20. 16PRELIMINARY CY7C1339 Ordering Information Speed Package Operating (MHz) Ordering Code Name Package Type ange 133 CY7C1339-166AS A101 100-Lead Thin Quad Flat Pack Commercial 100 CY7C1339-133AS A101 100-Lead Thin Quad Flat Pack Commercial 75 GY7G1339-100AG A101 100-Lead Thin Quad Flat Pack Gommersial 166 CY7C1339L-166AG Ai01 100-Lead Thin Quad Flat Pack Commercial 433 CY7C1339L-133AC A104 100-Lead Thin Quad Flat Pack Commercial 100 CY7C1339L-100AG A101 100-Lead Thin Quad Flat Pack Commercial Shaded area contains preliminary information. Document #: 38-00723-A Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 DIMENSIONS ARE IN MILLIMETERS. + 16.0040.20 14,000.10 1.4020.05 0.30+0.08 22.0020.20 0.65 l2*tt SEE DETAIL A TYP. (8X) a ToL 0.20 MAX. R 0.08 MIN. 0.20 MAX. 0* MIN. 160 MAX. f ) STAND-OFF 3 0.05 MIN. 0.05 MIN: SEATING PLANE a GAUGE PLANE \ oo \ 0.09 MIN. t or-7 O20 MAX. 0.602015 4 0.20 MIN. 1.00 REF. = DETAIL A 51-85050-A Cypress Semiconductor Corporation, 1999. The information contained herein is subject io change without notice. Cypress Semiconductor Corporation assumes no responsibility tor the use ofany circuitry other than circuliry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize Its products for use as critical components in life-support sysiems where a maliunction or failure may reasonably be expected o result in significant injury io the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in deing so indemnifies Cypress Semiconductor against all charges.