SPICE Device Model Si2301DS Vishay Siliconix P-Channel 1.25-W, 2.5-V Rated MOSFET CHARACTERISTICS * P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model schematic is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70982 17-Apr-01 www.vishay.com 1 SPICE Device Model Si2301DS Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Typical Unit V Static Gate Threshold Voltage VGS(th) a On-State Drain Current ID(on) a Drain-Source On-State Resistance rDS(on) VDS = VGS, ID = -250 A 0.92 VDS -5 V, VGS = -4.5 V 34 VDS -5 V, VGS = -2.5 V 8.6 VGS = -4.5 V, ID = -2.8 A 0.095 VGS = -2.5 V, ID = -2.0 A 0.133 A Forward Transconductance gfs VDS = -5 V, ID = -2.8 A 6.5 S Diode Forward Voltage VSD IS = -1.6 A, VGS = 0 V 0.80 V VDS = -6 V, VGS = -4.5 V, ID = -2.8 A 0.85 a Dynamic b Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd 5.3 nC 1.70 Input Capacitance Ciss Output Capacitance Coss 426 Reverse Transfer Capacitance Crss 98 td(on) 15 VGS = -6 V, VGS = 0 V, f = 1 MHz 228 pf Switchingc Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time tr td(off) tf VDD = -6 V, RL = 6 ID -1 A, VGEN = -4.5 V, RG = 6 20 ns 32 41 Notes a. Pulse test; pulse width 300 s, duty cycle 2% b. For design aid only, not subject to production testing c. Switching time is essentially indepenednt of operating temperature www.vishay.com 2 Document Number: 70982 17-Apr-01 SPICE Device Model Si2301DS Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 70982 17-Apr-01 www.vishay.com 3