SPICE Device Model Si2301DS
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 7098 2 www.vishay.com
17-Apr-01 1
P-Channel 1.25-W, 2.5-V Rated MOSFET
CHARACTERISTICS
• P-Channel Vert ical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switc hi ng Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model schematic is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-to-5V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold vol tage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge charact erist ics while avoiding convergenc e difficulties
of the switched C
g
d model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of t he devic e.
SUBCIRCUIT MODEL SCHEMA TIC
SPICE Device Model Si2301DS
Vishay Siliconix
www.vishay.com Docu ment Number: 70982
217-Apr-01
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions Typical Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = −250 µA0.92 V
VDS ≤ −5 V, VGS = −4.5 V 34
On-State Drain CurrentaID(on) VDS ≤ −5 V, VGS = −2.5 V 8.6 A
VGS = −4.5 V, ID = −2.8 A 0.095
Drain-Source On-State ResistancearDS(on) VGS = −2.5 V, ID = −2.0 A 0.133 Ω
Forward Transconductanceagfs VDS = −5 V, ID = −2.8 A 6.5 S
Diode Forward Voltage VSD IS = −1.6 A, VGS = 0 V 0.80 V
Dynamicb
Total Gate Charge Qg5.3
Gate-Source Charge Qgs 0.85
Gate-Drain Charge Qgd
VDS = −6 V, VGS = −4.5 V, ID = −2.8 A
1.70
nC
Input Capacitance Ciss 426
Output Capacitance Coss 228
Reverse Transfer Capacitance Crss
VGS = −6 V, VGS = 0 V, f = 1 MHz
98
pf
Switchingc
Turn-On Delay Time td(on) 15
Rise Time tr20
Turn-Off Delay Time td(off) 32
Fall Time tf
VDD = −6 V, RL = 6 Ω
ID ≅ −1 A, VGEN = −4.5 V, RG = 6 Ω
41
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%
b. For design aid only, not subject to production testing
c. Switching time is essentially indepenednt of operating temperature
SPICE Device Model Si2301DS
Vishay Siliconix
Document Number: 7098 2 www.vishay.com
17-Apr-01 3
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERW ISE NOTED)
