Clock Terminology - Cypress Semiconductor

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Clock Termino logy

Cypress Semiconductor Corporation • 3 9 01 North First Stre et • S a n Jose • CA 95134 • 408-943-2600

October 1994 - Revised July 9, 1997

Clock Terminology

There are many different (and often confusing) terms associ-

ated with cloc k-based devices. T his application note a ttempts

to clarify these terms, and hence serv es as a comprehens iv e

refere nce on clock termi n ology. This applic ation note can be

divided into two sections. The first section describes and dis-

tinguishes between various clock sources available today.

The second secti on def ines a nd distinguishes between vari -

ous parameters used to describe clocks. This section also

provides methods of measuring some of these paramet ers.

Clock Devices

There are a variety of cloc k d evices ava ilable today. Some of

them are described below.

Crystals

Crystal

is a basic piezoe lec tric quartz crystal. On its own, it

cannot generate electrical clocks. It has to be connected to a

clock oscill ator to get a clock waveform. There are t w o kinds

of crystals;

Series Resonant,

which c an be modeled as a high

Q series L-C circuit, and

Parallel Resonant,

which can be

mode led as a high Q pa rallel L-C circuit. The series resonant

crystal has minimum impedance at the resonating frequency,

while th e parallel resonant crystal has m aximum impedance

at the resona ting frequenc y . Cypress clock gen erators ex pect

parallel resonant crystals for the reference device.

Crystal Oscillators

Crystal Oscillator

is an oscillator with the crystal as the

feedback element. There are other kinds of oscillators with

active or pass iv e fee dback compone n ts, but the crystal oscil-

lator provides the most a ccurate and stable output frequency.

Crystal oscillators come in a var iety of packages, though the

4-pin package (Metal Can Oscillator) in the 300-mil 14-pin

DIP footprint is very popular. Surface mount and Half DIP

packages are also available. Finally, crystal oscillators are the

preferred clock source in most high-speed digital systems re-

quiring clocks.

Compensat ed Oscillators

The output frequency of a crystal oscillator vari es wit h t em-

perature and voltage. Applications that require a highly stable

clock usually use compensated oscillators.

Compensated

Oscillators

try to adjust the variation in frequency due to tem-

perature an d voltage.

Temperature Compensating Oscillators

(TCXO)

contain circuitry that compensates for temperature

changes , and hence combat frequency variations.

Oven Con-

trolled Oscillators

encas e th eir crystals in a temperature-con-

trolled oven , and so maintain a precise o perating tempe rature

at the crystal.

Double Oven Oscillators

contain two ovens,

with the crystal encased in the inner oven, and t he tempera-

ture control circuitr y and the inner ov en encased in th e outer

oven. Such oscillators provide even be tter temperature stabil-

ity than Oven Controlled Oscillators. Obviously, as the fre-

quency stability improves, the cost of the oscillator increases.

Volt a ge Controlled Oscillat or

The output of

Voltage Controlled Oscillators (VCO)

is con-

troll ed by a volt age control input pin. Variation between c on-

trol voltage and frequenc y is usually non linear over the entire

frequency range but is linear within subset ranges.

Frequency Synthesizers

Frequency Synthesizers use one or more

Phase-Locked

Loops (PLL)

to generate one to many d if ferent frequencies on

their outputs, from one or more reference sources. The refer-

ence f requency i s usually generated by a crystal atta ched to

the synthes izer. The design goal of freque ncy s ynthesizers is

to replace multiple oscillators in a system, and hence r educe

board space and cost.

Figure 1

shows a block diagr am of a

Phase L ocked Loop (PLL).

A PLL has two inputs, a reference input and a feedbac k input.

A PLL corrects frequency in two ways. The first, frequency

correction, corrects large differences in frequency between

the reference input and the feedback input. Frequency correc-

tion is akin to “rough” tuning and occurs when Fvco is less than

0.5Fref or greater than 2Fref. Phase correction is the “fine”

tuning and occurs when 0.5Fvco < Fref < 2Fvco.

The Phase/Frequency Detector dete cts differences in p hase

and frequency between the reference and feedback inputs

and generates compensating “Up” and “Down” signals de-

pending on whether the feedback frequency is lagging or

leading the reference frequency respectively. These control

signals are then p assed thr ough a charge pump and a loop

filter to generate a control voltage, which controls a Volt-

age-Controlled Oscillator (VCO ). The fr e quency of this oscil-

lator is depen dent on the Vctrl input. At steady state, the VCO

frequency is:

Fvco = Fref ✻ P/Q

The output fr equency of t he PLL can be expressed a s

Fout = (Fref ✻ P)/(Q ✻ N)

The

Sample Rate

of a Frequency Synthesizer determines

how often the inputs are sample d in order to perform phase

and frequency correction. It is expressed as Fref/Q.

The

Acquisition/Lock Time

of a PLL-based Frequency Syn-

thesizer is the amount of time ta ken by t he Frequency Syn-

thesizer to attain the target frequen cy af ter powe r-up, or after

a pr ogrammed output frequency change.

The

Resolution

of a PLL-based Frequency Synthesizer is

based on the number of bits in the P and Q counter. The

Resolution will determine in what size increments the fre-

quency can change.

The

Deadband

of a PLL-based Frequen cy Synthesizer is the

largest phas e d if ference between the reference and the feed-

back inputs, which will not be corrected by the PLL.

Clock Terminology

Multiple PLLs are needed within a single frequency synthe-

sizer to generate multiple unrelated frequencies.

Frequency synthesizers are gaining in popularity as system

complexity increases and s ystems utilize multiple clocks. The

term “Clock Generator” is interchangeably used with “Fre-

quency Synthesizer.”

Clock Buffers

Clock Buffer

is a device in which the output waveform di-

rectly follows the input waveform. The inpu t wav eform propa-

gates through the device and is redriven by the output buffers.

Hence, such devices have a propagation delay associated

with them. In addition, due to the differences between the

propagation delay through the device on each input-output

path, skew will exist on the outputs. An example of a clock

buffer is the 74F244, which is available from several manufac-

turers.

A cloc k buf fer may a lso use a PLL t o el iminate the delay from

input to output. Examples of such devices are the

CY2305/08/09.

Clock Parameters

This section contains defi niti ons and explanations of various

parameters used to describe clocks.

Clo ck Jitter

Jit ter can be defined a s the deviations in a clock’s output tran -

sitions fr om their ideal positions. Th e deviation can either be

leading or lagging the ideal position. Hence, jitter is expressed

in ±ns. Jitter ca n be classified into three categori es: cy cle-cy-

cle jitter, period jitter, and l ong-t erm jitter.

Cycle-cycle ji tter

is the dif feren ce in a cloc k’s period from one

cycle to the next. This k ind of jitter is the most difficult to mea-

sure and usually requires a Timing Interval Analyzer.

Figure

shows a graphical representation of cycle-cycle jitter . J1 and

J2 are the jitter values measured. The maximum of such val-

ues measu red over multiple cycles is the maximum cycle-cy-

cle jitter.

Figure 1. Bl ock Diagram of a Phase L ocked Loop

Phase/

Frequency

Detector

Charge

Pump Loop

Filter VCO “N”

Post

Divider

“Q”

Counter

“P”

Counter

Fref

Fvco

Fref/Q

Fvco/P

Ictrl Fvco

Vctrl Fvco/N

Fout

PLL Cont rol S ect ion

Fig ure 2. Cycle-Cycle Jitt er

Clock

t1t2t3

Jitter J1 = t2 – t1

Jitter J2 = t3 – t2

Clock Terminology

Period jitter

, also called short-term jitter, is a change in a

clo ck’s out put transit i on from its ideal position over consecu-

tive cloc k edges.

Figure 3

shows short-term jitter. Note that in

the case of short-term jitter, the variation of the rising edge of

clock from the ideal position is measured and expressed in

uni ts of time or fr equency.

Long-term jitter

is a chan ge in a clock’s ou tput transition from

its ideal position, over “many” cycles. The term “many” de-

pends on t he application and the frequenc y. For PC mother-

board and graphics applications, this term “many” usually re-

fers to 1 0–20 microseconds . For other applications, it may be

different.

Figure 4

shows a graphical representation of

long-term jitter.

Causes of Jitter

There are four primary causes of jitter as indicated below:

• Power supply noise

• The internal PLL of the synthesizer

• Random thermal noise from crystal, or any other resonat-

ing device.

• Random mechani cal noise from vibrations of the crystal

For a more detailed discussion on jitter, please refer to the

application note entitled “Jitter in PLL-Ba sed Systems.”

What Syst ems Does Clock Jitter Affect?

Clock jitter affects almost all high-speed synchronous sys-

tems. Common applications affected by jitter are PC mother-

boards, graphics cards, an d commu nications equipment.

Skew

Skew is the variation in arrival time of two signals specified to

arrive at the same time. Skew is composed of two part s, the

output skew of the driving device, and board design skew,

caused by layout variation of board traces.

Figure 5

explains

skew.

Figur e 3. Period Jitt er

Clock

Jitter

Ideal Cycle

Figure 4. Long-Term Jitter

Cycle 0

(Ideal)

Cycle N

(Lagging)

Cycle M

(Leading) Jitter

Jitter

Figure 5. Graphical Repres entation of Skew

Output A

(Reference)

Output B

Output C

Skew

(Leading)

Ske w

(Lagging)

Clock Terminology

Clock Driver Skew (Intrinsic Skew)

is the amount of skew

caused by the clo ck driver itself. There are two kinds of clock

driver devices; buffer devices and PLL-based devices. Skew

occurs on the output of the buffer devices because of the

differences in propagation delay of the input signal through

the device. A majority of this difference is attrib uted to differ -

ences in output loading. Skew in PLL-based devices c an be

very small, since a PLL-based device can be adjusted to com-

pensate for differences in output loading.

Board Design Skew (Extrinsic skew)

is the amount of skew

caused b y board layout issues s uch as:

• Trace Length: The amount of time for a signal to propagate

down a tra ce is dependent on t he material of t he PCB,

length of the trace, width of the trace and capacitive load-

ing. Different trace lengths cause different signa l propaga-

tion times, and hence cause skew.

• Threshold Voltage Variation: The threshold voltage of the

receiving device can cause skew . For example, if a receiv-

ing device has a threshold voltage of 1.2V and another

device h as a threshold vo ltage o f 1.7V, and the rise time of

the input signal is 1V/ns, then the two devices will switch

500 ps apart, which is skew.

• Capacitive Loading: The differences in capacitive loading

on traces will cause differences in t he clo ck r ise t imes at

the load. This affects the time at which the clock edge

crosses t he input threshold and results i n sk ew.

• Transmission Line Termination: With the extremely fast

edge r ates in today’s clock drivers, traces longer than 4

inches are considered transmission lines. Without proper

termination, these lines will exhibit transmission line effects

like voltage r eflections, which will cause skew.

Why Is Skew Import ant?

In high-speed systems, clock skew form s an important com-

ponent of timing margin. A skew of 1 ns is a significant portion

of a 15-ns cycle time. I f the timing budget does not allow for

skew, it is highly likely that the system will perform unreliably.

Measur ing Skew

The simplest method of measuring skew between two outputs

of a device is to display both waveforms in a dual-channel

oscil loscope and measure the di fference between the rising

edges. Thi s is the skew.

Clock buffer da tasheets usua lly spec ify two parameters,

“out-

put-to-output skew”

and

“part-to-part skew.”

The latter param-

eter includes the former. If neither parameter is specified,

then the maximum output skew is the difference between the

maximum and minimum propagation delay times through the

device.

Tolerance/Accuracy/Precision

is a measure of how close the

part operates to the specified (nominal) frequency, typically

referenced at ambient temperature (25oC +/- 5oC). This is

usually specifi ed for a crystal or oscillator. For e xample, if a

part is specified with a 25.000-MHz output, and the long-term

(user-defined) average of its output frequenc y is 2 5.0 01 MHz

at ambient t emperature, the part has +40 ppm accuracy. Ac-

curacy can be expressed as:

Accuracy=(L.T. Avg. Freq. – Nominal Freq.)/Nominal Freq.

Tolerance/Accuracy/Precision is usually specified with a max-

imum and minimum frequency deviation, expressed in per-

centage or parts per million. Frequency tolerance i s affected

or controlled by controlling the accuracy of the manufacturing

and calibrating process for the crystal.

Stability

Stability is a parameter usually associated with crystals and

oscillators. Stability is defined as the variation in operating

frequency f rom the ambient temperature freque ncy (freque n-

cy tolerance value) over the ope rating temperature range and

is e xpressed in ppm (part s per m illion).

This parameter is specified with a maxim um and minimum

frequency deviation, expressed in percent or parts per million.

W hy Is Stabil ity Import a nt?

Stab ility may caus e marginal operation of a design over c om-

plete temperature range, if it is not accounted for in the de-

sign.

Aging

Aging is defined as th e s ystematic change in frequency o ver

time due to internal changes in crystal/oscillator. It is usually

expressed in ppm/year, and may be incorporated in the Sta-

bility s pec, if it is not drawn out separat ely. It is a parameter

usually associated with crystal oscillators. New crystals age

faster than old crystals. Typical aging rates are of the order of

5 ppm/yr.

Why Is Aging Important?

Aging may cause marginal operati on of a design over an ex-

tended period of t ime, if it is not accounted f or i n the design.

Wander/Drift

Wander

and

Drift

are the same, and are defined for a cry stal

oscillator as the systemat ic change in frequency with time. It

equals aging plus other factors external to the crystal/oscilla-

tor.

Volta ge Sensitivity

Vo ltage Sens itivity

is the variations in frequency due to varia-

tions in operating voltage. It is expressed in ppm/volts. On

crystal oscillators, it is usually incorporated in the stability

spec. On PLL-based devices, it is usually incorporated in the

jitter spec.

Error

On a PLL-based device, it may not always be possible to get

the s pecified frequency on the outputs. The l imit ation is d ue

to the s ize of the in ternal “P” and “ Q” counters in the PLL (see

later sections for detailed information). If, for example, the

specified frequency is 25.000 MHz, and the PLL ca n out put

24.998 MHz, the error is –80 ppm.

Error

can be expressed as:

Error = (Nominal Freq. – Target Freq.)/Target Freq.

Note the difference between error and accuracy. Error speci-

fies the differ ence between the frequency you want, and the

frequency you get. Accuracy specifies the difference between

the frequency you get, and the long term a vera ge of this fre-

quency.

Slew

The rate of change of voltage or frequency is called

Slew

Slew is usually measured on the rising and falling edges of

Clock Terminology

of any circuitry othe r than circui try embodi ed in a Cy press Semi conductor p roduct. Nor does it convey or im ply any li cense under patent or other rights. Cypress Semicondu ctor does not authori ze

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusi on of Cypress

Semiconductor products in life-suppor t systems application implies that the manufacturer assumes al l risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

digital signals. However, rise times and fall times are more

commonly specified, instead of slew, in ve ndor’s catalogs.

Recently, with the adve n t of low-power devices , s lew is b eing

used to define a rate of change of frequency.

Duty Cycle

is the ratio of the output high time to the total cycle

time. It is expressed as a per cent age. 50% is the ideal dut y

cycle, though most clock manufacturers specify duty cycles

from 40% – 60%. Duty cycle is important in systems that use

both the rising and falling clock edges.

Duty cycles can be express ed for both TTL and CMOS devic-

es. For TTL devices, since the voltage swing is f rom 0V–3V,

the high t ime i s mea sured at the 1.5V leve l. Fo r CMOS devic-

es, since the voltage swing is from 0–Vdd Volts, the high time

is measured at Vdd/2. Hence, if a device claims to meet both

CMOS and TTL duty cycle measurements, it refers to the volt-

age at which the high time is measured, not the output voltage

swing.

Figure 6

shows the difference between CMOS and

TTL duty cycle measurement levels.

Conclusion

This application note presented clear and detailed descrip-

tions of various clock devices avail able today, along with pa-

rameters used to des cribe clo cks. It also provided methods of

measuring some of these parameters.

References

1. Johnson, Howard, and Graham, Martin,

High-Speed Digi-

tal Design: A Handbook of Black Magic.

PTR Prentice-Hall.

New Jersey, 1993.

Figure 6. CMO S/TTL Duty Cycl e Measur ement

Thigh

Tcycle

TTL Levels

Thigh

Tcycle

CMOS Levels

2.5V

1.5V