HCPL-M456 Small Outline, 5 Lead Intelligent Power Module Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-M456 consists of a GaAsP LED optically coupled to an integrated high gain photo detector. Minimized propagation delay difference between devices make these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. x Performance specified for common IPM applications over industrial temperature range: -40 C to 100 C Specifications and performance plots are given for typical IPM applications. x Very high Common Mode Rejection (CMR): 15 kV/Ps at VCM = 1500 V x Safety approval UL recognized per UL1577 (file no. E55361) - 3750Vms for 1 minute 6 Truth Table 5 3 SHIELD x Minimized Pulse Width Distortion (PWD = 370 ns) x CTR > 44% at IF = 10 mA Schematic Diagram 1 x Fast maximum propagation delays tPHL = 400 ns, tPLH = 550 ns 4 LED VO ON L OFF H x Lead free option "-000E" Applications x IPM isolation x Isolated IGBT/MOSFET gate drive x AC and brushless dc motor drives x Industrial inverters The connection of a 0.1 PF bypass capacitor between pins 4 and 6 is recommended. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information HCPL-M456 is UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part number RoHS Compliant Non RoHS Compliant HCPL-M456 -000E No option -500E #500 X -060E -060 X -560E -560 X Package Surface Mount SO-5 Tape & Reel IEC/EN/DIN EN 60747-5-2 Quantity X 100 per tube X 1500 per reel X X 100 per tube X 1500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-M456-560E to order product of SO-5 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant. Example 2: HCPL-M456 to order product of SO-5 Surface Mount package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation `#XXX' is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use `-XXXE`. HCPL-M456 Outline Drawing Pin Location (for reference only) ANODE MXXX XXX 4.4 0.1 (0.173 0.004) 1 7.0 0.2 (0.276 0.008) CATHODE 3 6 VCC 5 VOUT 4 GND TYPE NUMBER (LAST 3 DIGITS) DATE CODE 3.6 0.1* (0.142 0.004) 2.5 0.1 (0.098 0.004) 0.4 0.05 (0.016 0.002) 0.102 0.102 (0.004 0.004) 0.15 0.025 (0.006 0.001) 7 MAX. 1.27 BSC (0.050) 0.71 MIN (0.028) Dimensions in millimeters (inches) * Maximum mold flash on each side is 0.15 mm (0.006) Note: Floating lead protrusion is 0.15 mm (6 mils) max. 2 MAX. LEAD COPLANARITY = 0.102 (0.004) Land Pattern Recommendation 4.4 (0.17) 1.3 (0.05) 2.5 (0.10) 2.0 (0.080) 8.27 (0.325) 0.64 (0.025) DIMENSION IN MILLIMETERS (INCHES) Figure 1. 5 Pin SOIC Package (JEDEC MO-155) Device Outline Drawing. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 C Operating Temperature TA -40 100 C Average Input Current [1] IF(avg) 25 mA Peak Input Current [2] (50% duty cycle, <1 Ps pulse width) IF(peak) 50 mA Peak Transient Input Current (<1 Ps pulse width, 300 pps) IF(tran) 1.0 A Reverse Input Voltage (Pin 3-1) VR 5 Volts Average Output Current (Pin 5) IO(avg) 15 mA Output Voltage (Pin 5-4) VO -0.5 30 Volts Supply Voltage (Pin 6-4) VCC -0.5 30 Volts Output Power Dissipation[3] PO 100 mW Total Power Dissipation[4] PT 145 mW Infrared and Vapor Phase Reflow Temperature 3 See Reflow Thermal Profile below. Solder Reflow Thermal Profile 300 TEMPERATURE (C) PREHEATING RATE 3 C + 1 C/-0.5C/SEC. REFLOW HEATING RATE 2.5 C 0.5C/SEC. 200 PEAK TEMP. 245 C PEAK TEMP. 240 C 2.5 C 0.5C/SEC. 30 SEC. 160 C 150 C 140 C SOLDERING TIME 200C 30 SEC. 3 C + 1 C/-0.5 C 100 PEAK TEMP. 230 C PREHEATING TIME 150 C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 200 250 TIME (SECONDS) Note: Non-halide flux should be used. Recommended Pb-Free IR Profile tp 260 +0/-5 C TEMPERATURE Tp TL 217 C Tsmax Tsmin 150 - 200 C TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE 20-40 SEC. RAMP-UP 3C/SEC. MAX. RAMP-DOWN 6C/SEC. MAX. ts PREHEAT 60 to 180 SEC. tL 60 to 150 SEC. NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 C, Tsmin = 150 C 25 t 25 C to PEAK TIME Note: Non-halide flux should be used. Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage VCC 4.5 30 Volts Output Voltage VO 0 30 Volts Input Current (ON) IF(on) 10 20 mA Input Voltage (OFF) VF(off ) -5 0.8 V Operating Temperature TA -40 100 C 4 Insulation Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap External Clearance L(101) 5 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking External Creepage L(102) 5 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 mm Insulation thickness between emitter and detector; also known as distance through insulation. 200 Volts DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap Internal Clearance Tracking Resistance CTI Isolation Group IIIa Material Group DIN VDE 0110 Regulatory Notes x The HCPL-M456 is recognized under the component program of U.L. (File No. 55361) for dielectric withstand proof voltages of 2500 VRMS, 1 minute. Electrical Specifications Over recommended operating conditions unless otherwise specified: TA = -40 C to +100 C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off ) = -5 V to 0.8 V Parameter Symbol Min. Typ.* Units Test Conditions Current Transfer Ratio CTR 44 90 % IF = 10 mA, VO = 0.6 V Low Level Output Current IOL 4.4 9.0 mA IF = 10 mA, VO = 0.6 V Low Level Output Voltage VOL 0.3 0.6 V IO = 2.4 mA Input Threshold Current ITH 1.5 5.0 mA VO = 0.8 V, IO = 0.75 mA 2 High Level Output Current IOH 5 50 PA VF = 0.8 V High Level Supply Current ICCH 0.6 1.3 mA VF = 0.8 V, VO = Open 9 Low Level Supply Current ICCL 0.6 1.3 mA IF = 10 mA, VO = Open 9 1.8 Input Forward Voltage VF 1.5 Temperature Coefficient of Forward Voltage 'VF /'TA -1.6 Input Reverse Breakdown Voltage BVR Input Capacitance CIN Input-Output Insulation Voltage VISO Resistance (Input - Output) RI-O Capacitance (Input - Output) CI-O *All typical values at 25 C, VCC = 15 V. 5 Max. Fig. Note 5 2,3 9 4 V IF = 10 mA mV/C IF = 10 mA V IR = 10 PA pF f = 1 MHz, VF = 0 V VRMS RH < 50%, t = 1 min, TA = 25 C 6, 7 1012 : VI-O = 500 Vdc 6 0.6 pF f = 1 MHz 6 5 60 3750 5 Switching Specifications (RL= 20 k:) Over recommended operating conditions unless otherwise specified: TA = -40 C to +100 C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off ) = -5 V to 0.8 V Parameter Symbol Min. Typ.* Max. Units Propagation Delay Time to Low Output Level tPHL 30 200 400 ns CL = 100 pF ns CL = 10 pF Propagation Delay Time to High Output Level tPLH Pulse Width Distortion PWD Propagation Delay Difference Between Any 2 Parts tPLH-tPHL Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity 100 270 400 550 ns Test Conditions CL = 100 pF CL = 10 pF 130 200 450 ns -150 200 450 ns |CMH| 15 30 kV/Ps IF = 0 mA, VO > 3.0 V |CML| 15 30 kV/Ps IF = 10 mA, VO < 1.0 V IF(on) = 10 mA, VF(off ) = 0.8 V, VCC = 15.0 V, V THLH = 2.0 V, V THHL = 1.5 V Fig. Note 6, 8-12 8, 9 CL = 100 pF 13 10 VCC = 15.0 V, CL = 100 pF, VCM = 1500 VP-P, TA= 25 C 7 11 12 *All typical values at 25 C, VCC = 15 V. Notes: 1. Derate linearly above 90 C free-air temperature at a rate of 0.8 mA/C. 2. Derate linearly above 90 C free-air temperature at a rate of 1.6 mA/C. 3. Derate linearly above 90 C free-air temperature at a rate of 3.0 mW/C. 4. Derate linearly above 90 C free-air temperature at a rate of 4.2 mW/C. 5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO) to the forward LED input current (IF) times 100. 6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together. 7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 VRMS for 1 second (leakage detection current limit, II-O 5 PA). 8. Pulse: f = 20 kHz, Duty Cycle = 10%. 9. Use of a 0.1 PF bypass capacitor connected between pins 4 and 6 can improve performance by filtering power supply line noise. 10. The difference between tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications section.) 11. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 3.0 V). 12. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 1.0 V). 13. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given device. 6 LED Drive Circuit Considerations For Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 14. The HCPL-M456 improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and the optocoupler output pin and output ground as shown in Figure 15. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 13), can achieve 15 kV/Ps CMR while minimizing component complexity. Note that a CMOS gate is recommended in Figure 13 to keep the LED off when the gate is in the high state. Another cause of CMR failure for a shielded optocoupler is direct coupling to the optocoupler output pins through CLEDO1 in Figure 15. Many factors influence the effect and magnitude of the direct coupling including: the position of the LED current setting resistor and the value of the capacitor at the optocoupler output (CL). Techniques to keep the LED in the proper state and minimize the effect of the direct coupling are discussed in the next two sections. 7 CMR With The LED On (CMRL) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. The recommended minimum LED current of 10 mA provides adequate margin over the maximum ITH of 4.0 mA (see Figure 2) to achieve 15 kV/Ps CMR. The placement of the LED current setting resistor effects the ability of the drive circuit to keep the LED on during transients and interacts with the direct coupling to the optocoupler output. For example, the LED resistor in Figure 16 is connected to the anode. Figure 17 shows the AC equivalent circuit for Figure 16 during common mode transients. During a +dVCM/dt in Figure 17, the current available at the LED anode (Itotal) is limited by the series resistor. The LED current (IF) is reduced from its DC value by an amount equal to the current that flows through CLEDP and CLEDO1. The situation is made worse because the current through CLEDO1 has the effect of trying to pull the output high (toward a CMR failure) at the same time the LED current is being reduced. For this reason, the recommended LED drive circuit (Figure 13) places the current setting resistor in series with the LED cathode. Figure 18 is the AC equivalent circuit for Figure 13 during common mode transients. In this case, the LED current is not reduced during a +dVCM/dt transient because the current flowing through the package capacitance is supplied by the power supply. During a -dVCM/dt transient, however, the LED current is reduced by the amount of current flowing through CLEDN. But, better CMR performance is achieved since the current flowing in CLEDO1 during a negative transient acts to keep the output low. CMR With The LED Off (CMRH) IPM Dead Time and Propagation Delay Specifications A high CMR LED drive circuit must keep the LED off (VF VF(OFF)) during common mode transients. For example, during a +dVCM/dt transient in Figure 18, the current flowing through CLEDN is supplied by the parallel combination of the LED and series resistor. As long as the voltage developed across the resistor is less than VF(OFF) the LED will remain off and no common mode failure will occur. Even if the LED momentarily turns on, the 100 pF capacitor from pins 5-4 will keep the output from dipping below the threshold. The recommended LED drive circuit (Figure 13) provides about 10 V of margin between the lowest optocoupler output voltage and a 3 V IPM threshold during a 15 kV/Ps transient with VCM = 1500 V. Additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line connection in Figure 18, to clamp the voltage across the LED below VF(OFF). The HCPL-M456 includes a Propagation Delay Difference specification intended to help designers minimize "dead time" in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 22) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. Since the open collector drive circuit, shown in Figure 19, cannot keep the LED off during a +dVCM/dt transient, it is not desirable for applications requiring ultra high CMRH performance. Figure 20 is the AC equivalent circuit for Figure 19 during common mode transients. Essentially all the current flowing through CLEDN during a +dVCM/dt transient must be supplied by the LED. CMRH failures can occur at dv/dt rates where the current through the LED and CLEDN exceeds the input threshold. Figure 21 is an alternative drive circuit which does achieve ultra high CMR performance by shunting the LED in the off state. To minimize dead time the designer must consider the propagation delay characteristics of the optocoupler as well as the characteristics of the IPM IGBT gate drive circuit. Considering only the delay characteristics of the optocoupler (the characteristics of the IPM IGBT gate drive circuit can be analyzed in the same way) it is important to know the minimum and maximum turn-on (tPHL) and turn-off (tPLH) propagation delay specifications, preferably over the desired operating temperature range. The limiting case of zero dead time occurs when the input to Q1 turns off at the same time that the input to Q2 turns on. This case determines the minimum delay between LED1 turn-off and LED2 turn-on, which is related to the worst case optocoupler propagation delay waveforms, as shown in Figure 23. A minimum dead time of zero is achieved in Figure 23 when the signal to turn on LED2 is delayed by (tPLH max - tPHL min) from the LED1 turn off. Note that the propagation delays used to calculate PDD are taken at equal temperatures since the optocouplers under consideration are typically mounted in close proximity to each other. (Specifically, tPLH max and tPHL min in the previous equation are not the same as the tPLH max and tPHL min, over the full operating temperature range, specified in the data sheet.) This delay is the maximum value for the propagation delay difference specification which is specified at 370 ns for the HCPL-M456 over an operating temperature range of -40 C to 100 C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time occurs in the highly unlikely case where one optocoupler with the fastest tPLH and another with the slowest tPHL are in the same inverter leg. The maximum dead time in this case becomes the sum of the spread in the tPLH and tPHL propagation delays as shown in Figure 24. The maximum dead time is also equivalent to the difference between the maximum and minimum propagation delay difference specifications. The maximum dead time (due to the optocouplers) for the HCPL-M456 is 520 ns (= 370 ns (-150 ns)) over an operating temperature range of -40 C to 100 C. 8 1.05 NORMALIZED OUTPUT CURRENT IO - OUTPUT CURRENT - mA 10 8 6 4 VO = 0.6 V 100 C 25 C -40 C 2 0 0 5 10 15 IF - FORWARD CURRENT - mA 0.90 0.85 0.80 -40 VF = 0.8 V VCC = VO = 4.5 V OR 30 V 4.5 V 30 V 1.0 0.5 0 -40 -20 0 20 40 60 TA - TEMPERATURE - C 80 100 1000 2.0 1.5 IF = 10 mA VO = 0.6 V Figure 3. Normalized Output Current vs. Temperature. IF - FORWARD CURRENT - mA IOH - HIGH LEVEL OUTPUT CURRENT - PA 0.95 20 Figure 2. Typical Transfer Characteristics. -20 0 20 40 60 TA - TEMPERATURE - C Figure 4. High Level Output Current vs. Temperature. 9 1.00 80 100 100 10 TA = 25 C IF + VF - 1.0 0.1 0.01 0.001 1.10 1.20 1.30 1.40 1.50 VF - FORWARD VOLTAGE - VOLTS Figure 5. Input Current vs. Forward Voltage. 1.60 IF(ON) =10 mA 1 6 0.1 PF 5 + - VOUT 4 SHIELD tf VO + - VCC = 15 V CL* 3 If 20 k: tr 90% 90% 10% 10% VTHHL *TOTAL LOAD CAPACITANCE tPHL VTHLH tPLH Figure 6. Propagation Delay Test Circuit. IF 1 B VCM 6 0.1 PF 5 A GV = VCM 't Gt 20 k: VOUT + V = 15 V - CC OV 100 pF* + 3 Dt 4 SHIELD VFF *100 pF TOTAL CAPACITANCE - SWITCH AT A: IF = 0 mA VCC - + VO VCM = 1500 V Figure 7. CMR Test Circuit. 10 VO SWITCH AT B: IF = 10 mA Typical CMR Waveform. VOL 800 IF = 10 mA VCC = 15 V 400 CL = 100 pF RL = 20 K: (EXTERNAL) IF = 10 mA VCC = 15 V CL = 100 pF 600 TA = 25 C tP - PROPAGATION DELAY - ns tP - PROPAGATION DELAY - ns 500 tPLH tPHL 300 200 100 -40 -20 0 20 40 60 TA - TEMPERATURE - C 80 tP - PROPAGATION DELAY - ns tP - PROPAGATION DELAY - ns 800 600 400 200 0 0 100 200 300 400 CL - LOAD CAPACITANCE - pF 500 Figure 10. Propagation Delay vs. Load Capacitance. tP - PROPAGATION DELAY - ns VCC = 15 V CL = 100 pF RL = 20 K: TA = 25 C 200 0 5 10 15 IF - FORWARD LED CURRENT - mA Figure 12. Propagation Delay vs. Input Current. 11 tPLH tPHL 300 100 40 50 IF = 10 mA CL = 100 pF RL = 20 K: TA = 25 C tPLH tPHL 1200 1000 800 600 400 200 0 5 10 15 20 VCC - SUPPLY VOLTAGE - V Figure 11. Propagation Delay vs. Supply Voltage. 500 400 20 30 RL - LOAD RESISTANCE - K: 1400 IF = 10 mA VCC = 15 V RL = 20 K: TA = 25 C tPLH tPHL 1000 10 Figure 9. Propagation Delay vs. Load Resistance. 1400 1200 200 0 100 Figure 8. Propagation Delay with External 20 k: RL vs. Temperature. tPLH tPHL 400 20 25 30 1 +5 V 310 : 6 0.1 PF 5 3 *100 pF TOTAL CAPACITANCE Figure 13. Recommended LED Drive Circuit. 1 CLEDP 1 6 5 4 SHIELD CMOS 20 k: VOUT + - VCC = 15 V 100 pF CLEDN 3 4 Figure 14. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. +5 V CLEDP 6 CLED01 310 : 1 6 0.1 PF 5 5 3 CLEDN 3 4 SHIELD Figure 15. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. ITOTAL* 300 : ICLED01 IF 6 1 CLED01 VOUT + VR** - 4 + - * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dVCM/dt TRANSIENTS. VCM Figure 17. AC Equivalent Circuit for Figure 16 during Common Mode Transients. 12 20 k: 5 100 pF CLEDN 300 : 3 ICLEDN* VOUT SHIELD 4 * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dVCM/dt TRANSIENTS. ** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH PERFORMANCE. VR < VF (OFF) DURING +dVCM/dt. + - SHIELD 6 CLED01 100 pF CLEDN CLEDP 20 k: 5 3 *100 pF TOTAL CAPACITANCE Figure 16. LED Drive Circuit with Resistor Connected to LED Anode (Not Recommended). ICLEDP 1 4 SHIELD CMOS 20 k: VOUT + - VCC = 15 V 100 pF VCM Figure 18. AC Equivalent Circuit for Figure 13 during Common Mode Transients. +5 V 1 6 1 CLEDP 6 CLED01 5 3 Q1 Q1 4 SHIELD 20 k: 5 100 pF CLEDN 3 VOUT ICLEDN* SHIELD 4 + - * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dVCM/dt TRANSIENTS. VCM Figure 19. Not Recommended Open Collector LED Drive Circuit. Figure 20. AC Equivalent Circuit for Figure 19 during Common Mode Transients. +5 V 1 6 5 3 4 SHIELD Figure 21. Recommended LED Drive Circuit for Ultra High CMR. +5 V ILED1 310 : ILED2 310 : CMOS 6 0.1 PF 5 1 3 SHIELD HCPL-M456 SHIELD Figure 22. Typical Application Circuit. 13 VCC1 20 k: +HV VOUT1 Q1 3 CMOS +5 V IPM HCPL-M456 1 M 4 Q2 6 0.1 PF 5 4 VCC2 20 k: HCPL-M456 VOUT2 HCPL-M456 HCPL-4506 HCPL-M456 HCPL-M456 -HV ILED1 ILED1 VOUT1 VOUT2 Q1 OFF Q1 ON VOUT1 VOUT2 Q2 OFF Q2 ON ILED2 Q1 OFF Q1 ON Q2 OFF Q2 ON ILED2 tPLH MIN. tPLH MAX. tPHL MIN. tPLH MAX. PDD* MAX. PDD* MAX. = (tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN. tPHL MIN. tPHL MAX. *PDD = PROPAGATION DELAY DIFFERENCE MAX. DEAD TIME MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.) = (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.) = PDD* MAX. - PDD* MIN. NOTE: THE PROPAGATION DELAYS USED TO CALCULATE PDD ARE TAKEN AT EQUAL TEMPERATURES. *PDD = PROPAGATION DELAY DIFFERENCE NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES. Figure 23. Minimum LED Skew for Zero Dead Time. For product information and a complete list of distributors, please go to our web site: Figure 24. Waveforms for Deadtime Calculation. www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2011 Avago Technologies. All rights reserved. AV02-3306EN - December 14, 2011