HCPL-M456
Small Outline, 5 Lead Intelligent Power Module Optocoupler
Data Sheet
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Features
x Performance specied for common IPM applications
over industrial temperature range: -40° C to 100° C
x Fast maximum propagation delays
tPHL = 400 ns, tPLH = 550ns
xMinimized Pulse Width Distortion (PWD = 370 ns)
xVery high Common Mode Rejection (CMR):
15 kV/Ps at VCM = 1500 V
xCTR > 44% at IF = 10 mA
xSafety approval
UL recognized per UL1577 (le no. E55361)
– 3750Vms for 1 minute
xLead free option “-000E”
Applications
x IPM isolation
x Isolated IGBT/MOSFET gate drive
x AC and brushless dc motor drives
x Industrial inverters
Schematic Diagram
The connection of a 0.1 PF bypass capacitor between pins 4 and 6 is recommended.
Truth Table
LED VO
ON L
OFF H
Description
The HCPL-M456 consists of a GaAsP LED optically coupled
to an integrated high gain photo detector. Minimized
propagation delay dierence between devices make
these optocouplers excellent solutions for improving
inverter eciency through reduced switching dead time.
Specications and performance plots are given for typical
IPM applications.
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
6
5
4
1
3SHIELD
2
Ordering Information
HCPL-M456 is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Part number
Option
Package Surface Mount
Tape
& Reel
IEC/EN/DIN
EN 60747-5-2 Quantity
RoHS
Compliant
Non RoHS
Compliant
HCPL-M456 -000E No option SO-5 X 100 per tube
-500E #500 X X 1500 per reel
-060E -060 X X 100 per tube
-560E -560 X X X 1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-M456-560E to order product of SO-5 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-M456 to order product of SO-5 Surface Mount package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS
compliant option will use ‘-XXXE‘.
HCPL-M456 Outline Drawing
Pin Location (for reference only)
MXXX
XXX
6
5
43
1
7.0 ± 0.2
(0.276 ± 0.008)
2.5 ± 0.1
(0.098 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
VCC
VOUT
GND
CATHODE
ANODE
4.4 ± 0.1
(0.173 ± 0.004)
1.27
(0.050)BSC
0.15 ± 0.025
(0.006 ± 0.001)
0.71
(0.028)MIN
0.4 ± 0.05
(0.016 ± 0.002)
3.6 ± 0.1*
(0.142 ± 0.004)
Dimensions in millimeters (inches)
* Maximum mold ash on each side is 0.15 mm (0.006)
Note: Floating lead protrusion is 0.15 mm (6 mils) max.
TYPE NUMBER (LAST 3 DIGITS)
DATE CODE
7° MAX.
MAX. LEAD COPLANARITY
= 0.102 (0.004)
3
Figure 1. 5 Pin SOIC Package (JEDEC MO-155) Device Outline Drawing.
Land Pattern Recommendation
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Storage Temperature TS-55 125 °C
Operating Temperature TA-40 100 °C
Average Input Current [1] IF(avg) 25 mA
Peak Input Current [2]
(50% duty cycle, <1 Ps pulse width)
IF(peak) 50 mA
Peak Transient Input Current
(<1 Ps pulse width, 300 pps)
IF(tran) 1.0 A
Reverse Input Voltage (Pin 3-1) VR5 Volts
Average Output Current (Pin 5) IO(avg) 15 mA
Output Voltage (Pin 5-4) VO-0.5 30 Volts
Supply Voltage (Pin 6-4) VCC -0.5 30 Volts
Output Power Dissipation[3] PO100 mW
Total Power Dissipation[4] PT145 mW
Infrared and Vapor Phase Reow Temperature See Reow Thermal Prole below.
8.27
(0.325)
2.0
(0.080)
2.5
(0.10)
1.3
(0.05)
0.64
(0.025)
4.4
(0.17)
DIMENSION IN MILLIMETERS (INCHES)
4
Solder Reow Thermal Prole
Recommended Pb-Free IR Prole
Note: Non-halide ux should be used.
Note: Non-halide ux should be used.
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Power Supply Voltage VCC 4.5 30 Volts
Output Voltage VO0 30 Volts
Input Current (ON) IF(on) 10 20 mA
Input Voltage (OFF) VF(o) -5 0.8 V
Operating Temperature TA-40 100 °C
0
TIME (SECONDS)
TEMPERATURE (°C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160° C
140° C
150° C
PEAK
TEMP.
245° C
PEAK
TEMP.
240° C PEAK
TEMP.
230° C
SOLDERING
TIME
200°C
PREHEATING TIME
150° C, 90 + 30 SEC.
2.5° C ± 0.5°C/SEC.
3° C + 1° C/–0.5° C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3° C + 1° C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5° C ± 0.5°C/SEC.
217° C
RAMP-DOWN
6°C/SEC. MAX.
RAMP-UP
3°C/SEC. MAX.
150 - 200° C
260 +0/-5° C
t 25° C to PEAK
60 to 150 SEC.
20-40 SEC.
TIME WITHIN 5° C of ACTUAL
PEAK TEMPERATURE
tp
ts
PREHEAT
60 to 180 SEC.
tL
TL
Tsmax
Tsmin
25
Tp
TIME
TEMPERATURE
NOTES:
THE TIME FROM 25° C to PEAK
TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200° C, Tsmin = 150° C
5
Regulatory Notes
x The HCPL-M456 is recognized under the component program of U.L. (File No. 55361) for dielectric withstand proof
voltages of 2500 VRMS, 1 minute.
Insulation Related Specications
Parameter Symbol Value Units Conditions
Minimum External Air Gap
External Clearance
L(101) ≥ 5 mm Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking
External Creepage
L(102) ≥ 5 mm Measured from input terminals to output terminals,
shortest distance path along body.
Minimum Internal Plastic
Gap Internal Clearance
0.08 mm Insulation thickness between emitter and detector;
also known as distance through insulation.
Tracking Resistance CTI 200 Volts DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group DIN VDE 0110
Electrical Specications
Over recommended operating conditions unless otherwise specied:
TA = -40° C to +100° C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(o) = -5 V to 0.8 V
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Current Transfer Ratio CTR 44 90 % IF = 10 mA, VO = 0.6 V 5
Low Level Output Current IOL 4.4 9.0 mA IF = 10 mA, VO = 0.6 V 2,3
Low Level Output Voltage VOL 0.3 0.6 V IO = 2.4 mA
Input Threshold Current ITH 1.5 5.0 mA VO = 0.8 V, IO = 0.75 mA 2 9
High Level Output Current IOH 550PAV
F = 0.8 V 4
High Level Supply Current ICCH 0.6 1.3 mA VF = 0.8 V, VO = Open 9
Low Level Supply Current ICCL 0.6 1.3 mA IF = 10 mA, VO = Open 9
Input Forward Voltage VF1.5 1.8 V IF = 10 mA 5
Temperature Coecient of
Forward Voltage
'VF/'T
A-1.6 mV/°C IF = 10 mA
Input Reverse Breakdown
Voltage
BVR5VI
R = 10 PA
Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V
Input-Output Insulation
Voltage
VISO 3750 VRMS RH < 50%, t = 1 min,
TA = 25° C
6, 7
Resistance (Input - Output) RI-O 1012 :VI-O = 500 Vdc 6
Capacitance (Input - Output) CI-O 0.6 pF f = 1 MHz 6
*All typical values at 25° C, VCC = 15 V.
6
Switching Specications (RL= 20 k:)
Over recommended operating conditions unless otherwise specied:
TA = -40° C to +100° C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(o ) = -5 V to 0.8 V
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Propagation Delay
Time to Low
Output Level
tPHL 30 200 400 ns CL = 100 pF IF(on) = 10 mA,
VF(o) = 0.8 V,
VCC = 15.0 V,
VTHLH = 2.0 V,
VTHHL = 1.5 V
6, 8-12 8, 9
100 ns CL = 10 pF
Propagation Delay
Time to High
Output Level
tPLH 270 400 550 ns CL = 100 pF
130 CL = 10 pF
Pulse Width
Distortion
PWD 200 450 ns CL = 100 pF 13
Propagation Delay
Dierence Between
Any 2 Parts
tPLH-tPHL -150 200 450 ns 10
Output High Level
Common Mode
Transient Immunity
|CMH| 15 30 kV/PsI
F = 0 mA,
VO > 3.0 V
VCC = 15.0 V,
CL = 100 pF,
VCM = 1500 V
P-P,
TA= 25° C
711
Output Low Level
Common Mode
Transient Immunity
|CML|1530 kV/PsI
F = 10 mA,
VO < 1.0 V
12
*All typical values at 25° C, VCC = 15 V.
Notes:
1. Derate linearly above 90° C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 90° C free-air temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 90° C free-air temperature at a rate of 3.0 mW/°C.
4. Derate linearly above 90° C free-air temperature at a rate of 4.2 mW/°C.
5. CURRENT TRANSFER RATIO in per cent is dened as the ratio of output collector current (IO) to the forward LED input current (IF) times 100.
6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together.
7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (leakage detection
current limit, II-O ≤ 5 PA).
8. Pulse: f = 20 kHz, Duty Cycle = 10%.
9. Use of a 0.1 PF bypass capacitor connected between pins 4 and 6 can improve performance by ltering power supply line noise.
10. The dierence between tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay
Specications section.)
11. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a Logic High state (i.e., VO > 3.0 V).
12. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a Logic Low state (i.e., VO < 1.0 V).
13. Pulse Width Distortion (PWD) is dened as |tPHL - tPLH| for any given device.
7
LED Drive Circuit Considerations For Ultra High CMR
Performance
Without a detector shield, the dominant cause of opto-
coupler CMR failure is capacitive coupling from the
input side of the opto coupler, through the package, to
the detector IC as shown in Figure 14. The HCPL-M456
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts
the capacitively coupled current away from the sensitive
IC circuitry. However, this shield does not eliminate the
capacitive coupling between the LED and the opto coupler
output pin and output ground as shown in Figure 15.
This capacitive coupling causes perturbations in the LED
current during common mode transients and becomes
the major source of CMR failures for a shielded optocou-
pler. The main design objective of a high CMR LED drive
circuit becomes keeping the LED in the proper state (on
or o) during common mode transients. For example, the
recommended application circuit (Figure 13), can achieve
15 kV/Ps CMR while minimizing component complexity.
Note that a CMOS gate is recommended in Figure 13 to
keep the LED o when the gate is in the high state.
Another cause of CMR failure for a shielded optocoupler
is direct coupling to the optocoupler output pins through
CLEDO1 in Figure 15. Many factors inuence the eect and
magni tude of the direct coupling including: the position
of the LED current setting resistor and the value of the
capacitor at the optocoupler output (CL).
Techniques to keep the LED in the proper state and
minimize the eect of the direct coupling are discussed in
the next two sections.
CMR With The LED On (CMRL)
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriv-
ing the LED current beyond the input threshold so that it
is not pulled below the threshold during a transient. The
recommended minimum LED current of 10 mA provides
adequate margin over the maximum ITH of 4.0 mA (see
Figure 2) to achieve 15 kV/Ps CMR.
The placement of the LED current setting resistor eects
the ability of the drive circuit to keep the LED on during
transients and interacts with the direct coupling to the
optocoupler output. For example, the LED resistor in
Figure 16 is connected to the anode. Figure 17 shows the
AC equivalent circuit for Figure 16 during common mode
transients. During a +dVCM/dt in Figure 17, the current
available at the LED anode (Itotal) is limited by the series
resistor. The LED current (IF) is reduced from its DC value
by an amount equal to the current that ows through
CLEDP and CLEDO1. The situation is made worse because
the current through CLEDO1 has the eect of trying to pull
the output high (toward a CMR failure) at the same time
the LED current is being reduced. For this reason, the rec-
ommended LED drive circuit (Figure 13) places the current
setting resistor in series with the LED cathode. Figure 18
is the AC equivalent circuit for Figure 13 during common
mode transients. In this case, the LED current is not
reduced during a +dVCM/dt transient because the current
owing through the package capacitance is supplied by
the power supply. During a -dVCM/dt transient, however,
the LED current is reduced by the amount of current
owing through CLEDN. But, better CMR performance
is achieved since the current owing in CLEDO1 during a
negative transient acts to keep the output low.
8
IPM Dead Time and Propagation Delay Specications
The HCPL-M456 includes a Propagation Delay Dierence
specication intended to help designers minimize “dead
time” in their power inverter designs. Dead time is the time
period during which both the high and low side power
transistors (Q1 and Q2 in Figure 22) are o. Any overlap in
Q1 and Q2 conduction will result in large currents owing
through the power devices between the high and low
voltage motor rails.
To minimize dead time the designer must consider the
propagation delay characteristics of the optocoupler
as well as the characteristics of the IPM IGBT gate drive
circuit. Considering only the delay characteristics of the
optocoupler (the charac ter is tics of the IPM IGBT gate drive
circuit can be analyzed in the same way) it is important
to know the minimum and maximum turn-on (tPHL) and
turn-o (tPLH) propagation delay specications, preferably
over the desired operating temperature range.
The limiting case of zero dead time occurs when the input
to Q1 turns o at the same time that the input to Q2 turns
on. This case determines the minimum delay between
LED1 turn-o and LED2 turn-on, which is related to the
worst case optocoupler propaga tion delay waveforms,
as shown in Figure 23. A minimum dead time of zero is
achieved in Figure 23 when the signal to turn on LED2
is delayed by (tPLH max - tPHL min) from the LED1 turn o.
Note that the propagation delays used to calculate PDD
are taken at equal temperatures since the optocoup lers
under consideration are typically mounted in close prox-
im ity to each other. (Specically, tPLH max and tPHL min in
the previous equation are not the same as the tPLH max
and tPHL min, over the full operating tempera ture range,
specied in the data sheet.) This delay is the maximum
value for the propagation delay dier ence specication
which is specied at 370 ns for the HCPL-M456 over an
operating tempera ture range of -40° C to 100° C.
Delaying the LED signal by the maximum propagation
delay dierence ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time occurs in
the highly unlikely case where one optocoupler with
the fastest tPLH and another with the slowest tPHL are in
the same inverter leg. The maximum dead time in this
case becomes the sum of the spread in the tPLH and tPHL
propagation delays as shown in Figure 24. The maximum
dead time is also equiv alent to the dierence between
the maximum and minimum propagation delay dier-
ence specications. The maximum dead time (due to the
optocoup lers) for the HCPL-M456 is 520 ns (= 370 ns -
(-150 ns)) over an operating temperature range of -40° C
to 100° C.
CMR With The LED O (CMRH)
A high CMR LED drive circuit must keep the LED o (VF
≤ VF(OFF)) during common mode transients. For example,
during a +dVCM/dt transient in Figure 18, the current
owing through CLEDN is supplied by the parallel combi-
nation of the LED and series resistor. As long as the voltage
developed across the resistor is less than VF(OFF) the LED
will remain o and no common mode failure will occur.
Even if the LED momentarily turns on, the 100 pF capacitor
from pins 5-4 will keep the output from dipping below the
threshold. The recommended LED drive circuit (Figure 13)
provides about 10 V of margin between the lowest opto-
coupler output voltage and a 3 V IPM threshold during a
15 kV/Ps transient with VCM = 1500 V. Additional margin
can be obtained by adding a diode in parallel with the
resistor, as shown by the dashed line connec tion in Figure
18, to clamp the voltage across the LED below VF(OFF).
Since the open collector drive circuit, shown in Figure 19,
cannot keep the LED o during a +dVCM/dt transient, it is
not desirable for applications requir ing ultra high CMRH
performance. Figure 20 is the AC equivalent circuit for
Figure 19 during common mode transients. Essen tially
all the current owing through CLEDN during a +dVCM/dt
transient must be supplied by the LED. CMRH failures can
occur at dv/dt rates where the current through the LED
and CLEDN exceeds the input threshold. Figure 21 is an
alternative drive circuit which does achieve ultra high
CMR performance by shunting the LED in the o state.
9
NORMALIZED OUTPUT CURRENT
TA – TEMPERATURE – °C
0.95
0.90
0.85 IF = 10 mA
VO = 0.6 V
1.00
0 40 60 100-40 -20 20 80
1.05
0.80
IOH – HIGH LEVEL OUTPUT CURRENT – PA
TA – TEMPERATURE – °C
1.5
1.0
0.5
2.0
0 40 60 100-40 -20 20 80
0
4.5 V
30 V
VF = 0.8 V
VCC = VO = 4.5 V OR 30 V
IF – FORWARD CURRENT – mA
0.001
VF – FORWARD VOLTAGE – VOLTS
10
1.0
0.1
1000
1.10 1.601.20 1.30 1.40 1.50
TA = 25° C
0.01
100
IO – OUTPUT CURRENT – mA
0
IF – FORWARD CURRENT – mA
6
4
2
10
8
51015200
VO = 0.6 V
100° C
25° C
-40° C
IF
VF
+
–
Figure 2. Typical Transfer Characteristics. Figure 3. Normalized Output Current vs. Temperature.
Figure 4. High Level Output Current vs. Temperature. Figure 5. Input Current vs. Forward Voltage.
10
Figure 7. CMR Test Circuit.
Figure 6. Propagation Delay Test Circuit.
Typical CMR Waveform.
0.1 PF
VCC = 15 V
20 k:
6
5
4
1
3SHIELD
IF(ON) =10 mA
VOUT
CL*
+
–
*TOTAL LOAD
CAPACITANCE
+
–
If
VO
VTHHL
tPHL tPLH
tftr
90%
10%
90%
10%
VTHLH
0.1 PF
VCC = 15 V
20 k:
6
5
4
1
3SHIELD
A
IF
VOUT
100 pF*
+
–
*100 pF TOTAL
CAPACITANCE
+
–
+
–
B
VFF
VCM = 1500 V
VCM
Dt
O V
VO
VO
SWITCH AT A: IF = 0 mA
SWITCH AT B: IF = 10 mA
VCC
VOL
VCM
't
GV
Gt=
11
Figure 8. Propagation Delay with External 20 k: RL vs. Temperature. Figure 9. Propagation Delay vs. Load Resistance.
Figure 10. Propagation Delay vs. Load Capacitance.
Figure 12. Propagation Delay vs. Input Current.
Figure 11. Propagation Delay vs. Supply Voltage.
tP – PROPAGATION DELAY – ns
TA – TEMPERATURE – °C
400
300
200
500
0 40 60 100-40 -20 20 80
100
tP – PROPAGATION DELAY – ns
0
CL – LOAD CAPACITANCE – pF
800
600
400
1400
200
1000
1200
100 200 300 4000 500
tP – PROPAGATION DELAY – ns
0
VCC – SUPPLY VOLTAGE – V
800
600
400
1400
200
1000
10 15 20 25530
1200
tP – PROPAGATION DELAY – ns
100
IF – FORWARD LED CURRENT – mA
300
500
200
400
10 155020
tPLH
tPHL tPLH
tPHL
IF = 10 mA
VCC = 15 V
CL = 100 pF
RL = 20 K: (EXTERNAL)
IF = 10 mA
VCC = 15 V
CL = 100 pF
TA = 25° C
tP – PROPAGATION DELAY – ns
RL – LOAD RESISTANCE – K:
600
400
200
800
30 5001020 40
tPLH
tPHL
tPLH
tPHL
IF = 10 mA
VCC = 15 V
RL = 20 K:
TA = 25° C
IF = 10 mA
CL = 100 pF
RL = 20 K:
TA = 25° C
tPLH
tPHL
VCC = 15 V
CL = 100 pF
RL = 20 K:
TA = 25° C
12
Figure 14. Optocoupler Input to Output Capacitance Model for Unshielded
Optocouplers.
Figure 13. Recommended LED Drive Circuit.
Figure 15. Optocoupler Input to Output Capacitance Model for Shielded
Optocouplers.
Figure 16. LED Drive Circuit with Resistor Connected to LED Anode (Not
Recommended).
Figure 17. AC Equivalent Circuit for Figure 16 during Common Mode Transients. Figure 18. AC Equivalent Circuit for Figure 13 during Common Mode Transients.
0.1 PF
VCC = 15 V
20 k:
6
5
4
1
3SHIELD
CMOS
310 :
+5 V
VOUT
100 pF
+
–
*100 pF TOTAL
CAPACITANCE
6
5
4
1
3
CLEDP
CLEDN
6
5
4
1
3
CLEDP
CLEDN SHIELD
CLED01
0.1 PF
VCC = 15 V
20 k:
6
5
4
1
3SHIELD
CMOS
310 :
+5 V
VOUT
100 pF
+
–
*100 pF TOTAL
CAPACITANCE
20 k:
6
5
4
1
3
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
300 :
VOUT
100 pF
ICLEDP
CLEDN SHIELD
CLED01
+
–
ITOTAL*
ICLED01
IF
VCM
20 k:
6
5
4
1
3
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
PERFORMANCE. VR < VF (OFF) DURING +dVCM/dt.
VOUT
100 pF
CLEDP
CLEDN
SHIELD
CLED01
+
–
ICLEDN*
300 :
+ VR** –
VCM
13
Figure 21. Recommended LED Drive Circuit for Ultra High CMR.
Figure 19. Not Recommended Open Collector LED Drive Circuit. Figure 20. AC Equivalent Circuit for Figure 19 during Common Mode Transients.
Figure 22. Typical Application Circuit.
6
5
4
1
3SHIELD
Q1
+5 V
20 k:
6
5
4
1
3
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
VOUT
100 pF
CLEDP
CLEDN
SHIELD
CLED01
+
–
ICLEDN*
Q1
VCM
6
5
4
1
3SHIELD
+5 V
0.1 PF20 k:
6
5
4
1
3SHIELD
CMOS
310 :
+5 V
VOUT1
HCPL-M456
ILED1 VCC1
0.1 PF20 k:
6
5
4
1
3SHIELD
CMOS
310 :
+5 V
VOUT2
HCPL-M456
ILED2 VCC2
M
Q2
Q1
-HV
+HV
IPM
HCPL-M456
HCPL-4506
HCPL-M456
HCPL-M456
HCPL-M456
Figure 23. Minimum LED Skew for Zero Dead Time. Figure 24. Waveforms for Deadtime Calculation.
VOUT1
VOUT2
ILED2
tPLH MAX.
PDD* MAX. =
(tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN.
tPHL MIN.
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
VOUT1
VOUT2
ILED2
tPLH MIN.
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
= (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.)
= (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.)
= PDD* MAX. - PDD* MIN.
tPHL MIN.
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
*PDD = PROPAGATION DELAY DIFFERENCE
tPLH MAX.
tPHL MAX.
PDD*
MAX.
MAX.
DEAD TIME
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
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Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-3306EN - December 14, 2011