This hardwa re specifi cation is primarily co ncerned with the Power PC™ MPC7457; howeve r ,
unless other wise note d, all i nformat ion h ere a lso a pplies to the MPC7447 . The MPC745 7 and
MPC7447 are implement ations of th e PowerPC microproce ssor family of reduced instr uction
set computer (RISC) microprocessors. This hardware specification describes pertinent
electrical and physical characteristics of the MPC7457. For functional characteristics of the
processor, refer to the M PC7450 RISC Microprocessor Family User’s Manual.
This hardw are s pecif icatio n contains the following topics:
Topic Page
Section 1.1, “Overview” 1
Section 1.2, “Features” 2
Section 1.3, “Comparison with the MPC7455, MPC7445, MPC7450, MPC7451,
and MPC7441” 7
Section 1.4, “General Parameters” 10
Section 1.5, “Electrical and Thermal Characteristics” 10
Section 1.6, “Pin Assignments” 33
Section 1.7, “Pinout Listings” 35
Section 1.8, “Package Description” 41
Section 1.9, “System Design Information” 47
Section 1.10, “Document Revision History” 61
Section 1.11, “Ordering Information” 63
To locate any published updates for this hardware specification, refer to the website at
http://www.motorola.com/semiconductors.
1.1 Overvie w
The MPC7457 is the fourth implementation of the fourth generation (G4) microprocessors
from Motorola. The MPC7457 implements the full PowerPC 32-bit architecture and is
targeted at networking and computing systems applications. The MPC7457 consists of a
processor core, a 512-Kbyte L2, and an internal L3 tag and controller that support a glueless
backside L3 cache through a dedicated high-bandwidth interface. The MPC7447 is identical
to the MPC7457 except that it does not support the L3 cache interface.
Advance Information
MPC7457EC
Rev. 4, 11/2003
MPC7457
RISC Microprocessor
Hardware Specifications
2MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Features Features
Figure 1 shows a block diagram of the MPC7457. The core is a high-performance superscalar design
supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage
subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other
system r esources. Th e L3 interfac e supports 1, 2, or 4 Mbyt es of ext ernal SRAM for L3 cache and /or private
memory data. For systems implementing 4 Mbytes of SRAM, a maximum of 2 Mbytes may be used as
cache; the remaining 2 Mbytes must be private memory.
Note that t he MPC7457 is a footprint-compatib le, drop-in replace ment in a MPC7455 application if the cor e
power supply is 1.3 V.
1.2 Features
This section summarizes features of the MPC7457 implementation of the PowerPC architecture.
Major features of the MPC7457 are as follows:
• High-performance, superscalar microprocessor
— As many as four instructions can be fetched from the instruction cache at a time.
— As many as three instructions can be dispatched to the issue queues at a time.
— As many as 12 instructions can be in the instruction queue (IQ).
— As many as 16 instructions can be at some stage of execution simultaneously.
— Single-cycle execution for most instructions
— One instruction per clock cycle throughput for most instructions
— Seven-stage pipeline control
• Eleven independent execution units and three register files
— Branch processing unit (BPU) features static and dynamic branch prediction
– 128-entry (32-s et, four-wa y set-a ssociative) bra nch target i nstruction cache (BTIC), a cac he
of branc h instruct ions that ha ve been enc ountered in branch/loop c ode sequences . If a tar get
instruction is in t he BTIC, it is fetched int o the instructi on queue a cycle soone r than it can
be made available from the instruction cache. Typically , a fetch that hits the BTIC provides
the first four instructions in the target stream .
– 2048-entry branch history (BHT) with two bits per entry for four levels of
prediction—not-taken, strongly not-taken, taken, and strongly taken
– Up to three outstanding speculative branches
– Branch instructions that do not update the count register (CTR) or link register (LR) are
often removed from the instruction stream.
– Eight-entry link register stack to predict the target address of Branch Conditional to Link
Register (bclr) inst ructions
— Four integer units (IUs) that share 32 GPRs for integer operands
– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
multiply, divide, and move to/from special-purpose register instructions
– IU2 executes miscellaneous instructions including the CR logical operations, integer
multiplication and division instructions, and move to/from special-purpose register
instructions
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 3
Features
Figure 1. MPC7457 Block Diagram
+
Integer
Reservation
Station
Unit 2
+
Integer
Reservation
Station
Unit 2
Additional Features
• Time Base Counter/Decrementer
• Clock Multiplier
• JTAG/COP Interface
• Thermal/Power Management
• Performance Monitor
+
+
x ÷
FPSCR
FPSCR
PA
+ x ÷
Instruction Unit Instruction Queue
(12-Word)
96-Bit (3 Instructions)
Reservation
Integer
128-Bit (4 Instructions)
32-Bit
Floating-
Point Unit
64-Bit
Reservation
Load/Store Unit
(EA Calculation)
Finished
32-Bit
Completion Unit
Completion Queue
(16-Entry)
Tags 32-Kbyte
D Cache
36-Bit 64-Bit
Integer
Stations (2)
Reservation
Station
Reservation
Stations (2) FPR File
16 Rename
Buffers
Stations (2-Entry)
GPR File
16 Rename
Buffers
Reservation
Station
VR File
16 Rename
Buffers
64-Bit
128-Bit
128-Bit
Completes up
Completed
Instruction MMU
SRs
(Shadow) 128-Entry
IBAT Array
ITLB Tags 32-Kbyte
I Cache
Stores
Stores
Load Miss
Vector
Touch
Queue
(3)
VR Issue FPR Issue
Branch Processing Unit
CTR
LR
BTIC (128-Entry)
BHT (2048-Entry)
Fetcher
GPR Issue
(6-Entry/3-Issue) (4-Entry/2-Issue) (2-Entry/1-Issue)
Dispatch
Unit Data MMU
SRs
(Original) 128-Entry
DBAT Array
DTLB
Vector Touch Engi ne
32-Bit
EA
L1 Castout
Status
L2 Store Queu e (L2SQ )
Vector
FPU
Reservation
Station
Reservation
Station
Reservation
Station
Vector
Integer
Unit 1
Vector
Integer
Unit 2
Vector
Permute
Unit
Line
Tags Block 0 (32-Byte) Status
Block 1 (32-Byte)
Memory Subsystem
Snoop Push/
Interventions
L1 Castouts
Bus Accumulator
L1 Push
(4)
Unit 2 Unit 1
to three
per clock
instructions
L1 Load Queue (LLQ)
L1 Load Miss (5)
Cacheable Store Request(1)
Instruc ti on Fe tch (2)
L1 Service
L1 Store Queue
(LSQ)
L3 Cache Controller
1
L3CR
StatusTags
Bus Accumulator
Block 0/1
Line
System Bus Inter face
L2 Prefetch (3)
64-Bit Data
(8-Bit Parity)
External SRAM Address Bus Data Bus
Queues
Castout
Bus Store Queue
Push
Load
Queue (11)
Queue (9)/
Queue (10)
2
Notes: 1. The L3 cache interface is not implemented on the MPC7447.
2. The Castout Queue and Push Queue share resources such for a combined total of 10 entries.
The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.
512-K b yte Unifie d L2 C ach e Con tr ol ler
19-Bit Address
(1, 2, or 4 Mbytes)
4MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Features Features
— Five-stage FPU and a 32-entry FPR file
– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Hardware support for denormalized numbers
– Thirty-two 64-bit FPRs for single- or double-precision operands
— Four vector units and 32-entry vector register file (VRs)
– Vector permute unit (VPU)
– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as
vector add instructions (for example, vaddsbs, vaddshs, and vaddsws)
– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as
vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and
vmladduhm)
– Vector floating-point unit (VFPU)
— Three-stage load/store unit (LSU)
– Supports integer, floating-point, and vector instruction load/store traffic
– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream
operations
– Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle
throughput
– Four-cycle FPR load latency (single, double) with one-cycle throughput
– No additional delay for misaligned access within double-word boundary
– Dedicated adder calculates effective addresses (EAs)
– Supports store gathering
– Performs alignment, normalization, and precision conversion for floating-point data
– Executes cache control and TLB instructions
– Performs alignment, zero padding, and sign extension for integer data
– Supports hits under misses (multiple outstanding misses)
– Supports both big- and little-endian modes, including misaligned little-endian accesses
• Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions,
respectively, in a cyc le. Instruction dispatch require s the following:
— Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2
— A maximum of three instructions can be dispatched to the issue queues per clock cycle
— Space must be avail able i n the CQ for a n in stru ction to dis patch (t his i nclude s inst ruct ions t hat
are assigned a space in the CQ but not in an issue queue)
• Rename buffers
— 16 GPR rename buffers
— 16 FPR re name buffers
— 16 VR rename buffers
• Dispatch unit
— Decode/dispatch stage fully decodes each instruction
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 5
Features
• Completion unit
— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
• Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycl e
— Caches can be disabled in software.
— Caches can be locked in software.
— ME SI data cac he coheren cy maintai ned in hardware
— Separate copy of data cache tags for efficient snooping
— Parity support on cache and tags
— No snooping of instruction cache except for icbi instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
• Level 2 (L2) cache interface
— On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total nine-cycle load latency for an L1 data cache mis s that hits in L2
— PLRU replacement algorithm
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity supp ort on cache
• Level 3 (L3) cache interface (not implemented on MPC7447)
— Provides critical double-word forwarding to the requesting unit
— Internal L3 cache controller and tags
— External data SRAMs
— Support for 1-, 2-, and 4-Mbyte (MB) total SRAM space
— Support for 1- or 2-MB of cache space
— Cache write-back or write-through operation programmable on a per-page or per-block basis
6MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Features Features
— 64-byte (1-MB) or 128-byte (2-MB) sectored line size
— Priv ate memory capa bility for h alf (1 MB minim um) or all of th e L3 SRAM space for a t otal of
1-, 2-, or 4-MB of private memory
— Supports MSUG2 dual data rate (DDR) synchronous burst SRAMs, PB2 pipelined
synchronous burst SRAMs, and pipelined (register-register) late write synchronous burst
SRAMs
— Supports parity on cache and tags
— Configurable core-to-L3 frequency divisors
— 64-bit external L3 data bus sustains 64 bits per L3 clock cycle
• Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address; 32- or 36-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and
memory coherency enforced/memory coherency not enforced on a page or block basis
— Separate IBATs and DBATs (eight each) also defined as SPRs
— Separate instruct ion and data translation lookaside buffers (TLBs)
– Both TLBs are 128-entry, two-way set-associative, and use LRU replacement algorithm
– TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is
performed in hardware or by system software)
• Efficient data flow
— Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits
— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs
— L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache
— As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data
cache and L2/L3 bus
— As many as 16 out-of-order transactions can be present on the MPX bus
— Store merging for multiple store misses to the same line. Only coherency action taken
(addres s-only) fo r store misse s mer ged to all 32 bytes of a cache block (no da ta tenure nee ded).
— Three-entry finished store queue and five-entry completed store queue between the LSU and the
L1 data cache
— Separate additional queues for efficient buffering of outbound data (such as castouts and
write-through stores) from the L1 data cache and L2 cache
• Multiprocessing support features include the following:
— Hardware-enforced, MESI cache coherency protocols for data cache
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
other mult iprocessor operations
• Power and thermal management
— 1.3-V processor core
— The following three power-saving modes are available to the system:
– Nap—Instruction fetching is halted. Only those clocks for the time base, decrementer, and
JTAG logic remain running. The part goes into the doze state to snoop memory operations
on the bus and back to nap using a QREQ/QACK processor-system handshake protocol.
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 7
Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441
– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the
PLL in a locked and running state. All internal functional units are disabled.
– Deep sleep—When the part is in the sleep state, the sys tem can disable the PLL. The system
can then disable the SYSCLK source for greater system power savings. Power-on reset
procedur es for rest arti ng an d relo cking t he PLL mu st be f ollowed on e xitin g the de ep slee p
state.
— Thermal management facility provides software-controllable thermal management. Thermal
management is performed through the use of three supervisor-level registers and an
MPC7457-specific thermal management exception.
— Instru ction cache throt tling provide s control of inst ruction fetch ing to limit power consump tion
• Performance monitor can be used to help debug system designs and improve software efficiency
• In-system testability and debugging features through JTAG boundary-scan capability
• Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
— Array bu ilt-in self test (ABIST)—factory test only
• Re liability and serviceabi lity
— Parity checking on system bus and L3 cache bus
— Parity checking on the L2 and L3 cache tag arrays
1.3 Comparison with the MPC7455, MPC7445,
MPC7450, MPC7451, and MPC74 41
Table 1 compares the key features of the MPC7457 with the key features of the earlier MPC7455,
MPC7445, MPC7450, MPC74 51, and MPC7441. To achieve a higher frequency, the n umber of logi c level s
per cycle is reduced. Also, to achieve this higher frequency, the pipeline of the MPC7457 is extended
(compare d to the MPC7400 ), while mai nt ain ing the sa me l eve l of perf orma nce as measure d by t he number
of instructions executed per cycle (IPC).
Table 1. Microarchitectur e Comparison
Mi croarchitectural Specs MPC7457/MPC7447 MPC7455/MPC7445 MPC7450/MPC7451/
MPC7441
Basic Pipeline Functions
Logic inversions per cycle 18 18 18
Pipeline stages up to execute 5 5 5
Total pipeline stages (minimum) 7 7 7
Pipeline maximum instruction
throughput 3 + Branch 3 + Br anch 3 + Branch
Pipeline Resou r ces
Instruction buffer size 12 12 12
Compl eti on buffer size 16 16 16
Renames (integer, float, vector) 16, 16, 16 16, 16, 16 16, 16, 16
8MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441 Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441
Maximum Execution Throughput
SFX 333
Vector 2 (any 2 of 4 units) 2 (any 2 of 4 units) 2 (any 2 of 4 units)
Scalar floating-point 1 1 1
Out-of-Order Window Size in Execution Queues
SFX integer units 1 entry × 3 queues 1 entry × 3 queues 1 entry × 3 queues
Vector units In order, 4 queues In order, 4 queues In order, 4 queues
Scalar floating-point unit In order In order In order
Branch Processing Resources
Prediction structures BTIC, BHT, link stack BTIC, BHT, link stack BTIC, BHT, link stack
BTIC size, associativity 128-entry, 4-way 128-entry, 4-way 128-entry, 4-way
BHT size 2K-entry 2K-entry 2K-entry
Link stack depth 8 8 8
Unreso lv ed bran ch es suppo rted 3 3 3
Branch taken penalty (BTIC hit) 1 1 1
Minimum misprediction penalty 6 6 6
Execution Unit Timings (Latency-Throughput)
Aligned load (integer, float, vector) 3-1 , 4-1, 3-1 3-1 , 4-1, 3-1 3-1, 4-1, 3-1
Misaligned load (integer, float, vector) 4-2, 5-2, 4-2 4-2, 5-2, 4-2 4-2, 5-2, 4-2
L1 miss, L2 hit latency 9 data/13 instruction 9 data/13 instruction 9 data/13 instruction
SFX (aDd Sub , Shift, Rot, Cmp, logical s) 1-1 1-1 1-1
Integer multiply (32 × 8, 32 × 16, 32 × 32) 3-1, 3- 1, 4-2 3 -1, 3-1, 4-2 3 -1, 3-1, 4-2
Scalar float 5-1 5-1 5-1
VSFX (vector simple) 1-1 1-1 1-1
VCFX (vector complex) 4-1 4-1 4-1
VFPU (vector float) 4-1 4-1 4-1
VPER (vector permute) 2-1 2-1 2-1
MMUs
TLBs (instruction and data) 128-entry, 2-way 128-entry, 2-way 128-entry, 2-way
Tablewalk me cha ni sm H ardware + software Hardwar e + software Hardw a re + software
Instruction BATs/data BATs 8/8 8/8 4/4
Table 1. Microarchitecture Comparison (continued)
Mi croarchitectural Specs MPC7457/MPC7447 MPC7455/MPC7445 MPC7450/MPC7451/
MPC7441
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 9
Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441
L1 I Cache/D Cache Features
Size 32K/32K 32K/32K 32K/32K
Associativity 8-way 8-way 8-way
Locking granularity Way Way Way
Parity on I cache Word Word Word
Parity on D cache Byte B yte Byte
Number of D cache misses (load/store) 5/1 5/1 5/1
Data stream touch engines 4 streams 4 streams 4 streams
On-Chip Cache Features
Cache level L2 L2 L2
Size/associativity 512-Kbyte/8-way 256-Kbyte/8-way 256-Kbyte/8-way
Access width 256 bits 256 bits 256 bits
Number of 32-byte sectors/line 2 2 2
Parity Byte Byte Byte
Off-Chip Cache Support 1
Cache level L3 L3 L3
Total SRAM space supported 1 MB, 2MB, 4 MB 21 MB, 2 MB 1 MB, 2 MB
On-chip tag logical size (cache space) 1MB, 2MB 1MB, 2MB 1MB, 2MB
Associativity 8-way 8-way 8-way
Number of 32-byte sectors/line 2, 4 2, 4 2, 4
Off-Chip data SRAM support MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2
Data path width 64 64 64
Direct mapped SRAM sizes 1 MB, 2 MB, 4MB 1 MB, 2 MB 1 MB, 2 MB
Parity Byte Byte Byte
Notes:
1. Not implemented on MPC7447, MPC7445, or MPC7441
2. The MPC7457 supports up to 4 MB of SRAM, of which a maximum of 2 MB can be configured as cache memory;
the remaining 2 MB may be unused or configured as private memory.
Table 1. Microarchitecture Comparison (continued)
Mi croarchitectural Specs MPC7457/MPC7447 MPC7455/MPC7445 MPC7450/MPC7451/
MPC7441
10 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
General Parameters General Parameters
1.4 Gene ral Para meters
The following list provides a summary of the general parameters of the MPC7457:
Technology 0.13 µm CMOS, nine-layer metal
Die size 9.1 mm × 10.8 mm
Transistor count 58 million
Logic design Fully-static
Packages MPC7447: Surface mount 360 ceramic ball grid array (CBGA)
MPC7457: Surface mount 483 ceramic ball grid array (CBGA)
Core power supply 1.3 V ± 50 mV DC nominal
I/O power supply 1.8 V ± 5% DC, or
2.5 V ± 5% DC, or
1.5 V ± 5% DC (L3 interface only, not implemented on MPC7447)
1.5 Electrical and Thermal Characteristics
This sect ion provides the AC and DC electrical spe cification s and thermal chara cteristics fo r the MPC7457.
1.5.1 DC Electrical Characteristics
The table s in this se ction descri be the MPC7457 DC electr ical charact eris tics .Ta ble 2 provides th e absol ute
maximum ratings.
Table 2. Absolute Maximum Ratings 1
Characteristic Symbol Maximum Value Unit Not es
Core supply voltage VDD –0.3 to 1.60 V 2
PLL supply voltage AVDD –0.3 to 1.60 V 2
Processor bus supply voltage BVSEL = 0 OVDD –0.3 to 1.95 V 3, 4
BVSEL = HRESET or OVDD OVDD –0.3 to 2.7 V 3, 5
L3 bus supply voltage L3VSEL = ¬HRESET GVDD –0.3 to 1.65 V 3, 6
L3VSEL = 0 GV DD –0.3 to 1.95 V 3, 7
L3VSEL = HRESET or GVDD GVDD –0.3 to 2.7 V 3, 8
Input voltage Processor bus Vin –0.3 to OVDD + 0.3 V 9, 10
L3 bus Vin –0.3 to GVDD + 0.3 V 9, 10
JTAG signals Vin –0.3 to OVDD + 0.3 V
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 11
Electrical and Thermal Characteristics
Figure 2 shows the undershoot and overshoot voltage on the MPC7457.
Figure 2. Overshoot/Undershoot Volt age
The MPC7457 provides several I/O voltages to support both compatibility with existing systems and
migration to future systems. The MPC7457 core voltage must always be provided at nominal 1.3 V (see
Table 4 for actual recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are
provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The
input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the
negatio n of the s ignal HRESET. The output voltage will swi ng from GND to the maxi mum voltage applie d
to the OVDD or GVDD power pins.
Storage temperature range Tstg –55 to 150 °C
Notes:
1. Functio nal and tested op erating condit ions are given in Table 4. Abs olute maximum ratings are stress rat ings on ly,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
2. Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1.0 V during normal operation; this limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2.0 V during normal operation; this limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4. BVSEL must be set to 0, such that the bus is in 1.8-V mode.
5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.
6. L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5-V mode.
7. L3VSEL must be set to 0, such that the bus is in 1.8-V mode.
8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.
9. Caution: Vin must not exceed OVDD or GVDD by more than 0.3 V at any time including during power-on reset.
10.Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
Table 2. Absolute Maximum Ratings 1 (continued)
Characteristic Symbol Maximum Value Unit Not es
VIH
GND
GND – 0.3 V
GND – 0.7 V Not to exceed 10%
OVDD/GVDD + 20%
VIL
OVDD/GVDD
OVDD/GVDD + 5%
of tSYSCLK
12 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Characteristi cs El ectrical and Thermal Characteristi cs
Table 4 provides the recommended operating conditions for the MPC7457.
Table 3. Input Threshold Voltage Setting
BVSEL Signal Processor Bus Input
Threshold is Relative to: L3VSEL Signal 1 L3 Bus Input Threshold is
Relative to: Notes
0 1.8 V 0 1.8 V 2, 3
¬HRESET Not Available ¬HRESET 1.5 V 2, 4
HRESET 2.5 V HRESET 2.5 V 2
1 2.5 V 1 2.5 V 2
Notes:
1. Not implemented on MPC7447
2. Caution: The input threshold selection must agre e with t he OVDD/GVDD voltages supp li ed. See note s in Table 2.
3. If used, pull-down resistors should be less than 250 Ω.
4. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.
Table 4. Recommended Operating Conditions 1
Characteristic Symbol Recommended Value Unit Notes
Min Max
Core supply voltage VDD 1.3 V ± 50 mV V
PLL supply voltage AVDD 1.3 V ± 50 mV V 2
Processor bus supply voltage BVSEL = 0 OVDD 1.8 V ± 5% V
BVSEL = HRESET or OVDD OVDD 2.5 V ± 5% V
L3 bus supply voltage L3VSEL = 0 GVDD 1.8 V ± 5% V
L3VSEL = HRESET or GVDD GVDD 2.5 V ± 5% V
L3VSEL = ¬HRESET GVDD 1.5 V ± 5% V 3
Input voltage Processor bus Vin GND OVDD V
L3 bus Vin GND GVDD V
JTAG signals Vin GND OVDD V
Die-junction temperature Tj0 105 °C
Notes:
1. These are th e recommen ded and tested ope rating c onditi ons. Prope r device ope ration ou t side of these condi tions
is not guaranteed.
2. This voltage is the input to the filter discussed in Section 1.9.2, “PLL Power Supply Filtering,” and not necessarily
the voltage at the AVDD pin, which may be reduced from VDD by the filter.
3. ¬HRESET is the inverse of HRESET.
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 13
Electrical and Thermal Characteristics
Table 5 provides the package thermal characteristics for the MPC7457.
Table 6 provides the DC electrical characteristics for the MPC7457.
Table 5. Package Thermal Characteristics 1
Characteristic Symbol Value Unit Notes
MPC7447 MPC7457
Junction-to-ambient thermal resistance, natural
convection RθJA 22 20 °C/W 2, 3
Junction-to-ambient thermal resistance, natural
convection, four-layer (2s2p) board RθJMA 14 14 °C/W 2, 4
Junction-to-ambient thermal resistance, 200 ft/min
airflow, single-layer (1s) board RθJMA 16 15 °C/W 2, 4
Junction-to-ambient thermal resistance, 200 ft/min
airflow, four-layer (2s2p) board RθJMA 11 11 °C/W 2, 4
Juncti on-t o-bo ard thermal resis tance RθJB 6 6 °C/W 5
Junction-to-case thermal resistance RθJC <0.1 <0.1 °C/W 6
Notes:
1. Refer to Section 1.9.8, “Thermal Management Information,” for more details about thermal management.
2. Junction tempera ture is a fun ction of on-c hip pow er dis sipa tion, p ac kage thermal resist ance , mou nting sit e (board )
temperat ure, ambient te mperature, airflow , powe r dissipa tion of other co mponent s on the board, a nd board the rmal
resistance.
3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal
4. Per JEDEC JESD51-6 with the board horizontal
5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
6. Thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Me thod 101 2.1) with th e calcula ted cas e temperat ure. The actual v alue of RθJC for the p art is less
than 0.1° C/W.
Table 6. DC Electrical Specifications
At recommended operating conditions. See Table 4.
Characteristic Nominal
Bus
Voltage 1Symbol Min Max Unit Notes
Input high voltage
(all input s incl udi ng SYSCLK) 1.5 VIH GVDD × 0.65 GVDD + 0.3 V 2
1.8 OVDD/GVDD × 0.65 OVDD/GVDD + 0.3 V
2.5 1.7 OVDD/GVDD + 0.3 V
Input low voltage
(all input s incl udi ng SYSCLK) 1.5 VIL –0.3 GVDD × 0.35 V 2, 6
1.8 –0.3 OVDD/GVDD × 0.35 V
2.5 –0.3 0.7 V
Input leakage current,
Vin = GVDD/OVDD
—I
in —30µA2, 3
14 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Characteristi cs El ectrical and Thermal Characteristi cs
Table 7 provides the power consumption for the MPC7457.
High-impedance (off-state)
leakage current, Vin = GVDD/OVDD
—I
TSI —30µA2, 3, 4
Output high voltage, IOH = –5 mA 1.5 VOH OVDD/GVDD – 0.45 — V 6
1.8 OVDD/GVDD – 0.45 — V
2.5 1.8 — V
Output low voltage, IOL = 5 mA 1.5 VOL —0.45V6
1.8 — 0.45 V
2.5 — 0.6 V
Capacitance,
Vin = 0 V,
f = 1 MHz
L3 interface — Cin —9.5pF5
All other inputs — 8.0 pF 5
Notes:
1. Nominal voltages; see Table 4 for recommended operating conditions.
2. For processor bus signals, the reference is OVDD while GVDD is the reference for the L3 bus signals.
3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals
4. The leakage is measured for nominal OVDD/GVDD and VDD, or both OVDD/GVDD and VDD must vary in the same
direction (for example, both OVDD and VDD vary by either +5% or –5%).
5. Capacitance is periodically sampled rather than 100% tested.
6. Appl icable to L3 bus interface only
Table 7. Power Consumption for MPC7457
Processor (CPU) Frequency Unit Notes
867 MHz 1000 MHz 1200 MHz 1267 MHz
Full-Power Mode
Typical 14.8 15.8 17.5 18.3 W 1, 2
Maximum 21.0 22.0 24.2 25.6 W 1, 3
Nap Mode
Typical 5.2 5.2 5.2 5.2 W 1, 2
Sleep Mode
Typical 5.1 5.1 5.1 5.1 W 1, 2
Deep Sleep Mode (PLL Disabled)
Table 6. DC Electrical Specifications (continued)
At recommended operating conditions. See Table 4.
Characteristic Nominal
Bus
Voltage 1Symbol Min Max Unit Notes
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 15
Electrical and Thermal Characteristics
1.5.2 AC Electrical Characteristics
This section p rovi de s t he AC electr ic al charact eri st ic s f or the MP C7457. Aft er fabri cat i on, functi onal pa rt s
are sorted by maximum processor core frequency as shown in Section 1.5.2.1, “Clock AC Specifications,”
and tested for conformance to the AC specifications for that frequency. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold
by maximum processor core frequency; see Section 1.11, “Ordering Information.”
1.5.2.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 6and represents the tested
operating frequencies of the devices. The maximum system bus frequency, fSYSCLK, given in Table 8 is
considered a practical maximum in a typical single-processor system. The actual maximum SYSCLK
frequency for any application of the MPC7457 will be a function of the AC timings of the MPC7457, the
AC timings for the syst em controller , bus loading, printed-circuit board topology, trace lengths, and so fo rth,
and may be less than the value given in Table 8.
Typical 5.0 5.0 5.0 5.0 W 1, 2
Notes:
1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OVDD
and GV DD) or PLL supply power (A VDD). OVDD and GVDD power is system dependent, but is t ypically < 5% of VDD
power. Worst case power consump tion for AVDD < 3 mW.
2. Typical power is an average value measured at the nominal recommended VDD (see Table 4) and 65°C while
running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.
3. Maximum power is the average measured at nominal VDD and maximum operating junction temperature (see
Table 4) while runn ing an entirely ca che-resident , cont rived sequence of ins tructions wh ich keep all the exec ution
unit s ma xi ma lly busy.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep
mod e. As a result, power consumption for this mode is not tested.
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See Table 4.
Characteristic Symbol
Maximum Processor Core Frequency
Unit Notes
867 MHz 1000 MHz 1200 MHz 1267 MHz
MinMaxMinMaxMinMaxMinMax
Processor freq uen cy fcore 600 867 600 1000 600 1200 600 1267 MHz 1
VCO frequency fVCO 1200 1733 1200 2000 1200 2400 1200 2534 MHz 1
SYSCLK frequency fSYSCLK 33167331673316733167MHz1, 2
SYSCLK cycle time tSYSCLK 6.0 30 6.0 30 6.0 30 6.0 30 ns 2
SYSCLK rise and fall time tKR, tKF —1.0—1.0—1.0—1.0ns 3
Table 7. Power Consumption for MPC7457 (continued)
Processor (CPU) Frequency Unit Notes
867 MHz 1000 MHz 1200 MHz 1267 MHz
16 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Characteristi cs El ectrical and Thermal Characteristi cs
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
SYSCLK duty cycle
measured at OVDD/2 tKHKL/
tSYSCLK
40 60 40 60 40 60 40 60 % 4
SYSCLK jitter — ± 150 — ± 150 — ± 150 — ± 150 ps 5, 6
Internal PLL relock time — 100 — 100 — 100 — 100 µs7
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK
(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Configuration,”
for valid PLL_CFG[0:4] settings.
2. Assumes lightly-loaded, single-processor system
3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V
4. Timing is guaranteed by design and characterization.
5. This represents total input jitter—short term and long term combined—and is guaranteed by design.
6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low
to allow cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.
7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This
specific ati on also app lie s w he n the PLL has been di sa bled and su bsequentl y re-enable d during sle ep m ode . Als o
note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the
power-on res et sequen ce.
Table 8. Clock AC Timing Specifications (continue d)
At recommended operating conditions. See Table 4.
Characteristic Symbol
Maximum Processor Core Frequency
Unit Notes
867 MHz 1000 MHz 1200 MHz 1267 MHz
MinMaxMinMaxMinMaxMinMax
SYSCLK VMVMVM CVIH
CVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
tKR tKF
tKHKL
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 17
Electrical and Thermal Characteristics
1.5.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7457 as defined in Figure 4 and
Figure 5. Timing specifications for the L3 bus are provided in Section 1.5.2.3, “L3 Clock AC
Specifications.”
Table 9. Processor Bus AC Timing Specifications 1
At recommended operating conditions. See Table 4.
Parameter Symbol 2All Speed Grades Unit Notes
Min Max
Input setup times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK, TA, TBEN, TEA, TS,
EXT_QUAL, PMON_IN, SHD[0:1], BMODE[0:1],
BMODE[0:1], BVSEL, L3VSEL
tAVKH
tDVKH
tIVKH
tMVKH
1.8
1.8
1.8
1.8
—
—
—
—
ns
8
Input hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,
PMON_IN, SHD[0:1]
BMODE[0:1], BVSEL, L3VSEL
tAXKH
tDXKH
tIXKH
tMXKH
0
0
0
0
—
—
—
—
ns
8
Output val id times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, C I, CKSTP_IN, DRDY, DTI[0:3],
GBL, HIT, P MON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT
tKHAV
tKHDV
tKHOV
—
—
—
2.0
2.0
2.0
ns
Output hol d time s:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, C I, CKSTP_IN, DRDY, DTI[0:3],
GBL, HI T, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT
tKHAX
tKHDX
tKHOX
0.5
0.5
0.5
—
—
—
ns
SYSCLK to output enable tKHOE 0.5 — ns
SYSCLK to output hi gh impedance (all ex cept TS, ARTR Y,
SHD0, SHD1)tKHOZ —3.5ns
SYSCLK to TS high impedance after precharge tKHTSPZ —1t
SYSCLK 3, 4, 5
Maximum delay to ARTRY/SHD0/SHD1 precharge tKHARP —1t
SYSCLK 3, 5
6, 7
18 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Characteristi cs El ectrical and Thermal Characteristi cs
Figure 4 provides the AC test load for the MPC7457.
Figure 4. AC Test Load
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge tKHARPZ —2t
SYSCLK 3, 5
6, 7
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge
of the inpu t SYSCLK. All output s pecificatio ns are measured from the midp oint of the rising edge of SYSCLK to the
midpoi nt of the s ig nal in q ues ti on. All outpu t tim in gs as sum e a pure ly res ist ive 50-Ω load (s ee Fi gu re 4). Input and
output tim ings are measu red at the pi n; time-o f-fligh t delays must be added for tra ce lengt hs, via s, and co nnecto rs
in the syste m .
2. The symbo logy u sed for t iming speci ficati ons he rein fol lows the pa ttern of t (signal)(state)(reference)(state) fo r inputs and
t(reference)(state)(signal)(state) for outputs. For exa mple, tIVKH symboliz es th e tim e inpu t sign als (I) reach the va lid s tate
(V) relativ e to t he SYSCL K refe renc e (K) g oin g to the h igh (H) st a te o r inp ut s etup tim e. And t KHOV symbolizes th e
time from SYSCLK(K) going high (H) unt il outputs (O) are va lid (V) or output valid time. Input hold tim e can be read
as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of
the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until
the output went invalid (OX).
3. tsysclk is the pe riod of the extern al clock (SYSCLK) i n ns . Th e nu mbers giv en i n th e t ab le must be mu lti pli ed b y th e
period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged
high before returning to high impedance as shown in Figure 6. The nominal precharge wid th for TS is 0.5 × tSYSCLK,
that is, l ess than the mini mum tSYSCLK period, to ensure that another master asserting TS on the follo wing cloc k will
not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid
time is tested for precharge.The high-impedance behavior is guaranteed by design.
5. Guaranteed by design and not tested.
6. Accordi ng to th e bus protoco l, ARTR Y can be dri ven by mul tiple b us ma ster s thro ugh the cloc k peri od imm ediat ely
following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any
master asserting it low in the first clock following AACK will then go to high impedance for one clock before
precharging it high during the second cycle after the assertion of AACK. The nominal prec ha rge width for AR TRY
is 1.0 tSYSCLK; that is, it should be high impedance as shown in Figure 6 before the first opportunity for another
master to assert ARTRY. Output va lid and output hol d timing i s te ste d fo r the signa l as se rted .The high-i mp eda nc e
behavior is guaranteed by design.
7. According t o th e MPX bus p rotocol , SHD0 a nd SHD1 can be driven by multiple bus masters beginning the cycle of
TS. T iming i s the sam e as AR TR Y, that is , the sig nal is h igh impedan ce for a fraction of a cy cle, then negated fo r up
to an en tire cycle (crossing a bu s cycle bo undary) befor e being three -stated ag ain. The n ominal precha rge widt h for
SHD0 and SHD1 is 1.0 tSYSCLK. The edges of the precharge vary depending on the programmed ratio of core to
bus (PLL configuratio ns).
8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These
param eters repres ent the inpu t setup and ho ld times fo r each samp le. These va lues are gua ranteed by d esign and
not tested. These inputs must remain stable after the second sample. See Figure 5 for sample timing.
Table 9. Processor Bus AC Timing Specifications 1 (continued)
At recommended operating conditions. See Table 4.
Parameter Symbol 2All Speed Grades Unit Notes
Min Max
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 19
Electrical and Thermal Characteristics
Figure 5 provides the mode select input timing diagram for the MPC7457.
Figure 5. Mode Input Timing Diagram
Figure 6 provides the input/output timing diagram for the MPC7457.
Figure 6. Input/Output Timing Diagram
HRESET
Mode Signals
VM = Midpoint Voltage (OVDD/2)
SYSCLK
1st sample 2nd sample
VM VM
SYSCLK
All Inputs
VM
VM = Midpoint Voltage (OVDD/2)
All Outpu t s tKHOX
VM
tKHDV
(Except TS,
ARTRY, SHD0, SHD1)
All Outpu t s
TS
ARTRY,
(Except TS,
ARTRY, SHD0, SHD1)
VM
t
KHOE
t
KHOZ
t
KHTSPZ
t
KHARPZ
t
KHARP
SHD1
SHD0,
tKHOV
tKHAV
tKHDX
tKHAX
tIXKH
tAXKH
tKHTSX
t
KHTSV
tKHTSV
t
KHARV
t
KHARX
tIVKH
tAVKH
tMVKH tMXKH
20 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Characteristi cs El ectrical and Thermal Characteristi cs
1.5.2.3 L3 Clock AC Specifications
The L3_CLK frequency is programmed by the L3 configuration register core-to-L3 divisor ratio. See
Table 18 for example core and L3 frequencies at various divisors. Table 10 provides the potential range of
L3_CLK output AC timing specifications as defined in Figure 7.
The maximum L3_CLK frequency is the core frequency divided by two. Given the high core frequencies
available in the MPC7457, however, most SRAM designs will be not be able to operate in this mode using
current technology and, as a result, will select a greater core-to-L3 divisor to provide a longer L3_CLK
period for read and write access to the L3 SRAMs. Therefore, the typical L3_CLK frequency shown in
Table 10 is consider ed to be the pr acti cal maximum in a typic al syst em. The maximum L3_CLK freq uency
for any appl i cat ion of the MPC7 457 wil l be a fun cti on of the AC timin gs of the MPC7457, the AC timing s
for the SRAM, bus loading, and pri nted-ci rcuit boar d trace length, and may be gr eater or le ss than the valu e
given i n Table 10. Note t hat SYSCLK i nput j itter and L3_CLK[0:1 ] outpu t ji tter are a lread y comp rehend ed
in the L3 bu s AC ti mi ng sp eci fi c at ion s a nd do n ot ne e d to b e se pa ra te ly ac c ou nte d for in an L3 A C ti m ing
analysis. Clock skews, where applicable, do need to be accounted for in an AC timing analysis.
Motorola is similarly limited by system constraints and cannot perform tests of the L3 interface on a
sockete d part on a functional tester at the maximum frequencie s of T able 10. Therefore, functional ope ration
and AC timing information are tested at core-to-L3 divisors which result in L3 frequencies at 250 MHz or
lower.
Table 10. L3_CLK Output AC Timing Specifications
At recommended operating conditions. See Table 4.
Parameter Symbol All Speed Grades Unit Notes
Minimum Typical Maximum
L3 clock frequency fL3_CLK — 200 — MHz 1
L3 clock cycle time tL3_CLK —5.0—ns1
L3 clock duty cycle tCHCL/tL3_CLK —50—%2
L3 clock output-to-output skew (L3_CL K0 to
L3_CLK1) tL3CSKW1 — — 100 ps 3
L3 clock output-to-output skew
(L3_CLK[0:1] to L3_ECHO_CLK[1,3]) tL3CSKW2 — — 100 ps 4
L3 clock jitter — — ± 75 ps 5
Notes:
1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependent. See Section 1.5.2.3,
“L3 Cloc k AC Specific ations,” for an ex planatio n that this ma ximum fre quency is not functio nally tes ted at speed by
Motorola. The minimum L3 clock frequency and period are fSYSCLK and tSYSCLK, respectively.
2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
3. Maximu m pos si ble skew betwe en L3_ CLK0 and L3_C LK1 . This p arameter is cri tic al to the address and con trol
signals which are common to both SRAM chips in the L3.
4. Maximum pos si bl e sk ew be tw ee n L3 _C LK0 and L3_ EC HO_ CLK 1 o r betwe en L3_CL K1 an d L3 _EC HO _CLK3 for
PB2 or Late Write SRAM. This parameter is critical to the read data signals because the processor uses the
feedback loop to latch data driven from the SRAM, each of which drives data based on L3_CLK0 or L3_CLK1.
5. Guaranteed by design and not tested. The input jitter on SYSCLK af fects L3 output clocks and the L3 address, dat a,
and control signals equally and, therefore, is already comprehended in the AC timing and does not have to be
consid ere d in the L3 tim in g ana ly si s. Th e clock-to -clo ck jit ter shown he re is unc ertainty in th e inte rna l clo ck peri od
caused by supply voltage noise or thermal effects. This is also comprehended in the AC timing specifications and
need not be cons ide r ed in the L3 tim ing analy sis.
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 21
Electrical and Thermal Characteristics
The L3_CLK timing diagram is shown in Figure 7.
Figure 7. L3_CLK_OUT Output Timing Diagram
1.5.2.4 L3 Bus AC Specifications
The MPC7457 L3 interface supports three different types of SRAM: source-synchronous, double data rate
(DDR) MSUG2 SRAM, Late Write SRAMs, and pipeline burst (PB2) SRAMs. Each requires a different
protocol on the L3 interface and a different routing of the L3 clock signals. The type of SRAM is
programmed in L3CR[22:23] and the MPC7457 then follows the appropriate protocol for that type. The
designer must connect and route the L3 signals appropriately for each type of SRAM. Following are some
observations about the L3 interface.
• The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7], and
L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched.
• For 1-Mbyte of SRAM, use L3_ADDR[16:0] (L3_ADDR[0] is LSB)
• For 2-Mbyte of SRAM, use L3_ADDR[17:0] (L3_ADDR[0] is LSB)
• For 4-Mbyte of SRAM, use L3_ADDR[18:0] (L3_ADDR[0] is LSB)
• No pull- up resistors are re quired for the L3 interface
• For high speed operations, L3 interface address and control signals should be a ‘T’ with minimal
stubs t o the t wo load s; dat a and clock si gnals shoul d be p oin t-to- point t o t heir singl e loa d. Figur e 8
shows the AC test load for the L3 interface.
Figure 8. AC Test Load for the L3 Interface
In general, if routing is short, delay-matched, and designed for incident wave reception and minimal
reflection, there is a high probability that the AC timing of the MPC7457 L3 interface will meet the
maximum frequency operation of appropriately chosen SRAMs. This is despite the pessimistic,
guard-ba nded AC spe cific ation s (see Tab le 12, Table 13, and Tabl e 14), the limita tions of func tiona l test ers
descri bed in Section 1.5.2.3, “L3 Clock AC Specificat ions,” and the uncertainty of clocks and signals which
inevitably make wors t-cas e critical path timing analysis pessimistic.
L3_CLK0 VM
tL3CR tL3CF
VM
VMVM
L3_CLK1
VM
VM
tL3_CLK
tCHCL
VM
L3_ECHO_CLK1
L3_ECHO_CLK3 VMVM VM VM
VMVM VM VM
For PB2 or Late Write:
tL3CSKW1
tL3CSKW2
tL3CSKW2
Output Z0 = 50 ΩGVDD/2
RL = 50 Ω
22 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Characteristi cs El ectrical and Thermal Characteristi cs
More specifically, certain signals within groups should be delay-matched with others in the same group
while intergroup routing is less critical. Only the address and control signals are common to both SRAMs
and additional timing margin is available for these signals. The double-clocked data signals are grouped
with individual clocks as shown in Figure 9 or Figure 11, depending on the type of SRAM. For example,
for the MSUG2 DDR SRAM (see Figure 9); L3DATA[0:31], L3DP[0:3], and L3_CLK[0] form a closely
coupled group of outputs from the MPC7457; while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0]
form a closely coupled group of inputs.
The MPC7450 RISC Micr oprocessor Family User’s Manual re fers to logica l setti ngs call ed ‘sampl e points ’
used in the synchronization of reads from the receive FIFO. The computation of the correct value for this
setti ng is sys tem-dependent and is describ ed in the MPC7450 RISC Micr o pr oce ssor Family User’s Manual.
Three specifications are used in this calculation and are given in Table 11. It is essential that all three
specifications are included in the calculations to determine the sample points, as incorrect settings can result
in error s and unpred ictable behavior. For more information, see the MPC7450 RISC Micr opr ocessor Family
User ’s Manual.
1.5.2.4.1 Effects of L3OHCR Settings on L3 Bus AC Specifications
The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control Register (L3OCHR).
Each field controls the timing for a group of signals. The AC timing specifications presented herein represent
the AC timin g when the regi ster cont ains the de fault value of 0x0000_0 000. Incrementi ng a field de lays the
associa te d signal s, incr easin g the outpu t vali d time and hold ti me of the af f ecte d signal s. In the spec ial cas e
of delaying an L3_CLK signal, the net effect is to decrease the output valid and output hold times of all
signals being latched relative to that clock signal. The amount of delay added is summarized in Table 12.
Note that these settings affect output timing parameters only and do not impact input timing parameters of
the L3 bus in any way.
Table 11. Sample Points Calculation Parameters
Parameter Symbol Max Unit Notes
Delay from processor clock to internal_L3_CLK tAC 3/4 tL3_CLK 1
Delay from internal_L3_CLK to L3_CLK[n] out put pin s tCO 3ns2
Delay from L3_ECHO_CLK[n] to receive latch tECI 3ns3
Notes:
1. This specification describes a logical offset between the internal clock edge used to launch the L3 address and
control signals (this cloc k edge i s phase-a ligned with the proces sor clock edge) and th e inter nal cloc k edge us ed to
launch the L3_CLK[ n] si gn als . Wi th p roper board rout ing, this offse t en sure s that the L3_CLK[ n] ed ge wi ll arriv e a t
the SRAM within a valid address window and provide adequate setup and hold time. This offset is reflected in the
L3 bus interface AC timing specifications, but must also be separately accounted for in the calculation of sample
points and, thus, is specified here.
2. This s pecificatio n is the de lay from a rising or fa lling edge on the intern al_L3_CLK signal to t he correspon ding rising
or falling edge at the L3CLK[n] pin s.
3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to data valid and ready to be
sampled from the FIFO.
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 23
Electrical and Thermal Characteristics
1.5.2.4.2 L3 Bus AC Specifications for DDR MSUG2 SRAMs
When using DDR MSUG2 SRAMs at th e L3 in terfa ce, th e part s shou ld be conne cted a s shown in Fig ure 9.
Outputs from the MPC7457 are actually launched on the edges of an internal clock phase-aligned to
SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock
output with 90° phase delay, so outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid
Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing
At recommended operating conditions. See Table 4.
Field na me1Affected
Signals Value
Output Valid Time Output Hold Time Unit Note
s
Parameter
Symbol 2Change 3Parameter
Symbol 2 Change 3
L3AOH L3_ADDR[18:0],
L3_CNTL[0:1] 0b00 tL3CHOV 0t
L3CHOX 0ps4
0b01 +50 +50
0b10 +100 +100
0b11 +150 +150
L3CLKn_OH All signals
latched by
SRAM
connected to
L3_CLKn
0b000 tL3CHOV,
tL3CHDV,
tL3CLDV
0t
L3CHOX,
tL3CHDX,
tL3CLDX,
04
0b001 – 50 – 50 5
0b010 – 100 – 100 5
0b011 – 150 – 150 5
0b100 – 200 – 200 5
0b101 – 250 – 250 5
0b110 – 300 – 300 5
0b111 – 350 – 350 5
L3DOHnL3_DATA[n:n+7]
, L3_DP[n/8] 0b000 tL3CHDV,
tL3CLDV
0t
L3CHDX,
tL3CLDX,
04
0b001 + 50 + 50
0b010 + 100 + 100
0b011 + 150 + 150
0b100 + 200 + 200
0b101 + 250 + 250
0b111 + 300 + 300
0b111 + 350 + 350
Notes:
1. See the MPC7450 RISC Microprocessor Family User’s Manual for specific information regarding L3OHCR.
2. See Table 13 and Table 14 for more information.
3. Approximate delay verified by simulation; not tested or characterized
4. Default value
5. Incr easing val ues of L3CLKn_O H delay th e L3_CLKn si gnal, eff ectively de creasing the output valid and output hol d
times of all signals latched relative to that clock signal by the SRAM; see Figure 9 and Figure 11.
24 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Characteristi cs El ectrical and Thermal Characteristi cs
times are typically negative when referenced to L3_CLKn because the data is launched one-quarter period
before L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address, control,
data, and L3_CLKn signals have propagated across the printed-wiring board.
Inputs t o the MPC7457 are source- synchronous wit h the CQ clock generat ed by the DDR MSUG2 SRAMs.
These CQ clocks are received on the L3_ECHO_CLKn inputs of the MPC7457. An internal circuit delays
the inc oming L3_ECHO_CLKn sign al such tha t it is positione d within t he valid da ta window at the inter nal
receiving latches. This delayed clock is used to capture the data into these latches which comprise the
receive FIFO. This clock is asynchronous to all other processor clocks. This latched data is subsequently
read out of the FIFO synchronously to the processor clock. The time between writing and reading the data
is set by the using the sample point settings defined in t he L3CR reg ister.
Tabl e 13 provides the L3 bus interf ace AC timing specific ations for the configurati on as shown in Figure 9,
assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8.
Table 13. L3 Bus Interface AC T iming Specifications for MSUG2
At recommended operating conditions. See Table 4.
Parameter Symbol All Speed Grades Unit Notes
Min Max
L3_CLK rise and fall time tL3CR, tL3CF —0.75ns1
Setup times: Data and parity tL3DVEH, tL3DVEL – 0.35 — ns 2, 3, 4, 9
Input hold times: Data and parity tL3DXEH, tL3DXEL 2.1 — ns 2, 4, 9
Valid times: Data and parity tL3CHDV, tL3CLDV —(– t
L3CLK/4) +
0.60 ns 5, 6, 7, 8
Valid times: All other outputs tL3CHOV —(t
L3CLK/4) +
0.65 ns 5, 7, 8
Output hol d time s: D at a and pa rity tL3CHDX, tL3CLDX, (tL3CLK/4) –
0.60 — ns 5, 6, 7, 8
Output hol d time s: All othe r outpu t s tL3CHOX (tL3CLK/4) –
0.50 —ns5, 7, 8
L3_CLK to high impedance: Data and
parity tL3CLDZ —(– t
L3CLK/4) +
0.60 ns
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 25
Electrical and Thermal Characteristics
L3_CLK to high impedance: All other
outputs tL3CHOZ —(t
L3CLK/4) +
0.65 ns
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage
of the rising or falling edge of the input L3_ECHO_CLKn (see Figure 10). Input tim in gs are me asu red at the pins.
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10. For consistency
with other input setup time specifications, this will be treated as negative input setup time.
4. tL3_CLK/4 is one-fourth the p eriod of L3_CLK n. This parameter indicates that the MPC7457 can latch an input signal
that is v ali d fo r onl y a sho rt time befo re an d a s ho rt tim e a fter the mid poi nt b etween the ris in g an d fa lli ng (o r fal lin g
and rising) edges of L3_ECHO_CLKn at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or f or DDR write data, a lso the falling)
edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output
timings assume a purely r esistive 50-Ω load (see Figure 8).
6. For DDR, the output dat a will typically lead the edge of L3_CLKn as sh own in Figu re 10. For co nsistency with other
output valid time specifications, this will be treated as negative output valid time.
7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid
and output hold times such that the specified output signal will be valid for approximately one L3_CLK period
start ing thre e-fourth s of a cl ock b efore th e edge on whic h the SR AM wil l sampl e it an d endi ng one -fou rth of a clock
period after the edge it will be sampled.
8. Assumes default value of L3OHCR. See Section 1.5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC
Specifications” for more information.
9. L3 input setup and hold times are actually functions of L3 clock frequency in a manner similar to L3 output timing
characteristics. The timing parameter values shown are based upon characterization at 200 MHz. Motorola is
currentl y studying these p arameters in ord er to provide the values in a format that accurately ref lects this f requency
dependence.
Table 13. L3 Bus Interface AC Timing Specifications for MSUG2 (continue d)
At recommended operating conditions. See Table 4.
Parameter Symbol All Speed Grades Unit Notes
Min Max
26 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Characteristi cs El ectrical and Thermal Characteristi cs
Figure 9 shows the typical connection diagram for the MPC7457 interfaced to MSUG2 DDR SRAMs.
Figure 9. Typical Source Synchronous 4-Mbyte L3 Cache DDR Interface
{L3DATA[0:15],
{L3DATA[16:31],
{L3_DATA[32:47],
L3ADDR[18:0]
L3_CNTL[0]
L3_CLK[0]
L3_CLK[1]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3ECHO_CLK[2]
L3_ECHO_CLK[3]
{L3DATA[48:63],
L3DP[0:1]}
L3DP[2:3]}
L3DP[4:5]}
L3DP[6:7]}
CQ
SA[18:0]
CK
B1
B2
SRAM 0
SRAM 1
CQ
D[0:17]
D[18:35]
CQ
SA[18:0]
CK
B1
B2
CQ
D[0:17]
D[18:35]
L3_CNTL[1]
NC
NC
GND
GND
GND
NC
NC
GND
GND
GND
MPC7457
Denotes
Receive (SRAM
to MPC7457)
Aligned Signals
Denotes
Transmit
(MPC7457 to
SRAM)
Aligned Signals
GVDD/2 1
GVDD/2 1
CQ
CK
B3
G
CQ
LBO
CQ
CK
B3
G
CQ
LBO
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 27
Electrical and Thermal Characteristics
Figure 10 shows the L3 bus timing diagrams for the MPC7457 interfaced to MSUG2 SRAMs.
Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
1.5.2.4.3 L3 Bus AC Specifications for PB2 and Late W rite SRAMs
When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as shown in
Figure 11. These SRAMs ar e sy nchr ono us to the MPC7457; o ne L3_CLK n signal is output to each SRAM
to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed
L3_CLKn signa l i t r ece ive d. The MPC74 57 ne eds a copy of t ha t de la yed clock whi ch l aunc hed the SRAM
read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and
L3_ECHO_CLK3 must be routed halfway to the SRAMs and returned to the MPC7457 inputs
L3_ECHO_CLK0 and L3_ ECHO_CLK2, respectively. Thus, L3_ECHO_CLK0 and L3_ ECHO_CLK2 are
phase-aligned with the input clock received at the SRAMs. The MPC7457 will latch the incoming data on
the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.
Table 14 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11,
assuming the timing relationships of Figure 12 and the loading of Figure 8.
L3_ECHO_CLK[0,1,2,3]
L3 Data and Data
VM
VM = Midpoint Voltage (GVDD/2)
Parity Inputs
L3_CLK[0,1]
ADDR, L3CNTL
VM
tL3CHOV tL3CHOX
VM
L3DATA WRITE
tL3CHOZ
VM
VM VM VM
tL3CHDV
tL3CHDX
VM VMVM
Outputs
Inputs
tL3CLDV
tL3CLDX
tL3CLDZ
tL3DVEH
tL3DXEL
tL3DVEL
tL3DXEH
Note: tL3DVEH and tL3DVEL as drawn here are negative numbers, that is, input setup time is
time after the clock edge.
Note: tL3CHDV and tL3CLDV as drawn here will be negative numbers, that is, output valid time will be
time before the clock edge.
28 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Characteristi cs El ectrical and Thermal Characteristi cs
Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
Parameter Symbol All Speed Grades Unit Notes
Min Max
L3_CLK rise and fall time tL3CR, tL3CF —0.75ns1, 2
Setup times: Data and parity tL3DVEH 0.1 — ns 2, 3
Input hold times: Data and parity tL3DXEH — 0.7 ns 2, 3
Valid times: Data and parity tL3CHDV — 2.5 ns 2, 4, 5, 6
Valid times: All other outputs tL3CHOV — 1.8 ns 5, 6
Output hol d time s: D at a and pa rity tL3CHDX 1.4 — ns 2, 4, 5, 6
Output hol d time s: All othe r outpu t s tL3CHOX 1.0 — ns 2, 5, 6
L3_CLK to high impedance: Data and parity tL3CHDZ —3.0ns2
L3_CLK to high impedance: All other outputs tL3CHOZ —3.0ns2
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. Timing behavior and characterization are currently being evaluated.
3. All inpu t specif ications are measure d from the midpoi nt of the s ignal i n question t o the mid point vo ltage of the rising
edge of the input L3_ECHO_CL K n (see Figure 10). Input timings are measured at the pins.
4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of
the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-Ω load (see Figure 10).
5. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid
and output hold times such that the specified output signal will be valid for approximately one L3_CLK period
start ing thre e-fourth s of a cl ock b efore th e edge on whic h the SR AM wil l sampl e it an d endi ng one -fou rth of a clock
period after the edge it will be sampled.
6. Assumes default value of L3OHCR. See Section 1.5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC
Specifications” for more information.
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 29
Electrical and Thermal Characteristics
Figure 11 shows t he t ypi cal conne ct ion diagra m for the MPC7457 int er fa ced to PB2 SRAMs or Late Write
SRAMs.
Figure 11. Typical Synchronous 1-MByte L3 Cache Late Write or PB2 Interf ace
L3_ADDR[16:0]
L3_CNTL[0] SA[16:0]
K
K
SS
SW
ZZ
G
SRAM 0
DQ[0:17]
DQ[18:36]
L3_CNTL[1]
GVDD/2 1
GND
GND
SRAM 1
GVDD/2 1
GND
GND
{L3_DATA[0:15],
{L3_DATA[16:31],
{L3_DATA[32:47],
L3_CLK[0]
L3_CLK[1]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[2]
{L3_DATA[48:63],
L3_DP[0:1]}
L3_DP[2:3]}
L3_DP[4:5]}
L3_DP[6:7]}
Denotes
Receive (SRAM
to MPC7457)
Aligned Signal s
MPC7457
Denotes
Transmit
(M PC7457 to
SRAM)
Aligned Signal s
L3_ECHO_CLK[3]
SA[16:0]
K
K
SS
SW
ZZ
G
DQ[0:17]
DQ[18:36]
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
30 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Characteristi cs El ectrical and Thermal Characteristi cs
Figure 12 shows the L3 bus timing diagrams for the MPC7457 interfaced to PB2 or Late Write SRAMs.
Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs
1.5.2.5 IEEE 11 49.1 AC Timing Specifications
Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14 through
Figure 17.
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions. See Table 4.
Parameter Symbol Min Max Unit Notes
TCK frequen cy of operation fTCLK 033.3MHz
TCK cycl e time tTCLK 30 — ns
TCK clock pulse width measured at 1.4 V tJHJL 15 — ns
TCK rise and fall times tJR and tJF 02ns
TRST assert time tTRST 25 — ns 2
Input setup times:
Boundary-scan data
TMS, TDI tDVJH
tIVJH
4
0—
—
ns 3
Input hold times:
Boundary-scan data
TMS, TDI tDXJH
tIXJH
20
25 —
—
ns 3
Valid times:
Boundary-scan data
TDO tJLDV
tJLOV
4
420
25
ns 4
L3_ECHO_CLK[0,2]
L3 Data and Data
VM
VM = Midpoint Voltage (GVDD/2)
tL3DVEH
tL3DXEH
Parity Inputs
L3_CLK[0,1]
ADDR, L3_CNTL
VM
tL3CHOV tL3CHOX
VM
L3DATA WRITE
tL3CHDZ
Outputs
Inputs
L3_ECHO_CLK[1,3]
tL3CHDV tL3CHDX
tL3CHOZ
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 31
Electrical and Thermal Characteristics
Figure 13 provides the AC test load for TDO and the boundary-scan outputs of the MPC7457.
Figure 13. Alternate AC Test Load for the JTAG Interface
Figure 14 provides the JTAG clock input timing diagram.
Figure 14. JTAG Clock Input Timing Diagram
Figure 15 provides the TRST timing diagram.
Figure 15. TRST Timing Diagram
Output hol d time s:
Boundary-scan data
TDO tJLDX
tJLOX
30
30 —
—
ns 4
TCK to output high impedance:
Boundary-scan data
TDO tJLDZ
tJLOZ
3
319
9
ns 4, 5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load
(see Figure 13). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)
At recommended operating conditions. See Table 4.
Parameter Symbol Min Max Unit Notes
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
VMVMVM
VM = Midpoint Voltage (OVDD/2)
tTCLK
tJR tJF
tJHJL
TCLK
TRST tTRST
VM = Midpoint Voltage (OVDD/2)
VM VM
32 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Characteristi cs El ectrical and Thermal Characteristi cs
Figure 16 provides the boundary-scan timing diagram.
Figure 16. Boundary-Scan Timing Diagram
Figure 17 provides the test access port timing diagram.
Figure 17. Test Access Port Timing Diagram
VMTCK
Boundary
Boundary
Boundary
Data Outputs
Data Inputs
Data Outputs VM = Midpoint Voltage (OVDD/2)
tDXJH
tDVJH
tJLDV
tJLDZ
Input
Data Valid
Output Data Valid
Output Data Valid
tJLDX
VM
VM
TCK
TDI, TMS
TDO Output Data Valid
VM = Midpoint Voltage (OVDD/2)
tIXJH
tIVJH
tJLOV
tJLOZ
Input
Data Valid
TDO Output Data Valid
tJLOX
VM
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 33
Pin Assignments
1.6 Pin Ass ignments
Figure 18 (Part A) shows the pin out of the MPC7447, 360 CBGA package as vi ewed fr om the to p surf ace.
Part B shows the side profile of the CBGA package to indicate the direction of the top surface view.
Figure 18. Pinout of the MPC7447, 360 CBGA Package as Viewed from the Top Surface
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1234 5678 910111213141516
Not to Scale
17 18 19
U
V
W
Part A
View
Part B
Die
Substrate Assembly
Encapsulant
34 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Pin Assignments Pin Assignments
Figure 19 (Part A) shows the pin out of the MPC7457, 483 CBGA package as vi ewed fr om the to p surf ace.
Part B shows the side profile of the CBGA package to indicate the direction of the top surface view.
Figure 19. Pinout of the MPC7457, 483 CBGA Package as Viewed from the Top Surface
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1234 5678 910111213141516
Not to Scale
17 18 19
U
V
W
20 21 22
Y
AA
AB
Part A
View
Part B
Die
Substrate Assembly
Encapsulant
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 35
Pinout Listings
1.7 Pinout Listings
Table 16 provides the pinout listing for the MPC7447, 360 CBGA package. Table 17 provides the pinout
listing for the MPC7457, 483 CBGA package.
NOTE
This pinout is not compatible with the MPC750, MPC7400, or MPC7410
360 BGA package.
Table 16. Pinout Listing for the MPC7447, 360 CBGA Package
Signal Name Pin Number Active I/O I/F Select 1Notes
A[0:35] E1 1, H1, C11, G3, F10, L2, D11, D1, C10 ,
G2, D12, L3, G4, T2, F4, V1, J4, R2, K5,
W2, J2, K4, N4, J3, M5, P5, N3, T1, V2,
U1, N5, W1, B12, C4, G10, B11
High I/O BVSEL 2
AACK R1 Low Input BVSEL
AP[0:4] C1, E3, H6, F5, G7 High I/O BVSEL
ARTRY N2 Low I/O BVSEL 3
AVDD A8 — Input N/A
BG M1 Low Input BVSEL
BMODE0 G9 Low Input BVSEL 4
BMODE1 F8 Low Input BVSEL 5
BR D2 Low Output BVSEL
BVSEL B7 High Input BVSEL 1, 6
CI J1 Low Output BVSEL 3
CKSTP_IN A3 Low Input BVSEL
CKSTP_OUT B1 Low Output BVSEL
CLK_OUT H2 High Output BVSEL
D[0:63] R15, W15, T14, V16, W16, T15, U15, P14,
V13, W13, T13, P13, U14, W14, R12, T12,
W12, V12, N11, N10, R11, U11, W11,
T11, R10, N9, P10, U10, R9, W10, U9,
V9, W5, U6, T5, U5, W7, R6, P7, V6, P17,
R19, V18, R18, V19, T19, U19, W19, U18,
W17, W18, T16, T18, T17, W3, V17, U4,
U8, U7, R7, P6, R8, W8, T8
High I/O BVSEL
DBG M2 Low Input BVSEL
DP[0:7] T3, W4, T4, W9, M6, V3, N8, W6 High I/O BVSEL
DRDY R3 Low Output BVSEL 7
DTI[0:3] G1, K1, P1, N1 High Input BVSEL 8
EXT_QUAL A11 High Input BVSEL 9
GBL E2 Low I/O BVSEL
36 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Pinout Listings Pinout Listings
GND B5, C3, D6, D13, E17, F3, G17, H4, H7,
H9, H11, H13, J6, J8, J10, J12, K7, K3,
K9, K11, K13, L6, L8, L10, L12, M4, M7,
M9, M11 , M13, N7, P3, P9, P12, R 5, R14,
R17, T7, T1 0, U3, U13, U17, V5, V8, V1 1,
V15
—— N/A
HIT B2 Low Output BVSEL 7
HRESET D8 Low Input BVSEL
INT D4 Low Input BVSEL
L1_TSTCLK G8 High Input BVSEL 9
L2_TSTCLK B3 High Input BVSEL 10
No Connect A6, A13, A14, A15, A16, A17, A18, A19,
B13, B14, B15, B16, B17, B18, B19, C13,
C14, C15, C16, C17, C18, C19, D14, D15,
D16, D17, D18, D19, E1 2, E13, E14, E15,
E16, E19, F12, F13, F14, F15, F16, F17,
F18, F19, G11, G12, G13, G14, G15,
G16, G19, H14, H15, H16, H17, H18,
H19, J14, J15, J16, J17, J18, J19, K15,
K16, K17, K18, K19, L14, L15, L16, L17,
L18, L19, M14, M15, M16, M17, M18,
M19, N12, N13, N14, N15, N16, N17,
N18, N19, P15, P16, P18, P19
—— — 11
LSSD_MODE E8 Low Input BVSEL 6, 12
MCP C9 Low Input BVSEL
OVDD B4, C2, C12, D5, E18, F2, G18, H3, J5,
K2, L5, M3, N6, P2, P8, P11, R4, R13,
R16, T6, T9, U2, U12, U16, V4, V7, V10,
V14
—— N/A
PLL_CFG[0:4] B8, C8, C7, D7, A7 High Input BVSEL
PMON_IN D9 Low Input BVSEL 13
PMON_OUT A9 Low Output BVSEL
QACK G5 Low Input BVSEL
QREQ P4 Low Output BVSEL
SHD[0:1] E4, H5 Low I/O BVSEL 3
SMI F9 Low Input BVSEL
SRESET A2 Low Input BVSEL
SYSCLK A10 — Input BVSEL
TA K6 Low Input BVSEL
TBEN E1 High Input BVSEL
TBST F11 Low Output BVSEL
Table 16. Pinout Listing for the MPC7447, 360 CBGA Package (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 37
Pinout Listings
TCK C6 High Input BVSEL
TDI B9 High Input BVSEL 6
TDO A4 High Output BVSEL
TEA L1 Low Input BVSEL
TEST[0:3] A12, B6, B10, E10 — Input BVSEL 12
TEST[4] D10 — Input BVSEL 9
TMS F1 High Input BVSEL 6
TRST A5 Low Input BVSEL 6, 14
TS L4 Low I/O BVSEL 3
TSIZ[0:2] G6, F7, E7 High Output BVSEL
TT[0:4] E5, E6, F6, E9, C5 High I/O BVSEL
WT D3 Low Output BVSEL 3
VDD H8, H10, H12, J7, J9, J11, J13, K8, K10,
K12, K14, L7, L9, L11, L13, M8, M10, M 12 —— N/A
Notes:
1. OVDD suppli es power to the process or bus, JTAG, and al l control s ignals; and V DD supplies powe r to the proce ssor
core and the PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to either GND
(select s 1.8 V) or to HRESET (selec ts 2.5 V). If used, the pul l-down resistor shoul d be less than 250 Ω. For actual
recommended value of Vin or supply voltages see Table 4.
2. Unused address pins must be pulled down to GND.
3. These p ins requi re we ak pul l-up re sisto rs (for e xample, 4.7 kΩ) to maint ain the co ntrol s ignal s in t he neg ated s tate
after they have been actively negated and released by the MPC7447 and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at
HRESET going high.
5. This signal must be negated during reset, by pull up to OVDD or negation by ¬HRESET (inverse of HRESET), to
ensure proper operation.
6. Internal pull up on die.
7. Ignored in 60x bus mode.
8. These signals must be pulled down to GND if unused, or if the MPC7447 is in 60x bus mode.
9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect
performance.
11.These signals are for factory use only and must be left unconnected for normal machine operation.
12.These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
13.This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
14.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper
operation.
Table 16. Pinout Listing for the MPC7447, 360 CBGA Package (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
38 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Pinout Listings Pinout Listings
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package
Signal Name Pin Number Active I/O I/F Select 1Notes
A[0:35] E10, N4, E8, N5, C8, R2, A7, M2, A6, M1,
A10, U2, N2, P8, M8, W4, N6, U6, R5, Y4, P1,
P4, R6, M7, N7, AA3, U4, W2, W1, W3, V4,
AA1, D10, J4, G10, D9
High I/O BVSEL 2
AACK U1 Low Input BVSEL
AP[0:4] L5, L6, J1, H2, G5 High I/O BVSEL
ARTRY T2 Low I/O BVSEL 3
AVDD B2 — Input N/A
BG R3 Low Input BVSEL
BMODE0 C6 Low Input BVSEL 4
BMODE1 C4 Low Input BVSEL 5
BR K1 Low Output BVSEL
BVSEL G6 High Input N/A 6, 7
CI R1 Low Output BVSEL 3
CKSTP_IN F3 Low Input BVSEL
CKSTP_OUT K6 Low Output BVSEL
CLK_OUT N1 High Output BVSEL
D[0:63] AB15, T14, R14, AB13, V14, U14, AB14, W16,
AA11, Y11, U12, W13, Y14, U13, T12, W12,
AB12, R12, AA13, AB1 1 , Y12, V11, T11, R11,
W10, T10, W11, V10, R 10, U10, AA 10, U9,
V7, T8, AB4, Y6, AB7, AA6, Y8, AA7, W8,
AB10, AA16, AB16, AB17, Y18, AB18, Y16,
AA18, W14, R13, W15, AA14, V16, W6, AA12,
V6, AB9, AB6, R7, R9, AA9, AB8, W9
High I/O BVSEL
DBG V1 Low Input BVSEL
DP[0:7] AA2, AB3, AB2, AA8, R8, W5, U8, AB5 High I/O BVSEL
DRDY T6 Low Output BVSEL 8
DTI[0:3]) P2, T5, U3, P6 High Input BVSEL 9
EXT_QUAL B9 High Input BVSEL 10
GBL M4 Low I/O BVSEL
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 39
Pinout Listings
GND A22, B1, B5, B12, B14, B16, B18, B20, C3,
C9, C21, D7, D13, D15, D17, D19, E2, E5,
E21, F10, F12, F14, F16, F19, G4, G7, G17,
G21, H 13, H15, H19, H5, J 3, J10, J12, J14,
J17, J21, K5, K9, K11, K13, K15, K19, L10,
L12, L14, L17, L21, M3, M6, M9, M11, M13,
M19, N10, N 12, N14, N 1 7, N2 1, P3 , P9, P11,
P13, P15, P19, R 17, R21, T1 3, T15, T19 , T4,
T7, T9, U17 , U21, V2, V5, V8, V12, V15 , V19,
W7, W17, W21 , Y3 , Y9, Y13 , Y15 , Y20 , AA5 ,
AA17, AB1, AB22
—— N/A
GVDD B13, B15, B17, B19, B21, D12, D14, D16,
D18, D21, E19, F13, F15, F17, F21, G19,
H12, H14, H17, H 21, J1 9, K17, K21, L19,
M17, M21, N19, P17, P21, R15, R19, T17,
T21, U19, V17, V21, W19, Y21
—— N/A 11
HIT K2 Low Output BVSEL 8
HRESET A3 Low Input BVSEL
INT J6 Low Input BVSEL
L1_TSTCLK H4 High Input BVSEL 10
L2_TSTCLK J2 High Input BVSEL 12
L3VSEL A4 High Input N/A 6, 7
L3ADDR[18:0] H11, F20, J16, E22, H18, G20, F22, G22,
H20, K1 6, J18, H22, J20, J22, K18, K20, L16 ,
K22, L18
High Output L3VSEL
L3_CLK[0:1] V22, C17 High Output L3VSEL
L3_CNTL[0:1] L20, L22 Low Outpu t L3VSEL
L3DATA[0:63] AA19, AB20, U16, W18, AA20, AB21, AA21,
T16, W20, U18, Y22, R 16, V20, W22, T1 8,
U20, N18, N20, N 16, N22, M16, M18 , M20,
M22, R18, T20, U22, T22, R20, P18, R22,
M15, G18, D22, E20, H16, C22, F18, D20,
B22, G16, A21, G15, E17, A20, C19, C18,
A19, A18, G14, E15, C16, A17, A16, C15,
G13, C 14, A14, E1 3, C13, G12, A13, E12,
C12
High I/O L3VSEL
L3DP[0:7] AB19, AA22, P22, P16, C20, E16, A15, A12 High I/O L3VSEL
L3_ECHO_CLK[0,2] V18, E18 High Input L3VSEL
L3_ECHO_CLK[1,3] P20, E14 HIgh I/O L3VSEL
LSSD_MODE F6 Low Input BVSEL 7, 13
MCP B8 Low Input BVSEL
No Connect A8, A11, B6, B11, C11, D 11, D3, D5 , E11, E7,
F2, F11, G2, H9 —— N/A 14
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
40 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Pinout Listings Pinout Listings
OVDD B3, C5, C7, C10, D2, E3, E9 , F5, G3, G9, H7,
J5, K3, L7, M5, N3, P7, R4, T3, U5, U7, U11,
U15, V3, V9, V13, Y2, Y5, Y7, Y10, Y17, Y19,
AA4, AA15
—— N/A
PLL_CFG[0:4] A2, F7, C2, D4, H8 High Input BVSEL
PMON_IN E6 Low Input BVSEL 15
PMON_OUT B4 Low Output BVSEL
QACK K7 Low Input BVSEL
QREQ Y1 Low Output BVSEL
SHD[0:1] L4, L8 Low I/O BVSEL 3
SMI G8 Low Input BVSEL
SRESET G1 Low Input BVSEL
SYSCLK D6 — Input BVSEL
TA N8 Low Input BVSEL
TBEN L3 High Input BVSEL
TBST B7 Low Output BVSEL
TCK J7 High Input BVSEL
TDI E4 High Input BVSEL 7
TDO H1 High Output BVSEL
TEA T1 Low Input BVSEL
TEST[0:5] B10, H6, H10, D8, F9, F8 — Input BVSEL 13
TEST[6] A9 — Input BVSEL 10
TMS K4 High Input BVSEL 7
TRST C1 Low Input BVSEL 7, 16
TS P5 Low I/O BVSEL 3
TSIZ[0:2] L1,H3,D1 High Output BVSEL
TT[0:4] F1, F4, K8, A5, E1 High I/O BVSEL
WT L2 Low Output BVSEL 3
VDD J9, J11, J13, J15, K 10, K12, K14, L9, L11,
L13, L15, M10, M12, M14, N9, N1 1, N13, N15,
P10, P12, P14
—— N/A
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 41
Package Description
1.8 Package Description
The foll owing sections pr ovide the package parameters and mecha nical dimensions for the CBGA pac kage.
1.8.1 Package Parameters for the MPC7447, 360 CBGA
The package parameters are as provided in the following list. The package type is 25 × 25 mm , 360-l ead
ceramic ball grid array (CBGA).
Package outline 25 × 25 mm
Interconnects 360 (19 × 19 ball array – 1)
Pitch 1.27 mm (50 mil)
Minimum module height 2.72 mm
Maximum module height 3.24 mm
Ball diameter 0.89 mm (35 mil)
VDD_SE NSE[0:1 ] G11, J8 — — N/A 17
Notes:
1. OVDD supplies power to the processor bus, JT AG, and all control signals except the L3 cache controls (L3CTL[0:1]);
GVDD supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3],
and L3_CLK[0:1]) and the L3 control signals L3_CNTL[0:1]; and VDD supplies power to the processor core and
the PLL (after filtering to become AVDD). For actual recommended value of Vin or supp ly voltages, see Table 4.
2. Unused address pins must be pulled down to GND.
3. These pi ns require w eak pull-up resistors (for exam ple, 4 .7 kΩ) to main tai n the co ntrol si gnals in the n egated st ate
after they have been actively negated and released by the MPC7457 and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at
HRESET going high.
5. This signal must be negated during reset, by pull up to OVDD or negation by ¬HRESET (inverse of HRESET), to
ensure proper operation.
6. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8 V) or to HRESET (selects
2.5 V). To program the L3 interface, conn ect L3VSEL to either GND (selects 1.8 V) or to HRESET (select s 2.5 V).
If used, pull-down resistors should be less than 250 Ω.
7. Internal pull up on die.
8. Ignored in 60x bus mode.
9. These signals must be pulled down to GND if unused or if the MPC7457 is in 60x bus mode.
10.These input signals for factory use only and must be pulled down to GND for normal machine operation.
11.Power must be supplied to GVDD, even when the L3 interface is disabled or unused.
12.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect
performance.
13.These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
14.These signals are for factory use only and must be left unconnected for normal machine operation.
15.This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
16.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper
operation.
17.These pins are internally connected to VDD. They are intended to allow an external device to detect the core voltage
level present at the processor core. If unused, they must be connected directly to VDD or left unconnected.
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
42 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Package Description Package Description
1.8.2 Mechanical Dimensions for the MPC7447, 360 CBGA
Figure 20 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447, 360
CBGA package.
Figure 20. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447,
360 CBGA Package
NOTES:
1. DIMENSIONING AND
TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN
MILLIMETERS.
3. TOP SID E A1 CORNER
INDEX IS A METALIZED
FEATURE WITH VARIOUS
SHAPES. BOTTOM SIDE A1
CORNER IS DESIGNATED
WITH A BALL MISSING
FROM THE ARRAY.
0.2
C
A
360X
D
2X
A1 CORNER
E
e
0.2
2X
C
B
12345678910111213141516
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
B0.3 A
0.15
b
A
0.15 A
171819
U
W
V
Millimeters
DIM MIN MAX
A 2.72 3.20
A1 0.80 1.00
A2 1.10 1.30
A3 — 0.6
b 0.82 0.93
D 25.00 BSC
D1 — 11.3
D2 8.0 —
D3 — 6.5
D4 10.9 11.1
e 1.27 BSC
E 25.00 BSC
E1 — 11.3
E2 8.0 —
E3 — 6.5
E4 9.55 9.75
Capacitor Region
1
D3
E2
E1
AA1
A2
A3
E4
D4
E3
D1
D2
0.35 A
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 43
Package Description
1.8.3 Substrate Capacitors for the MPC7447, 360 CBGA
Figure 21 shows the connectivity of the substrate capacitor pads for the MPC7447, 360 CBGA. All
capacito rs are 100 nF.
Figure 21. Substrate Byp ass Capacitors for the MPC7447, 360 CBGA
Capacitor Pad Number
-1 -2
C1 GND VDD
C2 GND VDD
C3 GND OVDD
C4 GND VDD
C5 GND VDD
C6 GND VDD
C7 GND VDD
C8 GND VDD
C9 GND OVDD
C10 GND VDD
C11 GND VDD
C12 GND VDD
C13 GND VDD
C14 GND VDD
C15 GND VDD
C16 GND OVDD
C17 GND VDD
C18 GND OVDD
C19 GND VDD
C20 GND VDD
C21 GND OVDD
C22 GND VDD
C23 GND VDD
C24 GND VDD
1
C1-2
C1-1 C2-1 C3-1 C4-1 C5-1 C6-1
C6-2C5-2C4-2C3-2C2-2
C18-1
C18-2 C17-2 C16-2 C15-2 C14-2 C13-2
C13-1C14-1C15-1C16-1C17-1
C12-1
C12-2 C11-2 C10-2 C9-2 C8-2 C7-2
C7-1C8-1C9-1C10-1C11-1
C19-2
C19-1 C20-1 C21-1 C22-1 C23-1 C24-1
C24-2C23-2C22-2C21-2C20-2
A1 CORNER
44 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Package Description Package Description
1.8.4 Package Parameters for the MPC7457, 483 CBGA
The package parameters are as provided in the following list. The package type is 29 × 29 mm, 483-lead
ceramic ball grid array (CBGA).
Package outline 29 × 29 mm
Interconnects 483 (22 × 22 ball array – 1)
Pitch 1.27 mm (50 mil)
Minimum module height —
Maximum module height 3.22 mm
Ball diameter 0.89 mm (35 mil)
1.8.5 Mechanical Dimensions for the MPC7457, 483 CBGA
Figure 21 provides the mechanical dimensions and bottom surface nomenclature for the MPC7457, 483
CBGA package.
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 45
Package Description
Figure 22. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7457,
483 CBGA Package
0.2
2X
NOTES:
1. DIMENSIONING AND
TOLERANCING
PER ASME Y14.5M, 1994.
2. DIMENSIONS IN
MILLIMETERS.
3. TOP SIDE A1 CORNER
INDEX IS A METALIZED
FEATURE WITH VARIOUS
SHAPES. BOTTOM SIDE .
A1 CORNER IS
DESIGNA TED WITH A BALL
MISSING FROM THE
ARRAY.
D
A1 CORNER
E
e
0.2
2X
C
B
12345678910111213141516
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
AA1
A2
A
0.15 A
171819
U
W
V
Millimeters
DIM MIN MAX
A 2.72 3.20
A1 0.80 1.00
A2 1.10 1.30
A3 -- 0.60
b 0.82 0.93
D 29.00 BSC
D1 — 12.5
D2 8.5 —
D3 — 8.4
D4 10.9 11.1
e 1.27 BSC
E 29.00 BSC
E1 — 12.5
E2 8.5 —
E3 — 8.4
E4 9.55 9.75
CA
483X
B0.3 A
0.15
b
202122
Y
AA
AB
Capa citor Region
1
D1
D3
E1
E3
D2
E2
A3
D4
E4
0.35 A
46 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Package Description Package Description
1.8.6 Substrate Capacitors for the MPC7457, 483 CBGA
Figure 23 shows the connectivity of the substrate capacitor pads for the MPC7457, 483 CBGA. All
capacito rs are 100 nF.
Figure 23. Substrate Byp ass Capacitors for the MPC7457, 483 CBGA
Capacitor Pad Number
-1 -2
C1 GND OVDD
C2 GND VDD
C3 GND GVDD
C4 GND VDD
C5 GND VDD
C6 GND GVDD
C7 GND VDD
C8 GND VDD
C9 GND GVDD
C10 GND VDD
C11 GND VDD
C12 GND GVDD
C13 GND VDD
C14 GND VDD
C15 GND VDD
C16 GND OVDD
C17 GND VDD
C18 GND OVDD
C19 GND VDD
C20 GND VDD
C21 GND OVDD
C22 GND VDD
C23 GND VDD
C24 GND VDD
1
C1-2
C1-1 C2-1 C3-1 C4-1 C5-1 C6-1
C6-2C5-2C4-2C3-2C2-2
C18-1
C18-2 C17-2 C16-2 C15-2 C14-2 C13-2
C13-1C14-1C15-1C16-1C17-1
C12-1
C12-2 C11-2 C10-2 C9-2 C8-2 C7-2
C7-1C8-1C9-1C10-1C11-1
C19-2
C19-1 C20-1 C21-1 C22-1 C23-1 C24-1
C24-2C23-2C22-2C21-2C20-2
A1 CORNER
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 47
System Design Information
1.9 System Design Information
This section provides system and thermal design recommendations for successful application of the
MPC7457.
1.9.1 PLL Configuration
The MPC7457 PLL is configur ed b y the PLL_CFG[0:4 ] signal s. For a give n SYSCLK (bus ) frequency, the
PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL conf iguration for
the MPC7457 is sh own in Tabl e 18 for a set of example fr equencies . In this exampl e, shaded cel ls repre sent
settings that, for a given SYSCLK frequ ency, result in core and/or VCO frequencies that do not comply with
the 1-GHz column in Table 8. Note that these configurations were different in devices before Rev F; see
Section 1.11.2, “Part Numbers Not Fully Addressed by This Document,” for more information regarding
documentation of prior revisions.
Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts
PLL_
CFG[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus (SYSCLK) Frequency
33.3
MHz 50
MHz 66.6
MHz 75
MHz 83
MHz 100
MHz 133
MHz 167
MHz
01000 2x 2x
10000 3x 2x
10100 4x 2x 667
(1333)
10110 5x 2x 667
(1333) 835
(1670)
10010 5.5x 2x 733
(1466) 919
(1837)
11010 6x 2x 600
(1200) 800
(1600) 1002
(2004)
01010 6.5x 2x 650
(1300) 866
(1730) 1086
(2171)
00100 7x 2x 700
(1400) 931
(1862) 1169
(2338)
00010 7.5x 2x 623
(1245) 750
(1500) 1000
(2000) 1253
(2505)
11000 8x 2x 600
(1200) 664
(1328) 800
(1600) 1064
(2128)
01100 8.5x 2x 638
(1276) 706
(1412) 850
(1700) 1131
(2261)
01111 9x 2x 600
(1200) 675
(1350) 747
(1494) 900
(1800) 1197
(2394)
01110 9.5x 2x 633
(1266) 712
(1524) 789
(1578) 950
(1900) 1264
(2528)
48 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
System Design Information System Design Information
10101 10x 2x 667
(1333) 750
(1500) 830
(1660) 1000
(2000)
10001 10.5x 2x 700
(1400) 938
(1876) 872
(1744) 1050
(2100)
10011 11x 2x 733
(1466) 825
(1650) 913
(1826) 1100
(2200)
00000 11.5x 2x 766
(532) 863
(1726) 955
(1910) 1150
(2300)
10111 12x 2x 600
(1200) 800
(1600) 900
(1800) 996
(1992) 1200
(2400)
11111 12.5x 2x 600
(1200) 833
(1666) 938
(1876) 1038
(2076) 1250
(2500)
01011 13x 2x 650
(1300) 865
(1730) 975
(1950) 1079
(2158)
11100 13.5x 2x 675
(1350) 900
(1800) 1013
(2026) 1121
(2242)
11001 14x 2x 700
(1400) 933
(1866) 1050
(2100) 1162
(2324)
00011 15x 2x 750
(1500) 1000
(2000) 1125
(2250) 1245
(2490)
11011 16x 2x 800
(1600) 1066
(2132) 1200
(2400)
00001 17x 2x 850
(1900) 1132
(2264)
00101 18x 2x 600
(1200) 900
(1800) 1200
(2400)
00111 20x 2x 667
(1334) 1000
(2000)
01001 21x 2x 700
(1400) 1050
(2100)
01101 24x 2x 800
(1600) 1200
(2400)
11101 28x 2x 933
(1866)
00110 PLL bypass PLL off, SYSCLK clocks core circuitry directly
Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (continued)
PLL_
CFG[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus (SYSCLK) Frequency
33.3
MHz 50
MHz 66.6
MHz 75
MHz 83
MHz 100
MHz 133
MHz 167
MHz
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 49
System Design Information
11110 PLL off PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:4] settings not listed are reserved.
2. The samp le bus- to-core fre quenc ies sh own are for refe ren ce only. Some PLL co nfigura tions may selec t bus, co re,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC7455; see Section 1.5.2.1,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.
However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must
be driven at one-hal f the frequ ency of SYSCLK and of fset i n phase to mee t the requi red inpu t setup tIVKH and hold
time tIXKH (see Table 9). The result is that the processor bus frequency is one-half SYSCLK while the internal
processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7455 regardless of the SYSCLK input.
Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (continued)
PLL_
CFG[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus (SYSCLK) Frequency
33.3
MHz 50
MHz 66.6
MHz 75
MHz 83
MHz 100
MHz 133
MHz 167
MHz
The MPC7457 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock frequency of the MPC7457. The
core-to-L3 frequency divisor for the L3 PLL is selected through the L3_CLK bits of the L3CR register. Generally, the divisor must be chosen
according to the frequency supported by the external RAMs, the frequency of the MPC7457 core, and timing analysis of the circuit board routing.
Table 19 shows various example L3 clock frequencies that can be obtained for a given set of core frequencies.
Table 19. Sample Core-to-L3 Frequencies 1
Core
Frequency
(MHz) ÷2 ÷2.5 ÷3 ÷3.5 ÷4 ÷4.5 ÷5 ÷5.5 ÷6 ÷6.5 ÷7 ÷7.5 ÷8
500 250 200 167 143 125 111 100 91 83 77 71 67 63
533 266 213 178 152 133 118 107 97 89 82 76 71 67
550 275 220 183 157 138 122 110 100 92 85 79 73 69
600 300 240 200 171 150 133 120 109 100 92 86 80 75
650 325 260 217 186 163 144 130 118 108 100 93 87 81
666 333 266 222 190 167 148 133 121 111 102 95 89 83
700 350 280 233 200 175 156 140 127 117 108 100 93 88
733 367 293 244 209 183 163 147 133 122 113 105 98 92
800 400 320 266 230 200 178 160 145 133 123 114 107 100
866 433 347 289 248 217 192 173 157 145 133 124 115 108
933 467 373 311 266 233 207 187 170 156 144 133 124 117
1000 500 400 333 285 250 222 200 182 166 154 143 133 125
1050 2525 420 350 300 263 233 191 191 175 162 150 140 131
1100 2550 440 367 314 275 244 200 200 183 169 157 147 138
1150 2575 460 383 329 288 256 209 209 192 177 164 153 144
1200 2600 480 400 343 300 267 218 218 200 185 171 160 150
1250 2638 500 417 357 313 278 227 227 208 192 179 167 156
1300 2650 520 433 371 325 289 236 236 217 200 186 173 163
Notes:
1. The core and L3 frequencies are for referen ce only . Note that maximum L3 frequency is design dep endent. Some examples may repres ent core or L3 frequencies
which ar e not useful, not supp orted, or not tested fo r the MP C7457; see Sectio n 1.5.2.3, “L3 Clock AC Specifications, ” for valid L3_C LK frequencie s and for more
information regarding the maximum L3 freq uency.
2. These core frequencies are not supported by all speed grades; see Table 8.
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 51
System Design Information
1.9.2 PLL Power Supply Filtering
The AVDD power signal is provided on the MPC7457 to provide power to the clock generation PLL. To
ensure sta bilit y of the internal clock, th e power supplied to the AVDD input signal should be filtered of any
noise in th e 500 kHz to 10 MHz resonant frequen cy range of the PLL. A circuit si milar to the one sho wn in
Figure 22 using s urface mount capacitors with minimum effective s eries inductance (ESL) is recommended.
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the per iphery
of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint, without the
inductance of vias.
The PLL power supply filter previously provided in the MPC7457 RISC Microprocessor Hardware
Specifications has been found to be less effective for Rev 1.1 devices with the low core voltages described
in this specification. As a result, the recommended value for the resistor in the circuit is being evaluated and
a new r ecommen datio n is ind icated in Figure 24. If the va lue i ndica ted i s not a vaila ble, t he ne arest sta ndard
value resistor may be used instead; a higher resistor value is recommended over a lower one. Motorola
continues to evaluate the filtering requirements of the MPC7457 and plans to make updated
recommendations as needed. Note that this recommendation applies to Rev. 1.1 devices only.
Figure 24. PLL Power Supply Filter Circuit
1.9.3 Decoupling Recommendations
Due to the MPC7457 dynami c power management feat ure, large ad dress and data buse s, and high operati ng
frequencies, the MPC7457 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC7457 system, and the MPC7457 itself requires a clean, tightly regulated source of
power . Therefore, it is r ecommended that the system des igner place at least one decouplin g capacitor at ea ch
VDD, OVDD, and GVDD pin of the MPC7457. It is also recommended that these decoupling capacitors
receive their power from separate VDD, OVDD/GVDD, and GND power planes in the PCB, utilizing short
traces to minimize inductance.
These capacitors should have a value of 0.01 or 0.1 µ F. Only ceramic surface mount technology (SMT)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where
connections are made along the length of the part. Consistent with the recommendations of Dr. Howard
Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentic e Ha ll, 19 93) and con tra ry to
previous recommendations for decoupling Motorola microprocessors, multiple small capacitors of equal
value are recommended over using multiple values of capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feed ing the VDD, GVDD, a nd OVDD planes, t o enable quic k rechar ging of th e smaller chi p capacitors. These
bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time
necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
VDD AVDD
400 Ω
2.2 µF 2.2 µF
GND Low ESL Surface Mount Capac itors
52 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
System Design Information System Design Information
1.9.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unus ed act i ve low inputs shou ld be t ied to OVDD. Unused active hi gh in put s shoul d be connecte d to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, GVDD, and GND pins in the
MPC7457. If the L3 interface is not used, GVDD should be connected to the OVDD power plane, and
L3VSEL should be connected to BVSEL; the remainder of the L3 interface may be left unterminated.
1.9.5 Output Buffer DC Impedance
The MPC7457 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature.
To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of
each resistor is varied until the pad voltage is OVDD/2 (see Figure 23).
The output impedance is the average of two components, the resistances of the pull-up and pull-down
devic es. When d ata is held low, SW2 is cl osed (SW1 is ope n), and RN is trimmed until the voltage at the
pad equa ls OVDD/2. RN then become s the resistance of the pull-down devices. When data is held high, SW1
is closed (SW2 is open), and RP is trim med un til the voltag e at the pad equa ls OV DD/2. RP then becomes
the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 =
(RP + RN)/2.
Figure 25. Driver Impedance Measurement
Tabl e 20 summar izes the si gnal i mpedance re sults. The impe dance i ncrea ses wit h junc tion t emperat ure a nd
is relatively unaffected by bus voltage.
Table 20. Impedan ce Character ist ics
VDD = 1.5 V, OVDD = 1.8 V ± 5%, Tj = 5°–85°C
Impedance Processor Bus L3 Bus Unit
Z0Typical 33–42 34–42 Ω
Maximum 31–51 32–44 Ω
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 53
System Design Information
1.9.6 Pull-Up/Pull-Down Resistor Requirements
The MPC7457 requires high-resistive (weak: 4.7-kΩ) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC7457 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pin s designated as bei ng for factory t est must be pull ed up to OVDD or down to GND to ensur e proper
device ope ration. For the MPC7447, 360 BGA, the pins that must be pulle d up to OV DD are: LSSD_MODE
and TEST[0:3]; the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. For the
MPC7457, 483 BGA, the pin s that must be pull ed up t o OVDD ar e: LSSD_MODE and TEST[0 :5]; the pin s
that must be pulled down are : L1_TSTCLK and TEST[6] . The CKSTP_IN signa l should li kewise be pul led
up through a pull-up resistor (weak or stronger: 4.7–1 kΩ) to prevent erroneous assertions of this signal.
In addit ion, the MPC74 57 has one open- drain style output tha t require s a pull-up resistor (weak or strong er:
4.7–1 kΩ) if it is used by the system. This pin is CKSTP_OUT.
If pul l-down resi stors are us ed to co nfigure BVSEL o r L3VSEL, the res istors sho uld be less than 250 Ω (see
Table 16). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and
pull-down resistors (1 kΩ or less) are recommended to configure these signals in order to protect against
erroneous switching due to ground bounce, power supply noise or noise coupling.
During i nactive pe ri ods on the bus, the ad dre ss and tra nsf er at tribute s may not be dri ven by any mas te r a nd
may, ther efore , float in the hig h-impeda nce stat e for rel ativ ely long per iods of ti me. Because the MPC7457
must continually monitor these signals for snooping, this float condition may cause excessive power draw
by the input receivers on the MPC7457 or by other receivers in the system. These signals can be pulled up
through weak (10 -kΩ) pull -up re sisto rs by the sys tem , addre ss bus driven mode ena bled ( see t he MPC7450
RISC Microprocessor Family Users’ Manual for more information about this mode), or they may be
otherwise driven by the system during inactive periods of the bus to avoid this additional power draw.
Prelimi nary studies ha ve shown the additi onal power draw by the MPC7457 in put receivers to be negligible
and, in any event, none of these measures are necessary for proper device operation. The snooped address
and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.
If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through weak
pull-do wn resistors. If the MPC7457 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak
pull-down resistors.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pull-up s, or tha t those sign als be otherwise dr iven by the sy stem during ina ctive per iods by th e sys tem. The
data bus signals are: D[0:63] and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, all parity
checking shoul d al so be dis abl ed t hr ough HID0, and all pari ty pi ns may be le ft unc onnected b y t he system.
The L3 interface does not normally require pull-up resistors.
1.9.7 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performa nce will be obtained if the TRST signal is asserted during power-on reset.
54 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
System Design Information System Design Information
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interf ace connect s primarily thr ough the JTAG port of the proces sor , with some a dditional s tatus monito ring
signals . The COP port requires the ability to independent ly assert HRESET or TRST in or der to fully c ontrol
the proce ssor . If the tar get system has independent re set sources, such as voltage monitors, watchdog timer s,
power supply failures, or push-button switches, the COP reset signals must be merged into these signals with
logic.
The arr angement sho wn in Figur e 24 allo ws the COP port to inde pendentl y assert HRESET or TRST, while
ensurin g t hat t he target c an drive HRESET as well . If the JTAG interface and COP heade r will not be used,
TRST should be ti ed to HRESET through a 0-Ω isolati on resistor so th at it is assert ed when the system re set
signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. While
Motoro la recommend s that the COP header be des igned into th e system as shown in Figure 24, if this is not
possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need
to be wired onto the system in debug situations.
The COP header shown in Figure 24 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has
pin 14 removed as a connector key.
There is no st anda rdi ze d way to number t he COP header shown in Figu re 24; con seq uent ly, many differen t
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 24 is common to all known emulators.
The QACK signal shown in Figure 24 is usually connected to the PCI bridge chip in a system and is an input
to the MPC7457 informing it that it can go into the quiescent state. Under normal operation this occurs
during a low-power mode selection. In order for COP to work, the MPC7457 must see this signal asserted
(pulled down). While shown on the COP header, not all emulator products drive this signal. If the product
does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products
implement open-drain type output s and can only drive QACK asserted; for these tools, a p ull-up r esistor can
be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the
pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to
populate both in a system. To preserve correct power-down operation, QACK should be merged via logic
so that it also can be driven by the PCI bridge.
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 55
System Design Information
Figure 2 6. JTAG Interface Connection
HRESET HRESET
From Target
Board Sources
HRESET
13 SRESET
SRESET SRESET
11
VDD_SENSE
6
5 1
15
2 kΩ10 kΩ
10 k Ω
10 kΩ
OVDD
OVDD
OVDD
OVDD
CHKSTP_IN CHKSTP_IN
8TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4TRST
7
16
2
10
(if any)
COP Header
14 2
Key
QACK
OVDD
OVDD
10 kΩOVDD
TRST
10 kΩOVDD
10 k Ω
10 kΩ
QACK
QACK
CHKSTP_OUT
CHKSTP_OUT
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No Pin
COP Connector
Physical Pin Out
10 kΩ 4OVDD
1
2 kΩ 3
0 Ω 5
Notes:
1. RUN/STOP, norm ally found on pin 5 of the COP h eader , is not i mplemented on the MPC7457. C onnect
pin 5 of the COP header to OVDD with a 10-kΩ pull-up resistor.
2. Key locatio n; pin 14 is not phy si ca ll y pres ent on the C OP hea der.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.
5. If the JTAG interface is imple mente d, connec t HRESET from the target source to TRST from the COP
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-Ω isolation resist or.
6. Though defined as a No-Connect, it is a common and recommended practice to use pin 12 as an
12 6NC
56 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
System Design Information System Design Information
1.9.8 Thermal Management Information
This sec tion provi des therma l management i nformation f or the cer amic ball g rid arra y (CBGA) package for
air-cooled applications. Proper thermal control design is primarily dependent on the system-level
design— the heat sink, air fl o w, an d thermal i nte rface mate ri al . To reduce the d ie- j unct ion temperature , hea t
sinks may be attached to the package by several methods—spring clip to holes in the printed-circuit board
or packa ge, and mounting c lip and scre w assembly (see Figure 25); however , due to the potent ial lar ge mass
of the heat sink, attachment through the pri nted-circuit board is suggeste d. If a spring clip is used, the spring
force should not exceed 10 pounds.
Figure 27. Package Exploded Cross-Sectional View with Several Heat Sink Options
The board designer can choose between several types of heat sinks to place on the MPC7457. There are
several commercially available heat sinks for the MPC7457 provided by the following vendors:
Aavid Thermall oy 603-224-9 988
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
Alpha Novatech 408-749-7601
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Research Corporation (IERC) 818-842-7277
413 North Moss St.
Burbank, CA 91502
Internet: www. ctsco rp.c om
Tyco Ele ctr oni cs 800-522-6752
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
Thermal
Heat Sink CBGA Package
Heat Sink
Clip
Printed-Circuit Board
Interface Ma teria l
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 57
System Design Information
Wakefield Engineering 603-635-5102
33 Bridge St.
Pelham, NH 03076
Internet: www.w akef ield.com
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
1.9.8.1 Internal Pack age Conduction Resistance
For the exposed-die packaging technology, shown in Table 3, the intrinsic conduction thermal resistance
paths are as follows:
• The die junction-to-case (actually top-of-die since silicon die is exposed) thermal resistance
• The die junction-to-ball thermal resistance
Figure 26 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-cir cui t boar d.
Figure 28. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Heat generated on the active side of the chip is conducted through the silicon, through the heat sink attach
material (or thermal interface material), and finally to the heat sink where it is removed by forced-air
convection.
Because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the
silicon may be neglected. Thus, the thermal interface material and the heat sink conduction/convective
thermal resistances are th e dominant terms .
1.9.8.2 Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the
thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism,
Figure 27 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,
graph ite/o il, flo roethe r oil) , a bar e join t, and a joi nt with therm al gr ease as a fun ction of co ntact pressu re.
As shown, the per fo rmanc e of these th er mal interf ace mater ia ls im pro ves with incr easing con tac t pr ess u r e.
External Resistance
External Resistance
Internal Resistance
Radiation Convection
Radiation Convection
Heat Sink
Printed-Circuit Board
Thermal Interface Material
Package/Leads
Die Junction
Die/Package
(No te the internal versus external package r esistance.)
58 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
System Design Information System Design Information
The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results
in a thermal resistance approximately seven times greater than the thermal grease joint.
Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board
(see Figure 25). Therefore, the synthetic grease offers the best thermal performance, considering the low
interface pressure and is recommended due to the high power dissipation of the MPC7457. Of course, the
selection of any thermal interface material depends on many factors—thermal performance requirements,
manufacturability, service temperature, dielectric properties, cost, etc.
Figure 29. Thermal Performance of Select Thermal Interface Material
The board designer can choose between several types of thermal interface. Heat sink adhesive materials
should be selected based on high conductivity, yet adequate mechanical strength to meet equipment
shock/vibration requirements. There are several commercially available thermal interfaces and adhesive
materials provided by the following vendors:
The Bergquist Company 800-347-4572
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
Chomerics, Inc. 781-935-4850
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
0
0.5
1
1.5
2
0 1020304050607080
Silicone Sheet (0.006 in.)
Bare Joint
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
Contact Pressure (psi)
Specific Thermal Res istance (K-in .2/W)
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 59
System Design Information
Dow-Corning Corporation 800-248-2481
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
Midland, MI 48686-0997
Internet: www.dow.com
Shin-Etsu MicroSi, Inc. 888-642-7674
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
Thermagon Inc. 888-246-9050
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
The following section provides a heat sink selection example using one of the commercially available heat
sinks.
1.9.8.3 Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
Tj = TI + Tr + (RθJC + Rθint + Rθsa) × Pd
where:
Tj is the die-junction temperature
TI is the inlet cabinet ambient temperature
Tr is the air temperature rise within the computer cabinet
RθJC is the junction-to-case thermal resistance
Rθint is the adhesive or interface material thermal resist ance
Rθsa is the heat sink base-to -ambient thermal resistan ce
Pd is the power dissipated by the device
During operation, the die-junction temperatures (Tj) should b e mainta ined l ess than the val ue sp ecified in
Tabl e 4. The tempera ture of ai r cool ing the c omponent great ly depe nds on the ambient inl et ai r tempe ratur e
and the air temper ature r ise with in the e lectron ic cabi net. An electr onic cabine t inlet-a ir tem perature (Ta)
may range from 30° to 40°C. The air temperature rise within a cabi net (Tr) may be in the range of 5° to 10°C.
The thermal resistance of the thermal interface material (Rθint) is typically about 1.5°C/W. For example,
assumi ng a Ta of 30°C, a T r of 5°C, a CBGA package RθJC = 0.1, and a typical power consumption (Pd) of
18.7 W, the following expression for Tj is obtained:
Die-jun ction tempera tur e: Tj = 30°C + 5°C + (0.1°C/W + 1.5°C/W + θsa) × 18.7 W
For thi s exampl e, a Rθsavalue of 2.1 °C/W o r les s is req uired to m ainta in th e die jun ction temper atu re bel ow
the maximum value of Table 4.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common
figure-of-merit used for comparing the thermal performance of various microelectronic packaging
technol ogi es, one should e xer cis e cauti on whe n o nly using this met ri c i n d et ermi ning ther mal mana gemen t
because no single parameter can adequately describe three-dimensional heat flow. The final die-junction
operati ng temperature is not only a functi on of the component-l evel thermal re sistance, but the sys tem-level
design an d its operat ing condit ions. In addi tion to th e component's power consumpt ion, a number of f actors
60 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
System Design Information System Design Information
affect the final operating die-junction temperature—airflow, board population (local heat flux of adjacent
components ), heat sin k effi ciency, heat sink attac h, heat sink pl acement, next- level inte rconnect te chnology,
system air temperature ri se, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today's
microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,
and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models
for the board, as well as system-level designs.
For system thermal modeling, the MPC7447 and MPC7457 thermal model is shown in Figure 28. Four
volumes will be used to represent this device. Two of the volumes, solder ball, and air and substrate, are
modeled usi ng the package out line size of the pa ckage. The other two, di e, and bump and underfi ll, have the
same size as the di e. The si lico n die sho uld be modeled 9.64 × 11.0 × 0.74 mm with t he heat source applie d
as a unifor m sourc e at the bot t om of the volume . The bump and und erf i ll laye r is modele d as 9.64 × 11 .0 ×
0.69 mm (or as a co llaps ed volume) with orth otropic mat erial prop erties: 0.6 W/(m • K) in the xy-pl ane and
2 W/( m • K) i n th e di rectio n of the z-axi s. T he su bst rate vol ume i s 25 × 25 × 1.2 mm (MPC7447) or 29 ×
29 × 1.2 mm (MPC7457), and this vol ume ha s 18 W/(m • K) is ot ropi c c onductivi ty. The solder ba ll and ai r
layer is modeled with the same horizontal dimensions as the substrate and is 0.9 mm thick. It can also be
modeled as a collapsed volume using orthotropic material properties: 0.034 W/(m • K) in the xy-plane
direction and 3.8 W/(m • K) in the direction of the z-axis.
Figure 30. Recommended Thermal Model of MPC7447 and MPC7457
Bump and Underfil l
Die
Substrate
Solder and Air
Die
Substrate
Side View of Model (Not to Scale)
Top View of Model (Not to Scale)
x
y
z
Conductivity Value Unit
Bump and Underfill
kx0.6 W/(m • K)
ky0.6
kz2
Substrate
k18
Solder Ball and Air
kx0.034
ky0.034
kz3.8
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 61
Document Revision History
1.10 Document Revision History
Table 21 provides a revision history for this hardware specification.
Table 21. Document Revision History
Revision
Number Substantive Change(s)
0 Initial release.
1 • Removed support for 1.5 V L3 interface voltage from Tables 3 and 4. 1.5 V I/O voltage is not
supported in current MPC7457 devices.
• Added package thermal characteristics values to Table 5, made minor revisions to Section 1.9.8.
• Added preliminary AC timing values to Tables 10 and 12.
• Added footnotes to Table 17.
1.1 Nontechnical reformatting
2 • Added substrate capacitor information in Sections 1.8.3 and 1.8.6.
• Increas ed minim um process or and VC O frequenc ies in Table 8 from 500 M Hz and 1000 MHz to 600
MHz and 1200 MHz (respectively).
• Corrected maximum processor frequency for 1300 MHz devices in Table 8 (changed from 1333 MHz
to 1300 MHz).
• Added value for to tL3CSKW1 Table 10.
• Added L3OHCR information in Section 1.5.2.4.1.
• Added values for tCO and tECI to Table 11.
• Added Note 8 to Table 13 and Note 6 to Table 14.
• Changed resistor value in PLL filter in Figure 24 from 10 Ω to 400 Ω.
• Added 867 MHz speed grade.
• Corrected Product Code in Tables 22 and 23.
• Added pull-up/pull-down recommendations for CKSTP_IN and PLL_CFG[0:4] to Section 1.9.6.
3 Corrected numerous errors in lists of pins associated with tKHOV, tKHOX, tIVKH, and tIXKH in Table 9.
Added support for 1.5 V L3 interface voltage; issues fixed in Rev 1.1.
Correc ted typos in Table 12.
Added data to Table 2.
Clarified address bus pull-up resistor recommendations in Section 1.9.6.
Modified Table 9, Figure 5, and Figure 6 to more accurately show when the mode select inputs
(BMODE[0:1], L3VSEL, BVSEL) are sampled and AC timing requirements
Table 10: Added skew and jitter values.
Table 14: Added AC timing values.
Table 23: Updated to reflect past and current part numbers not fully covered by this document.
Table 6: Remo ved CVIH and C VIL; VIH and VIL for SYSCLK i nput is th e sa me a s for ot her inpu t signal s,
and is now noted accordingly in this table.
Table 7: Removed Doze mode power entry (but left footnote 4 for clarity); documentation change only.
Nontechnical formatting
62 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Document Revision History Document Revision History
4 Tabl e 9:Correcte d pin list s for input and ou tput AC timing to co rrectly show HIT as an output- only signa l
Added specifications for 1267 MHz devices; removed specs for 1300 MHz devices.
Chang ed recommendati ons regarding u se of L3 clock ji tter in AC timing an alysis in Sectio n 1.5.2.3, “L3
Clock AC Spec ifi cation s”; the L3 jitte r is now ful ly compre hen ded in the AC ti mi ng spec s and do es not
need to be includ ed in the tim in g anal ys is .
Table 21. Document Revision History (continued)
Revision
Number Substantive Change(s)
MOTOROLA MPC7457 RISC Microprocessor Hardware Specifications 63
Ordering Information
1.11 Orde ring Information
Ordering information for the parts fully covered by this specification document is provided in
Section 1.11.1, “Part Numbers Fully Addressed by This Document.” Note that the individual part numbers
corres pond t o a maximum proces sor c ore f reque ncy. For a vaila ble freque ncies , c ontact your loca l Mo torol a
sales of f ice. In addi tion to the proce ssor fr equency, the part numbering sch eme also inc ludes an ap plica tion
modifier which may speci fy special applica tion condi tion s. Each part number also contai ns a rev ision leve l
code which re fe rs t o the die mask revision number. Section 1.11.2, “Par t Number s Not Fully Addre sse d by
This Document,” lists the part numbers which do not fully conform to the specifications of this document.
These special part numbers require an additional document called a part number specification.
64 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Ordering Information Ordering Information
1.11.1 Part Numbers Fully Addressed by This Document
Table 22 provides the Motorola part numbering nomenclature for the MPC7457.
1.11.2 Part Numbers Not Fully Addressed by This Document
Parts with application modifiers or revision levels not fully addressed in this specification document are
described in separate part number specifications which supplement and supersede this document. As such
parts are released, these specifications will be listed in this section.
Table 22. Part Numbering Nomenclature
PPC 74x7RXnnnn Lx
Product
Code Part
Identifier Package Processor
Frequency 1Application
Modifier Revision Level
PPC 27457
7447 RX = CBGA 867
1000
1200
1267
L: 1.3 V ± 50 mV
0 to 105°CB: 1.1; PVR = 8002 0101
Notes:
1. Processor core frequencies supported by parts addressed by this specification only. Parts addressed by part
number specifications may support other maximum core frequencies.
2. The P prefix i n a Motorola pa rt number designate s a “Pilot Production Proto type” as defined by Motorol a SOP 3-13.
These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be
shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the
qualification status and the fact that product changes may still occur while shipping pilot production prototypes.
Table 23. Part Numbering Nomenclature
PPC 74x7RXnnnn Nx
Product
Code Part
Identifier Package Processor
Frequency Application
Modifier Revision Level
PPC 7457 RX = CBGA 1000 N:1.1 V ± 50 mV
0 to 105°CB: 1.1; PVR = 8002 0101
867
733
600
7447 1000
867
MC 7447 1000
867
733
600
65 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Ordering Information Ordering Information
1.11.3 Part Marking
Parts are marked as the example shown in Figure 29.
Figure 31. Part Marking for BGA Device
BGA
Notes:
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
MMMM MM is the 6-dig it mask number.
ATWLYYWWA is the traceability code.
PPC7457
RX1200LB
MMMMMM
ATWLYYWWA
7457
BGA
PPC7447
RX1200LB
MMMMMM
ATWLYYWWA
7447
66 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Ordering Information Ordering Information
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67 MPC7457 RISC Microprocessor Hardware Specifications MOTOROLA
Ordering Information Ordering Information
THIS PAGE INTENTIONALLY LEFT BLANK
MPC7457EC
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