2015 Microchip Technology Inc. DS20005045C-page 1
Features
Single Voltage Read and Write Operations
- 2.7-3.6V
Serial Interface Architecture
- SPI Comp atible: Mode 0 and Mode 3
High Speed Clock Freque ncy
- 50/66 MHz conditiona l (see Table 5-6)
Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
Low Power Consumption:
- Active Read Current: 10 mA (typica l)
- S t andby Current: 5 µA (typical)
Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 32 KByte overlay blocks
- Uniform 64 KByte overlay blocks
Fast Erase and Byte-Program:
- Chip-Erase T ime: 35 ms (typical)
- Sector-/Block-Erase Time: 18 ms (typical)
- Byte-Program Time: 7 µs (typical)
Auto Address Increment (AAI) Programming
- Decrease total chip programming ti me over
Byte-Program operations
End-of-Write Detection
- Software polling the BUSY bit in S t atus Register
- Busy S t atus readout on SO pin in AAI Mode
Hold Pin (HOLD#)
- Suspends a serial sequence to the memory
without deselecting the device
Write Protection (WP#)
- Enables/Disables th e Lock-Down function of the
status register
Software Write Protection
- Write protection through Block-Pro tection bits in
status register
Temperature Range
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
Packages Available
- 8-lead SOIC (200 mils)
- 8-contact WSON (6mm x 5mm)
- 8-lead PDIP (300 mils)
All devices are RoHS compliant
Product Description
25 series Serial Flash family fea tures a four-wire, SPI-
compatible interface that allows for a low pin-count
package which occupies less board space and ulti-
mately lowers total system costs. The SST25VF080B
devices are enhanced with improved operating fre-
quency and lower powe r consumption. SST25VF080B
SPI serial flash memories are manufactured with pro-
prietary, high-performance CMOS SuperFlash technol-
ogy . The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches.
The SST25VF080B devices significantly improve per-
formance and reliability, while lowering power con-
sumption. The devices write (Program or Erase) with a
single power supply of 2.7-3.6V for SST25VF080B.
The total energy consumed is a function of the applied
voltage, current, and time of application. Sin ce for any
given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time,
the total energy consumed during any Erase or Pro-
gram operation is less than alternative flash memory
technologies.
The SST25VF080B device is offered in 8-lead SOIC
(200 mils), 8-contact WSON (6mm x 5mm), and 8-lead
PDIP (300 mils) packages. See Figure 2-1 for pin
assignments.
SST25VF080B
8 Mbit SPI Serial Flash
SST25VF080B
DS20005045C-page 2 2015 Microchip Technology Inc.
1.0 BLOCK DIAGRAM
FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM
1296 B1.0
I/O Buffers
and
Data Latches
SuperFlash
Memory
X - Decoder
Control Logic
Address
Buffers
and
Latches
CE#
Y - Decoder
SCK SI SO WP# HOLD#
Serial Interface
2015 Microchip Technology Inc. DS20005045C-page 3
SST25VF080B
2.0 PIN DESCRIPTION
FIGURE 2-1: PIN ASSIGNMENTS
TABLE 2-1: PIN DESCRIPTION
Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output da ta is shifted out on the falling edge of the clock input.
SI Serial Data Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#
pin. See “Hardware End -of-Write Detection” on page 10 for details.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for
the duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold To temporarily stop serial communicatio n with SPI flash memory without resetting
the device.
VDD Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF08 0B
VSS Ground
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
VDD
HOLD#
SCK
SI
Top View
1296 08-soic S2A P1.0
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
Top View
VDD
HOLD#
SCK
SI
1296 08-wson QA P2.0
8-lead SOIC 8-contact WSON
CE#
SO
WP#
VSS
VDD
HOLD#
SCK
SI
Top View
1296 08-pdip-PA-P3.0
8-lead PDIP
SST25VF080B
DS20005045C-page 4 2015 Microchip Technology Inc.
3.0 MEMORY ORGANIZATION
Th e SST25VF080B S u p e r Fl a s h memory array is orga-
nized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable
blocks.
4.0 DEVICE OPERATION
The SS T2 5VF 08 0B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
The SST25VF080B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam-
pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is dri ven after the falling edge
of the SCK clock signal.
FIGURE 4-1: SPI PROTOCOL
4.1 Hold Operation
The HOLD# pin is used to pause a serial sequence
underway with the SPI flash memory without resetting
the clocking sequence. To activate the HOLD# mode,
CE# must be in active low state. The HOLD# mode
begins when the SCK active low state coincides with
the falling edge of the HOLD# signal. The HOLD mode
ends when the HOLD# signal’s rising edge coincides
with the SCK active low state.
If the falling edge of the HOLD# signal does not coin-
cide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active
low state, then the device exits in Hold mode when the
SCK next reaches the active low state. See Figure 4-2
for Hold Condition waveform.
Once the device enters Hold mode, SO wil l be in high-
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it
resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold
condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be
driven active low. See Figure 5-3 for Hold timing.
FIGURE 4-2: HOLD CONDITION WAVEFORM
1296 SPIprot.0
MODE 3
SCK
SI
SO
CE#
MODE 3
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MODE 0MODE 0
HIGH IMPEDANCE
MSB
MSB
Active Hold Active Hold Active
1296 HoldCond.0
SCK
HOLD#
2015 Microchip Technology Inc. DS20005045C-page 5
SST25VF080B
4.2 Write Protection
SS T25 VF0 8 0B provides software W rite protection. The
Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protec-
tion bits (BP3, BP2, BP1, BP0, and BPL) in the status
register provide Write protection to the memory array
and the status register . See Table 4-3 for the Block-Pro-
tection description.
4.2.1 WRITE PROTECT PIN (WP#)
The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-
Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
4.3 Status Register
The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
During an internal Erase or Program operation, the sta-
tus register may be read only to determine the comple-
tion of an operation in progress. Table 4-2 describes
the function of each bit in the software status register.
4.3.1 BUSY
The Busy bit determines whether there is an internal
Erase or Program operation in progress. A “1” for the
Busy bit indicates the device is busy with an operation
in progress. A “0” indicates the device is ready for the
next valid operation.
4.3.2 WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the
internal memory Write Enable Latch. If the Write-
Enable-Latch bit is set to “1”, it indicates the device is
Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept
any memory Write (Program/Erase) commands. The
Write-Enable-Latch bit is automatically reset under the
following conditions:
•Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instructi on completion
Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Write-St a tus-Register instructions
TABLE 4-1: CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION
WP# BPL Execute WRSR Instruction
L1Not Allowed
L0Allowed
HXAllowed
TABLE 4-2: SOFTWARE STATUS REGISTER
Bit Name Function
Default at
Power-up Read/Write
0BUSY 1 = Internal Write operation is in progress
0 = No internal Write operation is in progress 0R
1WEL 1 = Device is memory W rite enabled
0 = Device is not memory W rite enabled 0R
2BP0 Indicate current level of block write protection (See Table 4-3)1R/W
3BP1 Indicate current level of block write protection (See Table 4-3)1R/W
4BP2 Indicate current level of block write protection (See Table 4-3)1R/W
5BP3 Indicate current level of block write protection (See Table 4-3)0R/W
6AAI Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0R
7BPL 1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are read/writable 0R/W
SST25VF080B
DS20005045C-page 6 2015 Microchip Technology Inc.
4.3.3 AUTO ADDRESS INCREMENT (AAI)
The Auto Address Increment Programming-Status bit
provides status on whether the device is in AAI pro-
gramming mode or Byte-Program mode. The default at
power up is Byte-Program mode.
4.3.4 BLOCK PROTECTION (BP3,BP2,
BP1, BP0)
The Block-Prot ection (BP3, BP2, BP1, BP0) bits define
the size of the memory area, as defined in Table 4- 3, to
be software protected against any memory Write (Pro-
gram or Erase) operation. The Write-Status-Register
(WRSR) instruction is used to pr ogram the BP3, BP2,
BP1 and BP0 bits as long as WP# is high or the Block-
Protect-Lock (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-
up, BP3, BP2, BP1 and BP0 are set to 1.
4.3.5 BLOCK PROTECTION LOCK-DOWN
(BPL)
WP# pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents
any further alteration of the BPL, BP3, BP2, BP1, and
BP0 bits. When the WP# pin is driven high (VIH), the
BPL bit has no effect and its value is “Don’t Care”. After
power-up, the BPL bit is reset to 0.
TABLE 4-3: SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25VF080B1
1. X = Don’t Care (RESERVED) default is “0
Protection Level
Status Register Bit2
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)
Protected Memory Address
BP3 BP2 BP1 BP0 8 Mbit
None X 0 0 0 None
Upper 1/16 X 0 0 1 F0000H-FFFFFH
Upper 1/8 X 0 1 0 E0000H-FFFFFH
Upper 1/4 X 0 1 1 C0000H-FFFFFH
Upper 1/2 X 1 0 0 80000H-FFFFFH
All Blocks X 1 0 1 00000H-FFFFFH
All Blocks X 1 1 0 00000H-FFFFFH
All Blocks X 1 1 1 00000H-FFFFFH
2015 Microchip Technology Inc. DS20005045C-page 7
SST25VF080B
4.4 Instructions
Instructions are used to read, write (Erase and Pro-
gram), and configure the SST25VF080B. The instruc-
tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program-
ming, Sector-Erase, Block-Erase, Write-Status-Regis-
ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com-
plete list of instructions is provided in Table 4-4. All
instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of
SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-S tatus-
Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com-
mands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.
TABLE 4-4: DEVICE OPERATION INSTRUCTIONS
Instruction Description Op Code Cycle1
1. One bus cycle is eight clock periods.
Address
Cycle(s)2
2. Address bits above the most significant bit of each density can be VIL or VIH.
Dummy
Cycle(s)
Data
Cycle(s)
Read Read Memory 0000 0011b (03H) 301 to
High-Speed Read Read Memory at higher speed 0000 1011b (0BH) 311 to
4 KByte Sector-Erase3
3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
Erase 4 KByte of
memory array 0010 0000b (20H) 300
32 KByte Block-Erase4
4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
Erase 32 KByte block
of memory array 0101 0010b (52H) 300
64 KByte Block-Erase5
5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
Erase 64 KByte block
of memory array 1101 100 0b (D8H) 300
Chip-Erase Erase Full Memory Array 0110 0000b (60H) or
1100 0111b (C7H) 000
Byte-Program To Program One Data Byte 0000 0010b (02H) 301
AAI-Word-Program6
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be pro-
grammed into the
initial address [A23-A1] with A0=1.
Auto Address Increment
Programming 1010 1101b (ADH) 302 to
RDSR7
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
Read-Status-Register 0000 0101b (05H) 001 to
EWSR Enable-Write-Status-Register 0101b 0000b (50H) 000
WRSR Write-Status-Register 0000 0001b (01H) 001
WREN Write-Enable 0000 0110b (06H) 000
WRDI Write-Disable 0000 0100b (04H) 000
RDID8
8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID
and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
Read-ID 1001 0000b (90H) or
1010 1011b (ABH) 301 to
JEDEC-ID JEDEC ID read 1001 1111b (9FH) 003 to
EBSY E n a b l e SO t o ou t put RY / B Y #
status during AAI programming 0111 0000b (70H) 000
DBSY Disable SO as R Y/BY#
status during AAI programming 1000 0000b (80H) 000
SST25VF080B
DS20005045C-page 8 2015 Microchip Technology Inc.
4.4.1 READ (25 MHz)
The Read instruction, 03H, supports up to 25 MHz
Read. The device outputs the data starting from the
specified address location. The data output stream is
continuous through all add resses unti l termina ted by a
low to high transition on CE#. The internal address
pointer will automatically increment until the highest
memory address is reached. Once the highest memory
address is reached, the address pointer will automati-
cally increment to the beginning (wrap-around) of the
address space. Once the data from address location
FFFFFH has been read, the next output will be from
address location 00000H.
The Read instruction is initiated by executing an 8-bit
command, 03H, followed by address bits [A23-A0].
CE# must remain active low for the duration of the
Read cycle. See Figure 4-3 for the Read sequence.
FIGURE 4-3: READ SEQUENCE
4.4.2 HIGH-SPEED-READ (66 MHz)1
The High-Speed-Read instruction, supporting up to
66 MHz Read, is initiated by executing an 8-bit com-
mand, 0BH, followed by address bits [A23-A0] and a
dummy byte. CE# must remain active low for the dura-
tion of the High-Speed-Re ad cycle. See Figure 4-4 for
the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to hi gh
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-
ment to the beginning (wrap-around) of the address
space. Once the data from address location FFFFFH
has been read, the next output will be from address
location 000 00H.
FIGURE 4-4: HIGH-SPEED-READ SEQUENCE
1296 ReadSeq_0.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
03
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 7047 48 55 56 63 64
N+2 N+3 N+4N N+1
DOUT
MSB MSB
MSB
MODE 0
MODE 3
DOUT DOUT DOUT DOUT
1.66 MHz operations occur under the conditions specified in
Table 5-6 on page 19.
1296 HSRdSeq.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.0B
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 47 48 55 56 63 64
N+2 N+3 N+4
NN+1
X
MSB
MSB
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
80
71 72
D
OUT
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)
2015 Microchip Technology Inc. DS20005045C-page 9
SST25VF080B
4.4.3 BYTE-PROGRAM
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte
must be in the erased state (FFH) when initiating a Pro-
gram operation. A Byte-Program instruction applied to a
protected memory area will be ignored.
Prior to any W rite operation, the W rite-Enable (WREN)
instruction must be executed. CE# must remain active
low for the duration of the Byte-Program instruction.
The Byte-Program instruction is initiated by executing
an 8-bit command, 02H, followed by address bits [A23-
A0]. Following the address, the data is input in order
from MSB (bit 7) to LSB (bit 0). CE# must be driven
high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait
TBP for the completion of the internal self-timed Byte-
Program operation. See Figure 4-5 for the Byte-Pro-
gram sequence.
FIGURE 4-5: BYTE-PROGRAM SEQUENCE
4.4.4 AUTO ADDRESS INCREMENT (AAI)
WORD-PROGRAM
The AAI program instruction allows multiple bytes of
data to be programmed without re-issuing the next
sequential address location. This feature decreases
total programming time when multiple bytes or entire
memory array is to be programmed. An AAI Word pro-
gram instruction pointing to a protected memory area
will be ignored. The selected address range must be in
the erased state (FFH) when initiating an AAI Word
Program operation. While within AAI Word Program-
ming sequence, only the following instructions are
valid: for software end-of-write detection—AAI Word
(ADH), WRDI (04H), and RDSR (05H); for hardware
end-of-write detection—AAI Word (ADH) and WRDI
(04H). There are three options to determine the com-
pletion of each AAI Word program cycle: hardware
detection by reading the Serial Output, software detec-
tion by polling the BUSY bit in th e software status reg-
ister, or wait TBP. Refer to“End-of-Write Detection” for
details.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. Initiate the AAI Word
Program instruction by executing an 8-bit command,
ADH, followed by address bits [A23-A0]. Following the
addresses, two bytes of data are input sequentially,
each one from MSB (Bit 7) to LSB (Bit 0). The first byte
of data (D0) is programmed into the initial address [A23-
A1] with A0=0, the second byte of Data (D1) is pro-
grammed into the initial address [A23-A1] with A0=1.
CE# must be driven high before executing the AAI
Word Program instruction. Check the BUSY status
before entering the next valid command. Once the
device indicates it is no longer busy, data for the next
two sequential addresses may be programmed, fol-
lowed by the next two, and so on.
When programming the last desired word , or th e high-
est unprotected memory address, check the busy sta-
tus using either the hardware or software (RDSR
instruction) method to check for program completion.
Once programming is complete, use the applicable
method to terminate AAI. If the device is in Software
End-of-Write Detection mode, execute the Write-Dis-
able (WRDI) instruction, 04H. If the device is in AAI
Hardware End-of-Write Detection mode, execute the
Write-Disable (WRDI) instruction, 04H, followed by the
8-bit DBSY command, 80H. There is no wrap mode
during AAI programming once the highest unprotected
memory address is reached. See Fi gures 4-8 and 4-9
for the AAI Word programming sequence.
4.4.5 END-OF-WRITE DETECTION
There are three meth ods to dete rmine co mpletion of a
program cycle during AAI Word programming: hard-
ware detection by reading the Serial Output, software
detection by polling the BUSY bit in the Software S tatus
Register, or wait TBP. The Hardware End-of-Write
detection method is described in the section below.
1296 ByteProg.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD. DIN
02
HIGH IMPEDANCE
15 16 23 24 31 32 39
MODE 0
MODE 3
MSBMSB
MSB LSB
SST25VF080B
DS20005045C-page 10 2015 Microchip Technology Inc.
4.4.6 HARDWARE END-OF-WRITE
DETECTION
The Hardware End-of-Write detection method elimi-
nates the overhead of polling the Busy bit in the Soft-
ware Status Register during an AAI Word program
operation. The 8-bit command, 70H, configures the
Serial Output (SO) pin to indicate Flash Busy status
during AAI Word programming. (see Figure 4-6) The 8-
bit command, 70H, must be executed prior to i nitiating
an AAI Word-Program instruction. Once an internal
programming operation begins, asserting CE# will
immediately drive the status of the internal flash status
on the SO pin. A ‘0’ indica tes the device is busy and a
‘1’ indicates the device is ready for the next instruction.
De-asserting CE# will return the SO pin to tri-state.
While in AAI and Hardware End-of-Write detection
mode, the only valid instructions are AAI Word (ADH)
and WRDI (04H).
To exit AAI Hardware End-of-Write detection, first exe-
cute WRDI instruction, 04H, to reset the Write-Enable-
Latch bit (WEL=0) and AAI bit. Then execute the 8-bit
DBSY command, 80H, to disable RY/BY# status during
the AAI command. See Figures 4-7 and 4-8.
FIGURE 4-6: ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
FIGURE 4-7: DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
CE#
SO
SI
SCK
01234567
70
HIGH IMPEDANCE
MODE 0
MODE 3
1296 EnableSO.0
MSB
CE#
SO
SI
SCK
01234567
80
HIGH IMPEDANCE
MODE 0
MODE 3
1296 DisableSO.0
MSB
2015 Microchip Technology Inc. DS20005045C-page 11
SST25VF080B
FIGURE 4-8: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
HARDWARE END-OF-WRITE DETECTION
FIGURE 4-9: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
SOFTWARE END-OF-WRITE DETECTION
CE#
SI
SCK
SO
1296 AAI.HW.3
Check for Flash Busy Status to load next valid
1
command
Load AAI command, Address, 2 bytes data
Note: 1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
0
AAA
AD D0 AD
MODE 3
MODE 0
D1 D2 D3
7
WREN
EBSY
07078 32 4715 16 23 24 31 04039 7 8 15 16 23
D
OUT
WRDI followed by DBSY
to exit AAI Mode
WRDI RDSR
7015
780
DBSY
70
CE# cont.
SI cont.
SCK cont.
SO cont.
Last 2
Data Bytes
AD
D
n-1 Dn
7 8 15 16 23
0
Check for Flash Busy Status to load next valid
1
command
SST25VF080B
DS20005045C-page 12 2015 Microchip Technology Inc.
4.4.7 4-KBYTE SECTOR-ERASE
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a prot ected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H, followed by address
bits [A23-A0]. Address bits [AMS-A12] (AMS =Most Sig-
nificant address) are used to determine the sector
address (SAX), remaining address bits ca n b e V IL or VIH.
CE# must be driven high before the instru ction is exe-
cuted. The user may poll the Busy bit in the software
status register or wait TSE for the completion of the
internal self-timed Sector-Erase cycle. See Figure 4-10
for the Sector-Erase sequence.
FIGURE 4-10: SECTOR-ERASE SEQUENCE
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
20
HIGH IMPEDANCE
15 16 23 24 31
MODE 0
MODE 3
1296 SecErase.0
MSBMSB
2015 Microchip Technology Inc. DS20005045C-page 13
SST25VF080B
4.4.8 32-KBYTE AND 64-KBYTE BLOCK-
ERASE
The 32-KByte Block-Erase instruction clears all bits in
the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a prot ected memory area will be
ignored. The 64-KByte Block-Erase instruction clears all bits
in the selected 64 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE # m us t r em a in
active low for the duration of any command sequ ence.
The 32-KByte Block-Erase instruction is initiated by
executing an 8-bit command, 52H, followed by address
bits [A23-A0]. Address bits [AMS-A15] (AMS = Most Sig-
nificant Address) are used to determine block a ddress
(BAX), remaining address bits can be VIL or VIH. CE#
must be driven high befo re the instruction is executed. The
64-KByte Block-Erase instruction is initiated by executing an
8-bit command D8H, followed by address bits [A23-A0].
Address bit s [AMS-A15] are used to determine block address
(BAX), re maining address bits can be VIL or VIH. CE# mu st
be driven high before the instruction is executed. T he user
may poll the Busy bit in the software status register or wait
TBE for the completion of the internal self-timed 32-
KByte Block-Erase or 64-KByte Block-Erase cycles.
See Figures 4-11 and 4-12 for the 32-KByte Block-
Erase and 64-KByte Block-Erase sequences.
FIGURE 4-11: 32-KBYTE BLOCK-ERASE SEQUENCE
FIGURE 4-12: 64-KBYTE BLOCK-ERASE SEQUENCE
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
52
HIGH IMPEDANCE
15 16 23 24 31
MODE 0
MODE 3
1296 32KBklEr.0
MSB MSB
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
D8
HIGH IMPEDANCE
15 16 23 24 31
MODE 0
MODE 3
1296 63KBlkEr.0
MSB MSB
SST25VF080B
DS20005045C-page 14 2015 Microchip Technology Inc.
4.4.9 CHIP-ERASE
The Chip-Erase instruction cle ars all bits in the devi ce
to FFH. A Chip-Erase instructio n will be ignored if any
of the memory area is pr otected. Pr ior t o any Write oper-
ation, the Write-Enable (WREN) instruction must be exe-
cuted. CE# must remain active low for the duration of
the Chip-Erase instruction sequence. The Chip-Erase
instruction is initiated by executing an 8-bit command,
60H or C7H. CE# must be driven high before the instruction
is executed. The user may poll the Busy bit in the software
status register or wait TCE for the completion of the
internal self-timed Chip-Erase cycle. See Figure 4-13
for the Chip-Erase sequence.
FIGURE 4-13: CHIP-ERASE SEQUENCE
4.4.10 READ-STATUS-REGISTER (RDSR)
The Read-Status-Register (RDSR) instruction allows
reading of the status register. The status register may
be read at any time even during a Write (Program/
Erase) operation. When a Write operation is in prog-
ress, the Busy bit may be checked before sending any
new commands to assure that the new commands are
properly received by the device. CE# must be driven
low before the RDSR instruction is entered and remain
low until the status data is read. Read-Status-R egister
is continuous with ongoing clock cycles until it is termi-
nated by a low to high transition of the CE#. See Figure
4-14 for the RDSR instruction sequence.
FIGURE 4-14: READ-STATUS-REGISTER (RDSR) SEQUENCE
CE#
SO
SI
SCK
01234567
60 or C7
HIGH IMPEDANCE
MODE 0
MODE 3
1296 ChEr.0
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1296 RDSRseq.0
MODE 3
SCK
SI
SO
CE#
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05
MODE 0
HIGH IMPEDANCE
Status
Register Out
MSB
MSB
2015 Microchip Technology Inc. DS20005045C-page 15
SST25VF080B
4.4.11 WRITE-ENABLE (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status Register to 1 allowing
Write operations to occur. The WREN instruction must
be executed prior to any Write (Program/Erase) opera-
tion. The WREN instruction ma y also be used to allow
execution of the Write-Status-Register (WRSR) instruc-
tion; however, the Write-Enable-Latch bit in the Status
Register will be cleared upon the rising edge CE# of the
WRSR instruction. CE# must be driven high before the
WREN instruction is executed.
FIGURE 4-15: WRITE ENABLE (WREN) SEQUENCE
4.4.12 WRITE-DISABLE (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new
Write operations from occurring. The WRDI instruction
will not termin ate any programming operation i n prog-
ress. Any program operation in progress may continue
up to TBP after executing the WRDI instruction. CE#
must be driven high before the WRDI instruction is exe-
cuted.
FIGURE 4-16: WRITE DISABLE (WRDI) SEQUENCE
4.4.13 ENABLE-WRITE-STATUS-
REGISTER (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction
and opens the status register for al terati on. The Write-
Status-Register instruction must be executed immedi-
ately after the execution of the Enable-Write-Status-
Register instruction. This two-step instruction
sequence of the EWSR instruction followed by the
WRSR instruction works like SDP (software data pro-
tection) command structure which prevents any acci-
dental alteration of the status register values. CE# must
be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction
is executed.
CE#
SO
SI
SCK
01234567
06
HIGH IMPEDANCE
MODE 0
MODE 3
1296 WREN.0
MSB
CE#
SO
SI
SCK
01234567
04
HIGH IMPEDANCE
MODE 0
MODE 3
1296 WRDI.0
MSB
SST25VF080B
DS20005045C-page 16 2015 Microchip Technology Inc.
4.4.14 WRITE-STATUS-REGISTER (WRSR)
The Write-Status-Register instruction writes new val-
ues to the BP3, BP2, BP1, BP0, and BPL bits of the sta-
tus register. CE# must be driven low before the
command sequence of the WRSR instruction is
entered and driven high before the WRSR instruction is
executed. See Figure 4-17 for EWSR or WREN and
WRSR instruction sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”.
When the WP# is lo w, the BPL bi t can only be set from
“0” to “1” to lock-down the status register , but cannot be
reset from “1” to “0”. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
and BP1 and BP2 bits in the status register can all be
changed. As long as BPL bit is set to 0 or WP# pin is
driven high (VIH) prior to the low-to-high transition of the
CE# pin at the end of the WRSR instruction, the bits in
the status register can all be altered by the WRSR
instruction. In this case, a single WRSR instruction can
set the BPL bit to “1” to lock down the status register as
well as altering the BP0, BP1, and BP2 bits at the same
time. See Table 4-1 for a summary description of WP#
and BPL functions.
FIGURE 4-17: ENABLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND
WRITE-STATUS-REGISTER (WRSR) SEQUENCE
4.4.15 JEDEC READ-ID
The JEDEC Read-ID instruction identifies the device as
SST25VF080B and the manufacturer as Microchip.
The device information can be read from executing the
8-bit command, 9FH. Following the JEDEC Read-ID
instruction, the 8-bit manufactu rer ’s ID, BFH, is output
from the device. After that, a 16-bit device ID is shifted
out on the SO pin. Byte 1, BFH, identifies the manufac-
turer as Microchip. Byte 2, 25H, i dentifies the memory
type as SPI Serial Flash. Byte 3, 8EH, identifies the
device as SST25VF080B. Th e instruction sequence is
shown in Figure 4 -18. Th e JEDEC R ead ID i nstru ction
is terminated by a low to high transitio n on C E# a t any
time during data output.
FIGURE 4-18: JEDEC READ-ID SEQUENCE
1296 EWSR.0
MODE 3
HIGH IMPEDANCE
MODE 0
STATUS
REGISTER IN
76543210
MSBMSBMSB
01
MODE 3
SCK
SI
SO
CE#
MODE 0
50 or 06
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TABLE 4-5: JEDEC READ-ID DATA
Manufacturer’s ID Device ID
Memory Type Memory Capacity
Byte1 Byte 2 Byte 3
BFH 25H 8EH
25 8E
1296 JEDECID.1
CE#
SO
SI
SCK
012345678
HIGH IMPEDANCE
15 1614 28 29 30 31
BF
MODE 3
MODE 0
MSBMSB
9 10111213 1718 32 34
9F
19 20 21 22 23 3324 25 26 27
2015 Microchip Technology Inc. DS20005045C-page 17
SST25VF080B
4.4.16 READ-ID (RDID)
The Read-ID instruction (RDID) identifies the devices
as SS T 25 VF 0 80 B and manufacturer as Microchip. This
command is backward compatible and should be used
as default device id entification when multiple versions
of SPI Serial Flash devices are used in a design. The
device information can be read from executing an 8-bit
command, 90H or ABH, followed by addre ss bits [A23-
A0]. Following the Read-ID instruction, the manufac-
turer’s ID is located in address 00000H and the device
ID is located in address 00001H. Once the device is in
Read-ID mode, the manufacturer’s and device ID out-
put data toggles between address 00000H and 00001H
until terminated by a low to high transition on CE#.
Refer to Tables 4-5 and 4-6 for device identification
data.
FIGURE 4-19: READ-ID SEQUENCE
TABLE 4-6: PRODUCT IDENTIFICATION
Address Data
Manufacturer’s ID 00000H BFH
Device ID
SST25VF080B 00001H 8EH
0 25045
1265 RdID.0
CE#
SO
SI
SCK
00
012345678
00 ADD1
90 or AB
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 47 48 55 56 63
BF Device ID BF Device ID
HIGH
IMPEDANCE
MODE 3
MODE 0
MSB MSB
MSB
Note: The manufacturer’s and device ID output stream is continuous until terminated by a low-to-high transition on
CE#.
Device ID = 8EH for SST25VF080B
SST25VF080B
DS20005045C-page 18 2015 Microchip Technology Inc.
5.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi-
mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these conditions or conditions greater than those defined in the operational
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
TABLE 5-1: OPERATING RANGE
Range Ambient Temp VDD
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V
TABLE 5-2: AC CONDITIONS OF TEST1
1. See Figures 5-5 and 5-6
Input Rise/Fall Time Output Load
5ns CL = 30 pF
TABLE 5-3: DC OPERATING CHARACTERISTICS
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDDR Read Current 10 mA CE#=0.1 VDD/0.9 VDD@25 MHz, SO=open
IDDR2 Read Current 15 mA CE#=0.1 VDD/0.9 VDD@50 MHz, SO=open
IDDW Program and Erase Current 30 mA CE#=VDD
ISB Standby Current 20 µA CE#=VDD, VIN=VDD or VSS
ILI Input Leakage Current AVIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current AVOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VIH Input High Vol tage 0.7 VDD VVDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOL2 Output Low Voltage 0.4 V IOL=1.6 mA, VDD=VDD Min
VOH Output High Volt age VDD-0.2 V IOH=-100 µA, VDD=VDD Min
TABLE 5-4: CAPACITANCE (TA = 25°C, F=1 MHz, OTHER PINS OPEN)
Parameter Description Test Condition Maximum
COUT1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Output Pin Capacitance VOUT = 0V 12 pF
CIN1Input Capacitance VIN = 0V 6 pF
2015 Microchip Technology Inc. DS20005045C-page 19
SST25VF080B
TABLE 5-5: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
NEND1Endurance 10,000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD mA JEDEC Standard 78
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 5-6: AC OPERATING CHARACTERISTICS
Symbol Parameter
25 MHz 50 MHz 66 MHz1,2
1. VDD = 3.0 - 3.6 V, CL = 15 pF
2. Characterized, but not fully tested
UnitsMin Max Min Max Min Max
FCLK3
3. Maximum clock frequency for Read Instruction, 03H, is 25 MHz
Serial Clock Frequency 25 50 66 MHz
TSCKH Serial Clock High Time 18 9 7 ns
TSCKL Serial Clock Low Time 18 9 7 ns
TSCKR4
4. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
Serial Clock Rise T ime (Slew
Rate) 0.1 0.1 0.1 V/ns
TSCKF Serial Clock Fall Time (Slew
Rate) 0.1 0.1 0.1 V/ns
TCES5
5. Relative to SCK.
CE# Active Setup Time 10 5 4 ns
TCEH5CE# Active Hold Time 10 5 4 ns
TCHS5CE# Not Active Setup Time 10 5 4 ns
TCHH5CE# Not Active Hold Ti me 10 5 4 ns
TCPH CE# High Time 100 50 100 ns
TCHZ CE# High to High-Z Output 15 8 6 ns
TCLZ SCK Low to Low-Z Output 000ns
TDS Data In Setup Time 522ns
TDH Data In Hold Time 553ns
THLS HOLD# Low Setup Time 10 5 4 ns
THHS HOLD# High Setup Time 10 5 4 ns
THLH HOLD# Low Hold Time 10 5 4 ns
THHH HOLD# High Hold Time 10 5 4 ns
THZ HOLD# Low to High-Z Output 20 8 8 ns
TLZ HOLD# High to Low-Z Output 15 8 8 ns
TOH Output Hold from SCK Change 000ns
TVOutput Valid from SCK 15 8 6 ns
TSE Sector-Erase 25 25 25 ms
TBE Block-Erase 25 25 25 ms
TSCE Chip-Erase 50 50 50 ms
TBP Byte-Program 10 10 10 µs
SST25VF080B
DS20005045C-page 20 2015 Microchip Technology Inc.
FIGURE 5-1: SERIAL INPUT TIMING DIAGRAM
FIGURE 5-2: SERIAL OUTPUT TIMING DIAGRAM
FIGURE 5-3: HOLD TIMING DIAGRAM
HIGH-Z HIGH-Z
CE#
SO
SI
SCK
MSB LSB
TDS TDH
TCHH TCES TCEH TCHS
TSCKR
TSCKF
TCPH
1296 SerIn.0
1296 SerOut.0
CE#
SI
SO
SCK
MSB
TCLZ
TV
TSCKH
TCHZ
TOH
TSCKL
LSB
THZ TLZ
THHH THLS THHS
1296 Hold.0
HOLD#
CE#
SCK
SO
SI
THLH
2015 Microchip Technology Inc. DS20005045C-page 21
SST25VF080B
5.1 Power-Up Specifications
All functionalities and DC specifications are specified
for a VDD ramp rate of greater than 1V per 100 ms (0v
- 3.0V in less than 300 ms). See Table 5-7 and Figure
5-4 for more information.
FIGURE 5-4: POWER-UP TIMING DIAGRAM
TABLE 5-7: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol Parameter Minimum Units
TPU-READ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
VDD Min to Read Operatio n 100 µs
TPU-WRITE1VDD Min to Wr i t e Operation 100 µs
Time
VDD Min
VDD Max
VDD
Device fully accessible
T
PU-READ
T
PU-WRITE
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
1296 PwrUp.0