REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
CMOS Dual 8-Bit
Buffered Multiplying DAC
AD7528
FEATURES
On-Chip Latches for Both DACs
+5 V to +15 V Operation
DACs Matched to 1%
Four Quadrant Multiplication
TTL/CMOS Compatible
Latch Free (Protection Schottkys not Required)
APPLICATIONS
Digital Control of:
Gain/Attenuation
Filter Parameters
Stereo Audio Circuits
X-Y Graphics
FUNCTIONAL BLOCK DIAGRAM
VREFA
AD7528
VREFB
RFB B
AGND
VDD
DB0
DB7
DATA
INPUTS
DAC A/
DAC B
CS
WR
DGND
CONTROL
LOGIC
INPUT
BUFFER LATCH
LATCH OUT B
OUT A
DAC B
DAC A
RFB A
GENERAL DESCRIPTION
The AD7528 is a monolithic dual 8-bit digital/analog converter
featuring excellent DAC-to-DAC matching. It is available in
skinny 0.3" wide 20-lead DIPs and in 20-lead surface mount
packages.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
Data is transferred into either of the two DAC data latches via a
common 8-bit TTL/CMOS compatible input port. Control
input DAC A/DAC B determines which DAC is to be loaded.
The AD7528’s load cycle is similar to the write cycle of a ran-
dom access memory and the device is bus compatible with most
8-bit microprocessors, including 6800, 8080, 8085, Z80.
The device operates from a +5 V to +15 V power supply, dis-
sipating only 20 mW of power.
Both DACs offer excellent four quadrant multiplication charac-
teristics with a separate reference input and feedback resistor for
each DAC.
PRODUCT HIGHLIGHTS
1. DAC-to-DAC matching: since both of the AD7528 DACs are
fabricated at the same time on the same chip, precise match-
ing and tracking between DAC A and DAC B is inherent.
The AD7528’s matched CMOS DACs make a whole new
range of applications circuits possible, particularly in the
audio, graphics and process control areas.
2. Small package size: combining the inputs to the on-chip DAC
latches into a common data bus and adding a DAC A/DAC B
select line has allowed the AD7528 to be packaged in either a
small 20-lead DIP, SOIC or PLCC.
ORDERING GUIDE
1
Temperature Relative Gain Package
Model
2
Ranges Accuracy Error Options
3
AD7528JN –40°C to +85°C±1 LSB ±4 LSB N-20
AD7528KN –40°C to +85°C±1/2 LSB ±2 LSB N-20
AD7528LN –40°C to +85°C±1/2 LSB ±1 LSB N-20
AD7528JP –40°C to +85°C±1 LSB ±4 LSB P-20A
AD7528KP –40°C to +85°C±1/2 LSB ±2 LSB P-20A
AD7528LP –40°C to +85°C±1/2 LSB ±1 LSB P-20A
AD7528JR –40°C to +85°C±1 LSB ±4 LSB R-20
AD7528KR –40°C to +85°C±1/2 LSB ±2 LSB R-20
AD7528LR –40°C to +85°C±1/2 LSB ±1 LSB R-20
AD7528AQ –40°C to +85°C±1 LSB ±4 LSB Q-20
AD7528BQ –40°C to +85°C±1/2 LSB ±2 LSB Q-20
AD7528CQ –40°C to +85°C±1/2 LSB ±1 LSB Q-20
AD7528SQ –55°C to +125°C±1 LSB ±4 LSB Q-20
AD7528TQ –55°C to +125°C±1/2 LSB ±2 LSB Q-20
AD7528UQ –55°C to +125°C±1/2 LSB ±1 LSB Q-20
NOTES
1
Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts
will be marked with cerdip designator “Q.”
2
Processing to MIL-STD-883C, Class B is available. To order, add suffix “/883B” to
part number. For further information, see Analog Devices’ 1990 Military Products
Databook.
3
N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
REV. B–2–
AD7528–SPECIFICATIONS
(VREF A = VREF B = +10 V; OUT A = OUT B = O V unless otherwise noted)
V
DD
= +5 V V
DD
= +15 V
Parameter Version
1
T
A
= +25°CT
MIN
, T
MAX
T
A
= +25°CT
MIN
, T
MAX
Units Test Conditions/Comments
STATIC PERFORMANCE
2
Resolution All 8 8 8 8 Bits
Relative Accuracy J, A, S ±1±1±1±1 LSB max This is an Endpoint Linearity Specification
K, B, T ±1/2 ±1/2 ±1/2 ±1/2 LSB max
L, C, U ±1/2 ±1/2 ±1/2 ±1/2 LSB max
Differential Nonlinearity All ±1±1±1±1 LSB max All Grades Guaranteed Monotonic Over
Full Operating Temperature Range
Gain Error J, A, S ±4±6±4±5 LSB max Measured Using Internal R
FB
A and R
FB
B
K, B, T ±2±4±2±3 LSB max Both DAC Latches Loaded with 11111111
L, C, U ±1±3±1±1 LSB max Gain Error is Adjustable Using Circuits
of Figures 4 and 5
Gain Temperature Coefficient
3
∆Gain/∆Temperature All ±0.007 ±0.007 ±0.0035 ±0.0035 %/°C max
Output Leakage Current
OUT A (Pin 2) All ±50 ±400 ±50 ±200 nA max DAC Latches Loaded with 00000000
OUT B (Pin 20) All ±50 ±400 ±50 ±200 nA max
Input Resistance (V
REF
A, V
REF
B) All 8 8 8 8 kΩ min Input Resistance TC = –300 ppm/°C, Typical
15 15 15 15 kΩ max Input Resistance is 11 kΩ
V
REF
A/V
REF
B Input Resistance
Match All ±1±1±1±1% max
DIGITAL INPUTS
4
Input High Voltage
V
IH
All 2.4 2.4 13.5 13.5 V min
Input Low Voltage
V
IL
All 0.8 0.8 1.5 1.5 V max
Input Current
I
IN
All ±1±10 ±1±10 µA max V
IN
= 0 or V
DD
Input Capacitance
DB0–DB7 All 10 10 10 10 pF max
WR, CS, DAC A/DAC B All 15 15 15 15 pF max
SWITCHING CHARACTERISTICS
3
See Timing Diagram
Chip Select to Write Set Up Time
t
CS
All 90 100 60 80 ns min
Chip Select to Write Hold Time
t
CH
All 0 0 10 15 ns min
DAC Select to Write Set Up Time
t
AS
All 90 100 60 80 ns min
DAC Select to Write Hold Time
t
AH
All 0 0 10 15 ns min
Data Valid to Write Set Up Time
t
DS
All 80 90 30 40 ns min
Data Valid to Write Hold Time
t
DH
All 0 0 0 0 ns min
Write Pulsewidth
t
WR
All 90 100 60 80 ns min
POWER SUPPLY See Figure 3
I
DD
All 2 2 2 2 mA max All Digital Inputs V
IL
or V
IH
All 100 500 100 500 µA max All Digital Inputs 0 V or V
DD
AC PERFORMANCE CHARACTERISTICS
5
V
DD
= +5 V V
DD
= +15 V
Parameter Version
1
T
A
= +25°CT
MIN
, T
MAX
T
A
= +25°CT
MIN
, T
MAX
Units Test Conditions/Comments
DC SUPPLY REJECTION (∆GAIN/∆V
DD
) All 0.02 0.04 0.01 0.02 % per % max ∆V
DD
= ±5%
CURRENT SETTLING TIME
2
All 350 400 180 200 ns max To 1/2 LSB. OUT A/OUT B Load = 100 Ω.
WR = CS = 0 V. DB0–DB7 = 0 V to V
DD
or
V
DD
to 0 V
PROPAGATION DELAY (From Digital In- V
REF
A = V
REF
B = +10 V
put to 90% of Final Analog Output Current) All 220 270 80 100 ns max OUT A, OUT B Load = 100 Ω C
EXT
= 13 pF
WR = CS = 0 V DB0–DB7 = 0 V to V
DD
or
V
DD
to 0 V
DIGITAL-TO-ANALOG GLITCH IMPULSE All 160 440 nV sec typ For Code Transition 00000000 to 11111111
OUTPUT CAPACITANCE
C
OUT
A All 50 50 50 50 pF max DAC Latches Loaded with 00000000
C
OUT
B 50 505050pF max
C
OUT
A 120 120 120 120 pF max DAC Latches Loaded with 11111111
C
OUT
B 120 120 120 120 pF max
AC FEEDTHROUGH
6
V
REF
A to OUT A All –70 –65 –70 –65 dB max V
REF
A, V
REF
B = 20 V p-p Sine Wave
V
REF
B to OUT B –70 –65 –70 –65 dB max @ 100 kHz
(Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as
Output Amplifiers)
PLCC
3 2 1 20 19
9 10 11 12 13
18
17
16
15
14
4
5
6
7
8
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
VREF A
DGND
DAC A/DAC B
(MSB) DB7
DB6
VREF B
VDD
WR
CS
DB0 (LSB)
AD7528
RFB A
OUT A
AGND
OUT B
RFB B
DB5
DB4
DB3
DB2
DB1
V
DD
= +5 V V
DD
= +15 V
Parameter Version
1
T
A
= +25°CT
MIN
, T
MAX
T
A
= +25°CT
MIN
, T
MAX
Units Test Conditions/Comments
CHANNEL-TO-CHANNEL ISOLATION Both DAC Latches Loaded with 11111111.
V
REF
A to OUT B All –77 –77 dB typ V
REF
A = 20 V p-p Sine Wave @ 100 kHz
V
REF
B = 0 V see Figure 6.
V
REF
B to OUT A –77 –77 dB typ V
REF
A = 20 V p-p Sine Wave @ 100 kHz
V
REF
A = 0 V see Figure 6.
DIGITAL CROSSTALK All 30 60 nV sec typ Measured for Code Transition 00000000 to
11111111
HARMONIC DISTORTlON All –85 –85 dB typ V
IN
= 6 V rms @ 1 kHz
NOTES
1
Temperature Ranges are J, K, L Versions: –40°C to +85°C
A, B, C Versions: –40°C to +85°C
S, T, U Versions: –55°C to +125°C
2
Specifications applies to both DACs in AD7528.
3
Guaranteed by design but not production tested.
4
Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA.
5
These characteristics are for design guidance only and are not subject to test.
6
Feedthrough can be further reduced by connecting the metal lid on the ceramic package
(suffix D) to DGND.
Specifications subject to change without notice.
AD7528, ideal maximum output is V
REF
– 1 LSB. Gain error of
both DACs is adjustable to zero with external resistance.
Output Capacitance
Capacitance from OUT A or OUT B to AGND.
Digital to Analog Glitch lmpulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal. Glitch impulse is measured with V
REF
A,
V
REF
B = AGND.
Propagation Delay
This is a measure of the internal delays of the circuit and is
defined as the time from a digital input change to the analog
output current reaching 90% of its final value.
Channel-to-Channel Isolation
The proportion of input signal from one DAC’s reference input
which appears at the output of the other DAC, expressed as a
ratio in dB.
Digital Crosstalk
The glitch energy transferred to the output of one converter due
to a change in digital input code to the other converter. Speci-
fied in nV secs.
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . V
DD
+ 0.3 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
PIN2
, V
PIN20
to AGND . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
A, V
REF
B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V
V
RFB
A, V
RFB
B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (J, K, L) Grades . . . . . . . . . . . –40°C to +85°C
Industrial (A, B, C) Grades . . . . . . . . . . . . –40°C to +85°C
Extended (S, T, U) Grades . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
CAUTION:
1. ESD sensitive device. The digital control inputs are diode
protected; however, permanent damage may occur on uncon-
nected devices subjected to high energy electrostatic fields.
Unused devices must be stored in conductive foam or shunts.
2. Do not insert this device into powered sockets. Remove
power before insertion or removal.
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of full scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For the
AD7528
REV. B –3–
DIP, SOIC
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD7528
DB4
DB5
DB6
OUT A
RFB A
VREF A
(MSB) DB7
DAC A/DAC B
DGND
DB3
DB2
DB1
RFB B
VREF B
VDD
DB0 (LSB)
CS
WR
AGND OUT B
AD7528
REV. B–4–
INTERFACE LOGIC INFORMATION
DAC Selection:
Both DAC latches share a common 8-bit input port. The con-
trol input DAC A/DAC B selects which DAC can accept data
from the input port.
Mode Selection:
Inputs CS and WR control the operating mode of the selected
DAC. See Mode Selection Table below.
Write Mode:
When CS and WR are both low the selected DAC is in the write
mode. The input data latches of the selected DAC are transpar-
ent and its analog output responds to activity on DB0–DB7.
Hold Mode:
The selected DAC latch retains the data which was present on
DB0–DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
Mode Selection Table
DAC A/DAC B CS WR DAC A DAC B
L L L WRITE HOLD
H L L HOLD WRITE
X H X HOLD HOLD
X X H HOLD HOLD
L = Low State; H = High State; X = Don’t Care.
WRITE CYCLE TIMING DIAGRAM
VDD
tDH
VIH
VIL
tDS
tWR
tAS tAH
tCS tCH
VDD
VDD
VDD
0
0
0
0
CHIP SELECT
DAC A/DAC B
WRITE
DATA IN
(DB0 – DB7) DATA IN STABLE
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED
FROM 10% TO 90% OF VDD.
VDD = +5V, tr = tf = 20ns;
VDD = +15V, tr = tf = 40ns;
2. TIMING MEASUREMENT REFERENCE LEVEL IS VIH + VIL
2
CIRCUIT INFORMATION—D/A SECTION
The AD7528 contains two identical 8-bit multiplying D/A con-
verters, DAC A and DAC B. Each DAC consists of a highly
stable thin film R-2R ladder and eight N-channel current steer-
ing switches. A simplified D/A circuit for DAC A is shown in
VREF A
AGND
DAC A DATA LATCHES
AND DRIVERS
2R
S1
2R
S2
2R
S3
2R
S8
2R
RRR
OUT A
RFB A
R
Figure 1. Simplified Functional Circuit for DAC A
Figure 1. An inverted R-2R ladder structure is used, that is, bi-
nary weighted currents are switched between the DAC output
and AGND thus maintaining fixed currents in each ladder leg
independent of switch state.
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows an approximate equivalent circuit for one of the
AD7528’s D/A converters, in this case DAC A. A similar
equivalent circuit can be drawn for DAC B. Note that AGND
(Pin 1) is common for both DAC A and DAC B.
The current source I
LEAKAGE
is composed of surface and junc-
tion leakages and, as with most semiconductor devices, approxi-
mately doubles every 10°C. The resistor R
O
as shown in Figure
2 is the equivalent output resistance of the device which varies
with input code (excluding all 0s code) from 0.8 R to 2 R. R is
typically 11 kΩ. C
OUT
is the capacitance due to the N-channel
switches and varies from about 50 pF to 120 pF depending
upon the digital input. g(V
REF
A, N) is the Thevenin equivalent
voltage generator due to the reference input voltage V
REF
A and
the transfer function of the R-2R ladder.
RFB A
AGND
OUT A
RO
g(VREF A, N) ILKG COUT
R
Figure 2. Equivalent Analog Output Circuit of DAC A
CIRCUIT INFORMATION–DIGITAL SECTION
The input buffers are simple CMOS inverters designed such
that when the AD7528 is operated with V
DD
= 5 V, the buffer
converts TTL input levels (2.4 V and 0.8 V) into CMOS logic
levels. When V
IN
is in the region of 2.0 volts to 3.5 volts the
input buffers operate in their linear region and pass a quiescent
current, see Figure 3. To minimize power supply currents it is
recommended that the digital input voltages be as close to the
supply rails (V
DD
and DGND) as is practically possible.
The AD7528 may be operated with any supply voltage in the
range 5 ≤ V
DD
≤ 15 volts. With V
DD
= +15 V the input logic
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
VIN – Volts
800
0
IDD mA (VDD = +5V)
1 2 3 4 5 6 7 8 9 10 11 13 1412
700
600
500
400
300
200
100
IDD mA (VDD = +15V)
9
8
7
6
5
4
3
2
1
VDD = +5V
VDD = +15V TA = +258C
ALL DIGITAL INPUTS
TIED TOGETHER
Figure 3. Typical Plots of Supply Current, I
DD
vs. Logic
Input Voltage V
IN
, for V
DD
= +5 V and +15 V
AD7528
REV. B –5–
Table I. Unipolar Binary Code Table
DAC Latch Contents Analog Output
MSB LSB (DAC A or DAC B)
1 1 1 1 1 1 1 1
–V
IN
255
256
1 0 0 0 0 0 0 1
–V
IN
129
256
1 0 0 0 0 0 0 0
–V
IN
128
256
=−V
IN
2
0 1 1 1 1 1 1 1
–V
IN
127
256
0 0 0 0 0 0 0 1
–V
IN
1
256
0 0 0 0 0 0 0 0
–V
IN
0
256
=0
Note: 1 LSB =
2
−8
()
V
IN
()
=1
256 V
IN
()
Table II. Bipolar (Offset Binary) Code Table
DAC Latch Contents Analog Output
MSB LSB (DAC A or DAC B)
1 1 1 1 1 1 1 1
+V
IN
127
128
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
–V
IN
1
128
0 0 0 0 0 0 0 1
–V
IN
127
128
0 0 0 0 0 0 0 0
–V
IN
128
128
Note: 1 LSB =
2
−7
()
V
IN
()
=1
128 V
IN
()
Table III. Recommended Trim Resistor
Values vs. Grade
Trim
Resistor J/A/S K/B/T L/C/U
R1; R3 1 k 500 200
R2; R4 330 150 82
VIN A
(± 10V)
AD7528
VIN B
(± 10V)
RFB B
AGND
VDD
DB0
DB7
DATA
INPUTS
DAC A/
DAC B
CS
WR
DGND
CONTROL
LOGIC
INPUT
BUFFER
OUT B
LATCH
R41
DAC B
C22
R31
DAC A
LATCH
VOUT B
AGND
RFB A
OUT A
R21
C12
VOUT A
AGND
R11
NOTES:
1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
2C1, C2 PHASE COMPENSATION (10pF–15pF) IS REQUIRED WHEN
USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
Figure 4. Dual DAC Unipolar Binary Operation
(2 Quadrant Multiplication); See Table I
VIN A
(± 10V)
AD7528
VIN B
(± 10V)
RFB B
AGND
VDD
DB0
DB7
DATA
INPUTS
DAC A/
DAC B
CS
WR
DGND
CONTROL
LOGIC
INPUT
BUFFER
OUT BLATCH
R41
DAC B
C23
R31
DAC A
LATCH
VOUT B
AGND
RFB A
OUT A
R21
C13
VOUT A
AGND
R11
A1
R72
10kV
R62
20kV
A2
R5
20kV
R11
5kV
AGND
R102
20kV
R92
10kV
A4
R8
20kV
R12
5kV
AGND
A3
NOTES:
1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
ADJUST R1 FOR VOUT A = 0V WITH CODE 10000000 IN DAC A LATCH.
ADJUST R3 FOR VOUT B = 0V WITH CODE 10000000 IN DAC B LATCH.
2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R6, R7 AND R9, R10.
3C1, C2 PHASE COMPENSATION (10pF–15pF) MAY BE REQUIRED
IF A1/A3 IS A HIGH SPEED AMPLIFIER.
Figure 5. Dual DAC Bipolar Operation
(4 Quadrant Multiplication); See Table II
AD7528
REV. B–6–
APPLICATIONS INFORMATION
Application Hints
To ensure system performance consistent with AD7528 specifi-
cations, careful attention must be given to the following points:
1. GENERAL GROUND MANAGEMENT: AC or transient
voltages between the AD7528 AGND and DGND can cause
noise injection into the analog output. The simplest method
of ensuring that voltages at AGND and DGND are equal is
to tie AGND and DGND together at the AD7528. In more
complex systems where the AGND–DGND intertie is on the
backplane, it is recommended that diodes be connected in
inverse parallel between the AD7528 AGND and DGND
pins (1N914 or equivalent).
2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a
code-dependent output resistance which in turn causes a
code-dependent amplifier noise gain. The effect is a code-
dependent differential nonlinearity term at the amplifier
output which depends on V
OS
(V
OS
is amplifier input offset
voltage). This differential nonlinearity term adds to the R/2R
differential nonlinearity. To maintain monotonic operation, it
is recommended that amplifier V
OS
be no greater than 10% of
1 LSB over the temperature range of interest.
3. HIGH FREQUENCY CONSIDERATIONS: The output
capacitance of a CMOS DAC works in conjunction with the
amplifier feedback resistance to add a pole to the open loop
response. This can cause ringing or oscillation. Stability can
be restored by adding a phase compensation capacitor in
parallel with the feedback resistor.
DYNAMIC PERFORMANCE
The dynamic performance of the two DACs in the AD7528 will
depend upon the gain and phase characteristics of the output
amplifiers together with the optimum choice of the PC board
layout and decoupling components. Figure 6 shows the relation
INPUT FREQUENCY – Hz
–100
ISOLATION – dB
20k 50k 100k 200k 1M500k
–90
–80
–70
–60
–50
TA = +258C
VDD = +15V
VIN = 20V PEAK TO PEAK
Figure 6. Channel-to-Channel Isolation
AGND
V+
V–
AD644
VREF B*
VDD
CS
LSB
C1 LOCATION C2 LOCATION
VREF A*
DGND
DAC A/DAC B
MSB
PIN 8 OF TO-5 CAN (AD644)
AD7528 PIN 1
WR
AD7528
*NOTE
INPUT SCREENS
TO REDUCE
FEEDTHROUGH.
LAYOUT SHOWS
COPPER SIDE
(i.e., BOTTOM VIEW).
Figure 7. Suggested PC Board Layout for AD7528 with
AD644 Dual Op Amp
ship between input frequency and channel to channel isolation.
Figure 7 shows a printed circuit layout for the AD7528 and the
AD644 dual op amp which minimizes feedthrough and crosstalk.
SINGLE SUPPLY APPLICATIONS
The AD7528 DAC R-2R ladder termination resistors are con-
nected to AGND within the device. This arrangement is par-
ticularly convenient for single supply operation because AGND
may be biased at any voltage between DGND and V
DD
. Figure
8 shows a circuit which provides two +5 V to +8 V analog out-
puts by biasing AGND +5 V up from DGND. The two DAC
reference inputs are tied together and a reference input voltage
is obtained without a buffer amplifier by making use of the
constant and matched impedances of the DAC A and DAC B
reference inputs. Current flows through the two DAC R-2R
ladders into R1 and R1 is adjusted until the V
REF
A and V
REF
B
inputs are at +2 V. The two analog output voltages range from
+5 V to +8 V for DAC codes 00000000 to 11111111.
VOUT A = +5V TO +8V
VDD
DATA
INPUTS
DAC A/DAC B
CS
WR
GND
VDD = +15V
SUGGESTED
OP AMP:
AD644
VOUT B = +5V TO +8V
R1
10kV
2 VOLTS
R2
1kV
AD584J
AD7528
DB0
DB7
DAC A
DAC B
Figure 8. AD7528 Single Supply Operation
Figure 9 shows DAC A of the AD7528 connected in a positive
reference, voltage switching mode. This configuration is useful
in that V
OUT
is the same polarity as V
IN
allowing single supply
operation. However, to retain specified linearity, V
IN
must be in
the range 0 V to +2.5 V and the output buffered or loaded with
a high impedance, see Figure 10. Note that the input voltage is
connected to the DAC OUT A and the output voltage is taken
from the DAC V
REF
A pin.
VREF A
VIN (0V TO +2.5V)
VDD
+15V
AD7528
DAC A OUT A
VOUT
Figure 9. AD7528 in Single Supply, Voltage Switching Mode
VINA – Volts
3
2.5
ERROR – LSB
3.534567
2
1
TA = +258C
VDD = +15V
4.5 5.5 6.5 7.5
NONLINEARITY
DIFFERENTIAL
NONLINEARITY
Figure 10. Typical AD7528 Performance in Single Supply
Voltage Switching Mode (K/B/T, L/C/U Grades)
AD7528
REV. B –7–
CIRCUIT EQUATIONS
CCRRR R121245== =,,
fRC
QR
R
R
R
AR
R
C
F
FBB
O
F
S
=
=×
=
1
211
3
41
π
–
NOTE
DAC Equivalent Resistance
Equals
256 ×()DAC Ladder sis ce
DAC Digital Code
Re tan
MICROPROCESSOR INTERFACE
ADDRESS BUS
A**
A + 1 **
ADDRESS
DECODE
LOGIC
DAC A/DAC B
CS DAC A
DB0
DB7
WR
VMA
f2AD7528*
DAC B
DATA BUS
D0–D7
A0–A15
CPU
6800
*ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY
**A = DECODED 7528 ADDR DAC A
A + 1 = DECODED 7528 ADDR DAC B
Figure 11. AD7528 Dual DAC to 6800 CPU Interface
Figure 12. AD7528 Dual DAC to 8085 CPU Interface
PROGRAMMABLE WINDOW COMPARATOR
VREF A
RFB A VCC
DATA
INPUTS
DAC A/DAC B
CS
WR PASS/FAIL
OUTPUT
1kV
AD7528
DB0
DB7
DAC A
DAC B
OUT A
VDD
VREF B
+VREF
RFB B
3
27
AD311
COMPARATOR
OUT B
3
27
AD311
COMPARATOR
TEST INPUT
0 TO –VREF
Figure 13. Digitally Programmable Window Comparator
(Upper and Lower Limit Detector)
PROGRAMMABLE STATE VARIABLE FILTER
In this state variable or universal filter configuration (Figure 14)
DACs A1 and B1 control the gain and Q of the filter character-
istic while DACs A2 and B2 control the cutoff frequency, f
C
.
DACs A2 and B2 must track accurately for the simple expres-
sion for f
C
to hold. This is readily accomplished by the AD7528.
Op amps are 2 × AD644. C3 compensates for the effects of op
amp gain bandwidth limitations.
DAC A/DAC B
CS WR
VIN
VDD
DB0–DB7
DATA 1
DAC B1
RF
AD7528
DAC A/DAC B
CS WR
A3
VDD
DB0–DB7
DATA 2
AD7528
A2
A1
R3
10kV
DAC A1
RSDAC A2
R1
HIGH
PASS
OUTPUT
R4
30kV
R5
30kV
C3
47pF
C1
1000pF
DAC B2
R2
A4
C2
1000pF
LOW
PASS
OUTPUT
BAND
PASS
OUTPUT
Figure 14. Digitally Controlled State Variable Filter
The filter provides low pass, high pass and band pass outputs
and is ideally suited for applications where microprocessor
control of filter parameters is required, e.g., equalizer, tone
controls, etc.
Programmable range for component values shown is f
C
= 0 kHz
to 15 kHz and Q = 0.3 to 4.5.
In the circuit of Figure 13 the AD7528 is used to implement a
programmable window comparator. DACs A and B are loaded
with the required upper and lower voltage limits for the test,
respectively. If the test input is not within the programmed
limits, the pass/fail output will indicate a fail (logic zero).
AD7528
REV. B–8–
C681e–0–9/98
PRINTED IN U.S.A.
DIGITALLY CONTROLLED DUAL TELEPHONE
ATTENUATOR
In this configuration the AD7528 functions as a 2-channel digi-
tally controlled attenuator. Ideal for stereo audio and telephone
signal level control applications. Table IV gives input codes vs.
attenuation for a 0 dB to 15.5 dB range.
Input Code = 256 ⫻ 10 exp
−
Attenuation dB,
20
VIN B
VOUT A
VIN A
DATA BUS
DAC A/DAC B
CS
WR
AD7528
DB0
DB7
DAC A
DAC B
VDD
VOUT B
A1
A2
SUGGESTED
OP AMP: AD644
Figure 15. Digitally Controlled Dual Telephone Attenuator
Table IV. Attenuation vs. DAC A, DAC B Code for the Circuit
of Figure 15
Attn. DAC Input Code In Attn. DAC Input Code In
dB Code Decimal dB Code Decimal
0.0 1 1 1 1 1 1 1 1 255 88.0 0 1 1 0 0 1 1 0 102
0.5 1 1 1 1 0 0 1 0 242 88.5 0 1 1 0 0 0 0 0 96
1.0 1 1 1 0 0 1 0 0 228 89.0 0 1 0 1 1 0 1 1 91
1.5 1 1 0 1 0 1 1 1 215 89.5 0 1 0 1 0 1 1 0 86
2.0 1 1 0 0 1 0 1 1 203 10.0 0 1 0 1 0 0 0 1 81
2.5 1 1 0 0 0 0 0 0 192 10.5 0 1 0 0 1 1 0 0 76
3.0 1 0 1 1 0 1 0 1 181 11.0 0 1 0 0 1 0 0 0 72
3.5 1 0 1 0 1 0 1 1 171 11.5 0 1 0 0 0 1 0 0 68
4.0 1 0 1 0 0 0 1 0 162 12.0 0 1 0 0 0 0 0 0 64
4.5 1 0 0 1 1 0 0 0 152 12.5 0 0 1 1 1 1 0 1 61
5.0 1 0 0 1 0 0 0 0 144 13.0 0 0 1 1 1 0 0 1 57
5.5 1 0 0 0 1 0 0 0 136 13.5 0 0 1 1 0 1 1 0 54
6.0 1 0 0 0 0 0 0 0 128 14.0 0 0 1 1 0 0 1 1 51
6.5 0 1 1 1 1 0 0 1 121 14.5 0 0 1 1 0 0 0 0 48
7.0 0 1 1 1 0 0 1 0 114 15.0 0 0 1 0 1 1 1 0 46
7.5 0 1 1 0 1 1 0 0 108 15.5 0 0 1 0 1 0 1 1 43
For further applications information the reader is referred to
Analog Devices Application Note on the AD7528.
20-Lead Cerdip (Q-20)
0.97 (24.64)
0.935 (23.75)
SEATING
PLANE
0.02 (0.5)
0.016 (0.41)
0.07 (1.78)
0.05 (1.27)
0.15 (3.8)
0.125 (3.18)
0.20 (5.0)
0.14 (3.56)
0.11 (2.79)
0.09 (2.28)
20
110
11 0.28 (7.11)
0.24 (6.1)
PIN 1
0.14 (3.56)
0.125 (3.17)
158
08
0.32 (8.128)
0.29 (7.366)
0.011 (0.28)
0.009 (0.23)
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH
LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Plastic DIP (N-20)
SEATING
PLANE
0.021 (0.533)
0.015 (0.381) 0.065 (1.66)
0.045 (1.15)
0.11 (2.79)
0.09 (2.28)
0.145 (3.683)
MIN
0.125 (3.175)
MIN
20
110
11
PIN 1
1.07 (27.18) MAX
0.255 (6.477)
0.245 (6.223) 0.32 (8.128)
0.30 (7.62)
0.011 (0.28)
0.009 (0.23)
0.135 (3.429)
0.125 (3.17)
158
08
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH
LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42
20-Lead SOIC (R-20)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10) 0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC 0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
88
08
0.0291 (0.74)
0.0098 (0.25)3 458
11
20
10
1
0.5118 (13.00)
0.4961 (12.60)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
20-Lead Plastic Leaded Chip Carrier (P-20A)
0.021 (0.53)
0.013 (0.33)
0.032 (0.81)
0.026 (0.66)
0.180 (4.47)
0.165 (4.19) 0.12 (3.05)
0.09 (2.29)
0.020 (0.51) MIN
0.025 (0.64)
MIN
0.060 (1.53)
MIN
3
PIN 1
IDENTIFIER
4
19 18
8914
13
TOP VIEW
(PINS DOWN)
0.356 (9.04)
0.350 (8.89)SQ
0.048 (1.21)
0.042 (1.07)
0.02
(0.51)
MAX
0.050
(1.27)
BSC
0.02 (0.51)
MAX
0.395 (10.02)
0.385 (9.78) SQ
Package/Price Information
CMOS Dual 8-Bit Buffered Multiplying DAC
Model Status Package
Description Pin
Count Temperature
Range Price*
(100-499)
5962-8770101RA PRODUCTION CERDIP GLASS SEAL 20 MILITARY $32.98
5962-87701022A PRODUCTION CER. LEADLESS CHIP CARRIER 20 MILITARY $53.29
5962-8770102RA PRODUCTION CERDIP GLASS SEAL 20 MILITARY $35.21
5962-87701032A PRODUCTION CER. LEADLESS CHIP CARRIER 20 MILITARY $61.32
5962-8770103RA PRODUCTION CERDIP GLASS SEAL 20 MILITARY $39.26
AD7528ACHIPS PRODUCTION CHIPS/DIE SALES 20 INDUSTRIAL $8.05
AD7528AQ PRODUCTION CERDIP GLASS SEAL 20 INDUSTRIAL -
AD7528BCHIPS PRODUCTION CHIPS/DIE SALES 20 INDUSTRIAL $8.32
AD7528BQ PRODUCTION CERDIP GLASS SEAL 20 INDUSTRIAL -
AD7528CQ PRODUCTION CERDIP GLASS SEAL 20 INDUSTRIAL -
AD7528JN PRODUCTION PLASTIC/EPOXY DIP 20 COMMERCIAL $6.19
AD7528JN/+ OBSOLETE PLASTIC/EPOXY DIP 20 COMMERCIAL -
AD7528JP PRODUCTION PLASTIC LEAD CHIP CARRIER 20 COMMERCIAL $7.07
AD7528JP-REEL PRODUCTION PLASTIC LEAD CHIP CARRIER 20 COMMERCIAL -
AD7528JR PRODUCTION STD S.O. PKG (SOIC) 20 COMMERCIAL $7.07
AD7528JR-REEL PRODUCTION STD S.O. PKG (SOIC) 20 COMMERCIAL -
AD7528JR-REEL7 PRODUCTION STD S.O. PKG (SOIC) 20 COMMERCIAL -
AD7528KN PRODUCTION PLASTIC/EPOXY DIP 20 COMMERCIAL $6.40
AD7528KP PRODUCTION PLASTIC LEAD CHIP CARRIER 20 COMMERCIAL $7.35
AD7528KP-REEL PRODUCTION PLASTIC LEAD CHIP CARRIER 20 COMMERCIAL -
AD7528LN PRODUCTION PLASTIC/EPOXY DIP 20 COMMERCIAL $10.35
AD7528LP PRODUCTION PLASTIC LEAD CHIP CARRIER 20 COMMERCIAL $11.80
AD7528LR PRODUCTION STD S.O. PKG (SOIC) 20 COMMERCIAL $11.80
* This price is provided for budgetary purposes as recommended list price in U.S. Dollars per unit in the stated volume. Pricing displayed for Evaluation
Boards and Kits is based on 1-piece pricing. View Pricing and Availability for further information.
AD7528LR-REEL PRODUCTION STD S.O. PKG (SOIC) 20 COMMERCIAL -
AD7528LRS OBSOLETE SHRINK SO PACKAGE 20 COMMERCIAL -
AD7528LRS-REEL OBSOLETE SHRINK SO PACKAGE 20 COMMERCIAL -
AD7528SCHIPS PRODUCTION CHIPS/DIE SALES 20 MILITARY $15.70
AD7528SQ PRODUCTION CERDIP GLASS SEAL 20 MILITARY -
AD7528TQ PRODUCTION CERDIP GLASS SEAL 20 MILITARY -