EiceDRIVERTM SENSE High Voltage IGBT Driver for Automotive Applications 1EDI2010AS Single Channel Isolated Driver Data Sheet Hardware Description Rev 2.0, 2017-06-19 ATV PTS HVD Edition 2017-06-19 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2017 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. EiceDRIVERTM SENSE 1EDI2010AS Revision History Page or Item Subjects (major changes since previous revision) Rev 1.3.3, 2017-01-27 Page 49 New chapter with Failure behavior 2.4.9.4 (former reset events) Page 50 Reset Events Summary table updated due to new chapter 2.4.9.4 Table 2-15 Page 22 Updated figure 2-7. Page 124 GATE pin characteristics merged in Table 5-11 with TON/TOFF characteristics. Page 124 Added test conditions in Table 5-11 for TON/TOFF & GATE pin. Page 124 Merged VPCLPG and VPCLP in Table 5-11 due to test conditions. Same for IPCLP. Page 124 Removed unprecise footnote in Table 5-11. Page 113 Updated values for weak pull down in Table 5-12. Page 128 Moved DESAT input voltage range to DESAT characteristics in Table 5-16. Page 39 Updated Links of Registers in Chapter 2.4.6.1 and 2.4.6.2. Trademarks of Infineon Technologies AG AURIXTM, C166TM, CanPAKTM, CIPOSTM, CIPURSETM, EconoPACKTM, CoolMOSTM, CoolSETTM, CORECONTROLTM, CROSSAVETM, DAVETM, EasyPIMTM, EconoBRIDGETM, EconoDUALTM, EconoPIMTM, EiceDRIVERTM, eupecTM, FCOSTM, HITFETTM, HybridPACKTM, IRFTM, ISOFACETM, IsoPACKTM, MIPAQTM, ModSTACKTM, my-dTM, NovalithICTM, OptiMOSTM, ORIGATM, PRIMARIONTM, PrimePACKTM, PrimeSTACKTM, PRO-SILTM, PROFETTM, RASICTM, ReverSaveTM, SatRICTM, SIEGETTM, SINDRIONTM, SIPMOSTM, SmartLEWISTM, SOLID FLASHTM, TEMPFETTM, thinQ!TM, TRENCHSTOPTM, TriCoreTM. Other Trademarks Advance Design SystemTM (ADS) of Agilent Technologies, AMBATM, ARMTM, MULTI-ICETM, KEILTM, PRIMECELLTM, REALVIEWTM, THUMBTM, VisionTM of ARM Limited, UK. AUTOSARTM is licensed by AUTOSAR development partnership. BluetoothTM of Bluetooth SIG Inc. CAT-iqTM of DECT Forum. COLOSSUSTM, FirstGPSTM of Trimble Navigation Ltd. EMVTM of EMVCo, LLC (Visa Holdings Inc.). EPCOSTM of Epcos AG. FLEXGOTM of Microsoft Corporation. FlexRayTM is licensed by FlexRay Consortium. HYPERTERMINALTM of Hilgraeve Incorporated. IECTM of Commission Electrotechnique Internationale. IrDATM of Infrared Data Association Corporation. ISOTM of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLABTM of MathWorks, Inc. MAXIMTM of Maxim Integrated Products, Inc. MICROTECTM, NUCLEUSTM of Mentor Graphics Corporation. MifareTM of NXP. MIPITM of MIPI Alliance, Inc. MIPSTM of MIPS Technologies, Inc., USA. muRataTM of MURATA MANUFACTURING CO., MICROWAVE OFFICETM (MWO) of Applied Wave Research Inc., OmniVisionTM of OmniVision Technologies, Inc. OpenwaveTM Openwave Systems Inc. RED HATTM Red Hat, Inc. RFMDTM RF Micro Devices, Inc. SIRIUSTM of Sirius Satellite Radio Inc. SOLARISTM of Sun Microsystems, Inc. SPANSIONTM of Spansion LLC Ltd. SymbianTM of Symbian Software Limited. TAIYO YUDENTM of Taiyo Yuden Co. TEAKLITETM of CEVA, Inc. TEKTRONIXTM of Tektronix Inc. TOKOTM of TOKO KABUSHIKI KAISHA TA. UNIXTM of X/Open Company Limited. VERILOGTM, PALLADIUMTM of Cadence Design Systems, Inc. VLYNQTM of Texas Instruments Incorporated. VXWORKSTM, WIND RIVERTM of WIND RIVER SYSTEMS, INC. ZETEXTM of Diodes Zetex Limited. Last Trademarks Update 2011-02-24 Data Sheet Hardware Description 3 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 1.1 1.2 1.3 Product Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feature Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Target Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 11 2 2.1 2.2 2.2.1 2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.4.1 2.4.4.2 2.4.4.3 2.4.4.4 2.4.4.4.1 2.4.4.4.2 2.4.4.5 2.4.4.5.1 2.4.4.5.2 2.4.4.5.3 2.4.4.5.4 2.4.4.5.5 2.4.4.5.6 2.4.4.5.7 2.4.4.5.8 2.4.4.5.9 2.4.5 2.4.5.1 2.4.5.2 2.4.5.2.1 2.4.5.2.2 2.4.5.2.3 2.4.5.3 2.4.5.4 2.4.5.5 2.4.5.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pull Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Word Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ENTER_CMODE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ENTER_VMODE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXIT_CMODE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Events and State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Emergency Turn-Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ready, Disabled, Enabled and Active State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Modes Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activating the device after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activating the device after an Event Class A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 13 13 15 15 16 17 19 20 20 20 21 23 23 24 26 28 28 28 29 29 29 30 30 30 31 31 31 32 33 33 34 34 35 35 36 37 37 38 Data Sheet Hardware Description 4 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Table of Contents 2.4.6 Driver Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.6.2 Switching Sequence Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.6.3 Passive Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.7 Fault Notifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.8 EN Signal Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.9 Internal Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.9.1 Lifesign watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.9.2 Oscillator Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.9.3 Memory Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.9.4 Hardware Failure Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.10 Reset Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11 Operation in Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1 Static Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.1 Configuration of the SPI Parity Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.2 Configuration of NFLTA and NFLTB clear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.3 Configuration of NFLTA activation in case of Boundary Check event . . . . . . . . . . . . . . . . . . . 2.4.11.1.4 Configuration of pin ADCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.5 Configuration of the STP Minimum Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.6 Configuration of the Digital Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.7 Configuration of the VBE Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.8 Clamping of DESAT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.9 Activation of the Pulse Suppressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.10 Configuration of the Verification Mode Time Out Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.11 DESAT Threshold Level Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.12 UVLO2 Threshold Level Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.13 DACLP Operating Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.14 Configuration of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.15 Configuration of the DESAT Blanking Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.16 Configuration of the OCP Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.17 Configuration of the TTOFF sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.1.18 Configuration of the TTON Delay TO Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.2 Dynamic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.11.3 Delay Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.12 Low Latency Digital Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.13 Analog Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.13.2 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.13.3 Boundary Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 44 46 46 47 48 48 48 48 49 50 51 51 51 51 51 51 52 52 52 52 52 52 52 52 52 52 53 53 53 53 53 54 54 56 56 58 59 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.3 3.3.1 3.4 3.4.1 3.4.2 3.5 60 60 61 61 63 64 65 65 66 66 67 68 Protection and Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervision Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions: Category A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions: Category B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions: Category C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shoot Through Protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions: Category D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet Hardware Description 5 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Table of Contents 3.5.1 3.5.2 3.5.3 Operation in Verification Mode and Weak Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Weak Turn On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Internal Clock Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4 4.1 4.2 4.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Primary Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Secondary Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Read / Write Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5 5.1 5.2 5.3 5.4 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9 5.5.10 5.5.11 5.5.12 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary I/O Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary I/O Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Latency Digital Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Insulation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Data Sheet Hardware Description 6 115 115 118 119 119 120 120 121 122 124 126 128 129 129 130 131 132 133 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS List of Figures List of Figures Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 2-9 Figure 2-10 Figure 2-11 Figure 2-12 Figure 2-13 Figure 2-14 Figure 2-15 Figure 2-16 Figure 2-17 Figure 2-18 Figure 2-19 Figure 2-20 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 5-1 Figure 5-2 Figure 6-1 Figure 6-2 EiceSENSE Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PWM Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STP: Inhibition Time Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STP: Example of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI Regular Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SPI Daisy Chain Bus Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Response Answer Principle - Daisy Chain Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Response Answer Principle - Regular Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI Commands Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Operating Modes State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output Stage Diagram of Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TTOFF: Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TTON: Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TTOFF: pulse suppressor aborting a turn-on sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Idealized Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Low Latency Digital Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Application Example NTC Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Application Example: Diode Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Application Example: VDCLINK Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DESAT Function: Diagram of Principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DESAT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 DESAT Operation with DESAT clamping enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 OCP Function: Principle of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Shoot Through Protection: Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Idealized Weak Turn-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Typical Application Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Recommended Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Data Sheet Hardware Description 7 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS List of Tables List of Tables Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Table 2-15 Table 2-16 Table 2-17 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 5-13 Table 5-14 Table 5-15 Table 5-16 Table 5-17 Table 5-18 Table 5-19 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Internal pull devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI Command Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Word Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ENTER_CMODE request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ENTER_VMODE request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 EXIT_CMODE request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 NOP request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 READ request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 WRITEH request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 WRITEL request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Failure Notification Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 System Supervision Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Failure Events Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Reset Events Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Pin behavior (primary side) in case of reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Pin behavior (secondary side) in case of reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Safety Related Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 DESAT Protection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 OCP Function Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 External Enable Function Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Power Supply Voltage Monitoring Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 STP Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SPI Error Detection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Primary Clock Supervision Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Register Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Bit Access Terminology . . . . . . . . . . . . . . . . . . . . . . . 72 Read Access Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Write Access Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Power Supplies Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Internal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Electrical Characteristics for Pins: INP, INSTP, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Electrical Characteristics for Pins: NRST/RDY, SCLK, SDI, NCS, DIO1 (input), ADCT . . . . . . . 122 Electrical Characteristics for Pins: SDO, DIO1 (output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Electrical Characteristics for Pins: NFLTA, NFLTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Electrical Characteristics for Pins: TON, TOFF & GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Electrical Characteristics for Pins: DEBUG, DIO2(input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Electrical Characteristics for Pins: DIO2, DACLP (Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Electrical Characteristics for Pin: AIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 DESAT characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 OCP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Digital channel characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Data Sheet Hardware Description 8 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS List of Tables Table 5-20 Table 5-21 Table 5-22 Table 5-23 SPI Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isolation Characteristics referring to IEC 60747-5-2 (VDE 0884 - 10):2006-12 . . . . . . . . . . . . . . Isolation Characteristics referring to UL 1577. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet Hardware Description 9 131 132 133 133 Rev 2.0, 2017-06-19 1EDI2010AS 1 Product Definition This color corresponds to the EiceSENSE. 1.1 Overview The 1EDI2010AS is a high-voltage IGBT gate driver designed for motor drives above 5 kW. The 1EDI2010AS is based on Infineon's Coreless Transformer (CLT) technology, providing galvanic insulation between low voltage and high voltage domains. The device has been designed to support IGBT technologies up to 1200 V. The 1EDI2010AS can be connected on the low voltage side ("primary" side) to 5 V logic. A standard SPI interface allows the logic to configure and to control the advanced functions implemented in the driver. On the high voltage side ("secondary" side), the 1EDI2010AS is dimensioned to drive an external booster stage. Short propagation delays and controlled internal tolerances lead to minimal distortion of the PWM signal. The 1EDI2010AS supports advanced functions (such as two level turn-on, two level turn-off, etc.), that can be controlled and configured via a standard SPI interface. The internal 8-bit ADC (SAR) with programmable gain and offset enables the sensing of either the DC-link voltage, the phase voltage or of the temperature sensor located on the power module (such as NTC, Temperature Diode, etc.). The digitalized value can be read via the SPI interface on the primary side. The ADC allows thus to save significant costs on system level, since it removes the need for discrete isolation ICs. The 1EDI2010AS can be used optimally with Infineon's 1EBN100XAE "EiceDRIVERTM Boost" booster stage family. 1.2 Feature Overview The following features are supported by the 1EDI2010AS: Functional Features * * * * * * * Single Channel IGBT Driver. On-chip galvanic insulation (basic insulation as per DIN EN 60747-5-2). Support of existing IGBT technologies up to 1200V. Low propagation delay and minimal PWM distortion. Support of 5 V logic levels (primary side). Supports both negative and zero Volt VEE2 supply voltage. 16-bit Standard SPI interface (up to 2 MBaud) with daisy chain support (primary side). Product Name Ordering Code Package 1EDI2010AS SP001299836 PG-DSO-36 Data Sheet Hardware Description 10 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Product Definition * * * * * * * * * * * * * * * * * * * * * * * Enable input pin (primary side). Pseudo-differential inputs for critical signals (primary side). Power-On Reset pin (primary side). Debug mode. Internal Pulse Suppressor. Fully Programmable Active Clamping Inhibit signal (secondary side). Fully programmable Two-Level Turn On (TTON). Fully programmable Two-Level Turn Off (TTOFF). 8-bit ADC with programmable offset and gain and flexible trigger mechanism. Emulated digital channel. Programmable Desaturation monitoring. Overcurrent protection with programmable threshold. Automatic Emergency Turn-Off in failure case. Undervoltage supervision of 5V and 15V supplies. Programmable UVLO2 and DESAT thresholds for MOSFET usage. Safe internal state machine. Internal lifesign watchdog. Weak turn-on. NFLTA and NFLTB notification pins for fast system response time (primary side). Individual error and status flags readable via SPI. Compatible to EiceBoost family. 36-pin PG-DSO-36 green package. Automotive qualified (as per AEC Q100). 1.3 * * * Target Applications Inverters for automotive Hybrid Electric Vehicles (HEV) and Electric Vehicles (EV). High Voltage DC/DC converter. Industrial Drive. Data Sheet Hardware Description 11 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2 Functional Description 2.1 Introduction The 1EDI2010AS is an advanced single channel IGBT driver that can also be used for driving power MOS devices. The device has been developed in order to optimize the design of high performance automotive inverters. The device is based on Infineon's Coreless Transformer Technology and consist of two chips separated by a galvanic isolation. The low voltage (primary) side can be connected to a standard 5 V logic. The high voltage (secondary) side is in the DC-link voltage domain. Internally, the data transfers are ensured by two independent communication channels. One channel is dedicated to transferring the ON and OFF information of the PWM input signal only. This channel is unidirectional (from primary to secondary). Because this channel is dedicated to the PWM information, latency time and PWM distortion are minimized. The second channel is bidirectional and is used for all the other data transfers (e.g. status information, etc). The 1EDI2010AS supports advanced functions, such as Two Level Turn-On and Two Level Turn-Off, in order to optimize the switching behavior of the IGBT. Furthermore, it supports several protection functions such as DESAT, Overcurrent protection, etc. Data Sheet Hardware Description 12 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.2 Pin Configuration and Functionality 2.2.1 Pin Configuration 1 VEE2 GND1 36 2 TON IREF1 35 3 VCC2 VCC1 34 4 TOFF INSTP 33 5 DESAT 6 GATE 7 8 INP 32 REF0 31 GND2 EN 30 IREF2 NRST/RDY 29 9 VEE2 GND1 28 10 OCP NFLTA 27 11 OCPG NFLTB 26 12 VREG ADCT 25 13 DEBUG SDO 24 14 DACLP NCS 23 15 AIP SDI 22 16 AIN SCLK 21 17 DIO2 DIO1 20 18 VEE2 GND1 19 Figure 2-1 EiceSENSE Pin Configuration Table 2-1 Pin Configuration Pin Number Symbol I/O Voltage Class Function 1,9,18 VEE2 Supply Supply Negative Power Supply1). 2 TON Output 15V Secondary Turn-On Output. 3 VCC2 Supply Supply 4 TOFF Output 15V Secondary Turn-Off Output. 5 DESAT Input 15V Secondary Desaturation Protection Input. 6 GATE Input 15V Secondary Gate Monitoring Input. 7 GND2 Ground Ground Ground. 8 IREF2 Input 5V Secondary External Reference Input. 10 OCP Input 5V Secondary Over Current Protection. 11 OCPG Ground Ground Ground for the OCP function, 12 VREG Output 5V Secondary Reference Output Voltage. 13 DEBUG Input 5V Secondary Debug Input. Data Sheet Hardware Description Positive Power Supply. 13 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description Table 2-1 Pin Configuration (cont'd) Pin Number Symbol I/O Voltage Class Function 14 DACLP Output 5V Secondary Active Clamping Disable Output. 15 AIP Input 5V Analog Secondary ADC Positive Analog Input 16 AIN Input 5V Analog Secondary ADC Negative Analog Input 17 DIO2 Input / Output 5V Secondary Digital I/O. 19, 28, 36 GND1 Ground Ground Ground2). 20 DIO1 Input / Output 5V Primary Digital I/O. 21 SCLK Input 5V Primary SPI Serial Clock Input. 22 SDI Input 5V Primary SPI Serial Data Input. 23 NCS Input 5V Primary SPI Chip Select Input (low active). 24 SDO Output 5V Primary SPI Serial Data Output. 25 ADCT Input 5V Primary ADC Trigger Input. 26 NFLTB Output 5V Primary Fault B Output (low active, open drain). 27 NFLTA Output 5V Primary Fault A Output (low active, open drain). 29 NRST/RDY Input/Output 5V Primary Reset Input (low active, open drain). This signal notifies that the device is "ready". 30 EN Input 5V Primary Enable Input. 31 REF0 Ref. Ground Ground Reference Ground for signals INP, INSTP, EN. 32 INP Input 5V Primary Positive PWM Input. 33 INSTP Input 5V Primary Monitoring PWM Input. 34 VCC1 Supply Input Supply Positive Power Supply. 35 IREF1 Input 5V Primary External Reference Input. 1) 2) All VEE2 pins must be connected together. All GND1 pins must be connected together. Data Sheet Hardware Description 14 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.2.2 Pin Functionality 2.2.2.1 Primary Side GND1 Ground connection for the primary side. VCC1 5V power supply for the primary side (referring to GND1). INP Non-inverting PWM input of the driver. The internal structure of the pad makes the IC robust against glitches. An internal weak pull-down resistor to VREF0 drives this input to Low state in case the pin is floating. INSTP Monitoring PWM input for shoot through protection. The internal structure of the pad makes the IC robust against glitches. An internal weak pull-down resistor to VREF0 drives this input to Low state in case the pin is floating. REF0 Reference Ground signal for the signals INP, INSTP, EN. This pin should be connected to the ground signal of the logic issuing those signals. EN Enable Input Signal. This signal allows the logic on the primary side to turn-off and deactivate the device. An internal weak pull-down resistor to VREF0 drives this input to Low state in case the pin is floating. NFLTA Open-Drain Output signal used to report major failure events (Event Class A). In case of an error event, NFLTA is driven to Low state. This pin shall be connected externally to VCC1 with a pull-up resistance. NFLTB Open-Drain Output signal used to report major failure events (Event Class B). In case of an error event, NFLTB is driven to Low state. This pin shall be connected externally to VCC1 with a pull-up resistance. SCLK Serial Clock Input for the SPI interface. An internal weak pull-up device to VCC1 drives this input to high state in case the pin is floating. SDO Serial Data Output (push-pull) or the SPI interface. SDI Serial Data Input for the SPI interface. An internal weak pull-up device to VCC1 drives this input to high state in case the pin is floating. Data Sheet Hardware Description 15 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description NCS Chip Select input for the SPI interface. This signal is low active. An internal weak pull-up device to VCC1 drives this input to High state in case the pin is floating. IREF1 Reference input of the primary chip. This pin shall be connected to VGND1 via an external resistor. NRST/RDY Open drain reset input. This signal is low-active. When a valid signal is received on this pin, the device is brought in its default state. This signal is also used as a "ready notification". A high level on this pin indicates that the primary chip is functional. DIO1 I/O for the digital channel. Depending of the chosen configuration of the device, this pin can be an input or an output (push-pull). An internal weak pull-down resistor to VGND1 drives this input to Low state in case the pin is floating. ADCT ADC Trigger Input. An internal weak pull-down device to VGND1 drives this input to Low state in case the pin is floating. 2.2.2.2 Secondary Side VEE2 Negative power supply for the secondary side, referring to VGND2. VCC2 Positive power supply for the secondary side, referring to VGND2. GND2 Reference ground for the secondary side. DESAT Desaturation Protection input pin. The function associated with this pin monitors the VCE voltage of the IGBT. The detection threshold is programmable. An internal pull-up resistor to VCC2 drives this signal to High level in case it is floating. OCP Over Current Protection input pin. The function associated with this pin monitors the voltage across a sensing resistance located on the auxiliary path of a Current Sense IGBT. An internal weak pull-up resistor to the internal 5V reference drives this input to High state in case the pin is floating. OCPG Over Current Protection Ground. Data Sheet Hardware Description 16 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description TON Output pin for turning on the IGBT. TOFF Output pin for turning off the IGBT. GATE Input pin used to monitor the IGBT gate voltage. DEBUG Debug input pin. This pin is latched at power-up. When a High level is detected on this pin, the device enters a special mode where it can be operated without SPI interface. This feature is for development purpose only. This pin should normally be tied to VGND2. An internal weak pull-down resistor to VGND2 drives this input to Low state in case the pin is floating. IREF2 Reference input of the secondary chip. This pin shall be connected to VGND2 via an external resistor. VREG Reference Output voltage. This pin shall be connected to an external capacitance to VGND2. DACLP Output pin used to disable the active clamping function of the booster. DIO2 I/O for the digital channel. Depending of the chosen configuration of the device, this pin can be an input or an output (push-pull). An internal weak pull-down resistor to VGND2 drives this input to Low state in case the pin is floating. AIP ADC positive analog input. AIN ADC negative analog input. 2.2.2.3 Pull Devices Some of the pins are connected internally to pull-up or pull-down devices. This is summarized in Table 2-2. Table 2-2 Internal pull devices Signal Device INP Weak pull down to VREF0 INSTP Weak pull down to VREF0 EN Weak pull down to VREF0 SCLK Weak pull up to VCC1 Data Sheet Hardware Description 17 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description Table 2-2 Internal pull devices Signal Device SDI Weak pull up to VCC1 NCS Weak pull up to VCC1 ADCT Weak pull down to VGND1 DIO1 Weak pull down to VGND1 DESAT Weak pull up to VCC2 DIO2 Weak pull down to VGND2 OCP Weak pull up to 5V internal reference DEBUG Weak pull down to VGND2 Data Sheet Hardware Description 18 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.3 Block Diagram IREF1 OSC1 WDG WDG OSC2 IREF2 VCC1 GND2 P-Supply GND1 VEE2 P-Supply INP EN/FEN INSTP VCC2 VREG PWM Input Stage DEBUG Start-Stop Osc REF0 NCS Primary SDO SPI Interface Output Stage Switching Control Secondary SDI Logic TON Logic TOFF GATE DACLP SCLK OCP OCP NFLTA OCPG NFLTB DESAT ADCT DESAT AIP ADC NRST/RDY AIN DIO1 DIO2 Figure 2-2 Block Diagram Data Sheet Hardware Description 19 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4 Functional Block Description 2.4.1 Power Supplies On the primary side, the 1EDI2010AS needs a single 5 Vsupply source VCC1 for proper operation. This makes the device compatible to most of the microcontrollers available for automotive applications. On the secondary side, the 1EDI2010AS needs two power supplies for proper operation: * * The positive power supply VCC2 is typically set to 15 V (referring to VGND2). Optionally, a negative supply VEE2 (typically set to -8 V referring to VGND2) can be used. In case a negative supply is not needed, VEE2 shall be connected to VGND2. Undervoltage monitoring on VCC1 and VCC2 is performed continuously during operation of the device (see Chapter 3.3.1). A 5V supply for the digital domain on the secondary side is generated internally (present at pin VREG). 2.4.2 Clock Domains The clock system of the 1EDI2010AS is based on three oscillators defining each a clock domain: * * * One RC oscillator (OSC1) for the primary chip. One RC oscillator (OSC2) for the secondary chip excepting the output stage. One Start-Stop oscillator (SSOSC2) for the output stage on the secondary side. The two RC oscillators are running constantly. They are also monitored constantly, and large deviations from the nominal frequency are identified as a system failure (Event Class B, see Chapter 2.4.9.2). The Start Stop oscillator is controlled by the PWM command. Data Sheet Hardware Description 20 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.3 PWM Input Stage The PWM input stage generates from the external signals INP, INSTP and EN the turn-on and turn-off commands to the secondary side. The general structure of the PWM input block is shown Figure 2-3. VCC1 EN inhibit_act. en_valid LO GIC Inhibit Time Generation INSTP Validity Check INP pwm_cmd REF0 Figure 2-3 PWM Input Stage Signals INP, INSTP and EN are pseudo-differential, in the sense that they are not referenced to the common ground GND1 but to signal REF0. This is intended to make the device more robust against ground bouncing effects. Note: Glitches shorter than tINPR1occurring at signal INP are filtered internally. Note: Pulses at INP below tINPPD might be distorted or suppressed. The 1EDI2010AS supports non-inverted PWM signals only. When a High level on pin INP is detected while signals INSTP and EN are valid, a turn-on command is issued to the secondary chip. A Low level at pin INP issues a turnoff command to the secondary chip. Signal EN can inhibit turn-on commands received at pin INP. A valid signal EN is required in order to have turnon commands issued to the secondary chip. If an invalid signal is provided, the PWM input stage issues constantly turn-off commands to the secondary chip. The functionality of signal EN is detailed in Chapter 2.4.8. Note: After an invalid-to valid-transition of signal EN, a minimum delay of tINPEN should be inserted before turning INP on. As shown in Figure 2-4, signal INSTP provides a Shoot-Through Protection (STP) to the system. When signal at pin INSTP is at High level, the internal signal inhibit_act is activated. The inhibition time is defined as the pulse duration of signal inhibit_act. It corresponds to the pulse duration of signal INSTP to which a minimum dead time is added. During the inhibition time, rising edges of signal INP are inhibited. Bit PSTAT2.STP is set for the duration of the inhibition time. The deadtime is programmable with bit field PCFG2.STPDEL. Data Sheet Hardware Description 21 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description INSTP dead time inhibit_act INP Inhibition time pwm_cmd Figure 2-4 STP: Inhibition Time Definition It shall be noted that during the inhibition time, signal pwm_cmd is not forced to Low. It means that if the device is already turned-on when INSTP is High, it stays turned-on until the signal at pin INP goes Low. This is depicted in Figure 2-5. INSTP dead time inhibit_act Inhibited edge INP pwm_cmd Inhibition time Figure 2-5 STP: Example of Operation When a condition occurs where a rising edge of signal INP is inhibited, an error notification is issued. See Chapter 3.4.1 for more details. Note: The failure notification via bit PER.STPER is filtered internally for timings shorter than 1 OSC1 clock cycle. There will be no notification but may lead to a delay of signal INP. Data Sheet Hardware Description 22 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.4 SPI Interface This chapter describes the functionality of the SPI block. 2.4.4.1 Overview The standard SPI interface implemented on the 1EDI2010AS is compatible with most of the microcontrollers available for automotive and industrial applications. The following features are supported by the SPI interface: * * * * * * Full-duplex bidirectional communication link. SPI Slave mode (only). 16-bit frame format. Daisy chain capability. MSB first. Parity Check (optional) and Parity Bit generation (LSB). The SPI interface of the 1EDI2010AS provides a standardized bidirectional communication interface to the main microcontroller. From the architectural point of view, it fulfills the following functions: * * * * Initialization of the device. Configuration of the device (static and runtime). Reading of the status of the device (static and runtime). Operation of the verification modes of the device. The purpose of the SPI interface is to exchange data which have relaxed timing constraints compared to the PWM signals (from the point of view of the motor control algorithm). The IGBT switching behavior is for example controlled directly by the PWM input. Similarly, critical application failures requiring fast reaction are notified on the primary side via the feedback signals NFLTA, NFLTB and NRST/RDY. In order to minimize the complexity of the end-application and to optimize the microcontroller's resources, the implemented interface has daisy chain capability. Several (typically 6) 1EDI2010AS devices can be combined into a single SPI bus. Data Sheet Hardware Description 23 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.4.2 General Operation The SPI interface of the 1EDI2010AS supports full duplex operation. The interface relies on four communication signals: * * * * NCS: (Not) Chip Select. SCLK: Serial Clock. SDI: Serial Data In. SDO: Serial Data Out. The SPI interface of the 1EDI2010AS supports slave operation only. An SPI master (typically, the main microcontroller) is connected to one or several 1EDI2010AS devices, forming an SPI bus. Several bus topologies are supported. A regular SPI bus topology can be used where each of the slaves is controlled by an individual chip select signal (Figure 2-6). In this case, the number of slaves on the bus is only limited by the application's constraints. SCLK Master SCLK SDO SDI SDI SDO NCS1 NCS Slave 1 NCS2 SCLK ... SDI NCSn Slave 2 ... SDO NCS ... ... ... SCLK SDI Slave n SDO NCS Figure 2-6 SPI Regular Bus Topology In order to simplify the layout of the PCB and to reduce the number of pins used on the microcontroller's side, a daisy chain topology can also be used. The chain's depth is not limited by the 1EDI2010AS itself. A possible topology is shown Figure 2-7. Data Sheet Hardware Description 24 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description SCLK Master SCLK SDO SDI SDI SDO NCS NCS Slave 1 SCLK SDI Slave 2 ... SDO NCS ... ... SCLK ... SDI Slave n SDO NCS Figure 2-7 SPI Daisy Chain Bus Topology Physical Layer The SPI interface relies on two shift registers: * * A shift output register, reacting on the rising edges of SCLK. A shift input register, reacting on the falling edges of SCLK. When signal NCS is inactive, the signals at pins SCLK and SDI are ignored. The output SDO is in tristate. When NCS is activated, the shift output register is updated internally with the value requested by the previous SPI access. At each rising edge of the SCLK signal (while NCS is active), the shift output register is serially shifted out by one bit on the SDO pin (MSB first). At each falling edge of the clock pulse, the data bit available at the input SDI is latched and serially shifted into the shift input register. At the deactivation of NCS, the SPI logic checks how many rising and falling edges of the SCLK signal have been received. In case both counts differ and / or are not a multiple of 16, an SPI Error is generated. The SPI block then checks the validity of the received 16-bit word. In case of a non valid data, an SPI error is generated. In case no error is detected, the data is decoded by the internal logic. The NCS signal is active low. Input Debouncing Filters The input stages of signals SDI, SCLK, and NCS include each a Debouncing Filter. The input signals are that way filtered from glitches and noise. The input signals SDI and SCLK are analyzed at each edge of the internal clock derived from OSC1. If the same external signal value is sampled three times consecutively, the signal is considered as valid and is processed by the SPI logic. Otherwise, the transition is considered as a glitch and is discarded. Data Sheet Hardware Description 25 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description The input signal NCS is sampled at a rate corresponding to the period of the internal clock derived from OSC1. If the same external signal value is sampled two times consecutively, the signal is considered as valid and is processed by the SPI logic. Otherwise, the transition is considered as a glitch and is discarded. 2.4.4.3 Definitions Command A command is a high-level command issued by the SPI master which aims at generating a specific reaction in the addressed slave. The command is physically translated into a Request Message by the SPI master. The correct reception of the Request Message by the SPI slave leads to a specific action inside the slave and to the emission of an Answer Message by the slave. Example: the READ command leads to the transfer of the value of the specified register from the device to the SPI master. Word A word is a 16-bit sequence of shifted data bits. Transfer A transfer is defined as the SPI data transfers (in both directions) occurring between a falling edge of NCS and the next consecutive rising edge of NCS. Request Message A request message is a word issued by the SPI master and addressing a single slave. A request message relates to a specific command. Answer Message An answer message is a well-defined word issued by a single SPI slave as a response to a request message. Transmit Frame A transmit frame is a sequence of one or several words sent by the SPI Master within one SPI transfer. In regular SPI topologies, a transmit frame is in practice identical to a data word. In daisy chain topologies, a transmit frame is a sequence of data words belonging to different request messages. Receive Frame A receive frame is a sequence of one or several words received by the SPI Master within one SPI transfer. In regular SPI topologies, a receive frame is in practice identical to a data word. In daisy chain topologies, a receive frame is a sequence of data words belonging to different Answer Messages. The SPI protocol supported by the 1EDI2010AS is based on the Request / Answer principle. The master sends a defined request message to which the slave answers with the corresponding answer message (Figure 2-8, Figure 2-9). Due to the nature of the SPI interface, the Answer Message is shifted, compared to the Request Message, by one SPI transfer. It means, for example, that the last word of answer message n is transmitted by the slave while the master sends the first word of request message n+1. Data Sheet Hardware Description 26 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description Transfer ... inactive Chip Select NCS active Word i Transmit Frame Master Serial Output (seen at SDI) ... RM1 ... ... RM2 ... ... ... RMn Wn ... ... AM2 ... ... ... ... ... AMn ... Request Message for Slave i Receive Frame Master Serial Input (seen at SDO) ... ... ... ... AM1 ... ... Answer Message of Slave i Figure 2-8 Response Answer Principle - Daisy Chain Topology Transfer ... inactive Chip Select NCS for Slave i Master Serial Output (seen at SDI) active Transmit Frame Request Message RM1 RM2 ... ... RMn Word Master Serial Input (seen at SDO) ... AM1 AM2 ... AMn Answer Meassage Receive Frame Figure 2-9 Response Answer Principle - Regular Topology The first word transmitted by the device after power-up is the content of register PSTAT. Data Sheet Hardware Description 27 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.4.4 2.4.4.4.1 SPI Data Integrity Support Parity Bit By default, the SPI link relies on an odd parity protection scheme for each transmitted or received 16-bit word of the SPI message. The parity bit corresponds to the LSB of the 16-bit word. Therefore, the effective payload of a 16-bit word is 15 data bit (plus one parity bit). The parity bit check (on the received data) can be disabled by clearing bit PCFG.PAREN. In this case, the parity bit is considered as "don't care". The generation of the parity bit by the driver for transmitted words can not be disabled (but can be considered as "don't care" by the SPI master). Note: For fixed value commands (ENTER_CMODE, ENTER_VMODE, EXIT_CMODE, NOP), it has to be ensured that the value of the parity bit is correct even if parity check is disabled. Otherwise, an SPI error will be generated. 2.4.4.4.2 SPI Error When the device is not able to process an incoming request message, an SPI error is generated: the received message is discarded by the driver, bit PER.SPIERis set and the erroneous message is answered with an error notification (bit LMI set). Several failures generate an SPI error: * * * * * A parity error is detected on the received word. An invalid data word format is received (e.g. not a 16 bit word). A word is received, which does not corresponding to a valid Request Message. A command is received which can not be processed. For example, the driver receives in Active Mode a command which is only valid in other operating modes. Another typical example is a read access to the secondary while the previous read access is not yet completed (device "busy"). An SPI access to an invalid address. Data Sheet Hardware Description 28 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.4.5 Protocol Description 2.4.4.5.1 Command Catalog Table 2-3 gives an overview of the command catalog supported by the device. The full description of the commands and of the corresponding request and answer messages is provided in the following sections. Table 2-3 SPI Command Catalog Acronym Short Description Valid in Mode ENTER_CMODE Enters into Configuration Mode. OPM0, OPM1 ENTER_VMODE Enters into Verification Mode. OPM2 EXIT_CMODE Leaves Configuration Mode to enter into Configured Mode. OPM2 READ Reads the register value at the specified address. All NOP Triggers no action in the device (equivalent to a "nop"). All WRITEH Update the most significant byte of the internal write buffer. All WRITEL Updates the least significant byte of the internal write buffer, and All (with restrictions) copies the contents of the complete buffer into the addressed register. The write buffer is cleared afterwards. An overview of the commands is given Figure 2-10. Message ENTER_CMODE ENTER_VMODE EXIT_CMODE NOP READ WRITEH WRITEL 0 0 0 0 0 0 1 Command 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 0 0 0 A4 0 A4 0 0 0 1 A3 1 A3 0 0 1 0 A2 0 A2 0 1 0 0 A1 D15 A1 1 0 0 0 A0 D14 A0 Data 0 1 0 0 0 D13 D7 0 0 1 0 1 D12 D6 0 0 0 1 0 D11 D5 0 0 0 0 1 D10 D4 0 0 0 0 0 D9 D3 0 0 0 0 1 D8 D2 P 0 0 0 0 X X X Figure 2-10 SPI Commands Overview 2.4.4.5.2 Word Convention In order to simplify the description of the SPI commands, the following conventions are used (Table 2-4). Table 2-4 Word Convention Acronym Value Va(REGISTER) Value of register REGISTER PB Parity Bit Data Sheet Hardware Description 29 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description Table 2-4 Word Convention (cont'd) Acronym Value <<n Left shift operation of n bits. xH | yH Result of the operation: xH OR yH 2.4.4.5.3 ENTER_CMODE Command The goal of this function is to set the device into Configuration Mode. After reception of a valid ENTER_CMODE command, mode OPM2 is active. This command is only valid in Default Mode (OPM0 and OPM1). In case the request message is received while OPM1 is not active, the complete command is discarded and an SPI error occurs. Table 2-5 describes the request message and the corresponding answer message. Table 2-5 ENTER_CMODE request and answer messages Transfer 1 Transfer 2 Request message 1880H N.a. Answer message N.a. Va(PSTAT) 2.4.4.5.4 ENTER_VMODE Command The goal of this function is to set the device into Verification Mode. After reception of a valid ENTER_VMODE command, mode OPM5 is active. This command is only valid in Configuration Mode (OPM2). In case the request message is received while OPM2 is not active, the complete command is discarded and an SPI error occurs. Table 2-6 describes the request message and the corresponding answer message. Table 2-6 ENTER_VMODE request and answer messages Transfer 1 Transfer 2 Request message 1140H N.a. Answer message N.a. Va(PSTAT) 2.4.4.5.5 EXIT_CMODE Command When a valid EXIT_CMODE is received by the device, the Configuration Mode is left to Configured Mode (Mode OPM3 active). This command is only valid in Configuration Mode (OPM2). In case the request message is received while OPM2 is not active, the complete command is discardedand an SPI error occurs. Table 2-7 describes the request message and the corresponding answer message. Table 2-7 EXIT_CMODE request and answer messages Transfer 1 Transfer 2 Request message 1220H N.a. Answer message N.a. Va(PSTAT) Data Sheet Hardware Description 30 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.4.5.6 NOP Command This command triggers no specific action in the driver (equivalent to a "nop"). However, the mechanisms verifying the validity of the word are active. This command is valid in all operating modes. Table 2-8 describes the request message and the corresponding answer message. Table 2-8 NOP request and answer messages Transfer 1 Transfer 2 Request message 1410H N.a. Answer message N.a. Va(PSTAT) 2.4.4.5.7 READ Command This command aims at reading the value of the register whose address is specified in the request message. This command is valid in all operating modes. However, in OPM4 and OPM6, the use of the READ command is restricted (see Table 4-4). If an access outside the allowed address range is performed, the access is discarded as invalid and an SPI error occurs. Table 2-9 describes the request message and the corresponding answer message. Table 2-9 READ request and answer messages Transfer 1 Transfer 2 Request message See below N.a. Answer message N.a. Va(Register) Request message words Word 1: ( ADDRESS_5BIT << 7 )] | 002AH | PB. Answer message words Word 1: Value of REGISTER. 2.4.4.5.8 WRITEH This command aims at writing the upper byte of the internal write buffer with the specified value. This command has no other effect on the functionality of the device. This command is valid in all operating modes. Table 2-10 describes the request message and the corresponding answer message. Table 2-10 WRITEH request and answer messages Transfer 1 Transfer 2 Request message See below N.a. Answer message N.a. Va(PSTAT) Request message words Word 1: 4400H | ( DATA_8BIT << 1 ) | PB Data Sheet Hardware Description 31 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.4.5.9 WRITEL This command aims at updating the value of the register whose address is specified in the request message. This command is valid in all operating modes. However, depending on the active operating mode, this command is restricted to a given address range or specific registers (see Table 4-5). If an access outside the allowed address range is performed, the access is discarded as invalid and an SPI error occurs. At the reception of this command, the least significant byte of the internal buffer is written with the specified value, the contents of the buffer is copied to the register at the specified address and the complete write buffer is cleared. Table 2-11 describes the request message and the corresponding answer message. Table 2-11 WRITEL request and answer messages Transfer 1 Transfer 2 Request message See below N.a. Answer message N.a. Va(PSTAT) Request message words Word 1: A000H | ( ADDRESS_5BIT << 7 ) | ( DATA_6BIT << 1 ) | PB. Data Sheet Hardware Description 32 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.5 Operating Modes 2.4.5.1 General Operation At any time, the driver can be in one out of seven possible operating modes: * * * * * * * OPM0: Default Mode (default after reset, device is disabled). OPM1: Error Mode (reached after Event Class B, device is disabled). OPM2: Configuration Mode (device is disabled, configuration of the device can be modified). OPM3: Configured Mode (device is configured and disabled). OPM4: Active Mode (normal operation). OPM5: Verification mode (intrusive diagnostic functions can be triggered). OPM6: Weak active mode (the device can be turned on but with restrictions) The current active mode of the device is given by bit field SSTAT.OPMS. The concept of the device is based on the following general ideas: * * * The driver can only switch the IGBT on when OPM4 mode is active (exception: weak-turn on in OPM6). Starting from Mode OPM0 or OPM1, the Active Mode OPM4 can only be activated through a dedicated SPI command sequence and the activation of the hardware signal EN. As a result, the probability that the device goes to OPM4 mode due to random signals is negligible. Differentiations of errors: different classes of errors are defined, leading to different behavior of the device. The state diagram for the operating modes is given in Figure 2-11: Event Class B Event Class B All Reset Events Reset Event Event Class B Reset Event Event Class A OPM0 Default Reset Event EN TE R _ CM E" OD VM _ R N TE E OD E" OPM5 Verification OPM6 Weak Active EN Valid Transition OPM2 Configuration CLRS set OPM1 Error EN E" OD CM _ TE R EX Event Class A IT _ C MO DE " Event Class B OPM3 Configured OPM4 Active EN Valid Transition All Event Class B Reset Event Event Class B Reset Event Event Class B Reset Event Figure 2-11 Operating Modes State Diagram Data Sheet Hardware Description 33 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.5.2 Definitions 2.4.5.2.1 Events and State Transitions The transitions from one state to the other are based on "events" and / or SPI commands. The following classification is chosen for defining the events. Events Class A The following (exhaustive) list of events are defined as Events Class A: * * * * Occurrence of a DESAT event (leads to a safe turn-off sequence). Occurrence of an OCP event (leads to a safe turn-off sequence). Valid to Invalid transition on EN signal (leads to a regular turn-off sequence). ADC Boundary Check Violation Event (optional, can be disabled). When an Event Class A occurs, the output stage either initiates either a safe turn-off sequence (DESAT, OCP) or a regular turn-off sequence (all other events).The event is notified via an error bit in the corresponding register. Note: Contrarily to a reset event, an Event Class A does not affect the contents of the configuration registers. When an Event Class A occurs, the device may change its operating mode depending on which mode is active when the event occurs: * * If it was in OPM4, it goes in OPM3. If it was in OPM6, it goes in OPM5. In all other cases, the OPM is unaffected. A state transition due to an Event Class A leads to the activation of signal NFLTA. If no state transition occurs (if for example the device was not in OPM4 or OPM6), NFLTA is not activated (exception: ADC Boundary Check event - see Chapter 2.4.7 for more details on failure notifications). Events Class B The following (exhaustive) list of events are defined as Events Class B: * * Occurrence of a UVLO2 event. Verification Mode Time Out Error When an Event Class B occurs, the output stage initiates a regular turn-off sequence. The event is notified via an error bit in the corresponding register and (possibly) via the signal NFLTB. Note: Events Class B may affect the contents of the configuration registers. When an Event Class B occurs, the device may change its operating mode depending on which mode is active when the event occurs: if it was not in OPM1, it goes to OPM1. It is unaffected otherwise A state transition due to an Event Class B leads to the activation of signal NFLTB. If no state transition occurs (if for example the device was already in OPM1), NFLTB is not activated. See Chapter 2.4.7 for more details on failure notifications. Events Class C Generally speaking, Events Class C are error events that do not lead to a change of the operating mode of the device. The following (non-exhaustive) list of events is comprised within the Event Class C: * * * SPI Error. Shoot Through Protection error. Etc. Data Sheet Hardware Description 34 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description SPI Commands The following SPI commands have an impact on the device's operating mode. The SPI commands are described in Chapter 2.4.4.5. * * * * ENTER_CMODE. ENTER_VMODE. EXIT_CMODE. Setting of bit SCTRL.CLRS (by writing register PCTRL) Reset Events A reset sets the device (or part of the device) in its default state. Reset events are described in Chapter 2.4.10. Internal Supervision Error are leading to a reset event, for example. 2.4.5.2.2 Emergency Turn-Off Sequence The denomination "Emergency Turn-Off Sequence" (ETO) is used to describe the sequence of actions executed by the output stage of the device when an Event Class A, Class B or a Reset Event is detected. An ETO sequence is described by the following set of actions: * * A Turn-Off sequence is initiated. In case of DESAT or OCP event, a safe turn-off sequence is initiated. For the other events, a regular turn-off sequence is initiated. The device enters the corresponding OPM mode. As a consequence, the device is disabled. Once an ETO has been initiated, the device can not be reenabled for a maximum duration consisting of 256 OSC2 clock cycles. Consequently, the user shall wait for this duration before reenabling the device and sending PWM turn-on command. 2.4.5.2.3 Ready, Disabled, Enabled and Active State The device is said to be in Ready state in case no reset event is active on the primary chip. When the device is Ready, signal NRST/RDY is at High level. When the device is in Disabled State, the PWM turn-on commands are ignored. This means that whatever the input signal INP is, the output stage (if not tristated) delivers a constant turn-off signal to the IGBT. Unless otherwise stated, all other functions of the device work normally. When the device is not in Disabled State, it is said to be in Enabled State. In this case, the PWM signal command is processed normally (if the output stage is not tristated). Practically, the device is in Enabled State when either Mode OPM4 or Mode OPM6 is active. Active State corresponds to the normal operating state of the device. Practically, the device is in Active State when Mode OPM4 is active. Note: When the device is in Active State, it implicates it is in Enabled state. Data Sheet Hardware Description 35 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.5.3 Operation Modes Description Default Mode (OPM0) Mode OPM0 is the default operating mode of the device after power up or after a rest event. In OPM0, the device is in Disabled State. The following exhaustive list of events bring the device in OPM0 Mode: * * Occurrence of a Reset Event. Bit SCTRL.CLRS set while the device was in OPM1. Error Mode (OPM1) Mode OPM1 is the operating mode of the device after an Event Class B. The following exhaustive list of events bring the device in OPM1 Mode: * Occurrence of an Event Class B. In OPM1, when bit SCTRL.CLRS is set via the corresponding SPI command, the device shall normally jump to OPM0. However, in case the conditions for an Event Class B are met at that moment, no state transition occurs and the device stays in OPM1. The operation of bit SCTRL.CLRS on the secondary sticky bits works normally. In OPM1, when a valid ENTER_CMODE command is received, the device shall normally jump to OPM2. However, in case the conditions for an Event Class B are met at that moment, no state transition occurs and the device stays in OPM1 for the duration of the event. The state transition to OPM2 is executed as soon as the conditions leading to the Event Class B disappear.It shall be noted that no LMI error notification is issued. Configuration Mode (OPM2) Configuration Mode is the mode where the configuration of the device can be modified. When OPM2 is active, the device is in Disabled State. The following exhaustive list of events bring the device in Configuration Mode: * Reception of a valid ENTER_CMODE command while Mode OPM0 or OPM1 active. Configured Mode (OPM3) Configured Mode is the mode where the device is ready to be enabled. When OPM3 is active, the device is in Disabled State. The following exhaustive list of events bring the device in Mode OPM3: * * Reception of a valid EXIT_CMODE command while Mode OPM2 active. Event Class A while Mode OPM4 active. Active Mode (OPM4) The Active Mode corresponds to the normal operating mode of the device. When OPM4 is active, the device is in Active State. The following exhaustive list of event bring the device in Active Mode: * Invalid to Valid Transition on signal EN while Mode OPM3 active. Data Sheet Hardware Description 36 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description Verification Mode (OPM5) Verification Mode is the mode where intrusive verification functions can be started. When OPM5 is active, the device is in disabled state. The following exhaustive list of event bring the device in Verification Mode: * * Reception of a valid ENTER_VMODE command while Mode OPM2 active. Occurrence of an Event Class A while Mode OPM6 active. After a transition from Mode OPM2 to OPM5, an internal watchdog timer is started. If after time tVMTO, the device has not left both modes OPM5 or OPM6, a time-out event occurs and an Event Class B is generated. Weak Active Mode (OPM6) Weak Active Mode is the mode where the device can be activated to run diagnosis tests at system level. When OPM6 is active, the device is in Enabled State. A PWM turn-on command issues a Weak Turn-On on the secondary side. The following exhaustive list of event bring the device in Weak Active Mode: * Invalid to Valid Transition on signal EN while Mode OPM5 active. The watchdog counter started when entering Mode OPM5 is not reset when entering OPM6. Implementation Notes related to State Transitions * * * An Event Class A or Class B detected on the secondary side lead to an immediate reaction of the device's output stage. Due to the latency of the inter-chip communication, the notification on the primary side is slightly delayed. The activation of signal NFLTA or NFLTB is simultaneous to the corresponding state transition on the primary side. It is possible to change the operating mode while a failure condition is present. This may however lead to a new immediate error notification and state transition. 2.4.5.4 Activating the device after reset After a reset event, the device is in Mode OPM0 and disabled. In order to be active, the device needs to enter Configuration Mode with the ENTER_CMODE command. Once all the configurations have been performed, the Configuration Mode has to be exited with an EXIT_CMODE command. Once this is done, the device can enter the Active Mode when Invalid to Valid transition on pin EN is detected. 2.4.5.5 Activating the device after an Event Class A or B If during operation, an Event Class A occurs, the device enters the OPM3 (or OPM5). Bit field SSTAT.OPMS is updated accordingly. In order to reactivate the device, an invalid-to-valid transition has to be applied to signal EN. It means for example in EN Mode, that a Low-level and then a High level is applied to EN. If no Event Class A event is active, the device will enter OPM4 (respectively OPM6). If during operation, an Event Class B occurs, the device enters the Default Mode OPM1. Bit field SSTAT.OPMS is updated accordingly. In order to reactivate the device, the steps defined in Chapter 2.4.5.4 need to be performed. Data Sheet Hardware Description 37 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.5.6 Debug Mode The DEBUG pin gives the possibility to operate the device in the so-called Debug Mode. The goal of the Debug Mode is to operate the device without SPI interface. This mode should be used for development purpose only and is not intended to be used in final applications. At VCC2 power-on, the level at pin DEBUG is latched. In case a High level is detected, the device enters the Debug Mode. Bit SSTAT.DBG is then set. In Debug Mode, the regular operation of the internal state machine is modified, so that the device can only enter OPM3 or OPM4. As a result Modes OPM0, OPM1, OPM2, OPM5 and OPM6 are completely bypassed. In case of a Reset event, the device goes to OPM3 (instead of OPM0). Besides, in Debug Mode, events leading normally to an Event Class B are replaced an Event Class A, resulting in the activation of signal NFLTA. Event Class B are therefore not generated by the device in Debug Mode (and signal NFLTB shall not be used). It should be noted that the configuration of the device in Debug Mode corresponds to the default settings and can not be changed. In Debug Mode, the operation of the device is otherwise similar to regular operation. It means in particular that the signal EN has to be managed properly: when the device is in OPM3, a Low to High level transition has to be applied to the device in order to enter OPM4 (Active Mode). Note: Once it has been latched at power-on, the level on the pin DEBUG has no impact on the device until the next power-on event on the secondary side. Data Sheet Hardware Description 38 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.6 Driver Functionality The structure of the output stage and its associated external booster of the device is depicted Figure 2-12: VCC2 TON GATE VCC2 TONI TOFFI ACLI TONO R on TOFFO EiceDRIVERTM Sense/Lite EiceDRIVERTM Boost TOFF Rof f ASC DACLP DACLP GND2 VEE2 VEE2 GND2 Figure 2-12 Output Stage Diagram of Principle 2.4.6.1 Overview Two turn-off behaviors are supported by the device, depending on the event causing the turn-off action. * * Regular Turn-Off. Safe Turn-Off. A Safe Turn-Off sequence uses the timing and plateau level parameters defined in register SSTTOF. It is triggered by a DESAT or an OCP event only. A turn-off sequence which is not "Safe" is then "Regular". A Regular Turn-Off sequence uses the timing parameters defined in register SRTTOF and the plateau level defined by PCTRL2.GPOF. Two Level Turn-Off (TTOFF) Because a hard turn-off may generate a critical overvoltage on the IGBT leading eventually to its destruction, the 1EDI2010AS supports the Two Level Turn-Off functionality (TTOFF). The TTOFF function consists in switching the IGBT off in three steps in such a way that: 1. The IGBT gate voltage is first decreased with a reduced slew rate until a specific (and programmable) voltage is reached by the TOFF signal. 2. TOFF (and TON) voltage is stabilized at this level. The IGBT Gate voltage forms thus a plateau. 3. Finally, the switch-off sequence is resumed using hard commutation. The TTOFF delays and plateau voltage are fully programmable using the corresponding SPI commands. For a Regular Turn-Off sequence, the TTOFF delay is defined by bit field SRTTOF.RTVAL. Setting this field to 00H completely disables the TTOFF function for all Regular Turn-Off sequences (but this has no effect on Safe TurnOff sequences). The plateau level is defined by PCTRL2.GPOF. If this function is to be activated, a minimum value Data Sheet Hardware Description 39 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description for the delay time has to be programmed. Too small delays will not be visible as plateau on the output signal, may changes just the slew rate from VCC2 to plateau. For a Safe Turn-Off sequence, the TTOFF delay is defined by bit field SSTTOF.STVAL. Setting this field to 00H completely disables the TTOFF function for all Safe Turn-Off sequences (but this has no effect on Regular TurnOff sequences). If this function is to be activated, a minimum value for the delay time has to be programmed. The plateau level is defined by SSTTOF.GPS. The timing of a Safe Turn-Off event is in the clock domain of the main secondary oscillator (OSC2). The timing of a Regular Turn-Off event is in the clock domain of the Start-Stop Oscillator (SSOSC2), leading to high accuracy and low PWM distortion When using the TTOFF function (with a non-zero delay), the PWM command is received on pin INP is delayed by the programmed delay time (Figure 2-13). For pulses larger than the TTOFF delay (tPULSE > tTTOFF+two SSOSC cycles), the output pulse width is kept identical to the input pulse width. For smaller pulses (tPULSE < tTTOFF+2 two SSOSC cycles), the output pulse is identical to the programmed delay. The minimum pulse width delivered by the device to the IGBT is therefore the programmed delay time extended by two SSOSC cycles. The device allows for external booster voltage compensation at the IGBT gate. When bit SCFG.VBEC is cleared, the voltage at TOFF at the plateau corresponds to the programmed value. When bit SCFG.VBEC is set, an additional VBE (base emitter junction voltage of an internal pn diode) is substracted to the programmed voltage at TOFF in order to compensate for the VBE of an external booster. Data Sheet Hardware Description 40 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description a) t PULSE < t TTOFF + 2. t SSOSC Input Pulse t PDON 2. tSSOSC t TTOFF t TTOFF TTOFF Plateau Output Pulse b) tPULSE > tTTOFF + 2. tSSOSC Input Pulse tPDOFF t PDON tTTOFF tTTOFF Output Pulse tPULSE Figure 2-13 TTOFF: Principle of Operation Two Level Turn-On (TTON) In order to increase EM compatibility and the efficiency of the whole system, the 1EDI2010AS supports the Two Level Turn-On functionality (TTON). The TTON function consists in switching the IGBT on in three steps in such a way that: 1. The IGBT gate voltage is first increased until a specific (and programmable) voltage is reached by the TON signal. 2. TON (and TOFF) voltage is stabilized at this level. The IGBT Gate voltage forms thus a plateau. 3. Finally, the switch-on sequence is resumed up to the maximum output voltage. The TTON feature needs to be activated by configuring the delay with bit field STTON.TTONVAL. Data Sheet Hardware Description 41 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description The plateau voltage level can be configured during run time by updating bit field PCTRL.GPON. This bit field can also be programmed to a value generating a hard turn-on. When using the TTON function (with a non-zero delay), the PWM command is received on pin INP is not delayed by the programmed TTON delay time (Figure 2-14). However, the minimum pulse width that can be generated corresponds to the programmed TTON delay. Thus, for input pulses smaller than the TTON delay (tPULSE < tTTON), the output pulse width is extended. The device allows for external booster voltage compensation at the IGBT gate. When bit SCFG.VBEC is cleared, the voltage at TON at the plateau corresponds to the programmed value. When bit SCFG.VBEC is set, an additional VBE (base emitter junction voltage of an internal pn diode) is added to the programmed voltage at TON in order to compensate for the VBE of an external booster. The TON and TTOFF functions can be used simultaneously. a) tPULSE < tTTON Input Pulse t PDON TTON Plateau Output Pulse t TTON b) t PULSE > tTTON Input Pulse tPDOFF t PDON tTTON Output Pulse tPULSE Figure 2-14 TTON: Principle of Operation Data Sheet Hardware Description 42 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description Pulse Suppressor In order to increase the device's robustness against external disturbances, a pulse suppressor can be enabled by setting bit SCFG.PSEN. Register SRTTOF shall also programmed with a value higher than 2H. When a PWM turnon sequence occurs, the activation of the output stage is delayed by the programmed TTOFF number of cycles, as for a normal TTOFF sequence. However, the PWM command received by the secondary chip signal is internally sampled at every SSOSC cycle before the actual turn-on command is executed by the output stage. If at least one of the sampling point does not detect a high level, the turn-on sequence is aborted and the device is not switched on. In case a valid PWM ON command is detected by the secondary side after the decision point the previous sequence has been aborted, a new turn-on sequence is initiated. One of the consequence of activating the pulse suppressor is that all PWM pulses shorter than the programmed TTOFF plateau time are filtered out (Figure 2-15). Note: The Pulse Suppressor only acts on turn-on pulses, not on turn-off pulses. t PULSE < tTTOFF + 0.5 . t SSOSC SCFG.PSEN=1b Input Pulse Pulse filtered out Output Pulse Figure 2-15 TTOFF: pulse suppressor aborting a turn-on sequence Data Sheet Hardware Description 43 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.6.2 Switching Sequence Description Figure 2-16 shows an idealized switching sequence. When a valid turn-on command is detected, a certain propagation time tPDON is needed by the logic to transfer the PWM command to the secondary side. At this point the TTOFF delay time tTTOFF defined by bit field SRTTOF.RTVAL is added before the turn-on command is executed. Signal TON is then activated, while signal TOFF is deactivated. In case the two level turn-on function is active, signal TON is increased up to the plateau voltage defined by bit field PCTRL.GPON. The duration tTTON between the beginning of the turn-on sequence and the moment where the switching sequence is resumed is defined by bit field STTON.TTONVAL. When a valid turn-off command is detected, a certain propagation time tDOFF is needed by the command to be processed by the logic on the secondary side. This propagation time depends on the event having generated the turn-off action (non exhaustive list): * * * * * In case of a PWM turn-off command at pin INP, tDOFF=tPDOFF. In case of a DESAT Event, tDOFF=tOFFDESAT2. In case of an OCP event, tDOFF=tOFFOCP2. In case of an Event Class A on the primary side: tDOFF=tOFFCLA. In case of an Event Class B on the secondary side: tDOFF=tOFFCLB2. When the turn-off command is processed by the logic, signals TON and TOFF are decreased with the slew rate tSLEW fixed by hardware. Once the voltage at pin TOFF has reached the value defined by bit field PCTRL2.GPOF (or SSTTOF.GPS in the case of a safe turn-off), the turn-off sequence is interrupted. Time tTTOFF is defined as the moment when the device starts turning off signal TOFF, and the moment where the turn-off sequence is resumed. Depending on the event that triggered the turn-off sequence, tTTOFF is given by either bit field SRTTOF.RTVAL or SSTTOF.STVAL. Once the TTOFF time has elapsed, a hard commutation takes place, and signals TON and TOFF are driven to VEE2. Note: Once a turn-off sequence is started, it is completed to the end with the same delay parameters. Signal DACLP can be activated by configuring bit field SCFG.DACLC. At the moment when the hard commutation takes place, signal DACLP remains deactivated for time tACL fixed by hardware. When this time is elapsed, signal DACLP is reactivated (i.e. active clamping is disabled). The voltage level at pin DACLP can be read at bit SSTAT2.DACL Data Sheet Hardware Description 44 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description Turn-On event VTON tPDON Turn-Off event tTTOFF t DOFF t TTON ~ ~ VCC2 VEE2 ~ ~ VCC2 time tTTOFF VTOFF VEE2 time VGATE ~ ~ VCC2 VGPOFx VGPONx VEE2 time VDACLP ~ ~ 5V tACL GND2 time Figure 2-16 Idealized Switching Sequence Data Sheet Hardware Description 45 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.6.3 Passive Clamping When the secondary chip is not supplied, signals TOFF, TON and GATE are clamped to VEE2. The GATE pin is the sensing pin for this clamping and should be not overstressed. See "Electrical Characteristic" section for the electrical capability of this feature. 2.4.7 Fault Notifications The device provides two kinds of fault notification mechanisms: * * Pins NFLTA, NFLTB and NRST/RDY allow for fast error notification to the main microcontroller. All signals are active low. Error bits can be read by SPI. The activation of signal NRST/RDY is associated with Reset Events (see Chapter 2.4.10). The activation of signal NFLTA is associated with Class A Events. The activation of signal NFLTB is associated with Class B Events. In general the activation of signal NFLTA or NFLTB is linked to a state transition of the state machine. Handling Events Class A and B If an Event Class A occurs that leads to a state transition (from OPM4 to OPM3 or OPM6 to OPM5), signal NFLTA is activated. In case an Event Class A occurs that does not lead to a state transition, NFLTA is not activated (exception: ADC boundary check events). However, the corresponding error bit in register PER or SER is set. ADC Boundary Check events are handled in a special way. In case bit SCFG2.ACAEN is set, an ADC Boundary Check event leads to an Event Class A: an Emergency (regular) turn-off sequence is issued, and possibly a transition of the state machine and the activation of NFLTA. Bit SSTAT.FLTAS (and resultingly bit PSTAT2.FLTAP) is set as long as bits SADC.AOVS or SADC.AUVS is set. In case bit SCFG2.ACAEN is cleared, an ADC Boundary Check event does not lead to a transition of the state machine (NFLTA is not activated). Besides, no Emergency Turn-Off sequence is initiated. However, bit SER.AUVER and / or SER.AOVER is set. Therefore, when bit SCFG2.ACAEN is cleared, the ADC Boundary Check mechanism behaves like an Event Class C. Additionally, signal NFLTA can be activated directly by the status bits related to boundary check on the primary side.This allows to have signal NFLTA activated in any OPM mode in case of ADC Boundary Check Events. If bit PCFG.ADAEN is set, NFLTA is activated at the transition of bit PSTAT2.AXVP from 0B to 1B. If an Event Class B occurs that leads to a state transition (to OPM1), signal NFLTB is activated. In case an Event Class B occurs that does not lead to a state transition, NFLTB is not activated. However, the corresponding error bit in register PER or SER is set. The level issued by the device on pins NFLTA and NFLTB is given by bits PSTAT2.FLTA and PSTAT2.FLTB. The levels read by the device at those pins is given by bits PPIN.NFLTAL and PPIN.NFLTBL. In case a condition leading to an Event Class A is detected by the device, bit PSTAT2.FLTAP is set. In case a condition leading to an Event Class B is detected by the device, bit PSTAT2.FLTBP is set. Note: In case of short events (e.g. Desat or OCP event), it might not be possible to observe a change of the state of bits PSTAT2.FLTAP or FLTBP. Clearing Fault Notifications Table 2-12 summarizes how fault notifications are cleared: Data Sheet Hardware Description 46 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description Table 2-12 Failure Notification Clearing PCTRL.CLRP set PCTRL.CLRS set 1) EN Invalid to Valid transition NFLTA / B signals Primary Sticky Bits Secondary Sticky Bits De-assertion Cleared - - Cleared - - De-assertion 2) 1) If the device is in OPM1, setting bit SCTRL.CLRS leads to a transition to OPM0 2) Only in OPM3 and OPM5. In other Operating Modes, no de-assertion is done. A CLRP command (i.e. setting bit PCTRL.CLRP) clears all sticky bits on the primary side. A CLRS command (i.e. setting bit PCTRL.CLRS) clears all sticky bits on the secondary side. Signals NFLTA and NFLTB are de-asserted with an invalid to valid transition of signal EN. Besides, they can be de-asserted by a CLRP command, depending on the device' status. s * 2.4.8 EN Signal Pin The EN signal allows the logic on the primary side to have a direct control on the state of the device. A valid signal has to be provided on this pin. A valid to invalid transition of the signal on pin EN generates an Event Class A. Pin EN should be driven actively by the external circuit. In case this pin is floating, an internal weak pull-down resistor ensures that the signal is low. Note: It should be noted that even if the signal at pin EN is valid, the device can still be in disabled state. This may happen for example if another error is being detected A valid EN signal is defined as a digital High level. When EN is at Low level, the signal is considered as not valid and the device is in Disabled State. In case of a High-to-Low transition, an Event Class A is generated. An Invalid to Valid transition of signal EN deactivates signals NFLTA and NFLTB (when the device is in OPM3 or OPM5 only). The levels read by the device at pin EN is given by bits PPIN.ENL. The validity status of EN signal is given by bit PSTAT2.ENVAL. Data Sheet Hardware Description 47 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.9 Internal Supervision The Internal Supervision functionality is summarized in Table 2-13: Table 2-13 System Supervision Overview Parameter Short Description Function Monitoring of the key internal functions of the chip. Periodicity Continuous. Action in case of failure event See below Programmability No. The primary and secondary chips are equipped with internal verification mechanisms ensuring that the key functions of the device are operating correctly. The internal blocks which are supervised are listed below: * * * Lifesign watchdog: mutual verification of the response of both chips (both primary and secondary). Oscillators (both primary and secondary, including open / short detection on signals IREF1). Memory error (both primary and secondary). 2.4.9.1 Lifesign watchdog The primary and the secondary chips monitor each other by the mean of a lifesign signal. The periodicity of the lifesign is typically tLS. Each chip expects a lifesign from its counterpart within a given time window. In case a lifesign error is detected by a chip, a reset event is generated on both sides (lead to OPM0) as well as NFLTB pin is set. Due to the communication loss on both sides both bits PER.CERP and SER.CERS are set. Note: Bits PER.CERP and SER.CERS indicate a loss of communication event. The current status of the internal communication is indicated by bit PSTAT.SRDY. 2.4.9.2 Oscillator Monitoring The main oscillators on the primary and on the secondary side are monitored continuously. Two distinct mechanisms are used for this purpose: * * Lifesign Watchdog allows to detect significant deviations from the nominal frequency (both primary and secondary, see above). Open / short detection on pin IREF1. In case a failure is detected on pin IREF1, the primary chip is kept in reset state for the duration of the failure and signal NRST/RDY is asserted, This leads to the detection of a lifesign error by the secondary chip, generating thus an reset event. 2.4.9.3 Memory Supervision The configuration parameters of the device, stored in the registers, are protected with a parity bit protection mechanism. Both primary and secondary chips are protected (refer to Chapter 4). In case a failure is detected on the primary chip, it is kept in reset state, and both signal NRST/RDY and NFLTB are asserted. The secondary side initiates an Emergency (Regular) Turn-Off sequence. In case a memory failure is detected by the secondary chip, an Emergency (Regular) Turn-Off sequence is initiated. The secondary chip is kept in reset state for the duration of the failure. This leads to the detection of a lifesign error by the primary chip, generating thus an reset event. Data Sheet Hardware Description 48 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.9.4 Hardware Failure Behavior The internal supervision function can detect several failures which could lead to primary or secondary chip hold on (stay in reset). Failures which can be detected are mentioned in the table below. The supervision functions described in the chapters before will lead to this behavior. Table 2-14 Failure Events Summary Failure Event Primary Secondary Notification (primary) OSC1 not starting at power-up Reset Soft Reset * * * * IREF1 shorted to ground or open Reset Soft Reset * * * * Memory error on primary Reset Soft Reset * * * * OSC2 not starting at power-up - Hard Reset * * OSC2 misfunction during operation - Soft Reset * * VREG shorted to ground - Hard Reset * * Memory error on secondary - Hard Reset * * Data Sheet Hardware Description Notification (secondary) * NRST/RDY Low (driven by device during event). Bit PER.RSTP set (once * OSC1 valid again). Bit PER.CERP is not set. NFLTB activated at the end of the reset event. Bit SER.CERS set (in case of lifesign lost). Output Stage issues a PWM OFF command. * NRST/RDY Low (driven by device during event). Bit PER.RSTP set (once * IREF1 valid again). Bit PER.CERP is not set. NFLTB activated at the end of the reset event. Bit SER.CERS set (in case of lifesign lost). Output Stage issues a PWM OFF command. * NRST/RDY Low (driven by device during event). Bit PER.RSTP set (when * failure condition is removed). Bit PER.CERP is not set. NFLTB activated at the end of the reset event. Bit SER.CERS set (in case of lifesign lost). Output Stage issues a PWM OFF command. NFLTB activated, bit * PER.CERP set. Bit PSTAT.SRDY cleared Output Stage issues a PWM OFF command. * NFLTB activated, bit PER.CERP set. Bit PSTAT.SRDY cleared for the duration of the failure. Output Stage issues a PWM OFF command. NFLTB activated, bit * PER.CERP set. Bit PSTAT.SRDY cleared. * Output Stage issues a PWM OFF command. Bit SER.RSTS (once VCC2 valid again). * NFLTB activated, bit PER.CERP set. Bit PSTAT.SRDY cleared. Output Stage issues a PWM OFF command. 49 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.10 Reset Events A reset event sets the device and its internal logic in the default configuration. All user-defined settings are overwritten with the default values. The list of reset events and their effect is summarized in Table 2-15. Table 2-15 Reset Events Summary Reset Event Primary NRST/RDY input Reset signal active (driven externally) Secondary Notification (primary) Soft Reset * * * * UVLO1 Event Reset Soft Reset * * * * VCC2 reset event (communication loss due to voltage breakdown on VCC2 ) - Hard Reset * * Notification (secondary) * NRST/RDY Low (during event). * Bit PER.RSTEP and PER.RSTP set. Bit PER.CERP is not set. NFLTB activated at the end of the reset event. Bit SER.CERS set (in case of lifesign lost). Output Stage issues a PWM OFF command. NRST/RDY Low (driven * by device during event). Bit PER.RSTP set (once * VCC1 valid again). Bit PER.CERP is not set. NFLTB activated at the end of the reset event. Bit SER.CERS set (in case of lifesign lost). Output Stage issues a PWM OFF command. * NFLTB activated, bit PER.CERP set. Bit PSTAT.SRDY cleared * for the duration of the failure. Bit SER.RSTS (once VCC2 valid again). Output Stage issues a PWM OFF command. All reset events set the device in Mode OPM0. In a soft reset, the logic works further, but the registers use the default values. In case of a reset condition on the primary side, the behavior of the pin of the device is defined in Table 2-16. Table 2-16 Pin behavior (primary side) in case of reset condition Pin Output Level SDO Tristate NFLTB Low NFLTA Low NRST/RDY Low (GND1) Comments In case of a hard reset condition on the secondary side, the behavior of the pin of the device is defined in Table 2-17. Table 2-17 Pin behavior (secondary side) in case of reset condition Pin Output Level Comments TON Low (VEE2) Passive Clamping TOFF Low (VEE2) Passive Clamping DESAT Low (GND2) Clamped. Data Sheet Hardware Description 50 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description Table 2-17 Pin behavior (secondary side) in case of reset condition Pin Output Level Comments GATE Low (VEE2) Passive Clamping DACLP High (5V) 2.4.11 Operation in Configuration Mode This section describes the mechanisms to configure the device. 2.4.11.1 Static Configuration Parameters Static parameters can configured when the device is in Mode OPM2 by writing the appropriate configuration register. Once Mode OPM2 is left with the SPI Command EXIT_CMODE, the configuration parameters are frozen on both primary and secondary chips. This means in particular that write accesses to the corresponding registers are invalidated. This prevents static configurations to be modified during runtime. Besides, the configuration parameters on the primary and secondary side are protected with a memory protection mechanism. In case the values are not consistent, a Reset Event and / or an Event Class B is generated. 2.4.11.1.1 Configuration of the SPI Parity Check The SPI interface supports by default an odd parity check. The Parity Check mechanism (active at the reception of an SPI word) can be disabled by setting bit PCFG.PAREN to 0B. Setting bit PAREN to 1B enables the Parity Check. Parity Bit Generation for the transmitter can not be disabled. 2.4.11.1.2 Configuration of NFLTA and NFLTB clear mode The reaction of signals NFLTA and NFLTB to a clear primary command is defined by the values of respectively bits PCFG.CLFAM and PCFG.CLFBM. See Chapter 2.4.7 for more details. 2.4.11.1.3 Configuration of NFLTA activation in case of Boundary Check event Signal NFLTA is normally activated by a state transition of the internal state machine. However, it can also be configured to be activated in relation with bit PSTAT2.AXVP. This is configured thanks to bit PCFG.ADAEN. 2.4.11.1.4 Configuration of pin ADCT Signal ADCT can be used as a trigger source for the ADC on the secondary side. If PCFG.ADTEN is cleared, the voltage read on the pin is ignored by the device. If PCFG.ADTEN is set, an ADC conversion is triggered at a rising edge detected at pin ADCT. Data Sheet Hardware Description 51 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.11.1.5 Configuration of the STP Minimum Dead Time The minimum dead time for the Shoot-Through Protection can be programmed by writing bit field PCFG2.STPDEL. The value programmed corresponds to a number of OSC1 clock cycles. 2.4.11.1.6 Configuration of the Digital Channel The direction of pin can be programmed by writing bit field PCFG2.DIO1. The direction of pin DIO2 can be programmed by writing bit field SCFG.DIO2C. 2.4.11.1.7 Configuration of the VBE Compensation The VBE compensation of signal TON and TOFF can be activated or deactivated by writing bit SCFG.VBEC. See Chapter 2.4.6 for more details. 2.4.11.1.8 Clamping of DESAT pin By setting bit SCFG.DSTCEN, the DESAT signal is clamped to VGND2 while the output stage of the device issues a PWM OFF command and during blanking time periods. By clearing bit SCFG.DSTCEN, the DESAT clamping is only activated during blanking time periods. 2.4.11.1.9 Activation of the Pulse Suppressor The pulse suppressor function is associated with the TTOFF function and can be activated by setting bit SCFG.PSEN. When activated, SRTTOF.RTVAL shall be programmed with a minimum value. 2.4.11.1.10 Configuration of the Verification Mode Time Out Duration The duration of the time out in verification mode is selectable via bit SCFG.TOSEN. 2.4.11.1.11 DESAT Threshold Level Configuration The detection level of the DESAT comparator is selectable via bit SCFG.DSATLS. 2.4.11.1.12 UVLO2 Threshold Level Configuration The detection levels of the UVLO2 comparators are selectable via bit SCFG.UVLO2S. 2.4.11.1.13 DACLP Operating Mode Configuration The operating mode of pin DACLP is selectable via bit field SCFG.DACLC. 2.4.11.1.14 Configuration of the ADC The configuration of the ADC is selectable by writing register SCFG2. The limits of the boundary checker are selectable by writing register SBC. Note: Registers SCFG2 and SBC can only be written if bit SCFG.CFG2 is set to 1B. Data Sheet Hardware Description 52 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.11.1.15 Configuration of the DESAT Blanking Time The blanking time for the DESAT protection can be configured by writing bit field SDESAT.DSATBT. A minimum value for the blanking time has to be programmed. Note: The programmed OCP blanking time shall be smaller than the programmed DESAT blanking time. 2.4.11.1.16 Configuration of the OCP Function The blanking time for the OCP protection can be configured by writing bit field SOCP.OCPBT. Programming 0H deactivates the blanking time feature. In case a blanking time is required, a minimum value for the delay has to be programmed. The detection level of the OCP comparator is selectable via bit SCFG.OCPLS. Note: The programmed OCP blanking time shall be smaller than the programmed DESAT blanking time. 2.4.11.1.17 Configuration of the TTOFF sequences The TTOFF delays for Regular and Safe Turn-Off sequences can be programmed separately by writing registers SRTTOF or SSTTOF. The delay for Regular Turn-Off can also be configured using the Timing Calibration Feature. Programming 0H as a delay value disables the TTOFF for the concerned Turn-Off Sequence. Hard turn-off are performed instead. In case the TTOFF function is wished, a minimum value for the delay has to be programmed. When safe two level turn-off is used (non zero delay) in normal operating mode (OPM4), the programmed safe turn-off delay value shall be higher than the programmed regular two level turn of delay. The plateau level for safe two level turn off sequences can be programmed with bit field SSTTOF.GPS. The plateau level value for safe turn-off sequences shall be lower than the one selected for regular turn-off sequences. The regular TTOFF delay can be calibrated using the TCF feature of the device. 2.4.11.1.18 Configuration of the TTON Delay TO Update The TTON delay can be configured by writing bit field STTON.TTONVAL. Programming 0H as a delay value disables the TTON for all turn-on sequences. Hard turn-on are performed instead. In case the TTON function is wished, a minimum value for the delay has to be programmed. The TTON delay can be calibrated using the TCF feature of the device. 2.4.11.2 Dynamic Configuration The TTOFF (regular turn-off only) plateau level can be modified during runtime by writing bit field PCTRL2.GPOF. The value of this bit field is periodically transferred to the secondary side. The last valid received value by the primary side is available at bit field PSTAT.GPOFP. The value currently used by the secondary chip is available at bit field SCTRL.GPOFS. Similarly, The WTO and the TTON plateau level can be configured by writing bit field PCTRL.GPON. The value of this bit field is periodically transferred to the secondary side. The last valid received value by the primary side is available at bit field PSTAT.GPONP. The value currently used by the secondary chip is available at bit field SCTRL.GPONS. The plateau value stored in the device at the beginning of the corresponding switching sequence is latched and active until the upper next switching sequence. Data Sheet Hardware Description 53 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.11.3 Delay Calibration In order to compensate for timing errors due to part-to-part variations, a dedicated Timing Calibration Feature (TCF) has been implemented. The TCF works in such a way that the PWM input signal is used to start and stop a counter clocked by the Start-Stop Oscillator of the Output Stage. As a result, the following delays and timing can be configured that way: * * TTOFF delay for Regular Turn-Off. TTON delay. The TCF allows to compensate for part to part variations of the frequency of the Start-Stop oscillator. This results in better accuracy for application critical timing. Device specific variations, e.g. temperature related, are not compensated though. The TCF can be activated or deactivated in Configuration Mode by writing bit field SSCR.VFS2. The device shall then be set in OPM6 and the PWM signal applied. Details about the TCF operation are given in Chapter 3.5.3. 2.4.12 Low Latency Digital Channel The low latency digital channel aims at providing an alternative to discrete galvanic isolators. Digital signals can be transmitted through pins DIO1 and DIO2. The direction of the channel is given by bit field PCFG2.DIO1 and SCFG.DIO2C. The functionality of the channel is shown Figure 2-17. Data Sheet Hardware Description 54 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description DIO1 Output, DIO2 Input DIO2 tDSP tDSP DIO1 time DIO1 Input, DIO2 Output DIO1 tDPS tDPS DIO2 time Figure 2-17 Low Latency Digital Channel The voltage level at pin DIO1 can be read at bit PPIN.DIO1L. The voltage level at pin DIO2 can be read at bit SSTAT2.DIO2L. The input stages of signals DIO1 and DIO2 include each a Debouncing Filter. The input signals are that way filtered from glitches and noise. Data Sheet Hardware Description 55 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.13 Analog Digital Converter 2.4.13.1 Overview The key properties of the built-in ADC on the secondary side are: * * * * * * Successive Approximation method. 0V to 5 V input signal (input buffer). 8-bit resolution. Fast conversion time. Preamplifier with programmable gain. Selectable offset. The ADC operates by the method of the successive approximation. The ADC offers a flexible analog measurement capability, which fulfills the following functions (non exhaustive list): * * * Measurement of a NTC resistor located on the power module (Figure 2-18). Measurement of a temperature diode integrated into the IGBT (Figure 2-19). Measurement of the high voltage DC-Link or phase voltage (Figure 2-20). Device VINT ADCT IAIPCS AIP ADC Logic NTC GAINi VOFFSETi AIN GND Figure 2-18 Application Example NTC Measurement . Data Sheet Hardware Description 56 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description Device IAIPCS VINT ADCT AIP ADC Logic GAINi VOFFSETi AIN GND Figure 2-19 Application Example: Diode Measurement . VDCLINK Device IAIPCS=0 VINT ADCT AIP ADC Logic GAINi VOFFSETi AIN GND Figure 2-20 Application Example: VDCLINK Measurement Note: The internal current source can be disabled by writing 0 to bit SCFG2.ACSS. Data Sheet Hardware Description 57 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.13.2 General Operation When it receives a valid trigger, the ADC samples the voltage provided by the input buffer.The result of the conversion is stored as a 8-bit value. The input buffer captures the voltage VAIP -VAIN. 0V (VAIP = VAIN) is converted as digital value 00H by the ADC. The conversion voltage range depends on the programmed gain of the input buffer. For example, if GAIN = 1 and VOFFi = 0V is programmed, VAIP -VAIN = 2.75V corresponds to digital value FFH. Once the conversion is completed, bit field SADC.ADCVAL is updated and bit SADC.AVFS is set. This Valid Flag can be cleared by SPI by a CLRS command. In case a trigger is received while a conversion is already in progress, any new conversion request is ignored until the running conversion is completed. Since the ADC can be assigned (statically) to different functions by the application, several operating modes can be chosen from in order to suit each of those specific roles. The configuration of the operating mode is done via the SPI interface. Trigger Sources In order to start a conversion, several trigger sources are available. Primary trigger source enable to trigger a conversion via * * a direct SPI write command via pin ADCT. In addition, trigger sources can be activated on the secondary side depending on the configuration of bit field SCFG2.ATS: * * Periodic trigger mode: in this mode, conversions are started automatically by the ADC at a periodical rate. The conversion period is fixed internally by design (parameter tATRIG). PWM trigger mode: in this mode, conversions are triggered by a PWM edge (rising or falling selectable). When the corresponding PWM signal is detected on the secondary side, a trigger is generated to the ADC after the delay programmed in bit field SCFG2.PWMD. The reference point for which the delay is started is the hard transition (ON or OFF). Operation Mode By setting SCFG2.ACSS, a current source can be activated that delivers a fixed current to pin AIP. Gain and Offset Configuration The gain and offset of the differential input buffer is configurable statically with bit fields SCFG2.AGS and SCFG2.AOS. Mathematical Model The following formula can be used to calculate a converted digital value from the voltage at the ADC input pins: VALDIG = (VAIP -VAIN -VOFFi) * GAINi * 255/VINT, where: (2.1) VINT is the internal ADC voltage. VALDIG is the digital value delivered by the ADC (from 0 to 255). VAIP is the voltage at pin AIP. VAIN is the voltage at pin AIN. VOFFi is the offset value selected by bit field SCFG2.AOS. GAINi is the gain value selected by bit field SCFG2.AGS. Data Sheet Hardware Description 58 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Functional Description 2.4.13.3 Boundary Check The Boundary Check mechanism automatically compares each conversion result to two boundary values. The result of the conversion is compared to the limits specified by bit fields SBC.LCB1A (lower limit) and LCB1B (upper limit). When a new conversion result is available, the result is compared with the boundary values stored in register SBC. The values used for the comparison are respectively SBC.LCB1A extended by the LSBs 0B0B (i.e.: (LCB1A <<2) & FCH ) and SBC.LCB1B extended by the LSBs 1B1B (ie: (LCB1B << 2) | 03H ). In case the conversion result is below each of the boundaries, error flag SER.AUVER is set. In case the conversion result is above each of the boundaries, error flag SER.AOVER is set. In case the conversion result is above or equal one boundary and below or equal the other boundary, no flag is set. (If lower and upper limit are programmed in the other way around the device gives wrong limit cross notifications .) The default limits are chosen such that the flags are never set whatever the conversion result is (equivalent to disabling the limit check). The failure reaction of the device to a Boundary Check event can be programed with bit SCFG2.ADAEN. Data Sheet Hardware Description 59 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Protection and Diagnostics 3 Protection and Diagnostics This section can describes the safety relevant functions implemented in the 1EDI2010AS. 3.1 Supervision Overview The 1EDI2010AS driver provides extended supervision functions, in order to support safety strategies on system level. Table 3-1 gives an overview of the implemented functions. Table 3-1 Safety Related Functions Protection Feature Description Cate- Comments gory DESAT Monitoring of the collector-emitter voltage of the IGBT A in ON state. See Chapter 3.2.1 OCP Monitoring of the current on the IGBT's auxiliary emitter A path. See Chapter 3.2.2 External Enable Fast deactivation via an external Enable signal on the A primary. See Chapter 3.2.3 ADC Boundary Check ADC Boundary Check A See Chapter 2.4.13.3 Power Supply Monitoring Under Voltage Lock-Out function on VCC1, VCC2. B See Chapter 3.3.1 STP Shoot Through Protection. C See Chapter 3.4.1 SPI Error Detection SPI Error Detection. C See Chapter 3.4.2 WTO Weak Turn-On Functionality D See Chapter 3.5.2 Internal Clock Supervision Plausibility check of the frequency of the internal oscillator. D See Chapter 3.5.3 TTOFF Two Level Turn-Off E See Chapter 2.4.6 SPI Communication SPI Communication (using register PRW). E See Chapter 4.1 E See Chapter 5.2 Overvoltage robustness Robustness against transient overvoltage on power supply. From the conceptual point of view, the protection functions can be clustered into five main categories. * * * * * Category A corresponds to the functions where the device "decides on its own", after the detection of an Event Class A, to change the state of the output stage and to disable itself. A dedicated action from the user is needed to reactivate the device (fast reactivation). Category B corresponds to the functions where the device "decides on its own", after the detection of an Event Class B, to change the state of the output stage and to disable itself. A complete reinitialization from the user is needed to reactivate the device (slow reactivation). Category C corresponds to the functions that only issue a notification in case an error is detected. Category D are intrusive supervision functions, aimed at being started when the application is not running. Category E corresponds to implemented functions or capabilities supported by the device whose use can enhance the overall safety coverage of the application. Data Sheet Hardware Description 60 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Protection and Diagnostics 3.2 Protection Functions: Category A 3.2.1 Desaturation Protection The integrated desaturation (DESAT) functionality is summarized in Table 3-2: Table 3-2 DESAT Protection Overview Parameter Short Description Function Monitoring of the VCE voltage of the IGBT. Periodicity Continuous while device issues a PWM ON command. Action in case of failure event 1. Emergency (Safe) Turn-off Sequence. 2. Error Flag SER.DESATER is set. 3. Assertion of signal NFLTA. Programmability Yes (blanking time & threshold level). The DESAT function aims at protecting the IGBT in case of short circuit. The voltage drop VCE over the IGBT is monitored via the DESAT pin while the device issues a PWM ON command. The voltage at pin DESAT is externally filtered by an external RC filter, and decoupled by an external diode (see Figure 3-1).The DESAT voltage is compared to an internal reference voltage. The result of this comparison is available by reading bit SSTAT2.DSATC. Vcc 2 Logic Class A Generation DESAT Comp DSAT VThreshold Clamping_active GND2 Figure 3-1 DESAT Function: Diagram of Principle At the beginning of a turn-on sequence, the voltage at pin DESAT is forced to Low level for the duration the blanking time defined by register SDESAT. Once the blanking time has elapsed, the voltage at pin DESAT is released and is compared to an internal reference voltage. Depending on the value of the decoupling capacitance, an additional "analog" blanking time will be added corresponding to the charging of the capacitance through the internal pull-up resistance (Figure 3-2). In case the measured voltage is higher than the selected internal threshold, an Emergency (Safe) Turn-Off sequence is initiated, bit SER.DESATER is set and a fault notification is issued on pin NFLTA (in case of an OPM transition the state machine - see Chapter 2.4.7). The threshold can be selected in OPM2 during configuration in SCFG.DSATLS. Writing 1 to DSATLS will select DESAT Reference Level VDESAT1 otherwise VDESAT0 is selected. The DESAT function is not active while the output stage is in PWM OFF state. Data Sheet Hardware Description 61 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Protection and Diagnostics The blanking time needs to be chosen carefully, since the DESAT protection may be de facto inhibited if the PWM ON-time is too short compared to the chosen blanking time. At turn-off, the DESAT signal is pulled down for the duration of the TTOFF plateau time, and extended by the blanking time once the hard turn off sequence is initiated. VTON / VTOFF t TTOFF tTTON ~ ~ VCC2 VEE2 time VDESAT t BLANK tBLANK ~ ~ VCC2 0V time Figure 3-2 DESAT Operation Note: . In case the DESAT pin is open, the pull-up resistance ensures that a DESAT event is generated at the next PWM turn-on command. DESAT Clamping during turn-off The internal pull-up resistance may lead to the unwanted charging of the DC-link capacitance via the DESAT pin. In order to overcome this, the DESAT function needs to be activated by clearing bit SCFG.DSTCEN. When this bit is set, pin DESAT is internally clamped to GND2 when a PWM OFF command is issued by the device. VTON / VTOFF tTTOFF tTTON ~ ~ VCC2 VEE2 time VDESAT tBLANK tBLANK ~ ~ VCC2 0V Clamping on Clamping on time Figure 3-3 DESAT Operation with DESAT clamping enabled Data Sheet Hardware Description 62 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Protection and Diagnostics 3.2.2 Overcurrent Protection The integrated Over Current Protection (OCP) functionality is summarized in Table 3-3: Table 3-3 OCP Function Overview Parameter Short Description Function Monitoring of the voltage drop over an external resistor located on the auxiliary emitter path of the IGBT. Periodicity Continuous while device issues a PWM ON command. Action in case of failure event 1. Emergency (Safe) Turn-off Sequence. 2. Error Flag SER.OCPER is set. 3. Assertion of signal NFLTA. Programmability Yes (blanking time and threshold level). The integrated Over Current Protection (OCP) function aims at protecting the IGBT in case of overcurrent and short-circuit conditions. The voltage drop over a sense resistor located on the auxiliary emitter path of the IGBT is monitored via the OCP while the device issues a PWM ON command. The voltage at pin OCP is externally filtered by an (optional) RC filter and compared to the internal reference threshold (see Figure 3-4). The result of these comparisons is available by reading bits SSTAT2.OCPC. Note: Bit SSTAT2.OCPC is blanked by the selected blanking time. At the beginning of a turn-on sequence, the internal evaluation of the voltage at pin OCP is inhibited for the duration the blanking time defined by register SOCP. Once the blanking time has elapsed, the voltage at pin OCP is compared to an internal reference voltage. In case the measured voltage at pin OCP is higher than the internal threshold VOCP, an Emergency (Safe) Turnoff sequence is initiated, bit SER.OCPER is set and a fault notification is issued on pin NFLTA (in case of an OPM transition the state machine - see Chapter 2.4.7). The OCP function is not active while the output stage is in PWM OFF state. The detection threshold can be selected by configuring bit field SCFG.OCPLS. 5V Logic Class A Generation OCP Comp1 Rsense V _threshold OCPG OCPG GND2 Figure 3-4 OCP Function: Principle of Operation Note: 1. Both DESAT and OCP protection mechanisms can be used simultaneously. 2. In case the OCP pin is open, the pull-up resistance ensures that an OCP event is generated. Data Sheet Hardware Description 63 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Protection and Diagnostics 3. If TLTO or TLTOFF times are used, these times should be taken into consideration for the blanking time as well to reach valid voltage levels. 3.2.3 External Enable The External Enable functionality is summarized in Table 3-4: Table 3-4 External Enable Function Overview Parameter Short Description Function External Enable. Periodicity Invalid signal on EN pin. Action in case of failure event 1. Emergency (Regular) Turn-off Sequence. 2. Error Flag PER.ENER is set. 3. Assertion of signal NFLTA. Programmability No. The functionality of the signal at pin EN is given in Chapter 2.4.8. In case of a Valid-to-Invalid signal transition, an error is detected. In this case, an Emergency (Regular) turn-off sequence is initiated, bit PER.ENER is set and a fault notification is issued on pin NFLTA (in case of an OPM transition the state machine - see Chapter 2.4.7). The current validity state of the signal at pin EN can be read on bit PSTAT2.ENVAL. Data Sheet Hardware Description 64 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Protection and Diagnostics 3.3 Protection Functions: Category B 3.3.1 Power Supply Voltage Monitoring The Power Supply Voltage Monitoring functionality is summarized in Table 3-5: Table 3-5 Power Supply Voltage Monitoring Overview Parameter Short Description Function Monitoring of VCC1, VCC2. Periodicity Continuous. Action in case of failure event 1. Emergency (Regular) Turn-off Sequence. 2. Error Flag PER.RSTP (UVLO1) or SER.UVLO2ER (UVLO2). 3. Assertion of signal NRST/RDY (UVLO1) or NFLTB (UVLO2). Programmability Yes(UVLO2 threshold level). In order to ensure a correct switching of the IGBT, the device supports an undervoltage lockout (UVLO) function for VCC1 and VCC2. The VCC1 voltage is compared (using an internal voltage comparator) to an internal reference threshold. If the power supply voltage VCC1 of the primary chip drops below VUVLO1L, an error is detected. In this case, an emergency (Regular) turn-off sequence is initiated and signal NRST/RDY goes low. In case VCC1 reaches afterwards a level higher than VUVLO1H, then the error condition is removed and signal NRST/RDY is deasserted. Besides, bit PER.RSTP is set. The VCC2 voltage is compared (using an internal voltage comparator) to an internal reference threshold. If the power supply voltage VCC2 of the secondary chip drops below VUVLO2L, an error is detected. In this case, an emergency (Regular) turn-off sequence is initiated, bit SER.UVLO2ER is set and signal NFLTB is activated (in case of an OPM transition the state machine - see Chapter 2.4.7). In case VCC2 reaches afterwards a level higher than VUVLO2H, then the error condition is removed and the device can be reenabled. The level of UVLO2 can be adjusted via configuration of SCFG.UVLO2S to fit lower supply voltage. The current status of the error detection of UVLO2 mechanism is available by reading bit SSTAT2.UVLO2M. Note: In case VCC2 goes below the voltage VRST2, the secondary chip is kept in reset state. Data Sheet Hardware Description 65 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Protection and Diagnostics 3.4 Protection Functions: Category C 3.4.1 Shoot Through Protection function The Shoot Through Protection (STP) functionality is summarized in Table 3-6: Table 3-6 STP Overview Parameter Short Description Function Prevents both High-Side and Low-Side Switches to be activated simultaneously. Periodicity Continuous. Action in case of failure event 1. The signal at pin INP is inhibited. 2. Error Flag PER.STPER is set. Programmability No. Programmability Yes (minimum dead time). With the implemented STP function, a low-side (resp. high-side) device is able to monitor the status of its highside (resp. low-side) counterpart. The input pin INSTP provides an input for the PWM signal of the driver's counterpart (Figure 3-5). PWM_HS PWM_LS INP INSTP HS Driver HS L o g i c OUT LOGIC INP INSTP Driver LS L o g i c OUT LS Figure 3-5 Shoot Through Protection: Principle of Operation In case one of the driver is in ON state, the driver's counterpart PWM input is inhibited, preventing it to turn-on (See Chapter 2.4.3). A minimum dead time is defined by hardware. This dead time is programmable via bit field PCFG2.STPDEL. Conceptually, the STP aims at providing an additional "line of defense" for the system in case erroneous PWM commands are issued by the primary logic. In normal operation, dead time management shall be performed at the microcontroller level. In case a PWM ON command is received on pin INP during the inhibition time, a failure event is detected. In this case, the high level at pin INP is ignored and bit PER.STPER is set. Data Sheet Hardware Description 66 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Protection and Diagnostics Note: Internal filter ensures that STPER is not set for glitches smaller than approximately 50ns. The STP can be tested by applying non valid INSTP and INP and by checking bit PSTAT2.STP. The STP can not be disabled. However, setting pin INSTP to VGND1 deactivates de facto the function. 3.4.2 SPI Error Detection The SPI Error Detection mechanisms are summarized in Table 3-7: Table 3-7 SPI Error Detection Overview Parameter Short Description Function Non valid SPI command detection and notification. Periodicity Continuous. Action in case of failure event Flag PER.SPIER is set. Programmability Yes (parity can be disabled). For more details, see Chapter 2.4.4.4. The SPI Error Detection Mechanism can be tested by inserting on purpose a dedicated error and by verifying that the device's reaction is conform to specification. Data Sheet Hardware Description 67 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Protection and Diagnostics 3.5 Protection Functions: Category D 3.5.1 Operation in Verification Mode and Weak Active Mode Verification Mode and Weak Active Mode are used to start intrusive test functions on device and system level, in order to verify during life time safety relevant functions. The following functions are supported in Verification and Weak Active Mode: * * * Weak Turn-On Internal Clock Supervision Timing Calibration Feature Intrusive test functions can only be started once a correct sequence of SPI commands has been received after reset. The implementation of the device ensures that no intrusive function can be started when the device is normally active. A time-out function ensures that the device quits OPM5 or OPM6 to OPM1 after a hardware defined time. The verification functions are triggered by setting the corresponding bit fields in registers PSCR or SSCR in OPM2. The settings are then activated in OPM5. Only one verification function should be activated at the time. Note: In OPM5 and OPM6 mode, it is recommended to have bit field SSTTOF.STVAL programmed to 0H. 3.5.2 Weak Turn On The Weak-Turn On (WTO) corresponds to the operation when Mode OPM6 is active. The purpose of the Weak Turn-On functionality is to perform a "probe" test of the IGBT, by switching it on with a reduced gate voltage, in order to limit the current through it in case of overcurrent conditions. This allows to avoid high currents when the system has no memory of the previous state. In Mode OPM6, when the driver initiates a turn-on sequence after the reception of a PWM command, the ON voltage at signal TON is defined by bit field SCTRL.GPONS. Figure 3-6 shows an idealized weak turn-on sequence. The device allows for external booster voltage compensation at the IGBT gate. When bit SCFG.VBEC is cleared, the voltage at TON at the plateau corresponds to the programmed value. When bit SCFG.VBEC is set, an additional VBE (base emitter junction voltage of an internal pn diode) is substracted to the programmed voltage at TON in order to compensate for the VBE of an external booster. Note: When using WTO, it is recommended to have the selected TTOFF (if active) plateau at a smaller voltage than the WTO voltage. Data Sheet Hardware Description 68 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Protection and Diagnostics Turn-On event Turn-Off event t TTOFF VGATE t DOFF t PDON VCC2 tTTOFF ~ ~ VGPONx VGPOFx VGATE1 VEE2 time VDACLP ~ ~ 5V t ACL GND2 time Figure 3-6 Idealized Weak Turn-On Sequence Note: VGPOFx have to be smaller as VGPONx to get a lower plateau. Data Sheet Hardware Description 69 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Protection and Diagnostics 3.5.3 Internal Clock Supervision The Primary Clock Supervision functionality is summarized in Table 3-8: Table 3-8 Primary Clock Supervision Overview Parameter Short Description Function Supervision of the frequency of OSC1 and SSOSC2. Periodicity On Request. Action in case of event N.a. Programmability No The clock supervision function consists on the primary clock supervision and the TCF feature. Primary Clock Supervision The purpose of this supervision function is to measure the frequency the oscillator OSC1. This function works in such a way that the PWM input signal is used to start and stop a counter clocked by OSC1. The function is activated when the device is in OPM5 or OPM6. The counter is incremented for the duration of the High level at pin INP. At a High-to-Low transition at pin INP, the counter is stopped, and its content is transferred to bit field PCS.CSP. A plausibility check can therefore be made by the logic. In case of a long INP pulse, the counter does not overflow but stays at the maximum value until cleared. PCS.CSP is cleared by setting bit PCTRL.CLRP. The INP signal is not issued at the output stage. Note: OSC2 is indirectly monitored by the Life Sign mechanism. Timing Calibration Feature The purpose of this function is to measure the frequency of oscillator SSOC2. The PWM input signal is used to start and stop a counter clocked by SSOSC2. The function is activated when the device is in OPM6 (only). The counter is incremented for the duration of the High level at pin INP. At a High-to-Low transition at pin INP, the counter is stopped, and its content is transferred to bit field SCS.SCSS. A plausibility check can therefore be made by the logic. In case of a long INP pulse, the counter does not overflow but stays at the maximum value until cleared. SCS.SCSS is cleared by a reset event or verification mode time out. The INP signal is not issued at the output stage. Data Sheet Hardware Description 70 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description 4 Register Description This chapter describes the internal registers of the device. Table 4-2 provides an overview of the implemented registers. The abbreviations shown in Table 4-3 are used in the whole section. Table 4-1 Register Address Space Module Base Address End Address SPI 00H 1FH Table 4-2 Note Register Overview Register Short Name Register Long Name Offset Address Register Description, Wakeup Value Reset Value Primary Register Description PID Primary ID Register 00H n.a. 4911H PSTAT Primary Status Register 01H n.a. 0F54H PSTAT2 Primary Second Status Register 02H n.a. 0010H PER Primary Error Register 03H n.a. x80xH PCFG Primary Configuration Register 04H n.a. 0004H PCFG2 Primary Second Configuration Register 05H n.a. 0045H PCTRL Primary Control Register 06H n.a. 001CH PCTRL2 Primary Second Control Register 07H n.a. 0015H PSCR Primary Supervision Function Control Register 08H n.a. 0001H PRW Primary Read/Write Register 09H n.a. 0001H PPIN Primary Pin Status Register 0AH n.a. 0xxxH PCS Primary Clock Supervision Register 0BH n.a. 0001H Register Description, SID Secondary Registers Description Secondary ID Register n.a. 10H SSTAT Secondary Status Register 8921H n.a. 11H SSTAT2 Secondary Second Status Register 0001H n.a. 12H SER Secondary Error Register 0xxxH n.a. 13H SCFG Secondary Configuration Register xxxxH n.a. 14H C111H SCFG2 Secondary Second Configuration Register 15H n.a. 0800H SSCR Secondary Supervision Function Control Register 17H n.a. 0001H SDESAT Secondary DESAT Blanking Time Register 18H n.a. 2000H SOCP Secondary OCP Blanking Time Register 19H n.a. 0001H Data Sheet Hardware Description 71 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Table 4-2 Register Overview (cont'd) Register Short Name Register Long Name Offset Address Wakeup Value Reset Value SRTTOF Secondary Regular TTOFF Configuration Register 1AH n.a. 0001H SSTTOF Secondary Safe TTOFF Configuration Register 1BH n.a. 2081H STTON Secondary TTON Configuration Register 1CH n.a. 0001H SADC Secondary ADC Result Register 1DH n.a. 0001H SBC Secondary ADC Boundary Register 1EH n.a. FC01H SCS Secondary Clock Supervision Register 1FH n.a. 0001H The registers are addressed wordwise. Table 4-3 Bit Access Terminology Mode Symbol Description read/write rw This bit or bit field can be written or read. read r This bit or bit field is read only. write w This bit or bit field is write only (read as read/write hardware affected rwh As rw, but bit or bit field can also be modified by hardware. read hardware affected rh As r, but bit or bit field can also be modified by hardware. sticky s Bits with this attribute are "sticky" in one direction. If their reset value is once overwritten they can be switched again into their reset state only by a reset operation. Software and internal logic (except resetlike functions) cannot switch this type of bit into its reset state by writing directly the register. The sticky attribute can be combined to other functions (e.g. `rh'). Reserved / not implemented 0 Bit fields named `0' indicate not implemented functions. They have the following behavior: * Reading these bit fields returns 0H. * Writing these bit fields has no effect. These bit fields are reserved. When writing, software should always set such bit fields to 0H in order to preserve compatibility with future products. Reserved / not defined Res Certain bit fields or bit combinations in a bit field can be marked as `Reserved', indicating that the behavior of the device is undefined for that combination of bits. Setting the register to such an undefined value may lead to unpredictable results. When writing, software must always set such bit fields to legal values. Basic Access Types Data Sheet Hardware Description 72 0H). Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description 4.1 Primary Register Description Primary ID Register This register contains the identification number of the primary chip version. PID Offset Wakeup Value Primary ID Register Reset Value n.a. 00H 4911H 15 8 PVERS r 7 4 3 2 1 0 PVERS 0 LMI P r r rh rh Field Bits Type Description PVERS 15:4 r Primary Chip Identification This bit field defines the version of the primary chip. This bit field is hard-wired. 491H a11 A11 Step. 0 3:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 73 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Primary Status Register This register contains information on the status of the device. PSTAT Offset Wakeup Value Primary Status Register Reset Value n.a. 01H 15 12 11 0F54H 10 8 0 ERR GPONP r rh rh 1 0 7 6 5 4 2 ACT SRDY AVFP GPOFP LMI P rh rh rh rh rh rh Field Bits Type Description 0 15:12 r Reserved Read as 0B. ERR 11 rh Error Status This bit is the OR combination of all bits of register PER. 0B noError No error is detected. 1B error An error is detected. GPONP 10:8 rh Gate TTON Plateau Level Configuration Status This bit field indicates the latest turn-on plateau level configuration request (WTO, TTON) received by the primary side via the SPI interface. Coding is identical to bit field PCTRL.GPON. ACT 7 rh Active State Status This bit indicates if the device is in Active State (OPM4). 0B notActive The device is not in Active State. 1B active The device is in Active State. SRDY 6 rh Secondary Ready Status This bit indicates if the secondary chip is ready for operation. 0B notReady Secondary chip is not ready. 1B ready Secondary chip is ready. AVFP 5 rh ADC Result Valid Flag This bit field indicates if a valid ADC result is available in SADC. Note: This bit field is a mirror of SADC.AVFS Data Sheet Hardware Description 74 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Field Bits Type Description GPOFP 4:2 rh Gate Regular TTOFF Plateau Level Configuration Status This bit field indicates the latest turn-off plateau level configuration request (regular TTOFF) received by the primary side via the SPI interface. Coding is identical to bit field PCTRL2. GPOF. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 75 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Primary Second Status Register This register contains information on the status of the device. PSTAT2 Offset Wakeup Value Primary Second Status Register Reset Value n.a. 02H 15 12 0010H 11 10 9 8 0 AXVP STP FLTBP FLTAP r 4 rh 3 rh 2 rh 1 rh 0 OPMP FLTB FLTA ENVAL LMI P rh rhs rhs rh rh rh 7 5 Field Bits Type Description 0 15:12 r Reserved Read as AXVP 11 rh 0B. ADC Under Or Overvoltage Error Status This bit indicates if a boundary condition violation is occurring. Note: This bit is a mirror of the OR combination of bits SADC.AUVS and SADC.AOVS 0B 1B noError An error condition is not detected. error An error condition is being detected STP 10 rh Shoot Through Protection Status This bit is set in case the shoot through protection inhibition time (i.e. would inhibit a PWM rising edge). 0B inhibitionNotActive STP inhibition is not active. 1B inhibitionActive STP inhibition is active. FLTBP 9 rh Event Class B Status This bit indicates if the conditions leading to an event Class B are met. Note: This bit is a mirror of bit SSTAT.FLTBS 0B 1B FLTAP 8 rh noError No error condition detected. error An error condition is detected. Event Class A Status This bit indicates if the conditions leading to an event Class A are met. Note: This bit is a mirror of bit SSTAT.FLTAS 0B 1B Data Sheet Hardware Description 76 noError No error condition is detected. error An error condition is detected. Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Field Bits Type Description OPMP 7:5 rh Operating Mode This bit field indicates which operating mode is active. Note: This bit field is a mirror of bit field SSTAT.OPMS 000B 001B 010B 011B 100B 101B 110B 111B opm0 Mode OPM0 is active . opm1 Mode OPM1 is active . opm2 Mode OPM2 is active. opm3 Mode OPM3 is active. opm4 Mode OPM4 is active. opm5 Mode OPM5 is active. opm6 Mode OPM6 is active. Reserved. FLTB 4 rhs NFLTB Pin Driver Request This bit indicates what output state is driven by the device at pin NFLTB. This bit is sticky. 0B tristate NFLTB is in tristate. 1B lowLevel A Low Level is issued at NFLTB. FLTA 3 rhs NFLTA Pin Driver Request This bit indicates what output state is driven by the device at pin NFLTA. This bit is sticky. 0B tristate NFLTA is in tristate. 1B lowLevel A Low Level issued at NFLTA. ENVAL 2 rh EN Valid Status This bit indicates if the signal received on pin EN is valid. 0B notValid A non-valid signal is detected. valid A valid signal is detected. 1B LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 77 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Primary Error Register This register provides information on the error status of the device. PER Offset Wakeup Value Primary Error Register n.a. 03H 15 Reset Value 13 x80xH 12 11 10 9 8 0 RSTEP RSTP ENER STPER SPIER r rhs rhs rhs rhs rhs 3 2 1 0 7 6 5 Res ADER 0 CERP LMI P rh rhs r rhs rh rh Field Bits Type Description 0 15:13 r Reserved Read as 0B. RSTEP 12 rhs Primary External Hard Reset flag This bit indicates if a reset event has been detected on the primary chip due to the activation of pin NRST/RDY. This bit is sticky. 0B notSet No external hard reset event has been detected. 1B set An externally hard reset event has been detected. RSTP 11 rhs Primary Reset Flag This bit indicates if a reset event has been detected on the primary chip. This bit is sticky. 0B notSet No reset event has been detected. 1B set A reset event has been detected. ENER 10 rhs EN Signal Invalid Flag This bit indicates if an invalid-to-valid transition on signal EN has been detected. This bit is sticky. Note: This bit can not be cleared while an error condition is active (bit PSTAT2.ENVAL cleared). 0B 1B Data Sheet Hardware Description 78 notSet No event has been detected. set An event has been detected. Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Field Bits Type Description STPER 9 rhs Shoot Through Protection Error Flag This bit indicates if a shoot through protection error event has been detected. This bit is sticky. Note: This bit can not be cleared while an error condition is active (bit PSTAT2.STP set). 0B 1B notSet No event has been detected. set An event has been detected. SPIER 8 rhs SPI Error Flag This indicates if an SPI error event has been detected. This bit is sticky. 0B notSet No error event has been detected. 1B set An error event has been detected. Res 7 rh Reserved This bit field is reserved. ADER 6 rhs ADC Error Flag This bit indicates if a boundary condition violation has occurred. This bit is sticky. Note: This bit can not be cleared while an error condition is active (bit PSTAT2.AXVP set) 0B 1B 0 CERP 5:3 2 r rhs notSet No error condition has been detected. set An error condition has been detected has been detected. Reserved Read as 0B. Primary Communication Error Flag This indicates if a loss of communication event 1) with the secondary chip has been detected by the primary chip. This bit is sticky. Note: This bit can not be cleared while an error condition is active (bit PSTAT2.SRDY cleared). 0B 1B notSet No event has been detected. set An event has been detected. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. 1) This bit is not set after a reset event Data Sheet Hardware Description 79 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Primary Configuration Register This register is used to select the configuration of the device. PCFG Offset Wakeup Value Primary Configuration Register Reset Value n.a. 04H 0004H 15 8 0 r 7 6 5 0 ADTEN ADAEN r rw rw 4 3 2 1 0 Res PAREN LMI P rw rw rh rh Field Bits Type Description 0 15:7 r Reserved Read as 0B. ADTEN 6 rw ADC Trigger Input Enable This bit enables the generation of an ADC trigger in case of a transition from Low to High at pin ADCT. 0B disabled ADCT pin is disabled. 1B enabled ADCT pin is enabled ADAEN 5 rw NFLTA Pin Activation on Boundary Check Event Enable This bit enables the activation of signal NFLTA in case of a transition from 0B to 1B of bit PSTAT2. AXVP. 0B disabled NFLTA activation is disabled. 1B enabled NFLTA activation is enabled Res 4:3 rw Reserved This bit field is reserved and shall be written with 0B. PAREN 2 rw SPI Parity Enable This bit indicates if the SPI parity error detection is active (reception only). 0B disabled Parity Check is disabled. 1B enabled Parity Check is enabled. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 80 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Primary Second Configuration Register This register is used to select the configuration of the device. PCFG2 Offset Wakeup Value Primary Second Configuration Register Reset Value n.a. 05H 0045H 15 9 8 0 DIO1 r 1 rw 0 STPDEL LMI P rw rh rh 7 2 Field Bits Type Description 0 15:9 r Reserved Read as 0B. DIO1 8 rw DIO1 Pin Mode This bit field determines the direction of pin DIO1. 0B input DIO1 is an input. 1B output DIO1 is an output. STPDEL 7:2 rw Shoot Through Protection Delay This bit field determines the dead time for the shootthrough protection (in number of OSC1 clock cycles). 00H: 0 clock cycle. ... 01H 01 1 clock cycle. 3FH 3F 63 clock cycles. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 81 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Primary Control Register This register is used to control the device during run-time. PCTRL Offset Wakeup Value Primary Control Register Reset Value n.a. 06H 001CH 15 8 0 r 7 6 5 0 CLRS CLRP r rwh rwh 4 2 1 0 GPON LMI P rw rh rh Field Bits Type Description 0 15:7 r Reserved Read as 0B. CLRS 6 rwh Clear Secondary Sitcky Bits This bit is used to clear the sticky bits on the secondary side. This bit is automatically cleared by hardware . 0B noAction No action. 1B clear Clear sticky bits. CLRP 5 rwh Clear Primary Sitcky Bits This bit is used to clear the sticky bits on the primary side. This bit is automatically cleared by hardware . 0B noAction No action. 1B clear Clear sticky bits and deassert signals NFLTA and NFLTB. GPON 4:2 rw Gate TTON Plateau Level This bit field is used to configure the voltage of the plateau during Weak Turn-On and Two Level Turn-On. For voltage levels see Table 5-15. 0H gpon0 VGPON0 selected. 1H gpon1 VGPON1 selected. 2H gpon2 VGPON2 selected. 3H gpon3 VGPON3 selected. 4H gpon4 VGPON4 selected. 5H gpon5 VGPON5 selected. 6H gpon6 VGPON6 selected. 7H gpon6WtoOrHardSwitching V GPON6 (WTO) or Hard Switching (TTON). Data Sheet Hardware Description 82 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Field Bits Type Description LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 83 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Primary Second Control Register This register is used to control the device during run-time. PCTRL2 Offset Wakeup Value Primary Second Control Register Reset Value n.a. 07H 0015H 15 8 0 r 7 6 5 4 2 1 0 0 ACRP GPOF LMI P r rwh rw rh rh Field Bits Type Description 0 15:6 r Reserved Read as 0B. ACRP 5 rwh ADC Conversion Request This bit is used to trigger an ADC conversion. It can be set by a direct write or via pin ADCT. 0B none No conversion request pending. 1B pending A conversion request is pending.This bit is automatically cleared by hardware GPOF 4:2 rw Gate Regular TTOFF Plateau Level This bit field is used to configure the Two-Level Turn-Off plateau voltage (regular turn-off). For voltage levels see Table 5-15. 0H gpof0 VGPOF0 selected. 1H gpof1 VGPOF1 selected. 2H gpof2 VGPOF2 selected. 3H gpof3 VGPOF3 selected. 4H gpof4 VGPOF4 selected. 5H gpof5 VGPOF5 selected. 6H gpof6 VGPOF6 selected. 7H gpof7 VGPOF7 selected. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 84 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Primary Supervision Function Control Register This register is used to trigger the verification functions on the primary side. PSCR Offset Wakeup Value Primary Supervision Function Control Register Reset Value n.a. 08H 0001H 15 8 0 r 7 4 3 2 0 0 VFSP LMI P r rwh rh rh Field Bits Type Description 0 15:4 r Reserved Read as VFSP 1 3:2 rwh 0B. Primary Verification Function This bit field is used to activate the primary verification functions. Note: The selection defined by this bit field is only effective when the device enters Mode OPM5. This bit field is automatically cleared when entering OPM1. 00B disabled No function activated. 01B Reserved. 10B primaryClockSupervision Primary Clock Supervision active. 11B Reserved. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 85 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Primary Read/Write Register This register provides a readable and writable address space for data integrity test during runtime. This register is not associated with any hardware functionality. PRW Offset Wakeup Value Primary Read/Write Register Reset Value n.a. 09H 0001H 15 8 RWVAL rw 7 2 1 0 RWVAL LMI P rw rh rh Field Bits Type Description RWVAL 15:2 rw Data Integrity Test Register This bit field is "don't care" for the device. LMI 1 rh Last Message Invalid Flag This bit indicates if the last received SPI Message was correctly processed by the device. 0B noError Previous Message processed correctly. 1B error Previous Message not processed. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 86 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Primary Pin Status Register This register provides status information on the I/Os of the primary chip. PPIN Offset Wakeup Value Primary Pin Status Register Reset Value n.a. 0AH 0xxxH 15 9 8 0 DIO1L 3 2 1 rh 0 7 6 5 r 4 ADCTL NFLTBL NFLTAL ENL INSTPL INPL LMI P rh rh rh rh rh rh rh rh Field Bits Type Description 0 15:9 r Reserved Read as 0B. DIO1L 8 rh DIO1 Pin Level This bit indicates the logical level read on pin DIO1. 0B low Low-level is detected. 1B high High-level is detected. ADCTL 7 rh ADC Trigger Input Level This bit indicates the logical level read on pin ADCT. 0B low Low-level is detected. 1B high High-level is detected. NFLTBL 6 rh NFLTB pin level This bit indicates the logical level read on pin NFLTB. 0B low Low-level is detected. 1B high High-level is detected. NFLTAL 5 rh NFLTA pin Level This bit indicates the logical level read on pin NFLTA. 0B low Low-level is detected. 1B high High-level is detected. ENL 4 rh EN Pin Level This bit indicates the logical level read on pin EN. 0B low Low-level is detected. 1B high High-level is detected. INSTPL 3 rh INSTP Pin Level This bit indicates the logical level read on pin INSTP. 0B low Low-level is detected. 1B high High-level is detected. Data Sheet Hardware Description 87 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Field Bits Type Description INPL 2 rh INP Pin Level This bit indicates the logical level read on pin INP. 0B low Low-level is detected. 1B high High-level is detected. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B noError Previous Message was processed correctly. 1B error Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 88 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Primary Clock Supervision Register This register shows the result of the Primary Clock Supervision function. PCS Offset Wakeup Value Primary Clock Supervision Register Reset Value n.a. 0BH 0001H 15 8 CSP rh 7 2 1 0 0 LMI P r rh rh Field Bits Type Description CSP 15:8 rh Primary Clock Supervision This bit field is written by hardware by the Primary Clock Supervision function and gives the number of measured OSC1 clock cycles. Note: This bit field can be cleared by setting bit PCTRL.CLRP. 0 7:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 89 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description 4.2 Secondary Registers Description Secondary ID Register This register contains the identification number of secondary chip version. SID Offset Wakeup Value Secondary ID Register Reset Value n.a. 10H 8921H 15 8 SVERS r 7 4 3 2 1 0 SVERS 0 LMI P r r rh rh Field Bits Type Description SVERS 15:4 r Secondary Chip Identification This bit field defines the version of the secondary chip. This bit field is hard-wired. 0 3:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. Previous Message was discarded. 1B P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 90 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary Status Register This register contains information on the status of the device. SSTAT Offset Wakeup Value Secondary Status Register Reset Value n.a. 11H Field Bits Type Description Res 15 rh Reserved This bit field is reserved. 0 14:11 r Reserved Read as 0001H 0B. DBG 10 rh Debug Mode Active Flag This bit indicates if the Debug Mode is active. 0B notSet Debug Mode is not active. 1B set Debug Mode is active. Res 9:5 rh Reserved This bit field is reserved. PWM 4 rh PWM Command Status This bit indicates the status of the PWM command received from the primary side. 0B off PWM OFF command is detected. 1B on PWM ON command is detected. 0 3:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. Previous Message was discarded. 1B P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 91 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary Second Status Register This register contains information on the status of the device. SSTAT2 Offset Wakeup Value Secondary Second Status Register Reset Value n.a. 12H 0xxxH 15 9 8 0 DACL 1 rh 0 7 6 5 r 4 DIO2L UVLO2M OCPC DSATC 0 LMI P rh rh rh rh r rh rh 3 Field Bits Type Description 0 15:9 r Reserved Read as 2 0B. DACL 8 rh DACLP Pin outpout level This bit indicates the level read at pin DACLP. 0B low DACLP level is Low. 1B high DACLP level is High. DIO2L 7 rh DIO2 Pin Level This bit indicates the level read at pin DIO2. 0B low DIO2 level is Low. 1B high DIO2 level is High. UVLO2M 6 rh UVLO2 Event This bit indicates the result of the UVLO2 monitoring function. 0B noError No failure condition is detected. 1B error One failure condition is detected. OCPC 5 rh OCP Comparator Result This bit indicates the (blanked) output of the first comparator of the OCP function. 0B belowThreshold OCP voltage is below the internal threshold. 1B aboveThreshold OCP voltage is above the internal threshold. DSATC 4 rh DESAT Comparator Result This bit indicates the output of the comparator of the DESAT function. 0B belowThreshold DESAT voltage is below the internal threshold. 1B aboveThreshold DESAT voltage is above the internal threshold. Data Sheet Hardware Description 92 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Field Bits Type Description 0 3:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 93 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary Error Register This register provides information on the error status of the device. SER Offset Wakeup Value Secondary Error Register Reset Value n.a. 13H xxxxH 15 14 13 12 11 10 9 8 RSTS OCPER DESATER UVLO2ER 0 VMTO 0 rhs 7 rhs 6 rhs 5 rhs 4 r rhs 1 r 0 0 AOVER AUVER CERS 0 LMI P r rhs rhs rhs r rh rh Field Bits Type Description RSTS 15 rhs Secondary Hard Reset Flag This bit indicates if a hard reset event has been detected on the secondary chip (due to a V CC2 power-up). This bit is sticky. 0B notSet No hard reset event has been detected. 1B set A hard reset event has been detected. OCPER 14 rhs OCP Error Flag This bit indicates if an OCP event has been detected. This bit is sticky. 3 2 Note: This bit can not be cleared while an error condition is active (bit SSTAT2.OCPC set). 0B 1B notSet No event has been detected. set An event has been detected. DESATER 13 rhs DESAT Error Flag This bit indicates if a DESAT event has been detected. This bit is sticky. 0B notSet No event has been detected. 1B set An event has been detected. UVLO2ER 12 rhs UVLO2 Error Flag This bit indicates if an Undervoltage Lockout event (on VCC2 ) has been detected. This bit is sticky. Note: This bit can not be cleared while an error condition is active (bit SSTAT2.UVLO2M set). 0B 1B Data Sheet Hardware Description 94 notSet No event has been detected. set An event has been detected. Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Field Bits Type Description 0 11:10 r Reserved Read as 0B. VMTO 9 rhs Verification Mode Time-Out Event Flag This bit indicates if time-out event in Verification Mode has been detected. This bit is sticky. 0B notSet No event has been detected. 1B set An event has been detected. 0 8:7 r Reserved Read as 0B. AOVER 6 rhs ADC Overvoltage Error Flag This bit indicates if a boundary condition violation (overvoltage) occurred. This bit is sticky. 0B notSet An error condition has not been detected. 1B set An error condition has been detected. AUVER 5 rhs ADC Undervoltage Error Flag This bit indicates if a boundary condition violation (undervoltage) occurred. this bit is sticky. 0B notSet An error condition has not been detected. 1B set An error condition has been detected. CERS 4 rhs Communication Error Secondary Flag This indicates if a loss of communication event with the primary chip has been detected by the secondary chip. This bit is sticky. 0B notSet No event has been detected. 1B set An event has been detected. 0 3:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 95 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary Configuration Register This register is used to select the configuration of the device. SCFG Offset Wakeup Value Secondary Configuration Register n.a. 14H 15 14 Reset Value C111H 13 12 11 10 9 8 DACLC OCPLS UVLO2S DSATLS TOSEN PSEN DSTCEN rw rw 5 rw 4 rw 3 rw 2 rw 1 rw 0 DIO2C CFG2 VBEC 0 LMI P rw rwh rw r rh rh 7 6 Field Bits Type Description DACLC 15:14 rw DACLP Pin clamping outpout This bit field determines the functionality of pin DACLP. 00B low The pin delivers a constant Low level. 01B high The pin delivers a constant High level. 10B daclpSafe : DACLP function selected. The signal is active only in case of a Safe Turn-Off sequences. 11B daclpRegular : DACLP function selected. The signal is active for both Regular and Safe Turn-Off sequences. OCPLS 13 rw OCP Threshold Level This bit field configures the threshold level of the OCP function. 0B vocp0 Threshold VOCP0 selected . 1B vocp1 Threshold VOCP1 selected . UVLO2S 12 rw UVLO2 Threshold Level This bit field configures the threshold level of the UVLO2 function. 0B uvlo2l0 Threshold VUVLO2L0 selected . 1B uvlo2l1 Threshold VUVLO2L0 selected . DSATLS 11 rw DESAT Threshold Level This bit field configures the threshold level of the DESAT function. 0B vdesat0 Threshold VDESAT0 selected . 1B vdesat1 Threshold VDESAT1 selected . TOSEN 10 rw Verification Mode Time Out Duration This bit selects the duration of the verification mode timeout. 0B regular Regular time-out value (typ. 15 ms). 1B slow Slow time-out value (typ. 60 ms). Data Sheet Hardware Description 96 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Field Bits Type Description PSEN 9 rw Pulse Suppressor Enable This bit enables the internal pulse suppressor. 0B disabled Pulse suppressor is disabled. 1B enabled Pulse suppressor is enabled. DSTCEN 8 rw DESAT Clamping Enable This bit enables the internal clamping (to GND2) of the DESAT pin during PWM OFF commands. 0B disabled DESAT clamping is disabled. 1B enabled DESAT clamping is enabled. DIO2C 7:6 rw DIO2 Pin Mode This bit field determines the functionality of pin DIO2. 00B input DIO2 is an input. 01B output DIO2 is an output transferring the signal from DIO1. 10B Reserved. 11B Reserved. CFG2 5 rwh Secondary Advanced Configuration Enable This bit field enables write accesses to register SCFG2 and SBC. This bit is automatically cleared when mode OPM2 is left. 0B disabled Write access to SCFG2 and SBC are discarded. . 1B enabled Write access to SCFG2 and SBC are executed normally. VBEC 4 rw VBE Compensation Enable This bit enables the VBE compensation of the TTOFF, TTON and WTO plateau levels. 0B disabled VBE Compensation disabled. 1B enabled VBE Compensation enabled. 0 3:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 97 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary Second Configuration Registe This register is used to select the configuration of the device. It can only be written if SCFG.CFG2 is set. SCFG2 Offset Wakeup Value Secondary Second Configuration Register Reset Value n.a. 15H 0800H 15 14 13 12 10 ADCEN ACAEN ACSS AOS AGS rw 7 rw 6 rw 5 rw 3 rw 4 2 9 8 1 0 ATS PWMD 0 LMI P rw rw r rh rh Field Bits Type Description ADCEN 15 rw ADC Enable This bit field enables ADC function: 0B disabled ADC Disabled. 1B enabled ADC Enabled. ACAEN 14 rw ADC Event Class A Enable This bit field enables the generation of Event Class A in case of Boundary Check violation: 0B disabled No Event Class A is generated. 1B enabled An Event Class A is generated. ACSS 13 rw ADC Current Source This bit field activates the internal current source. 0B disabled Current source disabled. 1B enabled Current source I AIPCS selected. AOS 12:10 rw ADC Offset This bit field configures the offset value of the ADC. For voltage levels see Table 5-21. 0H ofst0 VOFF0 selected. 1H ofst1 VOFF1 selected. 2H ofst2 VOFF2 selected. 3H ofst3 VOFF3 selected. 4H ofst4 VOFF4 selected. 5H reserved. Data Sheet Hardware Description 6H reserved. 7H reserved. 98 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Field Bits Type Description AGS 9:8 rw ADC Gain This bit field configures the gain value of the ADC. 00B gain0 GAIN0 selected. 01B gain1 GAIN1 selected. 10B gain2 GAIN2 selected. 11B gain3 GAIN3 selected. ATS 7:6 rw ADC Secondary Trigger Mode This bit field configures the trigger mode of the ADC on the secondary side. 00B disabled No secondary trigger source active. 01B periodic Periodic trigger selected. 10B risingPwm PWM trigger selected (rising edge). 11B fallingPwm PWM trigger selected (falling edge). PWMD 5:4 rw ADC PWM Trigger Delay This bit field configures the offset value of the delay between PWM edge and ADC trigger, in case PWM Trigger Mode is selected. 00B delay0 16 OSC2 cycles selected. 01B delay1 32 OSC2 cycles selected. 10B delay2 48 OSC2 cycles selected. 11B delay3 64 OSC2 cycles selected. 0 3:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 99 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary Supervision Function Control Register This register is used to trigger the verification functions on the secondary side. SSCR Offset Wakeup Value Secondary Supervision Function Control Register Reset Value n.a. 17H 0001H 15 8 0 r 7 6 5 4 3 2 1 0 0 VFS2 0 LMI P r rwh r rh rh Field Bits Type Description 0 15:6 r Reserved Read as VFS2 5:4 rwh 0B. Secondary Verification Function This bit field is used to activate the secondary verification function. All other bit combinations are reserved. Note: The selection defined by this bit field is only effective when the device enters Mode OPM5. This bit field is automatically cleared when entering OPM1. 00B disabled No function activated. 01B tcf TCF function active. 0 3:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 100 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary DESAT Blanking Time Register This register configures the blanking time of the DESAT function. SDESAT Offset Wakeup Value Secondary DESAT Blanking Time Register Reset Value n.a. 18H 2000H 15 8 DSATBT rw 7 2 1 0 0 LMI P r rh rh Field Bits Type Description DSATBT 15:8 rw DESAT Blanking Time This bit field defines the blanking time of the DESAT function (in OSC2 clock cycles). A minimal value of at least AH has to be programmed. 0 7:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 101 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary OCP Blanking Time Register This register configures the blanking time of the OCP function. SOCP Offset Wakeup Value Secondary OCP Blanking Time Register Reset Value n.a. 19H 0001H 15 8 OCPBT rw 7 2 1 0 0 LMI P r rh rh Field Bits Type Description OCPBT 15:8 rw OCP Blanking Time This bit field defines the blanking time of the OCP function (in OSC2 clock cycles). Writing 0H to this field deactivates the digital blanking time generation. If used, a minimal value of at least AH has to be programmed. 0 7:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 102 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary Regular TTOFF Configuration Register This register shows the configuration of the TTOFF function for regular turn-off. SRTTOF Offset Wakeup Value Secondary Regular TTOFF Configuration Register Reset Value n.a. 1AH 0001H 15 8 RTVAL rw 7 2 1 0 0 LMI P r rh rh Field Bits Type Description RTVAL 15:8 rw Gate Regular TTOFF delay This bit field defines the TTOFF delay for a regular turnoff (in SSOSC2 clock cycles). Writing 00H to this field deactivates the TTOFF function for regular turn-off. If used, a value greater then 02H has to be programmed. 0 7:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 103 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary Safe TTOFF Configuration Register This register shows the configuration of the TTOFF function for safe turn-off. SSTTOF Offset Wakeup Value Secondary Safe TTOFF Configuration Register Reset Value n.a. 1BH 2081H 15 8 STVAL rw 7 5 4 2 1 0 GPS 0 LMI P rw r rh rh Field Bits Type Description STVAL 15:8 rw Gate Safe TTOFF delay This bit field defines the TTOFF delay for a safe turn-off (in OSC2 clock cycles). Writing 00H to this field deactivates the TTOFF function for regular turn-off. if used, a minimal value of at least 0AH has to be programmed. Note: 4. In OPM5 and OPM6, it is recommended to have this bit field programmed to 0H. 5. In OPM4, bit field STVAL shall be programmed with a higher value than field SRTTOF.RTVAL. 6. GPS 7:5 rw Gate Safe TTOFF Plateau Voltage This bit field defines the TTOFF plateau voltage for safe turn-off sequences. Coding is identical to PCTRL2.GPOF. Note: In OPM4, bit field GPS shall be programmed with a value smaller or equal than field PCTRL2.GPOF. 0 Data Sheet Hardware Description 4:2 r Reserved Read as 104 0B. Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Field Bits Type Description LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 105 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary TTON Configuration Register This register shows the configuration of the TTON function for regular turn-on. STTON Offset Wakeup Value Secondary TTON Configuration Register Reset Value n.a. 1CH 0001H 15 8 TTONVAL rw 7 2 1 0 0 LMI P r rh rh Field Bits Type Description TTONVAL 15:8 rw Gate TTON Delay This bit field defines the TTON delay (in SSOSC2 clock cycles). Writing 00H to this field deactivates the TTON function. If used, a minimal value of at least AH has to be programmed. 0 7:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 106 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary ADC Result Register This register provides status of the ADC channel. SADC Offset Wakeup Value Secondary ADC Result Register Reset Value n.a. 1DH 0001H 15 8 ADCVAL rh 7 6 5 4 0 AOVS AUVS AVFS r rh rh rhs 3 2 1 0 0 LMI P r rh rh Field Bits Type Description ADCVAL 15:8 rh ADC Result This bit field shows the results of the last conversion of the ADC channel. It is automatically updated every time a new conversion result is available. 0 7 r Reserved Read as 0B. AOVS 6 rh ADC Overvoltage Error Status This bit indicates if a boundary condition violation is occurring (Overvoltage). 0B noError An error condition is not detected. 1B error An error condition is being detected AUVS 5 rh ADC Undervoltage Error Status This bit indicates if a boundary condition violation is occurring (undervoltage). 0B noError An error condition is not detected. 1B error An error condition is being detected AVFS 4 rhs ADC Result Valid Flag This bit indicates if a new value is available. This bit is set every time bit field ADCVAL is updated with a new value. This bit is sticky. 0B notValid ADC result is not valid. 1B valid ADC result is valid. 0 3:2 r Reserved Read as Data Sheet Hardware Description 107 0B. Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Field Bits Type Description LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 108 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary ADC Boundary Register This register contains the values for the ADC boundary check. It can only be written if CFG2 is set. SBC Offset SCFG. Wakeup Value Secondary ADC Boundary Register Reset Value n.a. 1EH FC01H 15 10 9 8 LCB1B LCB1A rw rw 7 4 3 2 1 0 LCB1A 0 LMI P rw r rh rh Field Bits Type Description LCB1B 15:10 rw ADC Limit Checking Boundary B Second boundary used for the limit check mechanism. Should be used as upper limit. LCB1A 9:4 rw ADC Limit Checking Boundary A First boundary used for the limit check mechanism. Should be used as lower limit. 0 3:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 109 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Secondary Clock Supervision Register This register is for internal purpose only. SCS Offset Wakeup Value Secondary Clock Supervision Register Reset Value n.a. 1FH 0001H 15 8 SCSS rh 7 2 1 0 0 LMI P r rh rh Field Bits Type Description SCSS 15:8 rh Secondary Supervision Oscillator Clock Cycles This bit field is written by hardware by the TCF function and gives the number of measured Start Stop Oscillator clock cycles. 0 7:2 r Reserved Read as 0B. LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0B Previous Message was processed correctly. 1B Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. Data Sheet Hardware Description 110 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description 4.3 Read / Write Address Ranges Table 4-4 summarizes which register is accessible with a READ command for a given operating mode. Table 4-4 Read Access Validity OPM0/1 OPM2 OPM3 OPM4 OPM5 OPM6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X PID PSTAT PSTAT2 PER PCFG PCFG2 PCTRL PCTRL2 PSCR PRW PPIN PCS 1) SID X X X X 1) X 1) SSTAT X X X X 1) X 1) SSTAT2 X X X X X X X X X X X X X X X X X X 1) SSCR Data Sheet Hardware Description 111 X 1) X 1) SCFG2 X 1) 1) SCFG X 1) 1) SER X X 1) X X 1) Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Table 4-4 Read Access Validity (cont'd) OPM0/1 OPM2 OPM3 OPM4 OPM5 OPM6 X X X X X X 1) SDESAT X X X X 1) X 1) SOCP X X X X 1) X 1) SRTTOF X X X X X X X X X X X X X X X X X X X X X X X 1) SCS X 1) X 1) SBC X 1) 1) SADC X 1) 1) STTON X 1) 1) SSTTOF X X 1) X X 1) 1) Increased latency time Data Sheet Hardware Description 112 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Table 4-5 summarizes which register is accessible with a WRITEL command for a given operating mode. Table 4-5 Write Access Validity OPM0/1 OPM2 OPM3 OPM4 OPM5 OPM6 PID PSTAT PSTAT2 PER X PCFG X PCFG2 X X X X X X X X X X X X X X X X PCTRL PCTRL2 X PSCR X X PRW PPIN PCS SID SSTAT SSTAT2 SER X SCFG X SCFG2 1) X SSCR Data Sheet Hardware Description 113 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Register Description Table 4-5 Write Access Validity (cont'd) OPM0/1 OPM2 OPM3 OPM4 OPM5 OPM6 X SDESAT X SOCP X SRTTOF X SSTTOF X STTON SADC 1) X SBC SCS 1) Write access only if bit SCFG.CFG2 is set. Data Sheet Hardware Description 114 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5 Specification 5.1 Typical Application Circuit Table 5-1 Component Values Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Decoupling Capacitance Cd (Between VEE2 and GND2) 2 x 0.5 11 - F 10F capacitance next to the power supply source (e.g. flyback converter). 1 F close to the device. It is strongly recommended to have at least two capacitances close to the device (e.g. 2 x 500nF). Decoupling Capacitance Cd (Between VCC2 and GND2) - 11 - F 10F capacitance next to the power supply source (e.g. flyback converter). 1 F close to the device. Decoupling Capacitance Cd (Between VCC1 and GND1) - 11 - F 10F capacitance next to the power supply source (e.g. flyback converter). 1 F close to the device. Series Resistance Rs1 0 1 - k Pull-up Resistance Rpu1 - 10 - k Filter Resistance R1 - 1 - k Filter Capacitance C1 - 47 - pF Reference Resistance Rref1 - 26.71) - k high accuracy, as close as possible to the device Reference Capacitance Cref1 - 100 - pF As close as possible to the device. Pull-up Resistance Rpu2 - 10 - k 1) Reference Resistance Rref2 - 23.7 - k high accuracy, as close as possible to the device Reference Capacitance Cref2 - 100 - pF As close as possible to the device. DESAT filter Resistance Rdesat 1 3 - k Depends on required response time. DESAT filter Capacitance Cdesat - n/a - pF Depends on required response time. DESAT Diode Ddesat - n/a - - HV diode. Sense Resistance Rsense - n/a - Depends on IGBT specification. OCP filter Capacitance Cocp - n/a - pF Depends on required response time. Data Sheet Hardware Description 115 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification Table 5-1 Component Values (cont'd) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Depends on required response time. OCP & OCPG resistance Rocp, Rocpg 0 - 100 DACLP filter Resistance Rdaclp - 1 - k DACLP filter Capacitance Cdaclp - 470 - pF Active Clamping Resistance Racl1 - n/a - Depends on application requirements Active Clamping Resistance Racl2 - n/a - k Depends on application requirements Active Clamping Capacitance Cacli - n/a - nF Depends on application requirements TVS Diode Dtvsacl1, Dtvsacl2 - n/a - - Depends on application requirements Active Clamping Diode Dacl - n/a - - Depends on application requirements ACLI Clamping Diode Dacl2 - n/a - - Depends on application requirements VREG Capacitance Cvreg F As close as possible to the device. GATE Resistance Rgon 0.5 - - GATE Resistance Rgoff 0.5 - - GATE Clamping Diode Dgcl1 - n/a - - 2) GATE Clamping Diode Dgcl2 - n/a - - E.g. Schottky Diode. 2) GATE Series Resistance Rgate 0 10 - Optional component. VEE2 Clamping Diode Dgcl3 - n/a - - E.g. Schottky Diode. 2) ADC filter Resistance Radc - 10 - ADC filter Capacitance Cadc - 1 - nF 1 1) If other values are used functionality of IC not guaranteed. 2) Characteristics of this components are application specific. Data Sheet Hardware Description 116 Rev 2.0, 2017-06-19 LV Logic R pu1 117 GND1 R1 R1 RS1 R1 R1 R1 R1 R1 Rpu1 Cref1 Cd C1 C1 C1 C1 C1 C1 C1 C1 VCC1 GND1 GND1 GND1 GND1 GND1 REF0 REF0 Rpu1 Data Sheet Hardware Description Rref1 +5V GND1 IREF1 ADCT NCS IREF2 DACLP VEE2 VREG GND2 OCPG OCP GATE AIN (o) AIP (o) EiceDRIVER SENSE / LITE SCLK SDO SDI NRST/RDY REF0 EN GND2 Cref2 Cd Cd -8V GND2 Cadc Radc Cv reg Cocp GND2 Rocpg Rocp (o): EiceSENSE Only Dgc l3 (*) VCC2 VCC2 VEE2 Rgate(*) Cd TOFFO TONO GND2 EiceDRIVER Boost GND2 Lite TOFFI TOFF GND2 INSTP Rref2 GND2 Cdesat TONI DEBUG NFLTB Rdesat TON DESAT NFLTA Cd +15V INP VCC2 VCC1 VEE2 Dgc l2 (*) Dgcl1 (*) VCC2 Rgoff Rgon TDIODE Rsense Rtvsacl 2 Dac l Dtvsacl2(*) Ddes at EiceDRIVERTM SENSE 1EDI2010AS Specification Figure 5-1 Typical Application Example Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.2 Absolute Maximum Ratings Stress above the maximum values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5-2 Absolute Maximum Ratings1) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Junction temperature TJUNC -40 - 150 C Storage temperature TSTO -55 - 150 C Positive power supply (primary) VCC1 -0.3 - 6.0 V Referenced to GND1 Positive power supply (secondary) VCC2 -0.3 - 28 V Referenced to GND2 Negative power supply VEE2 -13 - 0.3 V Referenced to GND2 Power supply voltage difference VDS2 (secondary) VCC2-VEE2 - - 40 V Voltage on any I/O pin on primary VIN1 side except INP, INSTP, EN -0.3 - 6.0 V Referenced to GND1 Voltage on INP, INSTP, EN pins VINR1 -0.3 - 6.0 V Referenced to REF02) Voltage difference between REF0 and GND1 VDG1 -4 - 4 V Voltage difference between OCPG and GND2 VOCPG2 -0.3 - 0.3 V Output current on push-pull I/O on primary side IOUTPP1 - - 20 mA Output current on push-pull I/O on secondary side IOUTPP2 - - 5 mA Output current on open drain I/O IOUTOD1 on primary side - - 20 mA VREG Output DC current IREG2 - - 525 A CLOAD=1F Voltage on 5 V pin on sec. side VIN52 -0.3 - 6.0 V Referenced to GND2 Voltage on 15 V pin on secondary side. VIN152 VEE2-0.3 - VCC2+0.3 V Referenced to GND2, except DESAT Voltage on DESAT pin. VINDESAT -0.3 - VCC2+0.3 V Referenced to GND2 Power Dissipation - Pri. Chip PDISMAX1 - - 100 mW TAMB=125C Power Dissipation - Sec. Chip PDISMAX2 - - 600 mW TAMB=125C ESD Immunity VESD - - 2 kV HBM3) - - 750 V CDM4), pins 1, 16, 17, 36 500 V CDM4), all other pins MSL Level 1) 2) 3) 4) MSL n.a. 3 n.a. Not subject to production test. Absolute maximum Ratings are verified by design / characterization. Max. voltage of VINR1+VDG1 should be below 7V. According to EIA/JESD22-A114-B. According to JESD22-C101-C. Data Sheet Hardware Description 118 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.3 Operating range The following operating conditions must not be exceeded in order to ensure correct operation of the 1EDI2010AS. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 5-3 Operating Conditions Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Ambient temperature Tamb -40 - 125 C Positive power supply (primary) VCC1 4.65 5.0 5.5 V Referenced to GND11) Positive power supply (secondary) VCC2 13.0 15.0 18.0 V Referenced to GND22) Negative power supply VEE2 -10.0 -8.0 0 V Referenced to GND23) PWM switching frequency fsw - - 30 kHz 4) Common Mode Transient Immunity dVISO/dt -100 - 100 kV/s At 1000 V5) Pulsed Magnetic Field Transient Immunity HISO 1000 A/m 1) 2) 3) 4) 5) 6) -1000 tr=10s 5)6) Deterministic and correct operation of the device is guaranteed down to VUVLO1L. Deterministic and correct operation of the device is guaranteed down to VUVLO2L. Deterministic and correct operation of the device is guaranteed up to 0.3V. Maximum junction temperature of the device must not be exceeded. Not subject to production test. This parameter is verified by design / characterization. As per IEC 61000-4-9 5.4 Thermal Characteristics The indicated thermal parameters apply to the full operating range, unless otherwise specified. Table 5-4 Thermal Characteristics Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. RTHJA - 60 - K/W Tamb=125C1)2) Thermal Resistance Junction to Case RTHJC - - 41 K/W Tamb=125C1) Thermal Resistance Junction to Ambient 1) Not subject to production test. This parameter is verified by design / characterization. 2) The thermal characteristics are done with a 6 layers board with the dimension 30mm x 40mm x 1.5mm and a cu-thickness of 35m each layer (cooling areas should be foreseen on top and bottom, but shouldn't cover the isolation area of the IC). Data Sheet Hardware Description 119 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.5 Electrical Characteristics The indicated electrical parameters apply to the full operating range, unless otherwise specified. 5.5.1 Power Supply Table 5-5 Power Supplies Characteristics Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition UVLO1 Threshold High VUVLO1H 4.20 4.47 4.65 V Referenced to GND1 UVLO1 Threshold Low VUVLO1L 4.20 4.40 4.60 V Referenced to GND1 UVLO1 Hysteresis VUVLO1HYS 40 70 - mV UVLO2 Threshold High VUVLO2H0 11.5 12.5 13.0 V Referenced to GND2 VUVLO2H1 9.5 10.25 11 V Referenced to GND2 VUVLO2L0 11.0 11.7 12.5 V Referenced to GND2 VUVLO2L1 9 9.75 10.5 V Referenced to GND2 VUVLO2HY0 500 850 - mV VUVLO2H0/L0 selected VUVLO2HY1 400 500 - mV VUVLO2H1/L1 selected VCC2 Reset Level VRST2 7.9 8.3 8.8 V Referenced to GND2 Quiescent Current Input Chip IQ1 - 7.5 10 mA VCC1=5V, all I/Os inactive Quiescent Current Output Chip VCC2 IQVCC2 - 11 13 mA VCC2=15V, VEE2=-8V,all I/Os inactive Quiescent Current Output Chip VEE2 IQVEE2 - 1 2 mA VCC2=15V, VEE2=-8V,all I/Os inactive VCC1 ramp-up / down time tRP1 - - 0.5 V/ms Absolute value VCC2 ramp-up / down time tRP2 - - 1.5 V/ms Absolute value VEE2 ramp-up / down time tRP3 - - 0.8 V/ms Absolute value Power Dissipation - Primary Chip PDIS1 - 37.5 - mW TAMB=25C Power Dissipation - Secondary Chip PDIS2 - 175 - mW TAMB=25C, idle mode UVLO2 Threshold Low UVLO2 Hysteresis Data Sheet Hardware Description 120 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.5.2 Internal Oscillators Table 5-6 Internal Oscillators Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Primary / Secondary main oscillator frequency fclk1 14.0 16.6 19.1 MHz Resistances on pin IREF1 nominal Start/Stop Oscillator Frequency fclk2, fclkst2 15.0 17.1 19.0 MHz Resistances on pin IREF2 nominal Data Sheet Hardware Description 121 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.5.3 Primary I/O Electrical Characteristics Table 5-7 Electrical Characteristics for Pins: INP, INSTP, EN Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - 0.3xVCC1 V Referenced to REF0 Low Input Voltage VINPRL1 0 High Input Voltage VINPRH1 0.7xVCC1 - VCC1 V Referenced to REF0 Weak pull down resistance RPDIN1 20 - 100 k Referenced to REF0 Input Current IINPR1 - - 300 A Input Pulse Suppression tINPR1 - 20 - ns 1) Time between EN valid and INP High tINPEN Level 8 - - s 2) INP High / Low Duration tINPPD 250 - - ns INSTP High / Low Duration tINSTPPD 250 - - ns Minimum EN High or Low duration time. tENDC 10 - - s 2) 1) Not subject to production test. This parameter is verified by design / characterization. 2) Timing is given for hard ON/OFF switching condition only. Table 5-8 Electrical Characteristics for Pins: NRST/RDY, SCLK, SDI, NCS, DIO1 (input), ADCT Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - 0.3xVCC1 V Referenced to GND1 Low Input Voltage VINPL1 0 High Input Voltage VINPH1 0.7xVCC1 - VCC1 V Referenced to GND1 25 - 100 k Referenced to VCC1 Weak pull down resistance DIO1, ADCT RPDADDI1 25 - 100 k Referenced to GND1 Input Current IINP1 - - 400 A NRST/RDY Output Voltage in NonReady conditions. VOUTNR - - 1 V Vcc1=5V, Iload = 2 mA - 0.7 1 V Vcc1=0V, Iload = 500 A NRST/RDY driven-active time after power supplies are within operating range. tRST - 15.4 - s 1) NRST/RDY minimum activation time. tRSTAT 10 - - s Minimum DIO1 High or Low duration tDIO1DC time. 10 - - s Minimum ADCT High or Low duration tADCTDC time. 20 - - s Weak pull up resistance SCLK, SDI, RPUSPI1 NCS When configured as input 1) Not subject to production test. This parameter is verified by design / characterization. Data Sheet Hardware Description 122 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification Table 5-9 Electrical Characteristics for Pins: SDO, DIO1 (output) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Low Output Voltage VOUTPL1 - - 0.5 V Iload = 5 mA High Output Voltage VOUTPH1 3.85 - - V Iload = 5 mA Table 5-10 Electrical Characteristics for Pins: NFLTA, NFLTB Parameter Low Output Voltage Data Sheet Hardware Description Symbol VOUTDL1 Values Unit Note / Test Condition Min. Typ. Max. - - 0.5 123 V ISINK= 5 mA Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.5.4 Secondary I/O Electrical Characteristics Table 5-11 Electrical Characteristics for Pins: TON, TOFF & GATE Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - VCC2+0.3 V Referenced to GND2 TON & TOFF Output Voltage High V15OH2 VCC2-1 TON & TOFF Output Voltage Low V15OL2 VEE2-0.3 - VEE2+1 V Referenced to GND2 TON & TOFF Source / Sink Current I15O2 1 - - A 1)2) GATE Input voltage range V15GATE VEE2 - VCC2 V Referenced to GND2 Passive Clamping Voltage VPCLP - - VEE2+1 V Secondary chip not supplied, TON, TOFF & GATE shorted, ICLAMP= 10 mA. Passive Clamp Current IPCLP 5 - - mA Secondary chip not supplied, TON, TOFF & GATE shorted, VGATE=VEE2+2V 1) Not subject to production test. This parameter is verified by design / characterization. 2) Thermally limited. Table 5-12 Electrical Characteristics for Pins: DEBUG, DIO2(input) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Low Input Voltage V5INL2 0 - 1.5 V Referenced to GND2 High Input Voltage V5INH2 3.5 - 5.5 V Referenced to GND2 Weak pull down resistance RPDIN2 20 - 80 k Connected to GND2 Table 5-13 Electrical Characteristics for Pins: DIO2, DACLP (Output) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Output Voltage High V5OH2 4.0 - 5.25 V Referenced to GND2, Iload= 2 mA, VREG2= typ. Output Voltage Low V5OL2 0 - 0.5 V Referenced to GND2, Iload= 2 mA 10 - - s When configured as input Minimum DIO2 High or Low duration tDIO2DC time. Data Sheet Hardware Description 124 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification Table 5-14 Electrical Characteristics for Pin: AIP Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Voltage Range for Current Source VAIP 0 - 4.5 V IAIPCS= typ. Current Source IAIPCS - 1.05 - mA Rref2 = 23.7 kOhm1) Output Current Source Error IAIPCSER - 3 % Deviation from nominal value -3 1) Recommended resistance for specified limits. Other values may lead to malfunction. Data Sheet Hardware Description 125 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.5.5 Switching Characteristics Table 5-15 Switching Characteristics Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input to Output Propagation Delay ON tPDON 175 215 255 ns VCC1=5V, VCC2=15V, VEE2=-8V 1) Input to Output Propagation Delay OFF tPDOFF 175 215 255 ns VCC1=5V, VCC2=15V, VEE2=-8V 1) Input to Output Propagation Delay Distortion (tPDOFF-tPDON) tPDISTO -50 0 50 ns VCC1=5V, VCC2=15V, VEE2=-8V Input to Output Propagation Delay Distortion Variation for two consecutive pulses tPDISTOV - 25 - ns VCC1=5V, VCC2=15V, VEE2=-8V, TJUNC=25C 2) Rise Time tRISE - 120 205 ns VCC1=5V, VCC2=15V, VEE2=-8V, CLOAD = 10nF, 10%-90% - 30 50 ns VCC1=5V, VCC2=15V, VEE2=-8V, no load, 10%90% - 150 235 ns VCC1=5V, VCC2=15V, VEE2=-8V, CLOAD = 10nF, 90%-10% - 60 100 ns VCC1=5V, VCC2=15V, VEE2=-8V, no load, 90%10% VGPOF0 5.4 6.0 6.3 V VGPOF1 6.4 7.0 7.3 V VGPOF2 7.3 8.0 8.4 V VGPOF3 8.2 9.0 9.4 V Referenced to GND2, measured at pin TON shorted with TOFF, no VBE compensation, VCC2=15V,TJUNC=25C VGPOF4 9.2 10.0 10.5 V VGPOF5 10.1 11.0 11.5 V VGPOF6 11.1 12.0 12.6 V VGPOF7 12.1 13.0 13.6 V VGPOF0 4.7 5.3 5.6 V VGPOF1 5.7 6.3 6.6 V VGPOF2 6.6 7.3 7.7 V VGPOF3 7.6 8.3 8.7 V VGPOF4 8.5 9.3 9.8 V VGPOF5 9.5 10.3 10.8 V VGPOF6 10.5 11.3 11.9 V VGPOF7 11.5 12.3 12.9 V Fall Time Voltage during TTOFF Plateau level Voltage during TTOFF Plateau level Data Sheet Hardware Description tFALL 126 Referenced to GND2, measured at pin TON shorted with TOFF, with VBE compensation, VCC2=15V,TJUNC=25C Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification Table 5-15 Switching Characteristics (cont'd) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Temperature variation from dVTm40 configured VTTOFF(25C) @TJ= - 40C - -110 - mV 1)3) Temperature variation from dVT150 configured VTTOFF(25C) @TJ= 150C - 110 - mV 1)3) TTOFF decrease rate - 9 - V/s TTOFF delay deviation from nominal tDEVTTOFF -100 value 0 100 ns For a target time of 2s, using the TCF1)2) TTOFF Plateau Time - 2.6 - s SRTTOF.RTVAL=26H 5.6 6.0 6.4 V 6.5 7.0 7.5 V VGPON2 7.45 8.0 8.5 V VGPON3 8.4 9.0 9.6 V Referenced to GND2, measured at pin TON shorted with TOFF, no VBE compensation, VCC2=15V,TJUNC=25C VGPON4 9.35 10.0 10.6 V VGPON5 10.3 11.0 11.7 V VGPON6 11.25 12.0 12.75 V Referenced to GND2, measured at pin TON shorted with TOFF, no VBE compensation, VCC2=16.5V,TJUNC=25C Voltage during TTON / WTO Plateau VGPON0 level VGPON1 6.2 6.7 7.1 V 7.15 7.7 8.15 V VGPON2 8.1 8.7 9.2 V VGPON3 9.0 9.7 10.3 V Referenced to GND2, measured at pin TON shorted with TOFF, with VBE compensation, VCC2=15V,TJUNC=25C VGPON4 10.0 10.7 11.2 V VGPON5 10.7 11.4 12 V VGPON6 11.55 12.4 13.1 V Referenced to GND2, measured at pin TON shorted with TOFF, with VBE compensation, VCC2=16.5V,TJUNC=25C TTON Delay tTTON - 8 - s SCFG.TTONVAL=7FH DACLP Delay tACL - 5 - s 4) tSLEW tTTOFF Voltage during TTON / WTO Plateau VGPON0 level VGPON1 1) 2) 3) 4) Values are valid only in case of stand-alone switching transistion. Not subject to production test. Parameters are verified by design / characterization. Measured without VBE compensation. If a following switching sequence is turning off during this time the delay will extend. Data Sheet Hardware Description 127 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.5.6 Desaturation Protection Table 5-16 DESAT characteristics Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. DESAT Input voltage range V15DESAT 0 - VCC2 V Referenced to GND2 DESAT Reference Level VDESAT0 8.5 9 9.5 V VCC2 =15V, VEE2 =-8V VDESAT1 2.9 3 3.1 V DESAT Pull-up Resistance RDSATPU 19 30 44 k VCC2 =15V, VEE2 =-8V, VDESAT=2V DESAT Low Voltage VDESATL - 200 - mV Referenced to GND2, Desat clamping enabled, Isink= 5mA. DESAT blanking time deviation from programmed value dtDESATBL -20 - +20 % After transition of the PWM command, assuming a 1 s programmed blanking time1) 1) Not subject to production test. Parameters are verified by design / characterization. Data Sheet Hardware Description 128 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.5.7 Overcurrent Protection Table 5-17 OCP characteristics Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. VOCP0 277 300 318 mV Referenced to OCPG VOCP1 564 600 630 mV Referenced to OCPG OCP blanking time deviation from programmed value dtOCPBL -20 - +20 % After transition of the PWM command, assuming a 1 s programmed blanking time1) OCP Pull-up Resistance RPUOCP2 40 100 175 k to internal 5V reference. OC error detection threshold 1) Not subject to production test. Parameters are verified by design / characterization. 5.5.8 Low Latency Digital Channel Table 5-18 Digital channel characteristics Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input to output propagation time primary to secondary tDPS - 2 4.5 s 1) Input to output propagation time secondary to primary tDSP - 2 4.5 s 1) 1) Given for single events only. If other communication events occure simultanously max. timing will increase. Data Sheet Hardware Description 129 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.5.9 Error Detection Timing Table 5-19 Error Detection Timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Dead Time for Shoot Through Protection tDEAD 800 - 1200 ns Default Value2) Class A event detection to NFLTA activation tAFLTA - 2 4.5 s VCC2=typ., VCC1=typ., VEE2=typ.2) Class A event detection to turn off sequence activation tOFFCLA - - 400 ns VTOFF=VCC2 - 1 V, VCC2=typ., VCC1=typ., VEE2=typ.2) DESAT event detection to turn off sequence activation tOFFDESAT2 - - 430 ns VTOFF=VCC2 - 1 V, after blanking time elapsed, VCC2=typ., VCC1=typ., VEE2=typ.2) OCP event occurrence to turn off sequence activation tOFFOCP2 - - 150 ns VTOFF=VCC2 - 1 V, after blanking time elapsed, VCC2=typ., VCC1=typ., VEE2=typ.2) Class B event detection to NFLTB activation tBFLTB - 2 4.5 s VCC2=typ., VCC1=typ., VEE2=typ.2) Class B event detection to turn off sequence activation tOFFCLB2 - - 400 ns VTOFF=VCC2 - 1 V, VCC2=typ., VCC1=typ., VEE2=typ.1)2) Verification Mode time out tVMTO - 15 - ms After a transition from OPM2 to OPM5, SCFG.TOSEN = 0B1)2) - 60 - ms After a transition from OPM2 to OPM5, SCFG.TOSEN = 1B1)2) - 5 - s After error condition detected by logic. Life sign error detection time tLS 1) Verified by design / characterization. Not tested in production. 2) Deviation of the clock needs to be considered. Data Sheet Hardware Description 130 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.5.10 SPI Interface Table 5-20 SPI Interface Characteristics Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SPI frame size Nbit N.a. N*16 N.a. bit N is the daisy chain length Baud rate fCLK 0.1 - 2 MHz 1)2) Serial clock period tSCLKp 0.5 - - s 3) SCLK duty cycle DSCLK 45 - 55 % 3) SDI set-up time tSDIsu 65 - - ns 3) SDI hold time tSDIh 100 - - ns 3) NCS lead time tCSlead 1 - - s 3) NCS trail time tCStrail 1 - - s 3) NCS inactive time tCSinact 10 - - s 3) SDO enable time tSDOen - - 500 ns Cload =20pF3) SDO disable time tSDOdis - - 1 s Cload =20pF3) SDO valid time tSDOv 10 - 185 ns Cload =20pF3) 1) Low Limit verified by design / characterization. Not tested in production. 2) In Daisy Chain the max. Baud rate is 1.8 MHz. 3) Verified by design / characterization. Not tested in production. t CSinact tSCLKp NCS tSCLKhigh tSCLKlow tCSlead tCStrail SCLK tSDIsu tSDIh SDI tSDOen tSDOdis t SDOv SDO Figure 5-2 SPI Interface Timing Data Sheet Hardware Description 131 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.5.11 ADC Table 5-21 ADC parameter Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition ADC Resolution Res n.a. 8 n.a. bit 1) Sampling time tSMPL - 120 - clock 1) Conversion time tCONV - 211 - clock 1) ADCT trigger signal propagation time tPTRIG - 2 tbd s 1) Internal Voltage Range ADC VINT - 2.75 - V Resulting in 93 LSB/V Preamplifier Gain GAIN0, GAIN1 - 2/3 - - Resulting in 62 LSB/V GAIN2 - 1 - - Resulting in 93 LSB/V GAIN3 - 2 - - Resulting in 186 LSB/V VOFF0 - 0.0 - V VOFF1 - 0.5 - V VOFF2 - 1.0 - V VOFF3 - 1.5 - V VOFF4 - 2.0 - V Offset Error EROFF -3.1 - 3.1 LSB Gain Error ERGAIN -5 - 5 INL INL - 1 1.6 LSB 2) DNL DNL - 0.4 0.75 LSB 2) Accuracy3) TUE - - 6.5 LSB Neg. error results in min. value.2) Automatic trigger period tATRIG 4 - ms 1) ADC Offset - , from ADC trigger active to end of sampling phase, in OSC2 domain. , from ADC trigger active to result available in the register, in OSC2 domain. , from valid signal on pin ADCT to start of conversion, external trigger mode only. Neg. error results in min. offset.2) Neg. error results in min. gain.2) 1) Verified by design / characterization. Not tested in production. 2) Accuracy related parameters are defined when the device is not switching a PWM signal. 3) Total Unadjusted Error is the square sum of all worst rms errors (DNL, INL, EROFF and ERGAIN). Data Sheet Hardware Description 132 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Specification 5.5.12 Insulation Characteristics Table 5-22 Isolation Characteristics referring to IEC 60747-5-2 (VDE 0884 - 10):2006-12 Description Symbol Characteristic Installation classification per EN60664-1, Table 1: rated main voltage less than 150 Vrms rated main voltage less than 300 Vrms rated main voltage less than 600 Vrms I - IV I - III I - II Climatic Classification 40 / 125 / 21 Pollution Degree (EN 60664-1) 2 Unit Minimum External Clearance CLR 8.12 mm Minimum External Creepage CPG 8.24 mm Minimum Comparative Tracking Index CTI 175 Maximum Repetitive Insulation Voltage VIORM 1420 VPEAK Highest Allowable Overvoltage VIOTM 6000 VPEAK Maximum Surge Insulation Voltage VIOSM 6000 VPEAK 1) 1) Refer to VDE 0884 for a detailed description of Method a and Method b partial discharge Table 5-23 Isolation Characteristics referring to UL 1577 Description Symbol Characteristic Unit Insulation Test Voltage / 1 min VISO 3750 Vrms Insulation Test Voltage / 1 sec VISO 4500 Vrms Data Sheet Hardware Description 133 Rev 2.0, 2017-06-19 EiceDRIVERTM SENSE 1EDI2010AS Package Information 6 Package Information Figure 6-1 Package Dimensions Figure 6-2 Recommended Footprint Data Sheet Hardware Description 134 Rev 2.0, 2017-06-19 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG