HT9170B/HT9170D DTMF Receiver Features * Operating voltage: 2.5V~5.5V * Tristate data output for MCU interface * Minimal external components * 3.58MHz crystal or ceramic resonator * No external filter is required * 1633Hz can be inhibited by the INH pin * Low standby current (on power down mode) * HT9170B: 18-pin DIP package HT9170D: 18-pin SOP package * Excellent performance General Description Highly accurate switched capacitor filters are implemented to divide tone signals into low and high group signals. A built-in dial tone rejection circuit is provided to eliminate the need for pre-filtering. The HT9170B/D are Dual Tone Multi Frequency (DTMF) receivers integrated with digital decoder and bandsplit filter functions as well as power-down mode and inhibit mode operations. Such devices use digital counting techniques to detect and decode all the 16 DTMF tone pairs into a 4-bit code output. Selection Table Function Operating Voltage OSC Frequency Tristate Data Output Power Down 1633Hz Inhibit DV DVB Part No. HT9170B 2.5V~5.5V 3.58MHz O O O O 3/4 18 DIP HT9170D 2.5V~5.5V 3.58MHz O O O O 3/4 18 SOP Package Block Diagram P W D N V R E F B ia s C ir c u it V re f G e n e ra to r R T /G T E S T D V D V B X 2 X 1 3 .5 8 M H z C ry s ta l O s c illa to r L o w V P V N G S O P A S te e r in g C o n tr o l C ir c u it G ro u p F ilte r F re q u e n c y P r e - F ilte r D e te c to r H ig h G r o u p F ilte r C o d e D e te c to r D 0 D 1 D 2 D 3 IN H Rev. 1.10 L a tc h & O u tp u t B u ffe r 1 O E September 24, 2002 HT9170B/HT9170D Pin Assignment V P 1 1 8 V D D V P 1 1 8 V D D V N 2 1 7 R T /G T V N 2 1 7 R T /G T G S 3 1 6 E S T G S 3 1 6 E S T V R E F 4 1 5 D V V R E F 4 1 5 D V IN H 5 1 4 D 3 IN H 5 1 4 D 3 P W D N 6 1 3 D 2 P W D N 6 1 3 D 2 X 1 7 1 2 D 1 X 1 7 1 2 D 1 X 2 8 1 1 D 0 X 2 8 1 1 D 0 V S S 9 1 0 O E V S S 9 1 0 O E H T 9 1 7 0 B 1 8 D IP -A H T 9 1 7 0 D 1 8 S O P -A Pin Description I/O Internal Connection VP I Operational Amplifier VN I Operational amplifier inverting input GS O Operational amplifier output terminal VREEF O X1 I Pin Name VREF Description Operational amplifier non-inverting input Reference voltage output, normally VDD/2 oscillator The system oscillator consists of an inverter, a bias resistor and the necessary load capacitor on chip. A standard 3.579545MHz crystal connected to X1 and X2 terminals implements the oscillator function. X2 O PWDN I CMOS IN Pull-low Active high. This enables the device to go into power down mode and inhibits the oscillator. This pin input is internally pulled down. INH I CMOS IN Pull-low Logic high. This inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down. VSS 3/4 3/4 OE I CMOS IN Pull-high D0~D3 O CMOS OUT Tristate Receiving data output terminals OE=H: Output enable OE=L: High impedance DV O CMOS OUT Data valid output When the chip receives a valid tone (DTMF) signal, the DV goes high; otherwise it remains low. EST O CMOS OUT Early steering output (see Functional Description) RT/GT I/O CMOS IN/OUT VDD 3/4 3/4 Rev. 1.10 Negative power supply, ground D0~D3 output enable, high active Tone acquisition time and release time can be set through connection with external resistor and capacitor. Positive power supply, 2.5V~5.5V for normal operation 2 September 24, 2002 HT9170B/HT9170D Approximate internal connection circuits O P E R A T IO N A L A M P L IF IE R V R E F C M O S IN P u ll- h ig h O S C IL L A T O R X 1 V O P A V + V N V P C M O S O U T T r is ta te X 2 E N O P A G S 1 0 M 2 0 p F C M O S IN P u ll- lo w C M O S IN /O U T C M O S O U T 1 0 p F Absolute Maximum Ratings Supply Voltage ............................................-0.3V to 6V Storage Temperature ............................-50C to 125C Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-20C to 75C Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=25C Test Conditions Min. Typ. Max. Unit 3/4 2.5 5 5.5 V VDD Conditions VDD Operating Voltage 3/4 IDD Operating Current 5V 3/4 3/4 3.0 7 mA ISTB Standby Current 5V PWDN=5V 3/4 10 25 mA VIL Low Input Voltage 5V 3/4 3/4 3/4 1.0 V VIH High Input Voltage 5V 3/4 4.0 3/4 3/4 V mA IIL Low Input Current 5V VVP=VVN=0V 3/4 3/4 0.1 IIH High Input Current 5V VVP=VVN=5V 3/4 3/4 0.1 mA ROE Pull-high Resistance (OE) 5V VOE=0V 60 100 150 kW RIN Input Impedance (VN, VP) 5V 3/4 3/4 10 3/4 MW IOH Source Current (D0~D3, EST, DV) 5V VOUT =4.5V -0.4 -0.8 3/4 mA IOL Sink Current (D0~D3, EST, DV) 5V VOUT =0.5V 1.0 2.5 3/4 mA fOSC System Frequency 5V Crystal=3.5795MHz 3.5759 3.5795 3.5831 MHz Rev. 1.10 3 September 24, 2002 HT9170B/HT9170D A.C. Characteristics Symbol Parameter fOSC=3.5795MHz, Ta=25C Test Conditions Min. Typ. Max. 3V -36 3/4 -6 5V -29 3/4 1 Twist Accept Limit (Positive) 5V 3/4 10 3/4 dB Twist Accept Limit (Negative) 5V 3/4 10 3/4 dB Dial Tone Tolerance 5V 3/4 18 3/4 dB Noise Tolerance 5V 3/4 -12 3/4 dB Third Tone Tolerance 5V 3/4 -16 3/4 dB Frequency Deviation Acceptance 5V 3/4 3/4 1.5 % Frequency Deviation Rejection 5V 3.5 3/4 3/4 % Power Up Time (See Figure 4.) 5V 3/4 30 3/4 ms 3/4 10 3/4 MW 3/4 0.1 3/4 mA 3/4 25 3/4 mV 3/4 60 3/4 dB 3/4 60 3/4 dB 3/4 65 3/4 dB Conditions VDD Unit DTMF Signal Input Signal Level tPU dBm Gain Setting Amplifier RIN Input Resistance 5V IIN Input Leakage Current 5V VOS Offset Voltage 5V PSRR Power Supply Rejection 5V CMRR Common Mode Rejection 5V AVO Open Loop Gain 5V fT Gain Band Width 5V VOUT Output Voltage Swing 5V RL Load Resistance (GS) 5V CL Load Capacitance (GS) 5V VCM Common Mode Range 5V 3/4 VSS<(VVP,VVN)<VDD 3/4 100 Hz -3V<VIN<3V 3/4 3/4 1.5 3/4 MHz 3/4 4.5 3/4 VPP 3/4 3/4 50 3/4 kW 3/4 3/4 100 3/4 pF 3/4 3.0 3/4 VPP RL>100kW No load Steering Control tDP Tone Present Detection Time 5 16 22 ms tDA Tone Absent Detection Time 3/4 4 8.5 ms tACC Acceptable Tone Duration 3/4 3/4 42 ms tREJ Rejected Tone Duration 20 3/4 3/4 ms tIA Acceptable Inter-digit Pause 3/4 3/4 42 ms tIR Rejected Inter-digit Pause 20 3/4 3/4 ms tPDO Propagation Delay (RT/GT to DO) 3/4 8 11 ms tPDV Propagation Delay (RT/GT to DV) 3/4 12 3/4 ms 3/4 ms tDOV Output Data Set Up (DO to DV) 3/4 4.5 tDDO Disable Delay (OE to DO) 3/4 300 3/4 ns tEDO Enable Delay (OE to DO) 3/4 50 60 ns Note: DO=D0~D3 Rev. 1.10 4 September 24, 2002 HT9170B/HT9170D V 1 1 0 0 k W T o n e 0 .1 m F 2 3 4 1 0 0 k W 5 6 3 .5 7 9 5 4 5 M H z 8 7 2 0 p F 2 0 p F 9 V P V D D V N R T /G T G S E S T V R E F D V IN H D 3 P W D N D 2 X 1 D 1 X 2 D 0 V S S O E D D 0 .1 m F 1 8 1 7 1 6 1 5 3 0 0 k W 1 4 1 3 1 2 1 1 1 0 H T 9 1 7 0 B /D Figure 1. Test circuit Functional Description When input signals are recognized to be effective, DV becomes high, and the correct tone code (DTMF) digit is transferred. Overview The HT9170B/D tone decoders consist of three band pass filters and two digital decode circuits to convert a tone (DTMF) signal into digital code output. Steering control circuit An operational amplifier is built-in to adjust the input signal (refer to Figure 2). C V i The steering control circuit is used for measuring the effective signal duration and for protecting against drop out of valid signals. It employs the analog delay by external RC time-constant controlled by EST. V P R 1 V N R F The timing is shown in Figure 3. The EST pin is normally low and draws the RT/GT pin to keep low through discharge of external RC. When a valid tone input is detected, EST goes high to charge RT/GT through RC. H T 9 1 7 0 B /D G S V R E F When the voltage of RT/GT changes from 0 to VTRT (2.35V for 5V supply), the input signal is effective, and the correct code will be created by the code detector. After D0~D3 are completely latched, DV output becomes high. When the voltage of RT/GT falls down from VDD to VTRT (i.e.., when there is no input tone), DV output becomes low, and D0~D3 keeps data until a next valid tone input is produced. ( a ) S ta n d a r d in p u t c ir c u it V i1 V i2 C 1 R 1 C 2 R 2 V P V N R 3 R 4 R 5 G S H T 9 1 7 0 B /D By selecting adequate external RC value, the minimum acceptable input tone duration (tACC) and the minimum acceptable inter-tone rejection (tIR) can be set. External components (R, C) are chosen by the formula (refer to Figure 5.): V R E F ( b ) D iffe r e n tia l in p u t c ir c u it Figure 2. Input operation for amplifier application circuits tACC=tDP+tGTP; tIR=tDA+tGTA; The pre-filter is a band rejection filter which reduces the dialing tone from 350Hz to 400Hz. where tACC: Tone duration acceptable time tDP: EST output delay time (L(R)H) The low group filter filters low group frequency signal output whereas the high group filter filters high group frequency signal output. tGTP: Tone present time tIR: Inter-digit pause rejection time tDA: EST output delay time (H(R)L) Each filter output is followed by a zero-crossing detector with hysteresis. When each signal amplitude at the output exceeds the specified level, it is transferred to full swing logic signal. Rev. 1.10 tGTA: Tone absent time 5 September 24, 2002 HT9170B/HT9170D Timing Diagrams tR E J t IR t IA T o n e n T o n e tD P tD T o n e n + 1 tD P tD A P E S T tA R T /G T V C C T R T tG tP D 0 ~ D 3 T o n e C o d e n 1 tG T A T o n e C o d e n + 1 T o n e C o d e n tD tP T P D O O V tP D V D V D V tD D O tE D O O E Figure 3. Steering timing T o n e T o n e P W D N E S T tP U Figure 4. Power up timing Rev. 1.10 6 September 24, 2002 HT9170B/HT9170D V V D D D D V D D V D D H T 9 1 7 0 B /D H T 9 1 7 0 B /D C R T /G T R E S T C R T /G T R 1 E S T D 1 (a) Fundamental circuit: tGTP = R C Ln (VDD / (VDD - VTRT)) tGTA = R C Ln (VDD / VTRT) V R 2 (c) tGTP > tGTA : tGTP = R1 C Ln (VDD / (VDD - VTRT)) tGTA = (R1 // R2) C Ln (VDD / VTRT) D D V D D H T 9 1 7 0 B /D C R T /G T R 1 E S T D 1 R 2 (b) tGTP < tGTA : tGTP = (R1 // R2) C Ln (VDD - VTRT)) tGTA = R1 C Ln (VDD / VTRT) Figure 5. Steering time adjustment circuits DTMF dialing matrix C O L 3 C O L 4 R O W 1 C O L 1 C O L 2 1 2 3 A R O W 2 4 5 6 B R O W 3 7 8 9 C 0 # D R O W 4 * DTMF data output table Low Group (Hz) High Group (Hz) Digit OE D3 D2 D1 D0 697 1209 1 H L L L H 697 1336 2 H L L H L 697 1477 3 H L L H H 770 1209 4 H L H L L 770 1336 5 H L H L H 770 1477 6 H L H H L 852 1209 7 H L H H H 852 1336 8 H H L L L 852 1477 9 H H L L H 941 1336 0 H H L H L 941 1209 * H H L H H 941 1477 # H H H L L 697 1633 A H H H L H 770 1633 B H H H H L 852 1633 C H H H H H 941 1633 D H L L L L 3/4 3/4 ANY L Z Z Z Z Note: Z High impedance; Rev. 1.10 ANY Any digit 7 September 24, 2002 HT9170B/HT9170D Data output The data outputs (D0~D3) are tristate outputs. When OE input becomes low, the data outputs (D0~D3) are high impedance. Application Circuits Application Circuit 1 V 1 1 0 0 k W D T M F 2 3 0 .1 m F 4 1 0 0 k W 5 T o o th e r d e v ic e 6 7 8 X 't a l 9 C 2 V S S C 1 Note: V P V D D V N R T /G T G S E S T V R E F D V IN H D 3 P W D N D 2 X 1 D 1 X 2 D 0 V S S O E 1 8 D D 0 .1 m F 1 7 1 6 1 5 3 0 0 k W 1 4 1 3 1 2 T o o th e r d e v ic e 1 1 1 0 H T 9 1 7 0 B /D Xtal = 3.579545MHz crystal C1 = C2 @ 20pF Xtal = 3.58MHz ceramic resonator C1 = C2 @ 39pF Application Circuit 2 V 0 .1 m F R 1 0 .1 m F A v = R 5 = 2 R 5 3 0 k 0 0 0 k 5 0 0 0 W k W k W C 1 C 2 R T /G T D V IN H 6 P W D N D 3 D 2 7 X 't a l k W V N V R E F 5 W V D D G S 4 T o o th e r d e v ic e = 3 = 6 = 1 = 6 = 1 = 3 V P E S T R 4 R 2 R 2 R 4 R 3 = R 2 + R 4 Note: R 2 R 3 R 3 + R 5 R 1 + R 3 E x a m p le : A v R 1 R 2 R 3 R 4 R 5 1 1 8 0 p F D T M F 8 9 V S S X 1 D 1 X 2 D 0 V S S O E 1 8 D D 0 .1 m F 1 7 1 6 3 0 0 k W 1 5 1 4 1 3 1 2 1 1 T o o th e r d e v ic e 1 0 H T 9 1 7 0 B /D Xtal = 3.579545MHz crystal C1 = C2 @ 20pF Xtal = 3.58MHz ceramic resonator C1 = C2 @ 39pF Rev. 1.10 8 September 24, 2002 HT9170B/HT9170D Package Information 18-pin DIP (300mil) outline dimensions A B 1 8 1 0 1 9 H C D E a G I F Symbol Rev. 1.10 Dimensions in mil Min. Nom. Max. A 895 3/4 915 B 240 3/4 260 C 125 3/4 135 D 125 3/4 145 E 16 3/4 20 F 50 3/4 70 G 3/4 100 3/4 H 295 3/4 315 I 335 3/4 375 a 0 3/4 15 9 September 24, 2002 HT9170B/HT9170D 18-pin SOP (300mil) outline dimensions 1 0 1 8 B A 9 1 C C ' G H D E Symbol Rev. 1.10 a F Dimensions in mil Min. Nom. Max. A 394 3/4 419 B 290 3/4 300 C 14 3/4 20 C 447 3/4 460 D 92 3/4 104 E 3/4 50 3/4 F 4 3/4 3/4 G 32 3/4 38 H 4 3/4 12 a 0 3/4 10 10 September 24, 2002 HT9170B/HT9170D Product Tape and Reel Specifications Reel dimensions , 6 ) + * 6 SOP 18W Symbol Description A Reel Outer Diameter B Reel Inner Diameter Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 C Spindle Hole Diameter D Key Slit Width 2.00.5 T1 Space Between Flange 24.8+0.3 -0.2 T2 Reel Thickness 30.20.2 Rev. 1.10 11 September 24, 2002 HT9170B/HT9170D Carrier tape dimensions P 0 D P 1 t E F W C D 1 B 0 P K 0 A 0 SOP 18W Symbol W Description Dimensions in mm Carrier Tape Width 24.0+0.3 -0.1 16.00.1 P Cavity Pitch E Perforation Position 1.750.1 F Cavity to Perforation (Width Direction) 11.50.1 D Perforation Diameter 1.50.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.00.1 P1 Cavity to Perforation (Length Direction) 2.00.1 A0 Cavity Length 10.90.1 B0 Cavity Width 12.00.1 K0 Cavity Depth 2.80.1 t Carrier Tape Thickness 0.30.05 C Cover Tape Width Rev. 1.10 21.3 12 September 24, 2002 HT9170B/HT9170D Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 13 September 24, 2002