HT9170D-18SOPLF - HOLTEK - Datasheet.Live

HT9170B/HT9170D

DTMF Receiver

Selection Table

Function Operating

Voltage

OSC

Frequency

Tristate

Data Output

Power

Down

1633Hz

Inhibit DV DVB Package

Part No.

HT9170B 2.5V~5.5V 3.58MHz ÖÖÖÖ¾

18 DIP

HT9170D 2.5V~5.5V 3.58MHz ÖÖÖÖ¾

18 SOP

Block Diagram

Rev. 1.10 1 September 24, 2002

Features

·Operating voltage: 2.5V~5.5V

·Minimal external components

·No external filter is required

·Low standby current (on power down mode)

·Excellent performance

·Tristate data output for MCU interface

·3.58MHz crystal or ceramic resonator

·1633Hz can be inhibited by the INH pin

·HT9170B: 18-pin DIP package

HT9170D: 18-pin SOP package

General Description

The HT9170B/D are Dual Tone Multi Frequency (DTMF)

receivers integrated with digital decoder and bandsplit

filter functions as well as power-down mode and inhibit

mode operations. Such devices use digital counting

techniques to detect and decode all the 16 DTMF tone

pairs into a 4-bit code output.

Highly accurate switched capacitor filters are imple-

mented to divide tone signals into low and high group

signals. A built-in dial tone rejection circuit is provided to

eliminate the need for pre-filtering.

O P A

X 2

X 1

3 . 5 8 M H z

C r y s t a l

O s c i l l a t o r

V r e f

G e n e r a t o r

L o w G r o u p

F i l t e r

H i g h G r o u p

F i l t e r

S t e e r i n g C o n t r o l C i r c u i t

P r e - F i l t e r

V P

V N

G S

F r e q u e n c y

D e t e c t o r

C o d e

D e t e c t o r

L a t c h

O u t p u t

B u f f e r

O E

V R E F R T / G T E S T D V

D 0

D 1

D 2

D 3

I N H

B i a s

C i r c u i t

P W D N D V B

Pin Assignment

Pin Description

Pin Name I/O Internal

Connection Description

VP I Operational

Amplifier Operational amplifier non-inverting input

VN I Operational amplifier inverting input

GS O Operational amplifier output terminal

VREEF O VREF Reference voltage output, normally VDD/2

X1 I

oscillator

The system oscillator consists of an inverter, a bias resistor and the necessary

load capacitor on chip.

A standard 3.579545MHz crystal connected to X1 and X2 terminals imple-

ments the oscillator function.

X2 O

PWDN I CMOS IN

Pull-low

Active high. This enables the device to go into power down mode and inhibits

the oscillator. This pin input is internally pulled down.

INH I CMOS IN

Pull-low

Logic high. This inhibits the detection of tones representing characters A, B, C

and D. This pin input is internally pulled down.

VSS ¾¾

Negative power supply, ground

OE I CMOS IN

Pull-high D0~D3 output enable, high active

D0~D3 O CMOS OUT

Tristate

Receiving data output terminals

OE=²H²: Output enable

OE=²L²: High impedance

DV O CMOS OUT

Data valid output

When the chip receives a valid tone (DTMF) signal, the DV goes high; other-

wise it remains low.

EST O CMOS OUT Early steering output (see Functional Description)

RT/GT I/O CMOS IN/OUT Tone acquisition time and release time can be set through connection with ex-

ternal resistor and capacitor.

VDD ¾¾

Positive power supply, 2.5V~5.5V for normal operation

HT9170B/HT9170D

Rev. 1.10 2 September 24, 2002

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

V D D

R T / G T

E S T

D V

D 3

D 2

D 1

D 0

O E

V P

V N

G S

V R E F

I N H

P W D N

X 1

X 2

VSS

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

V D D

R T / G T

E S T

D V

D 3

D 2

D 1

D 0

O E

V P

V N

G S

V R E F

I N H

P W D N

X 1

X 2

VSS

H T 9 1 7 0 B

1 8 D I P - A

H T 9 1 7 0 D

1 8 S O P - A

Approximate internal connection circuits

Absolute Maximum Ratings

Supply Voltage ............................................-0.3V to 6V Storage Temperature ............................-50°Cto125°C

Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-20°Cto75°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings²may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

D.C. Characteristics Ta=25°C

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDD Conditions

VDD Operating Voltage ¾¾ 2.5 5 5.5 V

IDD Operating Current 5V ¾¾

3.0 7 mA

ISTB Standby Current 5V PWDN=5V ¾10 25 mA

VIL ²Low²Input Voltage 5V ¾¾¾

1.0 V

VIH ²High²Input Voltage 5V ¾4.0 ¾¾ V

IIL ²Low²Input Current 5V VVP=VVN=0V ¾¾

0.1 mA

IIH ²High²Input Current 5V VVP=VVN=5V ¾¾

0.1 mA

ROE Pull-high Resistance (OE) 5V VOE=0V 60 100 150 kW

RIN Input Impedance (VN, VP) 5V ¾¾

10 ¾MW

IOH Source Current (D0~D3, EST, DV) 5V VOUT =4.5V -0.4 -0.8 ¾mA

IOL Sink Current (D0~D3, EST, DV) 5V VOUT =0.5V 1.0 2.5 ¾mA

fOSC System Frequency 5V Crystal=3.5795MHz 3.5759 3.5795 3.5831 MHz

HT9170B/HT9170D

Rev. 1.10 3 September 24, 2002

V -

V +

O P E R A T I O N A L

A M P L I F I E R

V N

V P G S

X 1 X 2

O S C I L L A T O R

C M O S I N

P u l l - h i g h

C M O S O U T

T r i s t a t e

E N

C M O S O U T C M O S I N / O U T

V R E F

O P A

2 0 p F 1 0 M 1 0 p F

C M O S I N

P u l l - l o w

A.C. Characteristics fOSC=3.5795MHz, Ta=25°C

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDD Conditions

DTMF Signal

Input Signal Level

3V -36 ¾-6dBm

5V -29 ¾1

Twist Accept Limit (Positive) 5V ¾10 ¾dB

Twist Accept Limit (Negative) 5V ¾10 ¾dB

Dial Tone Tolerance 5V ¾18 ¾dB

Noise Tolerance 5V ¾-12 ¾dB

Third Tone Tolerance 5V ¾-16 ¾dB

Frequency Deviation Acceptance 5V ¾¾±1.5 %

Frequency Deviation Rejection 5V ±3.5 ¾¾%

tPU Power Up Time (See Figure 4.) 5V ¾30 ¾ms

Gain Setting Amplifier

RIN Input Resistance 5V ¾¾

10 ¾MW

IIN Input Leakage Current 5V VSS<(VVP,VVN)<VDD ¾0.1 ¾mA

VOS Offset Voltage 5V ¾¾±25 ¾mV

PSRR Power Supply Rejection 5V

100 Hz

-3V<VIN<3V

¾60 ¾dB

CMRR Common Mode Rejection 5V ¾60 ¾dB

AVO Open Loop Gain 5V ¾65 ¾dB

fTGain Band Width 5V ¾¾

1.5 ¾MHz

VOUT Output Voltage Swing 5V RL>100kW¾

4.5 ¾VPP

RLLoad Resistance (GS) 5V ¾¾

50 ¾kW

CLLoad Capacitance (GS) 5V ¾¾

100 ¾pF

VCM Common Mode Range 5V No load ¾3.0 ¾VPP

Steering Control

tDP Tone Present Detection Time 5 16 22 ms

tDA Tone Absent Detection Time ¾4 8.5 ms

tACC Acceptable Tone Duration ¾¾42 ms

tREJ Rejected Tone Duration 20 ¾¾

tIA Acceptable Inter-digit Pause ¾¾42 ms

tIR Rejected Inter-digit Pause 20 ¾¾

tPDO Propagation Delay (RT/GT to DO) ¾811

tPDV Propagation Delay (RT/GT to DV) ¾12 ¾ms

tDOV Output Data Set Up (DO to DV) ¾4.5 ¾ms

tDDO Disable Delay (OE to DO) ¾300 ¾ns

tEDO Enable Delay (OE to DO) ¾50 60 ns

Note: DO=D0~D3

HT9170B/HT9170D

Rev. 1.10 4 September 24, 2002

HT9170B/HT9170D

Rev. 1.10 5 September 24, 2002

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

V D D

R T / G T

E S T

D V

D 3

D 2

D 1

D 0

O E

V P

V N

G S

V R E F

I N H

P W D N

X 1

X 2

VSS

H T 9 1 7 0 B / D

0 . 1

3 0 0 k W

D D

3.579545M H z

1 0 0 k W

0 . 1

T o n e

2 0 p F2 0 p F

Figure 1. Test circuit

Functional Description

Overview

The HT9170B/D tone decoders consist of three band

pass filters and two digital decode circuits to convert a

tone (DTMF) signal into digital code output.

An operational amplifier is built-in to adjust the input sig-

nal (refer to Figure 2).

The pre-filter is a band rejection filter which reduces the

dialing tone from 350Hz to 400Hz.

The low group filter filters low group frequency signal

output whereas the high group filter filters high group

frequency signal output.

Each filter output is followed by a zero-crossing detector

with hysteresis. When each signal amplitude at the out-

put exceeds the specified level, it is transferred to full

swing logic signal.

When input signals are recognized to be effective, DV

becomes high, and the correct tone code (DTMF) digit is

transferred.

Steering control circuit

The steering control circuit is used for measuring the ef-

fective signal duration and for protecting against drop

out of valid signals. It employs the analog delay by exter-

nal RC time-constant controlled by EST.

The timing is shown in Figure 3. The EST pin is normally

low and draws the RT/GT pin to keep low through dis-

charge of external RC. When a valid tone input is de-

tected, EST goes high to charge RT/GT through RC.

When the voltage of RT/GT changes from 0 to VTRT

(2.35V for 5V supply), the input signal is effective, and

the correct code will be created by the code detector. Af-

ter D0~D3 are completely latched, DV output becomes

high. When the voltage of RT/GT falls down from VDD to

VTRT (i.e.., when there is no input tone), DV output be-

comes low, and D0~D3 keeps data until a next valid

tone input is produced.

By selecting adequate external RC value, the minimum ac-

ceptable input tone duration (tACC) and the minimum ac-

ceptable inter-tone rejection (tIR) can be set. External

components (R, C) are chosen by the formula (refer to Fig-

ure 5.):

tACC=tDP+tGTP;

tIR=tDA+tGTA;

where tACC: Tone duration acceptable time

tDP: EST output delay time (²L²®²H²)

tGTP: Tone present time

tIR: Inter-digit pause rejection time

tDA: EST output delay time (²H²®²L²)

tGTA: Tone absent time

V N

G S

V R E F

H T 9 1 7 0 B / D

CR 1

R F

( a ) S t a n d a r d i n p u t c i r c u i t

V P

V N

G S

V R E F

C 2 R 2

R 5

( b ) D i f f e r e n t i a l i n p u t c i r c u i t

V P

R 4R 3

C 1 R 1

Vi 1

Vi 2

H T 9 1 7 0 B / D

Figure 2. Input operation for amplifier application circuits

Timing Diagrams

HT9170B/HT9170D

Rev. 1.10 6 September 24, 2002

I A

I R

T o n e

EST

R T / G T

D 0 ~ D 3

D V

O E

P D V

DDO

P D O

A C C

E D O

G T A

R E J

D P

D A

G T P

D O V

T o n e n T o n e n + 1

T o n e C o d e n + 1

T R T

P D V

D P

T o n e C o d e n 1 T o n e C o d e n

Figure 3. Steering timing

T o n e

P W D N

EST

T o n e

P U

Figure 4. Power up timing

Figure 5. Steering time adjustment circuits

DTMF dialing matrix

DTMF data output table

Low Group (Hz) High Group (Hz) Digit OE D3 D2 D1 D0

697 1209 1 H L L L H

697 1336 2 H L L H L

697 1477 3 H L L H H

770 1209 4HLHL L

770 1336 5HLHLH

770 1477 6HLHHL

852 1209 7HLHHH

852 1336 8 H H L L L

852 1477 9 H H L L H

941 1336 0 H H L H L

941 1209 * H H L H H

941 1477 # H H H L L

697 1633 A H H H L H

770 1633 B HHHH L

852 1633 CHHHHH

941 1633 D H L L L L

¾¾

ANY L Z Z Z Z

Note: ²Z²High impedance; ²ANY²Any digit

HT9170B/HT9170D

Rev. 1.10 7 September 24, 2002

R O W 1

R O W 2

R O W 3

R O W 4

C O L 1 C O L 2 C O L 3 C O L 4

V D D

R T / G T

E S T

VD D

H T 9 1 7 0 B / D

(a) Fundamental circuit:

tGTP =R´C´Ln (VDD /(V

DD -VTRT))

tGTA =R´C´Ln (VDD /V

TRT)

R 1

V D D

R T / G T

E S T

R 2

D 1

VD D

H T 9 1 7 0 B / D

(b) tGTP <t

GTA :

tGTP = (R1 // R2) ´C´Ln (VDD -VTRT))

tGTA =R1´C´Ln (VDD /V

TRT)

R 1

V D D

R T / G T

E S T

R 2

D 1

VD D

H T 9 1 7 0 B / D

GTA :

tGTP =R1´C´Ln (VDD /(V

DD -VTRT))

tGTA = (R1 // R2) ´C´Ln (VDD /V

TRT)

Data output

The data outputs (D0~D3) are tristate outputs. When OE input becomes low, the data outputs (D0~D3) are high imped-

ance.

Application Circuits

Application Circuit 1

Application Circuit 2

HT9170B/HT9170D

Rev. 1.10 8 September 24, 2002

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

V D D

R T / G T

E S T

D V

D 3

D 2

D 1

D 0

O E

V P

V N

G S

V R E F

I N H

P W D N

X 1

X 2

V S S

0 . 1

300k

VD D

100k

0 . 1

D T M F

T o o t h e r d e v i c e

V S S

X ' t a l

C 1 C 2

T o o t h e r d e v i c e

H T 9 1 7 0 B / D

E x a m p l e :

A v = 3

R 1 = 6 0 k

R 2=100k

R 3 = 6 0 k

R 4=150k

R 5=300k

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

V D D

R T / G T

E S T

D V

D 3

D 2

D 1

D 0

O E

V P

V N

G S

V R E F

I N H

P W D N

X 1

X 2

V S S

0 . 1

300k

VD D

V S S

0 . 1

T o o t h e r d e v i c e

D T M F

X ' t a l

C 1 C 2

0 . 1

R 1

R 2

180pF

R 3

R 4

R 5

R 3 = R 2 R 4

R 2 + R 4

R 3 + R 5

R 1 + R 3

R 5

R 2

A v = =

H T 9 1 7 0 B / D

T o o t h e r d e v i c e

Note: X¢tal = 3.579545MHz crystal

C1=C2@20pF

X¢tal = 3.58MHz ceramic resonator

C1=C2@39pF

Note: X¢tal = 3.579545MHz crystal

C1=C2@20pF

X¢tal = 3.58MHz ceramic resonator

C1=C2@39pF

Package Information

18-pin DIP (300mil) outline dimensions

Symbol Dimensions in mil

Min. Nom. Max.

A 895 ¾915

B 240 ¾260

C 125 ¾135

D 125 ¾145

E16

¾20

F50

¾70

G¾100 ¾

H 295 ¾315

I 335 ¾375

a0°¾15°

HT9170B/HT9170D

Rev. 1.10 9 September 24, 2002

1 8

1 0

18-pin SOP (300mil) outline dimensions

Symbol Dimensions in mil

Min. Nom. Max.

A 394 ¾419

B 290 ¾300

C14

¾20

C¢447 ¾460

D92

¾104

E¾50 ¾

¾¾

G32¾38

¾12

a0°¾10°

HT9170B/HT9170D

Rev. 1.10 10 September 24, 2002

1 8

1 0

C '

Product Tape and Reel Specifications

Reel dimensions

SOP 18W

Symbol Description Dimensions in mm

A Reel Outer Diameter 330±1.0

B Reel Inner Diameter 62±1.5

C Spindle Hole Diameter 13.0+0.5

-0.2

D Key Slit Width 2.0±0.5

T1 Space Between Flange 24.8+0.3

-0.2

T2 Reel Thickness 30.2±0.2

HT9170B/HT9170D

Rev. 1.10 11 September 24, 2002

6 

6 ,

Carrier tape dimensions

SOP 18W

Symbol Description Dimensions in mm

W Carrier Tape Width 24.0+0.3

-0.1

P Cavity Pitch 16.0±0.1

E Perforation Position 1.75±0.1

F Cavity to Perforation (Width Direction) 11.5±0.1

D Perforation Diameter 1.5±0.1

D1 Cavity Hole Diameter 1.5+0.25

P0 Perforation Pitch 4.0±0.1

P1 Cavity to Perforation (Length Direction) 2.0±0.1

A0 Cavity Length 10.9±0.1

B0 Cavity Width 12.0±0.1

K0 Cavity Depth 2.8±0.1

t Carrier Tape Thickness 0.3±0.05

C Cover Tape Width 21.3

HT9170B/HT9170D

Rev. 1.10 12 September 24, 2002

PD 1

P 1P 0

K 0

B 0

A 0

HT9170B/HT9170D

Rev. 1.10 13 September 24, 2002

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due

malfunction

otherwise.

Holtek¢s

products

are

not

authorized

for

use

critical

components

life

support

devices

systems.

Holtek

reserves

the

right

alter

its

products

without

prior

notification.

For

the

most

up-to-date

information,

please visit our web site at http://www.holtek.com.tw.

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