5962-8983004RA - LINEAR TECHNOLOGY

REVISIONS

LTR DESCRIPTION DATE (YR-MO-DA) APPROVED

Changes in accordance with NOR 5962-R119-92.

92-02-12

M. A. Frye

Add device types 02, 03, and 04. Changes in table I and figure 1. Editorial

changes throughout.

93-05-26

M. A. Frye

Changes in accordance with NOR 5962-R010-94.

93-10-15

M. A. Frye

Incorporate revision C, NOR. Update drawing to current requirements.

Editorial changes throughout. - drw

07-04-25

Robert M. Heber

THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED.

REV

SHEET

REV

SHEET

REV STATUS REV D D D D D D D D D D D

OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11

PMIC N/A PREPARED BY

Rick C. Officer

DEFENSE SUPPLY CENTER COLUMBUS

STANDARD

MICROCIRCUIT

DRAWING

CHECKED BY

Charles E. Besore

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

APPROVED BY

Michael A. Frye

MICROCIRCUIT, LINEAR, DATA ACQUISITION

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

DRAWING APPROVAL DATE

90-03-08

SYSTEM, MONOLITHIC SILICON

AMSC N/A

REVISION LEVEL

SIZE

CAGE CODE

67268

5962-89830

SHEET

1 OF

DSCC FORM 2233

APR 97 5962-E386-07

STANDARD

MICROCIRCUIT DRAWING

SIZE

5962-89830

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

REVISION LEVEL

SHEET 2

DSCC FORM 2234

APR 97

1. SCOPE

1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in

accordance with MIL-PRF-38535, appendix A.

1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:

5962-89830 01 R A

Drawing number Device type

(see 1.2.1)

Case outline

(see 1.2.2)

Lead finish

(see 1.2.3)

1.2.1 Device types. The device types identify the circuit function as follows:

Device type Generic number Circuit function Gain error

01 LTC1090 10-bit data acquisition system ±2.0 LSB

02 LTC1290B 12-bit data acquisition system ±0.5 LSB

03 LTC1290C 12-bit data acquisition system ±1.0 LSB

04 LTC1290D 12-bit data acquisition system ±4.0 LSB

1.2.2 Case outline. The case outline is as designated in MIL-STD-1835 as follows:

Outline letter Descriptive designator Terminals Package style

R GDIP1-T20 or CDIP2-T20 20 Dual-in-line

1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.

1.3 Absolute maximum ratings. 1/

Supply voltage (V+) to GND or (V-) ................................................................. 12 Vdc

Negative supply voltage (V-)............................................................................ -6 V to GND

Analog and reference input voltage range ....................................................... (V-) -0.3 V to V+ +0.3 V

Digital input voltage range ............................................................................... -0.3 V to 12 V

Digital output voltage range ............................................................................. -0.3 V to V+ +0.3 V

Power dissipation (PD) ..................................................................................... 500 mW

Lead temperature (soldering, 10 seconds) ...................................................... +300°C

Storage temperature range.............................................................................. -65°C to +150°C

Junction temperature (TJ) ................................................................................ +175°C

Thermal resistance, junction-to-case (θJC)....................................................... See MIL-STD-1835

Thermal resistance, junction-to-ambient (θJA).................................................. 70°C/W

________

1/ All voltage values are with respect to ground with DGND, AGND, and REF- wired together, unless otherwise noted.

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1.4 Recommended operating conditions. 2/

Positive supply voltage range (V+) .................................................................. 4.5 V dc to 10 V dc

Negative supply voltage range (V-).................................................................. -5.5 V dc to 0 V dc

Shift clock frequency range (fSCLK):

Device type 01 ............................................................................................. 0 to 1.0 MHz

Device type 02, 03, 04.................................................................................. 0 to 2.0 MHz

A/D clock frequency range (fACLK):

Device type 01 ............................................................................................. fSCLK to 2.0 MHz

Device type 02, 03, 04.................................................................................. fSCLK to 4.0 MHz

Total cycle time (tCYC):

Device type 01 ............................................................................................. 10 SCLK + 48 ACLK cycles minimum

Device type 02, 03, 04.................................................................................. 12 SCLK + 56 ACLK cycles minimum

Hold time,

CS low after last SCLK negative edge (tHCS) ................................. 0 ns minimum

Hold time, DIN after SCLK positive edge (tHD):

Device type 01 ............................................................................................. 150 ns minimum

Device type 02, 03, 04.................................................................................. 50 ns minimum

Setup time,

CS negative edge before clocking in first address bit (tSUCS):

Device type 01 ............................................................................................. 2 ACLK cycles + 1 µs minimum

Device type 02, 03, 04.................................................................................. 2 ACLK cycles + 100 ns minimum

Setup time, DIN stable before SCLK positive edge (tSUD):

Device type 01 ............................................................................................. 400 ns minimum

Device type 02, 03, 04.................................................................................. 50 ns minimum

ACLK high time (tWHACLK), device type 01 ........................................................ 127 ns minimum

ACLK low time (tWLACLK), device type 01.......................................................... 200 ns minimum

CS high time during conversion (tWHCS):

Device type 01 ............................................................................................. 44 ACLK cycles ninimum

Device type 02, 03, 04.................................................................................. 52 ACLK cycles ninimum

Ambient operating temperature range (TA) ...................................................... -55°C to +125°C

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICATION

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-883 - Test Method Standard Microcircuits.

MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 - List of Standard Microcircuit Drawings.

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or

from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

________

2/ V+ = 5.0 V dc, unless otherwise noted.

STANDARD

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SIZE

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REVISION LEVEL

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DSCC FORM 2234

APR 97

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-

JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer

Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-

PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying

activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan

may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device.

These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-

PRF-38535 is required to identify when the QML flow option is used.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535, appendix A and herein.

3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are

as specified in table I and shall apply over the full ambient operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical

tests for each subgroup are described in table I.

3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed

in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN

number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device.

3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance

to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in

accordance with MIL-PRF-38535 to identify when the QML flow option is used.

3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an

approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to

listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535,

appendix A and the requirements herein.

3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided

with each lot of microcircuits delivered to this drawing.

3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing.

3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's

facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the

reviewer.

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SIZE

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REVISION LEVEL

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DSCC FORM 2234

APR 97

TABLE I. Electrical performance characteristics.

Test

Symbol

Conditions 1/

-55°C ≤ TA ≤ +125°C

unless otherwise specified

Group A

subgroups

Device

type

Limits

Unit

Min Max

High level input voltage VIH V+ = 5.25 V 1, 2, 3 All 2.0 V

Low level input voltage VIL V+ = 4.75 V 1, 2, 3 All 0.8 V

High level input current IIH V

IN = V+ 1, 2, 3 All 2.5 µA

Low level input current IIL V

IN = 0 V 1, 2, 3 All -2.5 µA

High level output voltage VOH V+ = 4.75 V, IO = 360 µA 1, 2, 3 All 2.4 V

Low level output voltage VOL V+ = 4.75 V, IO = 1.6 mA 1, 2, 3 All 0.4 V

Hi-Z output leakage IOZ VOUT = V+, CS high 1, 2, 3 All 3.0 µA

VOUT = 0 V, CS high -3.0

Positive supply current I+ CS high, REF+ open 1, 2, 3 01 2.5 mA

02, 03,

04 12

Reference current IREF V

REF = 5 V 1, 2, 3 01 1.0 mA

02, 03,

04 0.05

Negative supply current I- CS high, V- = -5 V 1, 2, 3 All 50 µA

Offset error 2/ VOS 1, 2, 3 01 ±0.5 LSB

02, 03,

04 ±1.5

Linearity error 2/, 3/ 1, 2, 3 01, 02,

03 ±0.5 LSB

04 ±0.75

Gain error 2/ AE 1, 2, 3 01 ±2.0 LSB

02 ±0.5

03 ±1.0

04 ±4.0

See footnotes at end of table.

STANDARD

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SIZE

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DEFENSE SUPPLY CENTER COLUMBUS

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REVISION LEVEL

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DSCC FORM 2234

APR 97

TABLE I. Electrical performance characteristics – continued.

Test

Symbol

Conditions 1/

-55°C ≤ TA ≤ +125°C

unless otherwise specified

Group A

subgroups

Device

type

Limits

Unit

Min Max

Total unadjusted error 2/, 4/ VREF = 5 V 1, 2, 3 01 ±2.0 LSB

Analog and REF input range

5/ 1, 2, 3 All (V-)

-0.02

(V+)

+0.02 V

On channel leakage current

6/ RON On channel = 5 V,

Off channel = 0 V 1, 2, 3 All 1 µA

On channel = 0 V,

Off channel = 5 V -1

Off channel leakage current

6/ ROFF On channel = 5 V,

Off channel = 0 V 1, 2, 3 All 1 µA

On channel = 0 V,

Off channel = 5 V -1

Delay time, SCLK negative

edge to DOUT data valid tdDO See figures 2 and 3 9, 10, 11 01 450 ns

02, 03,

04 270

Delay time, CS positive

edge to DOUT Hi-Z tdis See figures 2 and 3 9, 10, 11 01 300 ns

02, 03,

04 100

Delay time, 2nd CLK

negative edge to DOUT ten See figures 2 and 3 9, 10, 11 01 400 ns

enabled 02, 03,

04 200

DOUT fall time tf See figures 2 and 3 9, 10, 11 01 300 ns

02, 03,

04 130

DOUT rise time tr See figures 2 and 3 9, 10, 11 01 300 ns

02, 03,

04 50

1/ V+ = 5 V, VREF+ = 5 V, VREF- = 0 V, V- = 0 V for unipolar mode and -5 V for bipolar mode, ACLK = 4.0 MHz unless otherwise

specified.

2/ Applies for both unipolar and bipolar modes.

3/ Linearity error is specified between the actual end-points of the A/D transfer curve.

4/ Total unadjusted error includes offset, gain, linearity, multiplexer and hold step errors.

5/ Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages,

one diode drop below V- or one diode drop above VCC. Be careful during testing at low VCC levels (4.5 V), as high level

reference or analog inputs (5 V) can cause this input diode to conduct, especially at elevated temperatures, and cause

errors for inputs near full-scale. This specification allows 50 mV forward bias of either diode. This means that as long as

the reference or analog input does not exceed the supply voltage by more than 50 mV, the output code will be correct. To

achieve an absolute 0 V to 5 V input voltage range will therefore require a minimum supply voltage of 4.950 V over initial

tolerance, temperature variations and loading.

6/ Channel leakage current is measured after the channel selection

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REVISION LEVEL

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DSCC FORM 2234

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Device type 01, 02, 03, 04

Case outline R

Terminal

number Terminal symbol

1 CH0

2 CH1

3 CH2

4 CH3

5 CH4

6 CH5

7 CH6

8 CH7

9 COM

10 DGND

11 AGND

12 V-

13 REF-

14 REF+

15 CS

16 DOUT

17 DIN

18 SCLK

19 ACLK

20 V+

FIGURE 1. Terminal connections.

STANDARD

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DSCC FORM 2234

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NOTES:

1. Waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control.

2. Waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control.

FIGURE 2. Timing waveforms.

STANDARD

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FIGURE 3. Test circuits.

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DSCC FORM 2234

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4. VERIFICATION

4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,

appendix A.

4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices

prior to quality conformance inspection. The following additional criteria shall apply:

a. Burn-in test, method 1015 of MIL-STD-883.

(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level

control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify

the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method

1015 of MIL-STD-883.

(2) TA = +125°C, minimum.

b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter

tests prior to burn-in are optional at the discretion of the manufacturer.

TABLE II. Electrical test requirements.

MIL-STD-883 test requirements

Subgroups

(in accordance with

MIL-STD-883, method 5005,

table I)

Interim electrical parameters

(method 5004) 1

Final electrical test parameters

(method 5004) 1*, 2, 3, 9, 10, 11

Group A test requirements

(method 5005) 1, 2, 3, 9, 10, 11

Groups C and D end-point

electrical parameters

(method 5005)

* PDA applies to subgroup 1.

4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-

883 including groups A, B, C, and D inspections. The following additional criteria shall apply.

4.3.1 Group A inspection.

a. Tests shall be as specified in table II herein.

b. Subgroups 4, 5, 6, 7, and 8 in table I, method 5005 of MIL-STD-883 shall be omitted.

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4.3.2 Groups C and D inspections.

a. End-point electrical parameters shall be as specified in table II herein.

b. Steady-state life test conditions, method 1005 of MIL-STD-883.

(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision

level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in

method 1005 of MIL-STD-883.

(2) TA = +125°C, minimum.

(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.

5. PACKAGING

5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.

6. NOTES

6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications

(original equipment), design applications, and logistics purposes.

6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-

prepared specification or drawing.

6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for

the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.

6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system

application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be

used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC

5962) should contact DSCC-VA, telephone (614) 692-0544.

6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone

(614) 692-0547.

6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-

HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by

DSCC-VA.

STANDARD MICROCIRCUIT DRAWING BULLETIN

DATE: 07-04-25

Approved sources of supply for SMD 5962-89830 are listed below for immediate acquisition information only and shall

be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised

to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate

of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next

dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of

supply at http://www.dscc.dla.mil/Programs/Smcr/.

Standard

microcircuit drawing

PIN 1/

Vendor

CAGE

number

Vendor

similar

PIN 2/

5962-8983001RA 3/ LTC1090MJ/883C

5962-8983002RA 3/ LTC1290BMJ/883C

5962-8983003RA 3/ LTC1290CMJ/883C

5962-8983004RA 3/ LTC1290DMJ/883C

1/ The lead finish shown for each PIN representing

a hermetic package is the most readily available

from the manufacturer listed for that part. If the

desired lead finish is not listed contact the vendor

to determine its availability.

2/ Caution. Do not use this number for item

acquisition. Items acquired to this number may not

satisfy the performance requirements of this drawing.

3/ Not available from an approved source. The last known supplier is listed below.

Vendor CAGE Vendor name

number and address

64155 Linear Technology Corp.

1630 McCarthy Blvd.

Milpitas, CA 95035-7417

The information contained herein is disseminated for convenience only and the

Government assumes no liability whatsoever for any inaccuracies in the

information bulletin.