ADRV9001 System Development User Guide
UG-1828
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Preliminary Technical Data
System Development User Guide for the RF Agile Transceiver Family
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. PrA | Page 1 of 253
ADRV9001 TRANSCEIVER OVERVIEW
The ADRV9001 is a highly integrated, RF agile transceiver family offering two independently controlled transmitters, two independently
controlled receivers, integrated synthesizers, and digital signal processing functions. This document is designed to encompass
description of all functions available in the ADRV9001 family of products. Note that some variants may be developed for specific design
targets that do not encompass all available functions, so refer to the data sheet for the specific device to determine which features are
included.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 2 of 253
TABLE OF CONTENTS
ADRV9001 Transceiver Overview ................................................. 1
How To Use This Document .......................................................... 5
ADRV9002 Block Diagram ............................................................. 6
Product Highlights ........................................................................... 7
ADRV9002 .................................................................................... 7
Bandwidth And Sample Rate Support ...................................... 7
ADRV9001 Example Use Cases ................................................... 10
ADRV9001 in Dual-Band 2RT2R FDD Type Small-Cell
Application .................................................................................. 12
ADRV9001 in Single-Band 2T2R TDD Type Small-Cell
Application .................................................................................. 14
ADRV9001 in 1T1R FDD with DPD Type Application ...... 16
ADRV9001 in TETRA Type Portable Radio Application .... 18
ADRV9001 in DMR Type Portable Radio Application ........ 20
ADRV9001 in FDD Type Repeater Application ................... 22
ADRV9001 in TDD Type Repeater Application ................... 26
ADRV9001 in Radar Type Application .................................. 28
Software System Architecture Description ................................. 30
Software Architecture ................................................................ 30
Folder Structure .......................................................................... 31
Software Integration....................................................................... 33
Hardware Abstraction Layer .................................................... 33
Developing the Application ...................................................... 34
System Initialization and Shutdown ............................................ 36
TES Configuration and Initialization ...................................... 36
API Initialization Sequence ...................................................... 37
Shutdown Sequence ................................................................... 39
Serial Peripheral Interface (SPI) ................................................... 40
SPI Configuration ...................................................................... 40
SPI Bus Signals ............................................................................ 41
SPI Data Transfer Protocol ....................................................... 41
Timing Diagrams ....................................................................... 43
Data Interface .................................................................................. 45
General Description ................................................................... 45
Electrical Specification ............................................................... 45
CMOS Synchronous Serial Interface (CMOS-SSI) ............... 47
LVDS Synchronous Serial Interface (LVDS-SSI) .................. 54
SSI Timing Parameters .............................................................. 57
CSSI/LSSI Testability and Debug ............................................. 58
API Programming ...................................................................... 59
Microprocessor and System Control ........................................... 60
System Control ........................................................................... 61
Timing Parameters Control ...................................................... 61
Clock Generation and Multichip Synchronization ................... 75
Clock Generation ....................................................................... 75
Multichip Synchronization ....................................................... 76
ADRV9001 Communication with BBIC ................................ 77
Synthesizer Configuration and LO Operation ........................... 79
Clock Synthesizer ....................................................................... 79
RF Synthesizer ............................................................................ 79
Auxiliary Synthesizer ................................................................. 80
External LO ................................................................................. 80
API Operation ............................................................................ 82
Frequency Hopping ....................................................................... 84
Key Signals .................................................................................. 84
Framework .................................................................................. 85
Channel Use Cases ..................................................................... 85
Frequency Table Indexing ........................................................ 85
Modes of Operation ................................................................... 86
Configuration and User Information ...................................... 87
Calibration .................................................................................. 87
Hop Time Example .................................................................... 89
Transmitter Signal Chain .............................................................. 90
Data Interface ............................................................................. 90
Datapath ...................................................................................... 90
Digital Front End ....................................................................... 91
Bypass Mode ............................................................................... 93
SPI Mode ..................................................................................... 93
TDD Ramp Mode ...................................................................... 93
GPIO Mode ................................................................................. 94
IQ FM/FSK .................................................................................. 96
Analog Front End (AFE) ........................................................... 97
Transmit Data Chain API Programming ............................... 97
Receiver/Observation Receiver Signal Chain ............................. 99
Receive Data Chain .................................................................. 101
Analog Front-End Components ............................................ 102
LPF ............................................................................................. 103
ADC ........................................................................................... 103
Digital Front End Components ............................................. 103
DC Offset ................................................................................... 104
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QEC ............................................................................................ 104
DDC ........................................................................................... 105
Frequency Offset Correction PFIR ........................................ 105
RSSI ............................................................................................ 105
Receive Data Chain API Programming ................................ 106
Transmitter/Receiver/Observation Receiver Signal Chain
Calibrations ................................................................................... 107
Initial Calibrations ................................................................... 107
Tracking Calibrations .............................................................. 116
Rx Gain Control ........................................................................... 120
Receiver Data Path ................................................................... 121
Gain Control Modes ................................................................ 123
Gain Control Detectors ........................................................... 131
AGC Clock and Gain Block Timing ..................................... 134
Analog Gain Control API Programming ............................. 135
Digital Gain Control and Interface Gain (Slicer) ................ 142
Digital Gain Control and Interface Gain API Programming
.................................................................................................... 145
Usage Recommendations ....................................................... 146
TES Configuration and Debug information ........................ 146
Rx Demodulator ........................................................................... 149
Rx Narrow-band Demodulator Subsystem .......................... 149
Normal IQ Output Mode ....................................................... 152
Frequency Deviation Output Mode ...................................... 153
API Programming.................................................................... 154
Power Saving and Monitor Mode .............................................. 156
Power-Down Modes ................................................................ 156
Power-Down/Power-up Channel in Calibrated State ........ 157
Dynamic Interframe Power Saving ....................................... 157
Monitor Mode .......................................................................... 159
Digital Predistortion .................................................................... 162
Background ............................................................................... 162
ADRV9001 DPD Function ..................................................... 162
ADRV9001 DPD Supported Waveforms ............................. 163
ADRV9001 DPD Performance .............................................. 164
DPD Configuration ................................................................. 165
Board Configuration ............................................................... 172
DPD API Programming .......................................................... 173
DPD Tuning and Testing ....................................................... 173
General-Purpose Input/Output and Interrupt Configuration
......................................................................................................... 176
Digital GPIO Operation .......................................................... 177
TX DCLK OUT ......................................................................... 180
Analog GPIO Operation .......................................................... 180
Interrupt ..................................................................................... 181
Auxiliary Converters and Temperature Sensor ........................ 183
Auxiliary DAC (AuxDAC) ...................................................... 183
Auxiliary ADC (AuxADC) ...................................................... 183
Temperature Sensor ................................................................. 184
RF Port Interface Information .................................................... 185
Transmit Ports: TX1± and TX2± ........................................... 185
Receive Ports: RX1A±, RX1B±, RX2A±, and RX2B± ......... 185
External LO Ports: LO1± and LO2± ...................................... 185
Device Clock Port: DEV_CLK1± ........................................... 185
RF Rx/Tx Ports Impedance Data ............................................ 185
General Receiver Port Interface .............................................. 188
General Transmitter Bias and Port Interface ........................ 189
Impedance Matching Network Examples ............................. 192
Receiver RF Port Impedance Matching Network ................ 192
Receiver RF Port Impedance Match Measurement Data .... 196
Transmitter RF Port Impedance Matching Network .......... 197
Transmitter RF Port Impedance Match Measurement Data
..................................................................................................... 199
External LO Port Impedance Matching Network ................ 200
External LO Impedance Match Measurement Data ............ 203
Connection for External Device Clock (DEV_CLK_IN) .... 204
DEV_CLK_IN Phase Noise Requirements ........................... 205
Connection for MultiChip Synchronization (MCS) input . 206
Printed Circuit Board Layout Recommendations.................... 207
PCB Material And Stack Up Selection ................................... 207
Fan-out and Trace Space Guidelines ..................................... 208
Component Placement and Routing Priorities .................... 209
RF and Data Port Transmission Line Layout ....................... 215
Isolation Techniques Used on the ADRV9001 Evaluation
Card ............................................................................................ 222
Power Supply Recommendations ............................................... 225
ADRV9001 Evaluation System ................................................... 226
Initial Setup ................................................................................ 226
Hardware Kit ............................................................................. 226
Hardware Operation ................................................................ 229
Transceiver Evaluation Software (TES) ................................. 230
Transmitter Operation ............................................................. 239
Receiver Operation ................................................................... 242
Time Division Duplexing (TDD) ........................................... 245
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Tracking Calibrations .............................................................. 246
Digital Pre-Distortion .............................................................. 247
TDD Enablement Delays ........................................................ 247
Auxiliary DAC/ADC ............................................................... 247
Radio state ................................................................................. 247
Power Monitoring .................................................................... 248
Power Savings and Monitor Mode ........................................ 249
Log File ...................................................................................... 250
Using of Matlab and Python................................................... 251
Evaluation System Troubleshooting ..................................... 251
HAL Integration ........................................................................... 253
Preliminary Technical Data UG-1828
Rev. PrA | Page 5 of 253
HOW TO USE THIS DOCUMENT
START
Y
N
IMPLEMENT ADRV9001
APIs IN YOUR APPLICATION?
BUILDING YOUR OWN
HARDWARE
WITH ADRV900n?
Y
N
Y
N
Y
N
INTERFACING YOUR
SYSTEM WITH ADRV900n?
Y
N
LEARN MORE ABOUT
Rx DATA PATHS?
Y
N
LEARN MORE ABOUT
Tx DATA PATHS?
FOR ALL ELECTRICAL AND TIMING CHARACTERISTICS
REFER TO ADRV900n DATASHEET DOCUMENT.
Y
N
LEARN MORE
ABOUT REFERENCE AND
RF CLOCKING?
Y
N
LEARN WHAT ADRV9001 IS?
HAVE ADRV9001
EVALUATION SYSTEM?
GO TO ADRV9001 TRANSCEIVER OVERVIEW AND
ADRV9001 EXAMPLE USE CASES PARAGRAPHS.
GO TO ADRV9001 EVALUATION SYSTEM
PARAGRAPH FOR MORE INFORMATION
HOW TO USE IT.
GO TO SOFTWARE SYSTEM ARCHITECTURE
DESCRIPTION, SOFTWARE INTEGRATION AND
SYSTEM INITIALIZATION AND SHUTDOWN
PARAGRAPHS AS WELL AS HAL INTERFACE
DEFINITION APPENDIX FOR MORE INFORMATION.
GO TO PCB LAYOUT RECOMMENDATIONS, POWER
SUPPLY RECOMMENDATIONS AND RF PORT
INTERFACE INFORMATION PARAGRAPHS FOR
MORE INFORMATION
GO TO SERIAL PERIPHERAL INTERFACE (SPI), DATA
INTERFACE, MICROPROCESSOR AND SYSTEM
CONTROL, GENERAL PURPOSE INPUT/OUTPUT AND
INTERRUPT CONFIGURATION AND AUXILIARY
CONVERTERS AND TEMPERATURE SENSOR
PARAGRAPHS FOR MORE INFORMATION
GO TO CLOCK GENERATION AND MULTICHIP
SYNCHRONIZATION AND SYNTHESIZER
CONFIGURATION AND LO OPERATION
PARAGRAPHS FOR MORE INFORMATION
GO TO Rx/ORx SIGNAL CHAIN, Rx/ORx SIGNAL
CHAIN CALIBRATIONS, Rx GAIN CONTROL AND
Rx DEMODULATOR BLOCK PARAGRAPHS FOR
MORE INFORMATION
GO TO Tx SIGNAL CHAIN, Tx SIGNAL CHAIN
CALIBRATIONS AND DIGITAL PRE-DISTORTION
PARAGRAPHS FOR MORE INFORMATION
24159-001
Figure 1. Document Flow Chart for Document Navigation
UG-1828 Preliminary Technical Data
Rev. PrA | Page 6 of 253
ADRV9002 BLOCK DIAGRAM
HP
ADC
DAC
DAC
SPI PORT
MICROPROCESSOR
CLOCK
GENERATION
2
2
2
2
2
2
2
2
2
2
2
2
2
AUXILIARY
CLOCK
GENERATION
6CONTROLS
TX1_QDATA_IN±
TX1_IDATA_IN±
TX1_STROBE_IN±
TX1_DCLK_IN±
TX1_DCLK_OUT±
RX1_QDATA_OUT±
RX1_IDATA_OUT±
RX1_STROBE_OUT±
RX1_DCLK_OUT±
12 DGPIOs
4SPI
/n
LPF
LPF
90°
0°
MULTI CHIP
SYNCHRONIZATION
2
MCS
4
AuxADCs
12
AGPIOs
4
2
4
Rx1
RX1A+
RX1A–
RX1B+
RX1B–
TX1+
TX1–
Tx1
EXT_LO1+
EXT_LO1–
DEV_CLK+
DEV_CLK–
EXT_LO2+
EXT_LO2–
TX2+
TX2–
RX2A+
RX2A–
RX2B+
RX2B–
Rx2
Tx2
RX2_QDATA_OUT±
RX2_IDATA_OUT±
RX2_STROBE_OUT±
RX2_DCLK_OUT±
TX2_QDATA_IN±
TX2_IDATA_IN±
TX2_STROBE_IN±
TX2_DCLK_IN±
TX2_DCLK_OUT±
1.0V ANALO G
(OPTIONAL)
1.0V DIGITAL
1.3V ANALO G
1.8V DIGITAL
1.8V ANALO G
2
2
2
2
2
0/9
15/10
LP
ADC
LP
ADC
HP
ADC
DIGITAL SIGNAL PROCESSING:
- NARROW /WIDE BAND DECIM AT IO N
- DC OFFS ET CORRECTION ( DC)
- QUADRATURE ERROR CORRECTIO N (Q EC)
- NUMERI CAL LY CONTRO L LE D OSCI L LAT OR ( NCO)
- PROGRAM M ABL E F IR FILTER (PFIR)
- AUT OM ATIC G AIN CONTROL ( AGC)
- RECEIVER S IG NAL S TRENGTH INDICATO R (RSSI)
- OVERLOAD DETE CTORS
DATA
PORT
CMOS-SSI
OR
LVDS-SSI
DATA
PORT
CMOS-SSI
OR
LVDS-SSI
LO1
GENERATOR
RF V CO1
SYNTHESIZER
DEV_CLK
/XTAL
OSCILLATOR RF VCO 2
SYNTHESIZER
LO2
GENERATOR
/n
ADVANCED FEATURES
- F REQUENCY HOPPI NG
- DYNAMI C P ROFI L E SWI T CHING
- MONITOR MODE
CONTROL
INTERFACE
DIGITAL GPIOs
POWER
MANAGEMENT
LPF
LPF
90°
0°
DIGITAL SIGNAL PROCESSING:
- NARROW /WIDE BAND INTERPOLAT IO N
- L OCAL O S CILLATOR LE AKAGE SUPPRESSION ( LOL)
- QUADRATURE ERROR CORRECTIO N (Q EC)
- PROGRAM M ABL E F IR FILTER (PFIR)
- POWER AM PLIFI ER PROTECTI ON
- T X ATT ENUATION CO NT ROL
- DIRECT PL L MO DUL ATION
- DIG ITAL PRE-DI S TORTIO N (DPD)
90°
0°
DAC
DAC
LPF
LPF
DIGITAL SIGNAL PROCESSING:
- NARROW /WIDE BAND INTERPOLAT IO N
- L OCAL O S CILLATOR LE AKAGE SUPPRESSION ( LOL)
- QUADRATURE ERROR CORRECTIO N (Q EC)
- PROGRAM M ABL E F IR FILTER (PFIR)
- POWER AM PLIFI ER PROTECTI ON
- T x AT TENUAT IO N CONTROL
- DIRECT PL L MO DUL ATION
- DIG ITAL PRE-DI S TORTIO N (DPD)
DATA
PORT
CMOS-SSI
OR
LVDS-SSI
AuxADC,
AuxDACs,
ANALOG GPIOs
90°
0°
LPF
LPF
HP
ADC
HP
ADC
LP
ADC
LP
ADC
DIGITAL SIGNAL PROCESSING:
- NARROW /WIDE BAND DECIM AT IO N
- DC OFFS ET CORRECTION ( DC)
- QUADRATURE ERROR CORRECTIO N (Q EC)
- NUMERI CAL LY CONTRO L LE D OSCI L LAT OR ( NCO)
- PROGRAM M ABL E F IR FILTER (PFIR)
- AUT OM ATIC G AIN CONTROL ( AGC)
- RECEIVER S IG NAL S TRENGTH INDICATO R (RSSI)
- OVERLOAD DETE CTORS
DATA
PORT
CMOS-SSI
OR
LVDS-SSI
24159-002
Figure 2. ADRV9002 Block Diagram
Preliminary Technical Data UG-1828
Rev. PrA | Page 7 of 253
PRODUCT HIGHLIGHTS
ADRV9002
The ADRV9002 delivers a versatile combination of high performance and low power consumption required by battery powered radio
equipment and can operate in both frequency division duplex (FDD) and time division duplex (TDD) modes. The ADRV9002 operates
from 30 MHz to 6000 MHz covering the VHF, licensed and unlicensed cellular bands, and ISM bands. The IC is capable of supporting
both narrowband and wideband standards up to 40 MHz bandwidth on both receive and transmit.
The transceiver consists of direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and
transmitter sub-system includes DC offset correction, quadrature error correction, and programmable digital filters, eliminating the need
for these functions in the digital baseband. In addition, several auxiliary functions such as an auxiliary ADC, auxiliary DACs, and GPIOs
are integrated to provide additional monitoring and control capability.
The fully integrated phase locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the
transmitter, receiver, and clock sections. Careful design and layout techniques have been implemented to provide the isolation
demanded in high performance Mobile Radio applications.
All VCO and loop filter components are integrated to minimize the external component count. The LOs have flexible configuration
options and include fast lock modes.
The transceiver includes low power sleep and monitor modes to save power, which extends battery life of portable devices while
continuing to monitor communication.
The fully integrated low power digital predistortion (DPD) is supported by ADRV9002. It can linearize wideband signals as well as it has
been optimized for narrowband type signals to enable linearization of high efficiency power amplifiers. In use cases where the integrated
DPD is used, main receivers are used as a power amplifier observation path.
Power supply for ADRV9002 is distributed across four or five different voltage supplies – 2 or 3 analog and 2 digital. The analog supplies
are 1.8V, 1.3V, and 1.0V (in internal LDO bypass mode). 1.3V domain feeds directly some blocks and also internal LDO regulators for
some functions to maximum performance. 1.8V analog domain is used to optimize transmitter and auxiliary converter performance.
The digital processing blocks are supplied by a 1.0V source. In addition, a 1.8 V supply is used to supply all GPIO and interface ports that
connect with the baseband processor
High data rate and low data rate interfaces are supported using configurable CMOS or LVDS Synchronous Serial Interface choice.
The core of the ADRV9002 is controlled via a standard 3 or 4-wire serial port. All software control is communicated via this interface.
There is also a control interface that utilizes GPIO lines to provide hardware control to and from the device. These pins can be
configured to provide dedicated sets of functions for different application scenarios.
The block diagram in Figure 2 shows a high level view of the functions in the ADRV9002. Descriptions of each block with setup and
control details are provided in subsequent sections of this document.
BANDWIDTH AND SAMPLE RATE SUPPORT
The ADRV9002 supports the reception and transmission of channels up to 40 MHz bandwidth. Standard sample rates of 24 KHz
(typically for narrowband FM waveforms), 144 KHz and 288 KHz (typically for TETRA signals), and 1.92 MHz, 3.84 MHz, 7.68 MHz,
15.36 MHz, 23.04 MHz, 30.72 MHz, and 61.44 MHz (typically for LTE signals) are available.
In addition, the ADRV9002 supports an almost continuous range of sample rates between 24 KHz and 61.44 MHz. Some sample rates
cannot be supported due to internal clocking constraints.
Sample rate scaling is accomplished by enabling or disabling decimation or interpolation filters in the digital signal chain.
Data Interfaces
The ADRV9002 supports both CMOS and LVDS electrical interfaces for its data lanes. All data lanes support both electrical interfaces,
but concurrent operation of both interfaces is not supported. Each receive and transmit channel has a dedicated set of lanes for
transferring information.
The CMOS bus speed is limited to 80 MHz. Two operating modes are available for the CMOS-SSI electrical interface. For low sample
rates, a mode in which 32 bits (16 bits of I and Q data each) are serialized over a single lane, with two additional lanes total required for a
clock (SDR or DDR) and a frame synchronization signal, supports a maximum sample rate of 2.5 MHz.
For sample rates above 2.5 MHz, single channel data is serialized over four lanes, with two additional lanes total required for a clock
(SDR or DDR) and a frame synchronization signal, supporting a maximum sample rate of 20 MHz.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 8 of 253
The LVDS electrical interface supports two modes of operation. The 32 total bits of I and Q data are serialized over one LVDS lane (32
bits composed of 16 bits of I and 16 bits of Q data) or two LVDS-SSI lanes (each dedicated to 16 bits of I or Q data), with two additional
lanes total required for a DDR clock and a frame synchronization signal. Sample rates ranging from 24 KHz to 61.44 MHz are supported
via the LVDS-SSI interface, resulting in a maximum lane rate of 983.04 MHz.
Note that in LVDS-SSI mode, 12-bit I and Q words are supported for most sample rates.
RF LO Frequency Range and Multiplexing
The ADRV9002 supports a RF LO range from 30 MHz to 6 GHz. RF LOs can be generated via two internal PLLs, or applied externally to
the device. When LOs are provided from an external source, double or more of the desired frequency must be applied to the ADRV9002
to allow for the generation of quadrature signals internally.
An LO multiplexing scheme exists on the ADRV9002, that allows for the routing of either of the RFPLLs to any of the transmit or receive
channels. The RF channels and RFPLLs can operate concurrently and independently, off a common reference clock, thus enabling: FDD
operation, single or dual frequency repeater operation, multi-band TDD operation, and diversity operation amongst various other
configurations.
Frequency Hopping
The ADRV9002 supports various forms of frequency hopping, with the main distinguishing factor between them being frequency
transition time. RFPLL phase noise, and QEC and LOL algorithm performance may degrade as a function of decreasing frequency
transition time.
A fast frequency hopping (FFH) mode exists that supports 64 hop frequencies or less, that are pre-loaded by the user onto the
ADRV9002 at power-up. In this mode, the 64 frequencies are cycled through in a circular buffer fashion. Hopping between the
frequencies in FFH mode is triggered via a GPIO pin toggle. An API command with SPI transaction can also trigger a frequency hop,
albeit with a longer frequency transition time.
A random order FFH mode is also supported, whereby a finite set of frequencies already pre-loaded onto the ADRV9002 can be hopped
between in a random manner dictated by the user. Selecting the next frequency to hop to is accomplished by asserting a frequency index
word onto the GPIO bus. Alternatively, the API can be used to select the next frequency index, albeit with a longer frequency transition
time.
In addition to FFH mode, the ADRV9002 supports other frequency hopping modes where the desired hop frequencies need not be pre-
loaded into on-board memory. In these modes, desired hop frequencies can be streamed in via the API. Frequency transition times in
these modes are greater than that available in FFH mode.
Note that all frequency hopping modes are available for use in conjunction with the monitor mode described in the Power Consumption
Modes section.
Profile Switching
The ADRV9002 supports rapid switching between different RF channel profiles. A transmit or receive RF channel profile contains
settings such as bandwidth, sample rate, filtering, input port selection, AGC settings, and algorithm configuration. The profile switching
mode enables the support of waveforms that vary modulation schemes and bandwidths dynamically.
Low IF Reception
The receive digital datapath on the ADRV9002 contains an optional digital mixer that is driven by a programmable NCO. The RX LO is
offset from the frequency of the desired channel, and then the digital mixer and NCO are utilized to downconvert signal to base-band
before being processed by their baseband processor.
There are several advantages to offset the RX LO from the frequency of the desired channel: Impairments that exist about the RX LO,
such as LO-leakage, can be avoided. The effect of flicker noise from base-band circuits can be mitigated since the received signal is offset
from DC in the analog signal path. Also, image rejection can be improved if the RX LO is offset enough from the desired channel, such
that the image frequency lies in the attenuation region of the user’s external RF filter.
The low IF reception mode is targeted predominately towards low bandwidth channels, which supports offsets range of + 20 MHz about
the receiver LO.
Receive Dynamic Range and Blocking
As depicted in Figure 2, the ADRV9002 receive path consists of an input mixer, followed by a base-band filter that drives an ADC. A
highly programmable digital decimation and filtering datapath follows the ADC. RF analog gain control is provided in analog attenuator,
and additional gain is provided in the digital datapath via AGC loops.
Preliminary Technical Data UG-1828
Rev. PrA | Page 9 of 253
The ADC in the receive chain possesses a high dynamic range. Assuming a mixer gain of 0 dB, the ADC’s noise and maximum input
power referred to the RF input are -142 dBm/Hz and 8.6 dBm, respectively. These levels translate into a dynamic range in excess of 150
dB on a per Hertz basis. Taking into account the digital filtering and AGC loops, an even greater dynamic range can be achieved.
Given the high dynamic range of the receive ADC, very little channelization or blocker filtering occur in the analog signal chain since the
ADC can simultaneously absorb weak signals and large blockers. Blocker suppression and channelization are then achieved in the digital
signal path.
If reciprocal mixing of the RX LO phase noise by a large blocker close to the desired channel significantly degrades blocking
performance, a lower phase noise external LO source can be used in place of the on-board RFPLLs.
The receive path also contains two types of ADCs connected to the chip’s RF front end, that allow for the trade-off between power
consumption and dynamic range: a high performance ADC, and low power ADC that possess degraded dynamic range. Users can trade-
off receive channel dynamic range and power consumption by selecting between either set of ADCs.
Power Consumption Modes
The ADRV9002 provides users with various levels of power control. Power scaling on individual analog signal path blocks can be
performed to trade-off power and performance. In addition, enabling and disabling various blocks in TDD RX and TX frames to reduce
power can be customized, at the expense of RX/TX or TX/RX turn-around time.
A specialized “RX Monitor mode” exists that allows the ADRV9002 to autonomously poll a region of the spectrum for the presence of a
signal, while in a low power state. In this mode, the chip continuously cycles through sleep-detect-sleep states controlled by an internal
state machine. Power savings are achieved by ensuring that the sleep duty cycle is greater than the “detect” duty cycle.
In the “sleep” state, the chip is in a minimal power consumption configuration where few functions are enabled. After a pre-determined
period, the chip enters the “detect” state. In this state, the chip enables a receiver and performs a power measurement over a bandwidth
and at a RX LO frequency determined by the user. If the measured power level in the bandwidth is greater than a user-determined
threshold, the “Monitor Mode” state machine exits its cycle. Following the loop exit, an interrupt is provided via a GPIO pin to the user’s
baseband processor, and the entire receiver analog and digital chains within the ADRV9002 are powered up, assuming that normal signal
reception resumes due to the detection of a channel.
If the power measured over the bandwidth is less than the user-determined threshold, the chip resumes its sleep-detect-sleep cycle. The
sleep-detect duty cycle and durations, power measurement threshold, and RX LO are user-programmable, and are set before enabling
“Monitor Mode”.
Note that frequency hopping can be combined with “Monitor Mode”, allowing the ADRV9002 to dynamically change the RX LO while
performing the power measurement function.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 10 of 253
ADRV9001 EXAMPLE USE CASES
Intention of this section is to provide reader with overall idea how ADRV9001 integrated transceiver can operate as RF Front End in
different applications. Provided list is not exhaustive and there are other aplications where ADRV9001 can serve.
Each example is accompanied with table that explains main limitations and highlights what customer should look for when
implementing ADRV9001 in their end application.
SPI
RESET
DEV_CLKL_OUT
MCS
DEV_CLK
DGPIOs
Rx/Tx_ENABLE
GP_INT
VGA
BPF FILTER
LNA
PA LPF
BPF FILTER
LNA
ATTENUATOR
COUPLER
DUPLEXER
DUPLEXER
ANTE NNA A
ANTE NNA B
A
B
B
A
VCXO
BALUN
BALUN
BALUN
BALUN
BALUN
POWER IC
BALUN
BALUN
/2
SSI
DAC
BALUN
BALUN
VGA
PA LPF
ATTENUATOR
COUPLER
FUNCTIONALITY
RF RECEPTION (DIVERSITY/MI MO )
USED BY Tx1 I NIT CALI BRATIONS
RF RECEPTION (DIVERSITY/MI MO )
USED BY Tx2 I NIT CALI BRATIONS
RF TRANSMISSION (DIVERSITY/MI MO )
RF TRANSMISSION (DIVERSITY/MI MO )
RF I/O
Rx1A
Rx1B
Rx2A
Rx2B
Tx1
Tx2
ADRV9001
FPGA
OR
BBP
VDDA_1P0
VDDA_1P3
VDDA_1P8
VDD_1P0
VDD_1P8
RF PLL2
RF PLL1
/2
EXT LO2
EXT LO1
Tx1
Rx1A
Rx1B
Rx2A
Rx2B
Tx2
INT
QEC
LOL
Tx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx2
DATA
SSI
DAC INT
QEC
LOL
Tx2
DATA
AuxDACAuxADCAGPIOs
3/4/6/7/8/10
3/6/8
12/16
4
3/4
3/6/8
3/4/6/7/8/10
24159-003
Figure 3. ADRV9001 in Single-Band 2T2R FDD Type Small Cell Application
Table 1. Constrains and Limitations in Single-Band 2T2R FDD Type Small-Cell Application
Functionality Constrains and Limitations
Receiver Signal
Path
User has to ensure that appropriate level of isolation between Rx1 and Rx2 as well as Rx to Tx is provided at system
level. In example above, RxB inputs are utilized only during initialization calibrations. User should ensure that
appropriate attenuation is present in line to prevent Rx being overloaded by Tx signal.
Transmistter Signal
Path
User has to ensure that appropriate level of isolation between Tx1 and Tx2 as well as Rx to Tx is provided at system
level.
LO Generation In FDD type Small Cell application, ADRV9001 can use its internal LO to generate RF LO1 for uplink (Rx1 and Rx2) and
RF LO2 for downlink (Tx1 and Tx2). It is also possible to use external LO inputs in this mode of operation. External LO1
operating at 2x RF LO can be used for uplink and External LO2 operating at 2x RF LO can be used for downlink.
Preliminary Technical Data UG-1828
Rev. PrA | Page 11 of 253
Functionality Constrains and Limitations
RF Front End For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example:
depending of RF matching used on the RF ports user 2nd LO harmonic can be as high as -50dBc and 3rd harmonic
can be as high as -9 dBc. Therefore the RF filtering on the Rx and Tx path must ensure that signals at the LO harmonic
frequencies (up to 9th in some cases) are not affecting overall system performance.
DPD The DPD functionality is not available when ADRV9001 operates in 2R2T FDD mode.
Calibrations During Rx initialization sequence user needs to ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones. Maximum input signal amplitude should not exceed -82 dBm/MHz for wideband modes, TBD
dBm/MHz for narrowband modes. During Tx initialization sequence user needs to ensure that the power amplifier is
powered down to avoid unwanted emission of transmitter calibration tones at the antenna. No transmitter tracking
calibrations are available when ADRV9001 operates in 2R2T FDD mode.
AGPIOs
Analog GPIOs (operating at 1.8V level) can be used as read or write digital levels of in the end user system. AGPIOs can
be utilized to control states of external components or read back digital logic levels from external components.
DGPIOs Digital GPIOs can be used to perform real time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be utilized by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (e.g. temperature sensor). Maximum AuxADC input voltage can not
exceed 0.9V.
AuxDAC AuxDAC can be used to: control VCXO responsible for generating ADRV9001 Device clock, control any circuitry that
requires analog control voltage up to 1.8V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, ADRV9001 can be initialized using API functions only.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 12 of 253
ADRV9001 IN DUAL-BAND 2RT2R FDD TYPE SMALL-CELL APPLICATION
SPI
RESET
DEV_CLKL_OUT
MCS
DEV_CLK
DGPIOs
Rx/Tx_ENABLE
GP_INT
BPF FILTER
BAND A
LNA BAND A
LNA BAND B
ATTENUATOR
COUPLER
SPLITTER
DUPL EX E R BAND A
ANTENNA
DUAL BAND
A
B
A
B
VCXO
BALUN
BALUN
RF SWITCH
BALUN
BALUN
BALUN
POWER IC
BALUN
BALUN
/2
SSI
DAC
BALUN
BALUN
VGA
LPF
FUNCTIONALITY
RF RE CEP TI ON BAND A (DI V E RS IT Y /MI M O)
RF RE CEP TI ON BAND B (DI V E RS IT Y /MI M O) AND Tx INIT CALIBRATI ONS
RF RE CEP TI ON BAND A (DI V E RS IT Y /MI M O)
RF RE CEP TI ON BAND B (DI V E RS IT Y /MI M O) AND Tx INIT CALIBRATI ONS
RF TRANSMISS I ON BAND A AND BAND B (DIVERS IT Y /MI M O)
RF TRANSMISS I ON BAND A AND BAND B (DIVERS IT Y /MI M O)
RF I/O
Rx1A
Rx1B
Rx2A
Rx2B
Tx1
Tx2
ADRV9001
FPGA
OR
BBIC
VGA
PA BAND A LPF
VDDA_1P0
VDDA_1P3
VDDA_1P8
VDD_1P0
VDD_1P8
RF PLL2
RF PLL1
/2
EXT LO2
EXT LO1
Tx1
Rx1A
Rx1B
Rx2A
Rx2B
Tx2
INT
QEC
LOL
Tx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx2
DATA
SSI
DAC INT
QEC
LOL
Tx2
DATA
AuxDACAuxADCAGPIOs
3/4/6/7/8/10
3/6/8
3/4
3/6/8
3/4/6/7/8/10
12/16
4
COMBINER
DUPL EX E R BAND B
ATTENUATOR
COUPLER
SPLITTER
DUPL EX E R BAND B
A
B
A
BRF SWITCH
VGA
PA BAND A LPF
VGA
LPF
BPF FILTER
BAND A
BPF FILTER
BAND B
LNA BAND A
COMBINER
DUPL EX E R BAND B
24159-004
ANTENNA
DUAL BAND
PA BAND B
BPF FILTER
BAND B
LNA BAND B
PA BAND B
Figure 4. ADRV9001 in Dual-Band 2T2R FDD Type Small-Cell Application
Preliminary Technical Data UG-1828
Rev. PrA | Page 13 of 253
Dual-Band 2T2R FDD Overview
ADRV9001 transceiver with a minimum number of external components can be utilized to build complete dual-and RF-to-bits signal
chain that can serve as RF front end in small cell type applications. Note that in proposed solution, only one band can be utilized at the
time. ADRV9001 dual Rx and Tx signal chains enables user to implement MIMO or diversity in their system. ADRV9001 internal AGC
can be utilized to autonomously monitor and set appropriate gain level for Rx signal chains. For none time critical FDD type applications
control of the ADRV9001 TRx can be done thru API commands that utilize SPI interface.
Table 2. Constrains and Limitations in Dual-Band 2T2R FDD Type Small-Cell Application
Functionality Constrains and Limitations
Rx Signal Path
User has to ensure that appropriate level of isolation between Rx1 and Rx2 as well as Rx to Tx is provided at system
level. In example above, RxB inputs are utilized to work with Rx Band B signals as well as during initialization
calibrations. In this scenario, RF Balun selected for RxB inputs must work with both Band B and Tx Bands. User should
ensure that appropriate attenuation is present in line to prevent Rx being overloaded by Tx signal.
Tx Signal Path User has to ensure that appropriate level of isolation between Tx1 and Tx2 as well as Rx to Tx is provided at system
level.
LO Generation In FDD type Small cell application, ADRV9001 can use its internal LO to generate RF LO1 for uplink (Rx1 and Rx2) and
RF LO2 for downlink (Tx1 and Tx2). It is also possible to use external LO inputs in this mode of operation. External LO1
operating at 2x RF LO can be used for uplink and External LO2 operating at 2x RF LO can be used for downlink. It
should be noted that only one set of Rx inputs can be used at the time. This system can operate with two different
FDD bands but only one of those bands can be active at particular moment in time.
RF Front End
For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as
high as -50dBc and 3rd harmonic can be as high as -9 dBc. Therefore the RF filtering on the Rx and Tx path must ensure
that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system performance.
DPD The DPD functionality is not available when ADRV9001 operates in 2R2T FDD mode.
Calibrations During Rx initialization sequence user needs to ensure that there are no signals at the Rx input (external LNA should
be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx calibration tones.
Maximum input signal amplitude should not exceed -82 dBm/MHz for wideband modes, TBD dBm/MHz for
narrowband modes. During the transmitter initialization sequence, the user needs to ensure that the power amplifier
is powered down to avoid unwanted emission of transmitter calibration tones at the antenna. No transmitter tracking
calibrations are available when ADRV9001 operates in 2R2T FDD mode.
AGPIOs Analog GPIOs (operating at 1.8V level) can be used as read or write digital levels of in the end user system. AGPIOs can
be utilized to control states of external components or read back digital logic levels from external components.
DGPIOs
Digital GPIOs can be used to perform real time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be utilized by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (e.g. temperature sensor). Maximum AuxADC input voltage can not
exceed 0.9V.
AuxDAC AuxDAC can be used to: control VCXO responsible for generating ADRV9001 Device clock, control any circuitry that
requires analog control voltage up to 1.8V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync
If there is no need for multichip synchronization, ADRV9001 can be initialized using API functions only.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 14 of 253
ADRV9001 IN SINGLE-BAND 2T2R TDD TYPE SMALL-CELL APPLICATION
SPI
RESET
DEV_CLKL_OUT
MCS
DEV_CLK
DGPIOs
Rx/Tx_ENABLE
GP_INT
BPF FILTER
LNA
ATTENUATOR
RF SWITCH COUPLER
ANTE NNA A
VCXO
BALUN
BALUN
BALUN
BALUN
BALUN
POWER IC
BALUN
BALUN
/2
SSI
DAC
BALUN
BALUN
VGA
PA LPF
FUNCTIONALITY
RF RECEPTION (DIVERSITY/MI MO )
USED BY Tx1 I NIT CALI BRATIONS
RF RECEPTION (DIVERSITY/MI MO)
USED BY Tx2 I NIT CALI BRATIONS
RF TRANSMISSION (DIVERSITY/MI MO )
RF TRANSMISSION (DIVERSITY/MI MO )
RF I/O
Rx1A
Rx1B
Rx2A
Rx2B
Tx1
Tx2
ADRV9002
FPGA
OR
BBIC
VDDA_1P0
VDDA_1P3
VDDA_1P8
VDD_1P0
VDD_1P8
RF PLL2
RF PLL1
/2
EXT LO2
EXT LO1
Tx1
Rx1A
Rx1B
Rx2A
Rx2B
Tx2
INT
QEC
LOL
DPD
Tx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx2
DATA
SSI
DAC
Tx2
DATA
AuxDACAuxADCAGPIOs
3/4/6/7/8/10
3/6/8
12/16
4
3/4
3/6/8
3/4/6/7/8/10
BPF FILTER
LNA
ATTENUATOR
RF SWITCH
COUPLER
ANTE NNA B
PA LPF VGA
24159-005
INT
QEC
LOL
DPD
Figure 5. Single-Band 2T2R FDD Type Small-Cell Application
Single-Band 2T2R TDD Overview
ADRV9001 transceiver with minimum number of external components can be utilized to build complete RF-to-bits signal chain that can
serve as RF front end in TDD type small cell type applications. ADRV9001 dual Rx and Tx signal chains enables user to implement
MIMO or diversity in their system. In TDD type applications internal DPD block can be utilized to linearize external power amplifier
and improve overall system efficiency. ADRV9001 internal AGC can be utilized to autonomously monitor and set appropriate gain level
for Rx signal chains. For time critical TDD type applications control of the ADRV9001 TRx can be done by toggling control lines.
ADRV9001 can control external Rx/Tx switch using its analog GPIOs as well as provide power amplifier bias voltage by utilizing
AuxDAC outputs.
Preliminary Technical Data UG-1828
Rev. PrA | Page 15 of 253
Table 3. Constrains and Limitations in Single-Band 2T2R FDD Type Small-Cell Application
Functionality Constrains and Limitations
LO Generation
In TDD type Small Cell application, ADRV9001 can use its internal LO to generate RF LO1 for both uplink and
downlink. It is also possible to use external LO inputs in this mode of operation. External LO1 operating at 2x RF LO
can be used for both uplink and downlink.
RF Front End For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as
high as -50dBc and 3rd harmonic can be as high as -9 dBc. Therefore the RF filtering on the Rx and Tx path must
ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
DPD The DPD functionality can be utilized in the 2R2T TDD mode. Maximum channel bandwidth that DPD can support is
limited by ADRV9001 RF bandwidth divided by 3 or by 5. The DPD operation can be performed by ADRV9001 or
observation receiver data can be sent to the baseband processor via the receiver data port during transmit operation.
The receiver path used during DPD operation to perform transmitter observation is also used by the transmitter
tracking calibrations. In case of external DPD, the user must ensure that access to the receiver path during transmit
slots is time-shared between DPD operation and transmitter calibrations.
Calibrations During Rx initialization sequence user needs to ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones. Maximum input signal amplitude should not exceed -82 dBm/MHz for wideband modes, TBD
dBm/MHz for narrowband modes. During Tx initialization sequence user needs to ensure that Power Amplifier is
power down to avoid unwanted emission of Tx calibration tones at the antenna.
ADRV9001 needs to access Rx datapath during Tx time slots for Tx tracking calibration to operate. If user use Tx
observation path with DPD functionality performed by baseband processor then access to the Rx datapath during Tx
slots need to be time-shared between DPD operation and Tx calibrations.
AGPIOs Analog GPIOs (operating at 1.8V level) can be used as read or write digital levels of in the end user system. AGPIOs can
be utilized to control states of external components or read back digital logic levels from external components.
DGPIOs Digital GPIOs can be used to perform real time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be utilized by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (e.g. temperature sensor). Maximum AuxADC input voltage can not
exceed 0.9V.
AuxDAC AuxDAC can be used to: control VCXO responsible for generating ADRV9001 Device clock, generate pre-configured
ramp up/down signal that can be used to control power amplifier bias, control any circuitry that requires analog
control voltage up to 1.8V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, ADRV9001 can be initialized using API functions only.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 16 of 253
ADRV9001 IN 1T1R FDD WITH DPD TYPE APPLICATION
SPI
RESET
DEV_CLKL_OUT
MCS
DEV_CLK
DGPIOs
Rx/Tx_ENABLE
GP_INT
BPF FILTER
LNA
ATTENUATOR
COUPLER
DUPLEXER
ANTENNA
A
B
VCXO
BALUN
BALUN
BALUN
BALUN
BALUN
POWER IC
BALUN
BALUN
/2
SSI
DAC
BALUN
BALUN
VGA
PA LPF
FUNCTIONALITY
RF RECEPTION
NOT USED
USED BY Tx DPD AND CALIBRATI ONS
NOT USED
RF TRANSMISSION
NOT USED
RF I/O
Rx1A
Rx1B
Rx2A
Rx2B
Tx1
Tx2
ADRV9001
FPGA
OR
BBIC
VDDA_1P0
VDDA_1P3
VDDA_1P8
VDD_1P0
VDD_1P8
RF PLL2
RF PLL1
/2
EXT LO2
EXT LO1
Tx1
Rx1A
Rx1B
Rx2A
Rx2B
Tx2
Tx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx2
DATA
SSI
DAC
Tx2
DATA
AuxDACAuxADCAGPIOs
3/4/6/7/8/10
3/6/8
14/16
3
3/4
3/6/8
NC
EXTERNAL
LO SO URCE
OPTIONAL
TEMPERATURE
SENSOR
OPTIONAL
24159-006
INT
QEC
LOL
DPD
INT
QEC
LOL
DPD
Figure 6. ADRV9001 in 1T1R FDD with DPD Type Application
1T1R FDD with DPD Overview
ADRV9001 transceiver with minimum number of external components can be utilized to build complete RF-to-bits signal chain that can
serve as RF front end in FDD type applications that requires DPD. Internal DPD block can be utilized to linearize external power
amplifier and improve overall system efficiency. For systems that demand superior LO phase noise performance ADRV9001 allows user
to apply eternal RF LO. ADRV9001 internal AGC can be utilized to autonomously monitor and set appropriate gain level for Rx signal
chain. ADRV9001 can control external LNA using its analog GPIOs as well as provide power amplifier bias voltage by utilizing AuxDAC
outputs.
Preliminary Technical Data UG-1828
Rev. PrA | Page 17 of 253
Table 4. Constrains and Limitations in 1T1R FDD with DPD Type Application
Functionality Constrains and Limitations
LO Generation
In 1T1R FDD+DPD type applications, ADRV9001 can use its internal LO to generate RF LO1 for uplink and RF LO2 for
downlink. For applications with stringent RF LO requirements, user can use external LO inputs. External LO1 operating
at 2x RF LO can be used for uplink and separate external LO2 operating at 2x RF LO for downlink.
RF Front End For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as
high as -50dBc and 3rd harmonic can be as high as -9 dBc. Therefore the RF filtering on the Rx and Tx path must
ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
DPD The DPD functionality can be utilized in the 1T1R FDD mode with second Tx being disabled. Maximum channel
bandwidth that DPD can support is limited by ADRV9001 RF bandwidth divided by 3 or by 5. The DPD operation can
be performed by ADRV9001 or Rx data can be sent to baseband processor via Rx data port serving as observation Rx.
Rx path used during DPD operation to perform Tx observation is also used by the Tx tracking calibrations. In case of
external DPD, user has to ensure that access to the Rx path during Tx slots is time-shared between external DPD
operation and internal Tx calibrations.
Calibrations During Rx initialization sequence, user needs to ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones that are present at Rx input. Maximum input signal amplitude should not exceed -82 dBm/MHz for
wideband modes, TBD dBm/MHz for narrowband modes.
During Tx initialization sequence user needs to ensure that Power Amplifier is power down to avoid unwanted
emission of Tx calibration tones at the antenna. ADRV9001 needs to access Rx datapath during Tx time slots for Tx
tracking calibration to operate. If user use Tx observation path with DPD functionality performed by baseband
processor then access to the Rx datapath during Tx slots need to be time-shared between DPD operation and Tx
calibrations.
AGPIOs Analog GPIOs (operating at 1.8V level) can be used as read or write digital levels of in the end user system. AGPIOs can
be utilized to control states of external components (e.g. RF Switch, LNA) or read back digital logic levels from
external components.
DGPIOs Digital GPIOs can be used to perform real time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be utilized by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (e.g. temperature sensor). Maximum AuxADC input voltage can not
exceed 0.9V.
AuxDAC AuxDAC can be used to: control VCXO responsible for generating ADRV9001 Device clock, generate pre-configured
ramp up/down signal that can be used to control power amplifier bias or control any circuitry that requires analog
control voltage up to 1.8V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, ADRV9001 can be initialized using API functions only.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 18 of 253
ADRV9001 IN TETRA TYPE PORTABLE RADIO APPLICATION
SPI
RESET
DEV_CLKL_OUT
MCS
DEV_CLK
DGPIOs
Rx/Tx_ENABLE
GP_INT
BPF FILTER
LNA
ATTENUATOR
RF SWITCH COUPLER
ANTENNA
VCXO
BALUN
BALUN
BALUN
BALUN
POWER IC
BALUN
BALUN
/2
SSI
DAC
VGA
PA LPF
FUNCTIONALITY
RF RECEPTION
USED BY Tx DPD AND CALIBRATI ONS
RF TRANSMISSION
RF I/O
Rx1A
Rx1B
ADRV9001
FPGA
OR
BBIC
VDDA_1P0
VDDA_1P3
VDDA_1P8
VDD_1P0
VDD_1P8
RF PLL2
RF PLL1
/2
EXT LO2
EXT LO1
Tx1
Rx1A
Rx1B
Tx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx1
DATA
AuxDACAuxADCAGPIOs
3/4/6/7/8/10
3/6/8
14/16
2
3/4
TEMPERATURE
SENSOR
EXTERNAL
LO SO URCE
Tx1
24159-007
INT
QEC
LOL
DPD
Figure 7. ADRV9001 in TETRA Type Portable Radio Application
TETRA Type Portable Radio Overview
ADRV9001 transceiver with minimum number of external components can be utilized to build complete RF-to-bits signal chain that can
serve as RF front end in TETRA type applications. Internal DPD block can be utilized to linearize external power amplifier and improve
overall system efficiency. For systems that demand superior LO phase noise performance ADRV9001 allows user to apply eternal RF LO.
ADRV9001 internal AGC can be utilized to autonomously monitor and set appropriate gain level for Rx signal chain. For time critical
TDD type applications control of the ADRV9001 TRx can be done by toggling control lines. ADRV9001 can control external Rx/Tx
switch using its analog GPIOs as well as provide power amplifier bias voltage by utilizing AuxDAC outputs.
Table 5. Constrains and Limitations in TETRA Type Portable Radio Application
Functionality Constrains and Limitations
LO Generation In Portable Radio, TETRA type application, ADRV9001 can use its internal LO to generate RF LO1 for both uplink and
downlink. For applications with stringent RF LO requirements, user can use external LO inputs. External LO1 operating
at 2x RF LO can be used for both uplink and downlink.
RF Front End For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as
high as -50dBc and 3rd harmonic can be as high as -9 dBc. Therefore the RF filtering on the Rx and Tx path must
ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
Preliminary Technical Data UG-1828
Rev. PrA | Page 19 of 253
Functionality Constrains and Limitations
DPD The DPD functionality can be utilized in the 1T1R TDD mode. Maximum channel bandwidth that DPD can support is
imited by ADRV9001 RF bandwidth divided by 3 or by 5. The DPD operation can be performed by ADRV9001 or Rx
data can be sent to baseband processor via Rx data port during Tx operation. Rx path used during DPD operation to
perform Tx observation is also used by the Tx tracking calibrations. In case of external DPD, user has to ensure that
access to the Rx path during Tx slots is time-shared between external DPD operation and Tx calls.
Calibrations During Rx initialization sequence, user needs to ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones. Maximum input signal amplitude should not exceed -82 dBm/MHz for wideband modes, TBD
dBm/MHz for narrowband modes. During Tx initialization sequence user needs to ensure that Power Amplifier is
power down to avoid unwanted emission of Tx calibration tones at the antenna. ADRV9001 needs to access Rx
datapath during Tx time slots for Tx tracking calibration to operate. If user use Tx observation path with DPD
functionality performed by baseband processor then access to the Rx datapath during Tx slots need to be time-
shared between DPD operation and Tx calibrations.
AGPIOs Analog GPIOs (operating at 1.8V level) can be used as read or write digital levels of in the end user system. AGPIOs can
be utilized to control states of external components (e.g. RF Switch) or read back digital logic levels from external
components.
DGPIOs Digital GPIOs can be used to perform real time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be utilized by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (e.g. temperature sensor). Maximum AuxADC input voltage can not
exceed 0.9V.
AuxDAC AuxDAC can be used to: control VCXO responsible for generating ADRV9001 Device clock, generate pre-configured
ramp up/down signal that can be used to control power amplifier bias, control any circuitry that requires analog
control voltage up to 1.8V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, ADRV9001 can be initialized using API functions only.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 20 of 253
ADRV9001 IN DMR TYPE PORTABLE RADIO APPLICATION
SPI
RESET
DEV_CLKL_OUT
MCS
DEV_CLK
DGPIOs
Rx/Tx_ENABLE
GP_INT
BPF FILTER
LNA ATTENUATOR
RF SWITCH COUPLER
ANTENNA
VCXO
BALUN
BALUN
BALUN
BALUN
POWER IC
BALUN
BALUN
/2
SSI
DAC
VGA
PA LPF
FUNCTIONALITY
RF RECEPTION
USED BY Tx I NIT CALI BRATI O NS
RF TRANSMISSION
RF I/O
Rx1A
Rx1B
Tx1
ADRV9001
FPGA
OR
BBIC
VDDA_1P0
VDDA_1P3
VDDA_1P8
VDD_1P0
VDD_1P8
RF PLL2
RF PLL1
/2
EXT LO2
EXT LO1
Tx1
Rx1A
Rx1B
INT
QEC
LOL
Tx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx1
DATA
AuxDACAuxADCAGPIOs
3/4/6/7/8/10
3/6/8
14/16
2
3/4
TEMPERATURE
SENSOR
EXTERNAL
LO SO URCE
24159-008
Figure 8. ADRV9001 in DMR Type Portable Radio Application
DMR Type Portable Radio Overview
ADRV9001 transceiver with minimum number of external components can be utilized to build complete RF-to-bits signal chain that can
serve as RF front end in DMR type applications. For systems that demand superior LO phase noise performance ADRV9001 allows user
to apply eternal RF LO. ADRV9001 internal AGC can be utilized to autonomously monitor and set appropriate gain level for Rx signal
chain. For time critical TDD type applications control of the ADRV9001 TRx can be done by toggling control lines. ADRV9001 can
control external Rx/Tx switch using its analog GPIOs as well as provide power amplifier bias voltage by utilizing AuxDAC outputs.
Table 6. Constrains and Limitations in DMR type Portable Radio Application
Functionality Constrains and Limitations
Rx Signal Path User have to ensure that appropriate level of isolation between Rx1 and Rx2 as well as Rx to Tx is provided at system
level. In example above, RxB input is utilized only during initialization calibrations. The LNA connected to the Rx1A
should be powered down during Tx slots to ensure proper operation of the Tx calibration path (connected to the
Rx1B). User should ensure that appropriate attenuation is present in line to prevent Rx being overloaded by Tx signal.
LO Generation
In Portable Radio, DMR type application, ADRV9001 can use its internal LO to generate RF LO1 for both uplink and
downlink. For applications with stringent RF LO requirements, user can use external LO inputs. External LO1 operating
at 2x RF LO can be used for both uplink and downlink.
RF Front End For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as
high as -50dBc and 3rd harmonic can be as high as -9 dBc. Therefore the RF filtering on the Rx and Tx path must
ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
Preliminary Technical Data UG-1828
Rev. PrA | Page 21 of 253
Functionality Constrains and Limitations
DPD The DPD functionality is not available when ADRV9001 operates in 1T1R mode.
Calibrations During Rx initialization sequence user needs to ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones. Maximum input signal amplitude should not exceed -82 dBm/MHz for wideband modes, TBD
dBm/MHz for narrowband modes. During Tx initialization sequence user needs to ensure that Power Amplifier is
power down to avoid unwanted emission of Tx calibration tones at the antenna.
For Tx tracking calibrations to operate, ADRV9001 needs to access Rx datapath during Tx time slots to operate.
AGPIOs Analog GPIOs (operating at 1.8V level) can be used as read or write digital levels of in the end user system. AGPIOs can
be utilized to control states of external components (e.g. RF Switch) or read back digital logic levels from external
components.
DGPIOs For DMR type applications ADRV9001 supports RF Monitor mode of operation. DGPIO pins are used to: sent wake up
signal to baseband processor, allow baseband processor to move ADRV9001 into Monitor mode using hardware pins
(instead API command).
Digital GPIOs can also be used to perform real time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 2 GPIOs may be utilized by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (e.g. temperature sensor). AuxADC input voltage can not exceed 0.9V.
AuxDAC AuxDAC can be used to: control VCXO responsible for generating ADRV9001 Device clock, generate pre-configured
ramp up/down signal that can be used to control power amplifier bias, control any circuitry that requires analog
control voltage up to 1.8V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, ADRV9001 can be initialized using API functions only.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 22 of 253
ADRV9001 IN FDD TYPE REPEATER APPLICATION
SPI
RESET
DEV_CLKL_OUT
MCS
DEV_CLK
DGPIOs
Rx/Tx_ENABLE
GP_INT
VGA
BPF FILTER
LNA
PA LPF
BPF FILTER
LNA
ATTENUATOR
COUPLER
DUPLEXER
DUPLEXER
ANTE NNA A
ANTE NNA B
A
B
B
A
VCXO
BALUN
BALUN
BALUN
BALUN
BALUN
POWER IC
BALUN
BALUN
/2
SSI
DAC
BALUN
BALUN
VGA
PA LPF
ATTENUATOR
COUPLER
FUNCTIONALITY
RECEPTI ON OF RF BAND B
USED BY Tx1 I NIT CALI BRATIONS
RECEPTI ON OF RF BAND A
USED BY Tx2 I NIT CALI BRATIONS
TRANS M ISSION OF RF BAND A
TRANS M ISSION OF RF BAND B
RF I/O
Rx1A
Rx1B
Rx2A
Rx2B
Tx1
Tx2
ADRV9001
FPGA
OR
BBIC
VDDA_1P0
VDDA_1P3
VDDA_1P8
VDD_1P0
VDD_1P8
RF PLL2
RF PLL1
/2
EXT LO2
EXT LO1
Tx1
Rx1A
Rx1B
Rx2A
Rx2B
Tx2
INT
QEC
LOL
Tx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx2
DATA
SSI
DAC INT
QEC
LOL
Tx2
DATA
AuxDACAuxADCAGPIOs
3/4/6/7/8/10
3/6/8
12/16
4
3/4
3/6/8
3/4/6/7/8/10
24159-009
Figure 9. ADRV9001 in FDD Type Repeater Application with Baseband Processor Analyzing Traffic Data
ADRV9001 in FDD Type Repeater Application with Baseband Processor
ADRV9001 transceiver with minimum number of external components can be utilized to build complete RF-to-bits signal chain that can
serve as RF front end in repeater or frequency translator type applications. ADRV9001 internal AGC can be utilized to autonomously
monitor and set appropriate gain level for Rx signal chains. For none time critical FDD type applications control of the ADRV9001 TRx
can be done thru API commands that utilize SPI interface.
Table 7. Constrains and Limitations in FDD Type Repeater Application with Baseband Processor Analyzing Traffic Data
Functionality Constrains and Limitations
Rx Signal Path User has to ensure that appropriate level of isolation between Rx1 and Rx2 as well as Rx to Tx is provided at system
level. In example above, RxB inputs are utilized only during initialization calibrations. User should ensure that
appropriate attenuation is present in line to prevent Rx being overloaded by Tx signal.
Tx Signal Path User has to ensure that appropriate level of isolation between Tx1 and Tx2 as well as Rx to Tx is provided at system
level.
LO Generation
In FDD type Repeater application, ADRV9001 can use its internal LO to generate RF LO1 for uplink (example: Tx1 and
Rx1) and RF LO2 for downlink (example: Tx2 and Rx2). It is also possible to use external LO inputs in this mode of
operation. External LO1 operating at 2x RF LO can be used for uplink and External LO2 operating at 2x RF LO can be
used for downlink.
Preliminary Technical Data UG-1828
Rev. PrA | Page 23 of 253
Functionality Constrains and Limitations
RF Front End For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as
high as -50dBc and 3rd harmonic can be as high as -9 dBc. Therefore the RF filtering on the Rx and Tx path must
ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
DPD The DPD functionality is not available when ADRV9001 operates in 2R2T FDD mode.
Calibrations During Rx initialization sequence user needs to ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones. Maximum input signal amplitude should not exceed -82 dBm/MHz for wideband modes, TBD
dBm/MHz for narrowband modes. During Tx initialization sequence user needs to ensure that Power Amplifier is
power down to avoid unwanted emission of Tx calibration tones at the antenna.
No Tx tracking calibrations are available when ADRV9001 operates in 2R2T FDD mode.
AGPIOs Analog GPIOs (operating at 1.8 V level) can be used as read or write digital levels of in the end user system. AGPIOs
can be utilized to control states of external components or read back digital logic levels from external components.
DGPIOs Digital GPIOs can be used to perform real time monitoring of states of internal ADRV9001 blocks Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be utilized by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (e.g. temperature sensor). Maximum AuxADC input voltage can not
exceed 0.9V.
AuxDAC AuxDAC can be used to: control VCXO responsible for generating ADRV9001 Device clock, control any circuitry that
requires analog control voltage up to 1.8V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, ADRV9001 can be initialized using API functions only.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 24 of 253
SPI
RESET
DEV_CLKL_OUT
MCS
DEV_CLK
DGPIOs
Rx/Tx_ENABLE
GP_INT
VGA
BPF FILTER
LNA
PA LPF
BPF FILTER
LNA
ATTENUATOR
COUPLER
DUPLEXER
DUPLEXER
ANTE NNA A
ANTE NNA B
A
B
B
A
BALUN
BALUN
BALUN
BALUN
POWER IC
BALUN
BALUN
/2
DAC
BALUN
BALUN
VGA
PA LPF
ATTENUATOR
COUPLER
ADRV9001
VDDA_1P0
VDDA_1P3
VDDA_1P8
VDD_1P0
VDD_1P8
RF PLL2
RF PLL1
/2
EXT LO2
EXT LO1
Tx1
Rx1A
Rx1B
Rx2A
Rx2B
Tx2
INT
QEC
LOL
ADC DDC
DEC
QEC
DC
ADC DDC
DEC
QEC
DC
DAC INT
QEC
LOL
AuxDACAuxADCAGPIOs
SSI
Tx1
DATA
SSI
Rx1
DATA
SSI
Rx2
DATA
SSI
Tx2
DATA
µC
3/4
FUNCTIONALITY
RECEPTI ON OF RF BAND A
USED BY Tx1 I NIT CALI BRATIONS
RECEPTI ON OF RF BAND B
USED BY Tx2 I NIT CALI BRATIONS
TRANS M ISSION OF RF BAND A
TRANS M ISSION OF RF BAND B
RF I/O
Rx1A
Rx1B
Rx2A
Rx2B
Tx1
Tx2
24159-010
Figure 10. ADRV9001 in FDD Type Repeater Application Without Baseband Processor Analyzing Traffic Data
FDD Type Repeater Without Baseband Processor Overview
ADRV9001 transceiver with minimum number of external components can be utilized to build complete RF-to-RF signal chain that can
serve as repeater or frequency translator. ADRV9001 internal AGC can be utilized to autonomously monitor and set appropriate gain
level for Rx signal chains. For none time critical FDD type applications control of the ADRV9001 TRx can be done thru API commands
that utilize SPI interface. Support of external crystal enables very compact solution where ADRV9001 provides clock for microprocessor
that programs and monitors ADRV9001 operation.
Table 8. Constrains and Limitations in FDD Type Repeater Application Without Baseband Processor Analyzing Traffic Data
Functionality Constrains and Limitations
Rx Signal Path User has to ensure that appropriate level of isolation between Rx1 and Rx2 as well as Rx to Tx is provided at system
level. In example above, RxB inputs are utilized only during initialization calibrations. User should ensure that
appropriate attenuation is present in line to prevent Rx being overloaded by Tx signal.
Tx Signal Path User has to ensure that appropriate level of isolation between Tx1 and Tx2 as well as Rx to Tx is provided at system
level.
LO Generation In FDD type Repeater application, ADRV9001 can use its internal LO to generate RF LO1 for uplink (example: Tx1 and
Rx1) and RF LO2 for downlink (example: Tx2 and Rx2). It is also possible to use external LO inputs in this mode of
operation. External LO1 operating at 2x RF LO can be used for uplink and External LO2 operating at 2x RF LO can be
used for downlink.
Preliminary Technical Data UG-1828
Rev. PrA | Page 25 of 253
Functionality Constrains and Limitations
RF Front End For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as
high as -50dBc and 3rd harmonic can be as high as -9 dBc. Therefore the RF filtering on the Rx and Tx path must
ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
DPD The DPD functionality is not available when ADRV9001 operates in 2R2T FDD mode.
Calibrations During Rx initialization sequence user needs to ensure that there are no signals at the Rx input (external LNA should
be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx calibration tones.
Maximum input signal amplitude should not exceed -82 dBm/MHz for wideband modes, TBD dBm/MHz for
narrowband modes. During Tx initialization sequence user needs to ensure that Power Amplifier is power down to
avoid unwanted emission of Tx calibration tones at the antenna.
No Tx tracking calibrations are available when ADRV9001 operates in 2R2T FDD mode.
AGPIOs Analog GPIOs (operating at 1.8V level) can be used as read or write digital levels of in the end user system. AGPIOs can
be utilized to control states of external components or read back digital logic levels from external components.
DGPIOs Unused in this application example.
AuxADC
AuxADC can be used to monitor analog voltage (e.g. temperature sensor). Maximum AuxADC input voltage cannot
exceed 0.9V.
AuxDAC AuxDAC can be used to control any circuitry that requires analog control voltage up to 1.8V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, ADRV9001 can be initialized using API functions only.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 26 of 253
ADRV9001 IN TDD TYPE REPEATER APPLICATION
SPI
RESET
DEV_CLKL_OUT
MCS
DEV_CLK
DGPIOs
Rx/Tx_ENABLE
GP_INT
BPF FILTER
LNA
ATTENUATOR
COUPLER
ANTE NNA A
VCXO
BALUN
BALUN
BALUN
BALUN
BALUN
POWER IC
BALUN
BALUN
/2
SSI
DAC
BALUN
BALUN
VGA
PA LPF
FUNCTIONALITY
RECEPTI ON FROM ANTENNA A
USED BY Tx1 DPD AND CALIBRATI ONS
RECEPTI ON FROM ANTENNA B
USED BY Tx2 DPD AND CALIBRATI ONS
TRANS M ISSION ON ANT E NNA A
TRANS M ISSION ON ANT E NNA B
RF I/O
Rx1A
Rx1B
Rx2A
Rx2B
Tx1
Tx2
ADRV9001
FPGA
OR
BBIC
VDDA_1P0
VDDA_1P3
VDDA_1P8
VDD_1P0
VDD_1P8
RF PLL2
RF PLL1
/2
EXT LO2
EXT LO1
Tx1
Rx1A
Rx1B
Rx2A
Rx2B
Tx2
INT
QEC
LOL
Tx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx2
DATA
SSI
DAC INT
QEC
LOL
Tx2
DATA
AuxDACAuxADCAGPIOs
3/4/6/7/8/10
3/6/8
12/16
4
3/4
3/6/8
3/4/6/7/8/10
BPF FILTER
LNA
ATTENUATOR
COUPLER
ANTE NNA B
PA LPF VGA
CIRCULATOR
CIRCULATOR
24159-011
Figure 11. ADRV9001 in TDD Type Repeater Application with Baseband Processor Analyzing Traffic Data
TDD Type Repeater Overview
ADRV9001 transceiver with minimum number of external components can be utilized to build complete RF-to-bits signal chain that can
serve as RF front end in TDD type repeater or frequency translator applications. In TDD type applications internal DPD block can be
utilized to linearize external power amplifier and improve overall system efficiency. ADRV9001 internal AGC can be utilized to
autonomously monitor and set appropriate gain level for Rx signal chains. FPGA or baseband processor is responsible for appropriate
time alignment of Rx and Tx time slots. Control of the ADRV9001 Rx and Tx signal chains can be done by toggling control lines.
ADRV9001 can provide power amplifier bias voltage by utilizing AuxDAC outputs.
Preliminary Technical Data UG-1828
Rev. PrA | Page 27 of 253
Table 9. Constrains and Limitations in TDD Type Repeater Application with Baseband Processor Analyzing Traffic Data
Functionality Constrains and Limitations
LO Generation
In TDD type Repeater application, ADRV9001 can use its internal LO to generate RF LO1 for both uplink and downlink.
It is also possible to use external LO inputs in this mode of operation. External LO1 operating at 2x RF LO can be used
for both uplink and downlink.
RF Front End For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example:
depending of RF matching used on the RF ports user 2nd LO harmonic can be as high as -50dBc and 3rd harmonic
can be as high as -9 dBc. Therefore the RF filtering on the Rx and Tx path must ensure that signals at the LO harmonic
frequencies (up to 9th in some cases) are not affecting overall system performance.
DPD The DPD functionality can be utilized in the 2R2T TDD mode. Maximum channel bandwidth that DPD can support is
limited by ADRV9001 RF bandwidth divided by 3 or by 5. The DPD operation can be performed by ADRV9001 or ORx
data can be sent to baseband processor via Rx data port during Tx operation. Rx path used during DPD operation to
perform Tx observation is also used by the Tx tracking calibrations. In case of external DPD, user has to ensure that
access to the Rx path during Tx slots is time-shared between DPD operation and Tx calibrations.
Calibrations During Rx initialization sequence user needs to ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones. Maximum input signal amplitude should not exceed -82 dBm/MHz for wideband modes, TBD
dBm/MHz for narrowband modes. During Tx initialization sequence user needs to ensure that Power Amplifier is
power down to avoid unwanted emission of Tx calibration tones at the antenna.
ADRV9001 needs to access Rx datapath during Tx time slots for Tx tracking calibration to operate. If user use Tx
observation path with DPD functionality performed by baseband processor then access to the Rx datapath during Tx
slots need to be time-shared between DPD operation and Tx calibrations.
AGPIOs Analog GPIOs (operating at 1.8V level) can be used as read or write digital levels of in the end user system. AGPIOs can
be utilized to control states of external components or read back digital logic levels from external components.
DGPIOs Digital GPIOs can be used to perform real time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be utilized by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (e.g. temperature sensor). Maximum AuxADC input voltage can not
exceed 0.9V.
AuxDAC AuxDAC can be used to: control VCXO responsible for generating ADRV9001 Device clock, generate pre-configured
ramp up/down signal that can be used to control power amplifier bias, control any circuitry that requires analog
control voltage up to 1.8V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, ADRV9001 can be initialized using API functions only.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 28 of 253
ADRV9001 IN RADAR TYPE APPLICATION
SPI
RESET
DEV_CLKL_OUT
MCS
DEV_CLK
DGPIOs
Rx/Tx_ENABLE
GP_INT
BPF
FILTER
LNA
ATTENUATOR
RF SWITCH COUPLER
ANTENNA A
VCXO
CONTROLCLK #3
DEVI CE CL OCK AND
MUL TICHIP SYNC
DISTRIBUTION IC
MCS 3
MCS 1
CLK 1
MCS 2
CLK 2
BALUN
BALUN
BALUN
BALUN
BALUN
POWER IC
BALUN
BALUN
/2
SSI
DAC
BALUN
BALUN
VGA
PA LPF
FUNCTIONALITY
RF RECEPTION
USED BY Tx1 INIT CALIBRATIO NS
RF RECEPTION
USED BY Tx2 INIT CALIBRATIO NS
RF TRANSM ISSIO N
RF TRANSM ISSIO N
RF I/O
Rx1A
Rx1B
Rx2A
Rx2B
Tx1
Tx2
FUNCTIONALITY
RF RECEPTION
USED BY Tx1 INIT CALIBRATIO NS
RF RECEPTION
USED BY Tx2 INIT CALIBRATIO NS
RF TRANSM ISSIO N
RF TRANSM ISSIO N
RF I/O
Rx1A
Rx1B
Rx2A
Rx2B
Tx1
Tx2
ADRV9001
FPGA
OR
BBIC
VDDA_1P0
VDDA_1P3
VDDA_1P8
VDD_1P0
VDD_1P8
RF PLL2
RF PLL1
/2
EXT LO2
EXT LO1
Tx1
Rx1A
Rx1B
Rx2A
Rx2B
Tx2
INT
QEC
LOL
Tx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx1
DATA
ADC DDC
DEC
QEC
DC SSI
Rx2
DATA
SSI
DAC INT
QEC
LOL
Tx2
DATA
AuxDAC
AuxADCAGPIOs
3/4/6/7/8/10
3/6/8
12/16
4
3/4
3/6/8
3/4/6/7/8/10
2
2
BPF
FILTER
LNA
ATTENUATOR
COUPLER
ANTENNA B
PA LPF ATTENUATOR
COUPLER
VGA
DIGITAL STE P
ATTENUATOR
RF SWITCH
DIGITAL STEP
ATTENUATOR
SPI
RESET
DEV_CLKL_OUT
MCS
DEV_CLK
DGPIOs
Rx/Tx_ENABLE
GP_INT
BPF
FILTER LNA
RF SWITCH
ANTENNA A
BALUN
BALUN
BALUN
BALUN
BALUN
POWER IC
BALUN
BALUN
/2
SSI DAC
BALUN
BALUN
VGA PA
LPF
ADRV9001
VDDA_1P0
VDDA_1P3
VDDA_1P8
VDD_1P0
VDD_1P8
RF PLL2
RF PLL1
/2
EXT LO2
EXT LO1
Tx1
Rx1A
Rx1B
Rx2A
Rx2B
Tx2
INT
QEC
LOL
Tx1
DATA
ADC
DDC
DEC
QEC
DC
SSI
Rx1
DATA
ADC
DDC
DEC
QEC
DC
SSI
Rx2
DATA
SSI DAC
INT
QEC
LOL
Tx2
DATA
AuxDAC AuxADC AGPIOs
3/4/6/7/8/10
3/6/8
12/16
4
3/4
3/6/8
3/4/6/7/8/10
2
2
BPF
FILTER LNA ANTENNA B
PA
LPF
VGA
DIGITAL STEP
ATTENUATOR
RF SWITCH
DIGITAL STEP
ATTENUATOR
ATTENUATOR
COUPLER
24159-012
Figure 12. ADRV9001 in Radar type application
Preliminary Technical Data UG-1828
Rev. PrA | Page 29 of 253
Radar Type Application Overview
ADRV9001 transceiver with minimum number of external components can be utilized to build complete RF-to-bits signal chain that can
serve as RF front end building block in Radar type applications. ADRV9001 internal AGC can be utilized to autonomously monitor and
set appropriate gain level for Rx signal chains. Internal AGC can utilize analog GPIO interface to control external DSA in the Rx signal
chains. For time critical TDD type applications control of the ADRV9001 TRx can be done by toggling control lines. ADRV9001 can
control external Rx/Tx switch using its analog GPIOs as well as provide power amplifier bias voltage by utilizing AuxDAC outputs. Multi
Chip Sync signal together with DEV_CLK can be utilized to synchronize multiple ADRV9001 in end system.
Table 10. Constrains and Limitations in Radar Type Application
Functionality Constrains and Limitations
Rx Signal Path User has to ensure that appropriate level of isolation between Rx1 and Rx2 as well as Rx to Tx is provided at system
level. In example above, RxB input is utilized during Tx observation. The LNA connected to the Rx1A should be
powered down during Tx slots to ensure proper operation of the Tx observation path (connected to the Rx1B). User
should ensure that appropriate attenuation is present in line to prevent Rx input being overloaded by Tx signal.
LO Generation In Radar type application, ADRV9001 can use its internal LO to generate RF LO1 for both uplink and downlink. For
applications with stringent RF LO requirements, user can use external LO inputs. External LO1 operating at 2x RF LO
can be used for both uplink and downlink.
RF Front End For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as
high as -50dBc and 3rd harmonic can be as high as -9 dBc. Therefore the RF filtering on the Rx and Tx path must
ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
DPD The DPD functionality can be utilized in the 2R2T TDD mode. Maximum channel bandwidth that DPD can support is
limited by ADRV9001 RF bandwidth divided by 3 or by 5. The DPD operation can be performed by ADRV9001 or ORx
data can be sent to baseband processor via Rx data port during Tx operation. Rx path used during DPD operation to
perform Tx observation is also used by the Tx tracking calibrations. In case of external DPD, user has to ensure that
access to the Rx path during Tx slots is time-shared between DPD operation and Tx calibrations.
Calibrations During Rx initialization sequence user needs to ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones. Maximum input signal amplitude should not exceed -82 dBm/MHz for wideband modes, TBD
dBm/MHz for narrowband modes. During Tx initialization sequence user needs to ensure that Power Amplifier is
power down to avoid unwanted emission of Tx calibration tones at the antenna.
ADRV9001 needs to access Rx datapath during Tx time slots for Tx tracking calibration to operate. If user use DPD in
its system then access to Rx datapath during Tx slots need to be time-shared between DPD operation and Tx
calibrations.
AGPIOs Analog GPIOs (operating at 1.8V level) can be used as read or write digital levels of in the end user system. AGPIOs can
be utilized to control states of external components (e.g. RF Switch) or read back digital logic levels from external
components.
DGPIOs Digital GPIOs can be used to perform real time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be utilized by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (e.g. temperature sensor). Maximum AuxADC input voltage can not
exceed 0.9V.
AuxDAC AuxDAC can be used to: control VCXO responsible for generating Device clock, generate pre-configured ramp
up/down signal that can be used to control power amplifier bias, control any circuitry that requires analog control
voltage up to 1.8V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync ADRV9001 allows the user to synchronize multiple transceivers used in single system. ADRV9001 provides the
capability to accept an external reference clock and synchronize operation with other devices using simple control
logic. Logical pulses applied at MCS input align each device’s data clock with a common reference. Relationship of
MCS pulse to the DEV_CLK edge at the ADRV9001 pins needs to be preserved. For correct operation, it is critical to
match length of PCB traces that carry DEV_CLK and MCS signals to each ADRV9001 device.
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SOFTWARE SYSTEM ARCHITECTURE DESCRIPTION
This section provides information about the device driver Application Programming Interface (API) software developed by ADI for the
ADRV9001 transceiver. This section outlines the overall architecture, folder structure, and methods for using API software on the
customer platform. Note that this document does not explain the API library functions. Detailed information regarding the API
functions is in the doxygen document included with the SDK (ADRV9001_API.chm) located at /pkg/production/. ADRV9001_API.chm
is in compressed HTML format. For security reasons, .chm files can only be opened from a local drive. If you attempt to open from a
network drive, the file may look empty. Note that the ADRV9001 is baseline device for the product family; therefore, all API and
evaluation systems use this product number to delineate the product.
SOFTWARE ARCHITECTURE
Figure 13 illustrates the software architecture for the ADRV9001 evaluation platform.
ADRV9001
APIs
ARM STREAM
Rx GAIN TABLE TX ATTEN TABLE
ADRV9001 TES GUI (C#)
CLIENT DLL [AUTO-GENERATED C#]
HOST (WINDOWS)
TARGET [LINUX]
EVALUATION BOARD
WITH DUT
ADRV9001
DEVICE DRIVER API [C]
SERVER [AUTO-GENERATED C]
FPGA [HDL]
24159-013
FPGA
APIs
Figure 13. DRV9001 API Software Architecture (ADI Evaluation Platform)
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FOLDER STRUCTURE
Source files are provided by ADI in the folder structure shown in Figure 14. Each subfolder is explained in the following sections. ADI
understands that the developer may desire to use a different folder structure. Whereas Analog Devices provides ADRV9001 API source
code releases in the folder structure shown below, the developer may organize the ADRV9001 API into a custom folder organization ,if
required. This operation, however, does not permit the developer the right to modify the content of the ADRV9001 API source code.
24159-014
Figure 14. API Folder Structure
/c_src/common
Common code shared between all the devices, this contains: error handling facilities, logging faclities, and HAL access facilities.
/c_src/boards
This section contains the API for the ADI evaluation board, it can see all the devices that are present in the board and implements
functions like the board initialize function.
/c_src/devices
The devices folder includes the main API code for the ADRV9001 transceiver as well as auxiliary devices APIs used for the demo of
ADRV9001. The /adrv9001 folder contains the high level function prototypes, data types, macros, and source code used to build the final
user software system. The user is strictly forbidden to modify the files contained in the /adrv9001 or other devices in this section,
software support is not provided when these files have been modified. Analog Devices maintains this code. The only exception is that
user may modify #define macros in adi_adrv9001_user.h such as ADI_ADRV9001_VERBOSE mode to enable/disable API logging.
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/c_src/platforms
The /platforms folder provides the means for a developer to insert custom platform hardware driver code for system integration with the
ADRV9001 API. A description regarding the HAL interface is contained later in this document. The adi_platform.c/.h files contain
function pointers and the required prototypes necessary for the ADRV9001 API to work correctly. Modification of the function
prototypes in adi_platform.c is forbidden. The developer is responsible for implementing the code for each function to ensure the correct
hardware drivers are called for the user’s platform hardware. In the example code provided by ADI in adi_platform.c, the function
pointers are assigned to call the ZC706 platform functions. The adi_hal_PlatformSetup function allows for the swapping of platforms.
To support another platform, the function pointers in adi_platform.c should be assigned to call the platform functions specific for the
user’s platform hardware.
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SOFTWARE INTEGRATION
The ADRV9001 API package was developed using the ZC706 Evaluation platform. This section describes how to use the provided
ADRV9001 API in a custom hardware/software environment. This is readily accomplished because the API was developed abiding by
ANSI C constructs while maintaining Linux system call transparency. The ANSI C standard was followed to ensure agnostic processor
and operating system integration with the ADRV9001 API code.
LOGGING
DEVICE LAYER
ADRV9001
COMMON
PLATFORM LAYER
adi_platform
HARDWARE ABS TRACT IO N LAYE R
APPLI CATI ON HAL
IMPLEMENTATION
APPLI CATI ON USE S
PLATFORM LAYER
AS AN I NTERFACE
TO MAP TO
THE IR HAL
MODIFICATION BY
APPLICATION IS
FORBIDDEN
ERRORHAL
PLATFORM SPI LOGGING TIMER
PLATFORM SPI LOGGING TIMER
24159-015
Figure 15. Evaluation system Software stack
HARDWARE ABSTRACTION LAYER
Users who develop code to target custom hardware platforms use different drivers for the peripherals such as the SPI and GPIO
compared to the drivers chosen for the ADI evaluation platform. The hardware abstraction layer (HAL) interface is a set of function
pointers that the ADRV9001 API uses when it needs to access the target platform hardware. The ADI HAL is defined in adi_platform.h.
The prototypes of the required functions defined in adi_platform.h are an interface between the ADRV9001 API and the HAL;
modifying them breaks the ADRV9001 API.
The implementation of this interface is platform dependent and needs to be implemented by the end user. The function pointer
associated to the user HAL layer needs to be set in adi_platform.c. The current adi_platform.c provides example code that sets the HAL
function pointers for the ZC706 evaluation platform specific functions.
The following is an example of assignment of a subset of adi_common_ function pointers to ZC706 specific functions in adi_platform.c:
adi_hal_HwOpen = zc706sd20_HwOpen;
adi_hal_HwClose = zc706sd20_HwClose;
adi_hal_HwReset = zc706sd20_HwReset;
adi_hal_DevHalCfgCreate = zc706sd20_DevHalCfgCreate;
adi_hal_DevHalCfgFree = zc706sd20_DevHalCfgFree;
...
adi_hal_SpiWrite = zc706sd20_SpiWrite;
adi_hal_SpiRead = zc706sd20_SpiRead;
...
adi_hal_LogFileOpen = zc706sd20_LogFileOpen;
adi_hal_LogLevelSet = zc706sd20_LogLevelSet;
adi_hal_LogLevelGet = zc706sd20_LogLevelGet;
adi_hal_LogWrite = zc706sd20_LogWrite;
A full description of all HAL functions can be found in the ADRV9001_API.chm document.
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API Error Handling and Debug
Logging Functions
The API provides a simple logging feature function that may be enabled for debugging purposes. Available logging levels are given by
adi_common_LogLevel_e as shown in Table 11.
Table 11. Logging Level
Function Name Purpose
ADI_COMMON_LOG_NONE
All types of log messages not selected
ADI_COMMON_LOG_MSG Log message type
ADI_COMMON_LOG_WARN Warning message type
ADI_COMMON_LOG_ERR Error message type
ADI_COMMON_LOG_API API function entry for logging purposes
ADI_COMMON_LOG_API_PRIV Private API function entry for logging purposes
ADI_COMMON_LOG_BF BF function entry for logging purposes
ADI_COMMON_LOG_HAL ADI HAL function entry for logging purposes
ADI_COMMON_LOG_SPI SPI transaction type
ADI_COMMON_LOG_ALL All types of log messages selected
When logging is enabled, the APIs call to send debug information to the system via the HAL. The function adi_hal_LogLevelSet is used
to configure flags in the HAL to control the processing of message types from the API layer. ADI transceiver open hardware function,
adi_hal_HwOpen, calls this function to set the desired logging operation. This feature requires an implementation for the
adi_hal_LogWrite function. The developer must specify the logging level by assigning the appropriate flag values to the #define
ADI_ADRV9001_LOGGING in adi_adrv9001_user.h
Error Handling
Each ADRV9001 API function returns an int32_t value representing a recovery action, with 0 being “no action” or success. Recovery
actions are divided into:
• Warning actions are those that don’t have an impact at the time of executing the device API but can cause performance issues or
logging problems. The value of this actions is positive.
• Error actions are those that cause API not to be able to run and an action is required for API to go back to a good state. The value of
this actions is negative.
See the ADRV9001_API.chm document for additional details.
DEVELOPING THE APPLICATION
The user application needs to allocate the init (adi_adrv9001_Init_t) and device (adi_adrv9001_Device_t) structures. Users may want to
consider allocating memory from the heap for the adi_adrv9001_Device_t and adi_adrv9001_Init_t as the structures have members
expected to be on the order of TBD KB.
The adi_adrv9001_Init_t structure is used to contain the customer profile initialization settings to configure an ADRV9001 device. This
init structure is passed to the ADRV9001 API init functions during the initialization phase. This structure contains the device profile
settings, system clock settings, data interface settings, and ADRV9001 specific SPI slave controller settings. The application layer passes a
pointer to an instance of the adi_adrv9001_Init_t structure for a particular ADRV9001 device to handle the majority of the device core
initialization. After initialization is complete, the adi_adrv9001_Init_t structure may be deallocated if desired.
The adi_adrv9001_Device_t data structure contains information for a particular ADRV9001 device, including devHalInfo, error and
caching structures. To support multiple ADRV9001 devices, the Application would need to instantiate multiple adi_adrv9001_Device_t
structures to describe each physical ADRV9001 device. Multiple ADRV9001 devices can have their own adi_adrv9001_Init_t or can
share a common adi_adrv9001_Init_t if they are to be configurated identically.
devHalInfo
devHalInfo is a structure that allows the user to define and pass any platform hardware settings to the platform HAL layer functions. The
common device structure adi_common_Device_t contains devHalInfo. devHalInfo is passed to the platform specific HAL function as a
void *devHalCfg. ADRV9001 API functions shall not read or write the devHalInfo but pass it as parameter to all HAL function calls.
The Application developer must define devHalInfo per system HAL implementation requirements. The Application developer may
implement any structure to pass any hardware configuration information that the hardware requires between application layer and
platform layer. For example, devHalInfo contains SPI chip select information to be used for the physical ADRV9001 device.
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Note that the API functions are shared across all instances of physical ADRV9001 devices. The devHalInfo structure defined by the
developer identifies which physical ADRV9001 device is targeted (SPI chip select) when a particular ADRV9001 API function is called.
The developer may need to store other hardware information unique to a particular ADRV9001 device in this structure such as timer
instances or log file information.
Note for ADRV9001 API there is a requirement that only one thread may control and configure a specific device instance at any given
time.
devStateInfo
The devStateInfo member is of type adi_adrv9001_Info_t and is a runtime state container for the ADRV9001 API. The application layer
must allocate memory for this structure, on the order of TBD KB, but only the ADRV9001 API writes to the structure. The application
layer should allocate the devStateInfo structure with all zeroes. The API uses the devStateInfo structure to keep up with the current state
of the API (has it been initialized, ARM loaded, etc.), as well as a debug store for any run-time data, such as error codes, error sources,
and so forth. It is not intended for the application layer to access the devStateInfo member directly because API functions are provided to
access information of the last error.
Private vs Public API functions
The API is made up of multiple .c and .h files. Since the API is written in C, there are no language modifiers to identify a function as
private or public as commonly used in object oriented languages. Per the ADI coding standard, public API functions are denoted by the
function name prepended with “adi_adrv9001_” (for example, adi_adrv9001_Rx_Gain_Set()). Private helper functions lack the adi_
prefix and are not intended to be called by the customer application.
Most functions in the ADRV9001 API are prefixed with “adi_adrv9001_” and are for public use. However, many of these functions are
never called directly from the application. Utility functions that abstract some common operations, specifically initialization of the
ADRV9001, are provided in adi_adrv9001_utilities.c. For this reason, much of the initialization and other helper functions have been
separated from the top-level adi_adrv9001.c/ adi_adrv9001.h files to help the developer focus on the functions most commonly used by
the Application.
Include Files
For each major function block, there are generally three files: adi_[feature].c, adi_[feature].h and adi_[feature]_types.h. The ADRV9001
API places typedef definitions in files with _types postfix such as adi_adrv9001_types.h. These _types.h files are included within their
corresponding .h files and do no need to be manually included in the application layer code.
Note that the adi_adrv9001_user.h contain the #defines for API timeouts and SPI read intervals which may be set as needed by the
customer platform. The ADRV9001 user files are the only API files that the developer may change.
Restrictions
Analog Devices maintains the code in the /c_api/devices/* folders. Modification of this code by Application developers is forbidden.
Direct SPI read/write operation is forbidden when configuring an ADRV9001 or any other ADI devices used for the evaluation of
ADRV9001. Developers should only use the high level API functions defined in the public *.h files. Developers should not directly use
any SPI read/write functions in the Application for ADRV9001 configuration or control. ADI does not support any application
containing SPI writes that are reverse engineered from the original ADRV9001 API.
Delays, Waits, and Sleeps
A subset of ADRV9001 APIs require delays to allow the hardware to complete internal configurations. These ADRV9001 APIs request
the system to perform a wait or sleep by calling the HAL interface function adi_common_Wait_us/adi_common_Wait_ms. If the target
platform’s HAL interface implementation chooses to implement a thread-sleep, it is not permitted for the application to call another API
targeting the same ADRV9001 device. The application is required to wait/sleep and the API to complete before continuing with the
configuration of the device.
Wait/sleep periods are defined in adi_adrv9001_user.h. The timeout period values are the recommended period required to complete the
operation. Modifying these values is not recommended and may impact performance. During this time-out period, the status of
ADRV9001 is polled. The frequency of the polling the status during this timeout period may be modified by the user by adjusting the
value of the polling interval.
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SYSTEM INITIALIZATION AND SHUTDOWN
A graphical user interface (GUI) based transceiver evaluation software (TES) is provided to user to initialize and interact with the
ADRV9001 device. Through this TES, the user could provide high level system configuration parameters such as signal bandwidth,
sample rate and initial gain control settings to initialize the device. The TES utilizes the user provided parameters to set up an
initialization C structure and then makes multiple API calls in a proper order to initialize the device. During the normal operation of the
device, the TES allows further user interaction with the device, such as adjusting the transmit/receive gain on the fly. When the operation
is completed, the user could safely shut down the device through TES. Figure 16 describes the high level flow of the device operation
sequence and the user interaction through TES.
START
INITIALIZATION
NORMAL OPERATION
SHUTDOWN
END
USER PROVIDES
INITIALIZATION
PARAMETERS
TO TES.
TES SETS UP THE
C STRUCTURE
AND CALLS
API COMMANDS.
USER ADJUST
PARAMETERS ON
THE FLY THROUGH TES.
USER SAFELY
SHUTS DOWN THE
DEVICE THROUGH TES.
1: adi_adrv9001_InitAnalog
2: adi_adrv9001_Utilities_Resources_Load
3: adi_adrv9001_Utilities_InitRadio_Load
4: adi_adrv9001_cals_InitCals_Run
5: adi_adrv9001_Radio_Channel_Prime
1: adi_adrv9001_Shutdown
API COMMANDS
...
24159-017
Figure 16. High level Flow Chart of the Device Operation and User Interaction through TES
As indicated in Figure 16, the purpose of this section is to provide user information about the initialization and shutdown process for the
ADRV9001 device utilizing the APIs developed by ADI. Figure 16 listed all high level APIs used for initialization and shutdown. In the
later sections, the major steps associated with each high level API command is further discussed. Note with Software Development Kit
(SDK) provided to the user, The ADRV9001 device can be initialized through user’s own software program independent of TES.
However, the same API calling procedure described in this document should be followed.
Note all the information discussed in this section is subject to change over the time. It is not the intention of this section to explain every
related API function. Detailed information regarding the API functions can be found in the ADRV9001 Device API doxygen document.
In addition, this section does not describe API integration and the hardware abstraction Interface. Details of such can be found in the
Software Integration section and HAL Integration section. To find more details about the TES, refer to the Transceiver Evaluation
Software (TES) section.
TES CONFIGURATION AND INITIALIZATION
The TES provides a Config tab that contains all the setup options for the ADRV9001. Under the Config tab, the user could configure
each channel of the device for a desired profile under the Device Configuration subtab, which sets high level parameters such as duplex
mode, data port sample rates and RF channel bandwidth. Then the user could further initialize the options used by the device during
startup under the Initialization subtab, such as the carrier frequencies, ADC type and initial calibrations. Note GUI design could change
significantly over the time, see the ADRV9001 Evaluation System section for up-to-date information.
Based on the parameters set by user, an initialization structure, adi_adrv9001_Init_t, is formulated by TES to contain all the required
settings to configure the device. This structure contains the system configuration setting, the system clock settings, transmit/receive data
structure settings and Programmable FIR filter settings. Please refer to the doxygen document for more details.
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After all tabs are configured, the user must press the “Program” button in TES. This kicks off initialization programming. TES sends a
series of API commands that are executed by a dedicated Linux application on the platform. This initialization structure is passed to the
ADRV9001 API initialization functions during the initialization phase. When programming is completed, the system is fully calibrated.
With a few additional API calls, the device is ready to operate.
The TES also provides the capability of generating a MATLAB code or python (.py) script or C code which includes all high level API
initialization calls after successfully programming the device. Those automatically generated codes or scripts can be given a file name and
stored in a location of the user’s choice for future use.
API INITIALIZATION SEQUENCE
As aforementioned, the initialization sequence is comprised of a serial of API calls intermixed with user-defined function calls specific to
the hardware platform. The API functions perform all the necessary tasks for device configuration, calibration and control. The
following diagram describes the state machine of the device from power up to RF enabled.
POWER_UP
STANDBY
STANDBY
STANDBY
CALIBRATED
CALIBRATE
ADDITIONAL
CALIBRATIONS
PRIMED
PRIME
UNPRIME
MONITORING
RF
ENABLED
CALIBRATE FAIL
AUTO
RF DISABL E
RF DISABL E
MONITOR
DISABLE
MONITOR
ENABLE
24159-018
Figure 17. Device State Machine
As shown in Figure 17, after power up, the device automatically enters the standby state, then the device initialization and calibration
begin. If it is successful, the device moves to the calibrated state, otherwise, it remains in standby state. Note when TES completes
programming, the device is in the calibrated state. After the device is calibrated, it needs to be further moved to the primed state, which
indicates that the device is ready for operation. Then, through SPI or PIN mode, the device can be moved to the RF enabled state by
enabling the transmit/receive channels so transmit and reception can start. Optionally, for power saving, the device can also enter the
monitoring state from the primed state. Refer to Power Saving and Monitor Mode section for details. In TES, after programming, playing
the receiver or transmitter moves the device from the calibrated state to the primed state and then to the RF enabled state.
This section mainly discusses the device initialization procedure from the standby state to the RF_ENABLED state. The related high level
API functions are discussed briefly in the following subsections. Refer to the doxygen document for details of each API function.
Note for MIMO systems with multiple inputs and outputs channels, multiple ADRV9001 devices might be involved. To synchronize
among all the devices, it requires a common device clock (DEV_CLOCK) and a multichip synchronization (MCS) signal so that all the
internally generated analog and digital clocks are aligned among all the devices. In addition, the MCS is used to synchronize the device
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and baseband processor data interface for all devices. For simplicity, in the following descriptions, MCS operations are omitted from the
initialization steps. Refer to Clock Generation and Multichip Synchronization section in the user guide for more details.
Analog Initialization
Analog initialization API adi_adrv9001_InitAnalog() is the very first API call to configure the device after all dependent data structures
have been initialized. It mainly sets the master bias, validates the profile settings and configures the analog clocks.
Digital Initialization
After analog initialization, adi_adrv9001_Utilities_Resources_Load() is the next API call. It loads all the resources such as stream image,
ARM image, programmable FIR (PFIR) coefficients and etc. It also enables the internal microprocessor and initialize digital clocks.
This API further calls a set of sub-APIs as shown in Figure 18. The order of the major sub-API calls is from the left to the right
sequentially. The functionality of each sub-API is explained in the box below it. At the end, this function further programs transmit
attenuation configurations.
LOAD STREAM IMAGE
adi_adrv9001_Utilities_Resources_Load
LOAD ARM IMAGE LOAD ARM PROFILE LOAD PFIR
COEFFICIENTS
LOAD Tx/Rx/ORx
GAIN TABLES
START ARM.
INITIALIZE
DIGITAL CLOCKS,
PROGRAM
CLK PLL AND ETC.
adi_adrv9001_Utilities_
ArmImage_Load
adi_adrv9001_arm_
Profile_Write
adi_adrv9001_arm_
PfirProfiles_Write
adi_adrv9001_Utilities_
Tables_Load adrv9001_ArmStart
adi_adrv9001_Utilities_
StreamImage_Load
24159-019
Figure 18. Load Resources and Digital Initialization
Radio Initialization
After digital initialization, the next step is radio control initialization through API call adi_adrv9001_Utilities_InitRadio_Load(), which
is used to load any radio configuration data not passed by profile before performing initial calibrations, such as GPIO configurations and
PLL frequencies.
This API further calls a set of sub-APIs as shown in Figure 19 (private APIs are not shown). Similarly, the order of the major sub-API
calls is from the left to the right sequentially. The functionality of each sub-API is explained below it.
GPIO CONFIGURATION
adi_adrv9001_gpio_ControlInit_
CONFIGURE
adi_adrv9001_Utilities_InitRadio_Load
SET LOOP FILTER CONFIGURATION FOR
PLL LO1, PLL LO2 AND AUX PLL
SET CARRIER FREQUENCY
SET TDD TIMING PARAMETERS
ENABLE ADC DYNAMIC SWITCH
24159-020
Figure 19. Radio Control Initialization
Calibrations Initialization
The next step in initialization is to perform initial calibrations through API call adi_adrv9001_cals_InitCals_Run() based on calibration
mask. To understand calibration mask, see the Transmitter/Receiver/Observation Receiver Signal Chain Calibrations section. When
initial calibrations are correctly performed, the channel state is transitioned from standby to the calibrated state as shown in Figure 17.
Prime and RF Enable
The last step in initialization is to move the device from calibrate to the primed state through API call
adi_adrv9001_Radio_Channel_Prime(). The primed state indicates that the system is ready for operation when the Tx and Rx channels
are enabled by user.
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After the channel is primed, in order to start the normal transmit or reception activities, it needs to be further transitioned from primed
state to RF enabled state. This can be accomplished by a set of API calls. There are two modes for channel enabling, which are PIN mode
and SPI mode.
PIN Mode
1. Call adi_adrv9001_Radio_ChannelEnableMode_Set( ) to set the PIN mode
2. Toggle the pins (for example, Rx1_ENABLE and Tx1_ENABLE pins for Channel 1) to transition the channel to “RF ENABLED”
state.
SPI Mode
1. Call adi_adrv9001_Radio_ChannelEnableMode_Set( ) to set the SPI mode
2. Call adi_adrv9001_Radio_Channel_EnableRf( ) to transition the channel to “RF ENABLED” state.
SHUTDOWN SEQUENCE
After completing all the operations, the user should call API adi_adrv9001_Shutdown() through TES to safely shutdown ADRV9001
device. It performs a hardware reset to reset the ADRV9001 device into a safe state for shutdown or re-initialization.
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SERIAL PERIPHERAL INTERFACE (SPI)
The SPI bus provides the mechanism for digital control by a baseband processor. Each SPI register is 8 bits wide, and each register
contains control bits, status monitors, or other settings that control all functions of the device. This section is mainly an information-
only section meant to give the user an understanding of the hardware interface used by the baseband processor to control the device. All
control functions are implemented using the API detailed within this document. The following sections explain the specifics of this
interface.
SPI CONFIGURATION
Users can configure SPI settings for the device with different SPI controller configurations by configuring member values of the
adi_adrv9001_SpiSettings_t data structure. The adi_adrv9001_SpiSettings_t data structure contains:
typedef struct adi_adrv9001SpiSettings
{
uint8_t msbFirst;
uint8_t enSpiStreaming;
uint8_t autoIncAddrUp;
uint8_t fourWireMode;
adi_adrv9001_CmosPadDrvStr_e cmosPadDrvStrength;
} adi_adrv9001_SpiSettings_t;
The parameters for this structure are listed in Table 12.
Table 12. SPI Settings Data Structure
Structure Member Value Function Default
MSBFirst 0x00 Least significant bit first 0x01
0x01 Most significant bit first
enSpiStreaming 0x00 Disable SW feature. Section Multi-Byte Data Transfer (SPI
Streaming) describes this mode of operation.
0x00
0x01 Enable SW feature to improve SPI throughput. Section
Multi-Byte Data Transfer (SPI Streaming) describes this
mode of operation.
Not Recommended since most registers in ADRV9001 API
are not consecutive
autoIncAddrUp 0x00 Auto-decrement. Functionality intended to be used with SPI
Streaming.
Sets address auto-decrement -> next addr = addr -1
0x01
0x01 Auto-increment. Functionality intended to be used with SPI
Streaming.
Sets address auto-increment -> next addr = addr +1
fourWireMode 0x00 SPI hardware implementation. Use 3-wire SPI (SDIO pin is
bidirectional). Figure 23 shows example of SPI 3-wire mode
of operation.
NOTE: ADI's FPGA platform always uses 4-wire mode.
0x01
0x01 SPI hardware implementation. Use 4-wire SPI. Figure 21 and
Figure 22 show examples of SPI 4 –wire mode of operation.
NOTE: Default mode for ADI's FPGA platform is 4-wire mode.
cmosPadDrvStrength 0x00 5pF load @ 75 MHz 0x01
0x01 100pF load @ 20 MHz
Any value that is not listed in the table is invalid.
For more details please refer to ADRV9001_API doxygen file provided in ADRV9001 SDK package.
Preliminary Technical Data UG-1828
Rev. PrA | Page 41 of 253
SPI BUS SIGNALS
The SPI bus consists of the following signals:
SCLK
SCLK is the serial interface reference clock driven by the baseband processor (uses the SPI_CLK pin). It is only active while CSB is low.
The minimum SCLK frequency is 1 KHz. The maximum SCLK frequency is 50 MHz.
CSB
CSB is the active-low chip select that functions as the bus enable signal driven from the baseband processor to the device (uses the
SPI_EN pin). CSB is driven low before the first SCLK rising edge and is normally driven high again after the last SCLK falling edge. The
device ignores the clock and data signals while CSB is high. CSB also frames communication to and from the device and returns the SPI
interface to the ready state when it is driven high.
Forcing CSB high in the middle of a transaction aborts part or all of the transaction. If the transaction is aborted before the instruction is
complete or in the middle of the first data word, the transaction is aborted and the state machine returned to the ready state. Any
complete data byte transfers prior to CSB deasserting are valid, but all subsequent transfers in a continuous SPI transaction are aborted.
SDIO and SDO
When configured as a 4-wire bus, the SPI utilizes two data signals: SDIO and SDO. SDIO is the data input line driven from the baseband
processor (uses the SPI_DIO pin) and SDO is the data output from the device to the baseband processor in this configuration (uses the
SPI_DO pin). When configured as a 3-wire bus, SDIO is used as a bidirectional data signal that both receives and transmits serial data.
The SDO port is disabled in this mode.
The data signals are launched on the falling edge of SCLK and sampled on the rising edge of SCLK by both the baseband processor and
the device. SDIO carries the control field from the baseband processor to the device during all transactions, and it carries the write data
fields during a write transaction. In a 3-wire SPI configuration, SDIO carries the returning read data fields from the device to the
baseband processor during a read transaction. In a 4-wire SPI configuration, SDO carries the returning data fields to the baseband
processor.
The SDO and SDIO pins transition to a high impedance state when the CSB input is high. The device does not provide any weak pull-
ups or pull-downs on these pins. When SDO is inactive, it is floated in a high impedance state. If a valid logic state on SDO is required at
all time, an external weak pull-up/down (10kΩ value) should be added on the PCB.
SPI DATA TRANSFER PROTOCOL
The SPI is a flexible, synchronous serial communication bus allowing seamless interfacing to many industry standard microcontrollers
and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel
SSR protocols. The control field width for this device is limited to 16 bits, and multi-byte IO operation is allowed. This device cannot be
used to control other devices on the bus – it only operates as a slave.
There are two phases to a communication cycle. Phase 1 is the control cycle, which is the writing of a control word into the device. The
control word provides the serial port controller with information regarding the data field transfer cycle, which is Phase 2 of the
communication cycle. The Phase 1 control field defines whether the upcoming data transfer is read or write. It also defines the register
address being accessed.
Phase 1 Instruction Format
The 16-bit control field contains the following information:
MSB D14:D0
R/Wb A<14:0>
R/Wb—Bit 15 of the instruction word determines whether a read or write data transfer occurs after the instruction byte write. Logic high
indicates a read operation; logic zero indicates a write operation.
D14:D0—Bits A<14:0> specify the starting byte address for the data transfer during Phase 2 of the I/O operation.
All byte addresses, both starting and internally generated addresses, are assumed to be valid. That is, if an invalid address (undefined
register) is accessed, the IO operation continues as if the address space were valid. For write operations, the written bits are discarded,
and read operations result in logic zeros at the output.
Single-Byte Data Transfer
When enSpiStreaming = 0, a single-byte data transfer is chosen. In this mode, CSB goes active-low, the SCLK signal activates, and the
address is transferred from the baseband processor to the device.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 42 of 253
In LSB mode, the LSB of the address is the first bit transmitted from the baseband processor, followed by the next 14 bits in order from
next LSB to MSB. The next bit signifies if the operation is read (set) or write (clear). If the operation is a write, the baseband processor
transmits the next 8 bits LSB to MSB. If the operation is a read, the device transmits the next 8 bits LSB to MSB. Once the final bit is
transferred, the data lines return to their idle state and the CSB line must be driven high to end the communication session.
In MSB mode, the first bit transmitted is the R/Wb bit that determines if the operation is a read (set) or write (clear). The MSB of the
address is the next bit transmitted from the baseband processor, followed by the remaining 14 bits in order from next MSB to LSB. If the
operation is a write, the baseband processor transmits the next 8 bits MSB to LSB. If the operation is a read, the device transmits the next
8 bits MSB to LSB. Once the final bit is transferred, the data lines return to their idle state and the CSB line must be driven high to end
the communication session.
Multibyte Data Transfer
When enSpiStreaming = 1, a multi-byte data transfer is allowed. In this mode, data transfers across the bus as long as the CSB pin is low.
The autoIncAddrUp controls how the address changes for subsequent writes or reads. When autoIncAddrUp = 1, the address
increments from the starting address for each subsequent data transfer until CSB is driven high. If the last register address is reached, the
next address accessed is 0x000. When autoIncAddrUp = 0, the address decrements from the starting address for each subsequent data
transfer. If address 0x000 is reached, the next address that is accessed is the last register location defined in the register map. The register
address 0x000 is used to setup SPI interface as well as functionality to soft reset the device. Uncontrolled data written to the register
address 0x000 can cause SPI misconfigurations or can reset the device. It is strongly recommended that any data transfer using Multi-
Byte Data feature to be controlled so that 0x000 is only written once at startup.
For multi-byte data transfers in LSB mode, the LSB of the address is the first bit transmitted from the baseband processor, followed by
the next 14 bits in order from next LSB to MSB. The next bit signifies if the operation is read (set) or write (clear). If the operation is a
write, the baseband processor transmits the next 8 bits LSB to MSB. After the MSB is received, the address increments or decrements
based on the autoIncAddrUp parameter. The baseband processor then continues to transfer data in 8-bit words, LSB to MSB, until the
operation is terminated by CSB being driven high. If the operation is a read, the device transmits the next 8 bits LSB to MSB. It then
changes the address and continues to transfer data in 8-bit words, LSB to MSB, until the operation is terminated by CSB being driven
high.
For multibyte data transfers in MSB mode, the same process is followed, except the first bit transferred indicates if the operation is read
(set) or write (clear). The starting address is then transmitted by the baseband processor MSB to LSB, followed by the data transfer, MSB
to LSB. Address increment or decrement is still controlled by the autoIncAddrUp parameter.
Using multibyte data transfer mode provides little benefit because most registers in the device are not consecutive. It is up to the user to
determine if multibyte data transfer enhances device control in their end application compared to the single command format.
Example: LSB-First Multibyte Transfer, Auto-Incrementing Address
To complete a 4-byte write starting at register address 0x02A and ending with register 0x02D in LSB-first format, follow these
instructions when programming the master:
• Make sure that fourWireMode = 1 – the device is configured to work with 4-wire interface
• Make sure that MSBFirst = 0 - SPI operates in LSB first mode
• Make sure that autoIncAddrUp = 1 - the address pointer automatically increments
• Make sure that enSpiStreaming = 1 - a multibyte data transfer is allowed
• Force the CSB line low and keep it low until the last byte is transferred
• Send the instruction word 0101 0100 0000 000_0 (the last 0 indicates a write operation) to select 0x02A as the starting address
• Use the next 32 clock cycles to send the data to be written to the registers, LSB to MSB for each 8-bit word
• Make sure the CSB line is driven high after the last bit has been sent to 0x02D to end the data transfer
Example: MSB-First Multibyte Transfer, Autodecrementing Address
To complete a 4-byte write starting at register address 0x02A and ending with register 0x027 in LSB-first format, follow these
instructions when programming the master:
• Make sure that fourWireMode = 1 – the device is configured to work with 4-wire interface
• Make sure that MSBFirst = 1 - SPI operates in MSB first mode
• Make sure that autoIncAddrUp = 0 - the address pointer automatically decrements
• Make sure that enSpiStreaming = 1 - a multi-byte data transfer is allowed
• Force the CSB line low and keep it low until the last byte is transferred
• Send the instruction word 0_000 0000 0010 1010 (the first 0 indicates a write operation) to select 0x02A as the starting address
Preliminary Technical Data UG-1828
Rev. PrA | Page 43 of 253
• Use the next 32 clock cycles to send the data to be written to the registers, MSB to LSB for each 8-bit word
• Make sure the CSB line is driven high after the last bit has been sent to 0x027 to end the data transfer
TIMING DIAGRAMS
The diagrams in Figure 21 and Figure 22 illustrate the SPI bus waveforms for a single-register write operation and a single-register read
operation, respectively. In the first figure, the value 0x55 is written to register 0x00A. In the second value, register 0x00A is read and the
value returned by the device is 0x55. If the same operations were performed with a 3-wire bus, the SDO line in Figure 21 would be
eliminated, and the SDIO and SDO lines in Figure 22 would be combined on the SDIO line. Note that both operations use MSB-first
mode and all data is latched on the rising edge of the SCLK signal.
WRITE TO RE GI S TER 0x00A – VALUE = 0x55
24159-021
CSB
SCLK
SDIO
SDO
Figure 20. Nominal Timing Diagram, SPI Write Operation
READ REG ISTER 0x00A – VALUE = 0x55
CSB
SDIO
SCLK
SDO
24159-022
Figure 21. Nominal Timing Diagram, SPI Read Operation
Table 13 lists the timing specifications for the SPI bus. The relationship between these parameters is shown in Figure 23. This diagram
shows a 3-wire SPI bus timing diagram with the device returning a value of 0xD4 from register 0x00A and timing parameters marked.
Note that this is a single read operation, so the bus-ready parameter after the data is driven from the device (tHZS) is not shown in the
diagram.
Table 13. SPI Bus Timing Constraint Values
Parameter Min Typical Max Description
tCP 20 ns SCLK cycle time (clock period)
tMP 10 ns SCLK pulse width
tSC 3 ns CSB setup time to first SCLK rising edge
tHC 0 ns Last SCLK falling edge to CSB hold
tS 2 ns SDIO data input setup time to SCLK
tH 0 ns SDIO data input hold time to SCLK
tCO 3 ns 8 ns SCLK falling edge to output data delay (3-wire or 4-wire mode)
tHZM tH tCO (max) Bus turnaround time after baseband processor drives the last address bit
tHZS 0 ns tCO (max) Bus turnaround time after device drives the last data bit
UG-1828 Preliminary Technical Data
Rev. PrA | Page 44 of 253
SDIO
CSB
DON’ T CARE
DON’ T CARE
DON’ T CARE
DON’ T CARE
SCLK
t
SC
t
MP
t
CP
t
S
t
H
t
HZM
t
HC
t
CO
24159-023
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 22. 3-Wire SPI Timing with Parameter Labels, SPI Read
Preliminary Technical Data UG-1828
Rev. PrA | Page 45 of 253
DATA INTERFACE
GENERAL DESCRIPTION
This document defines the synchronous serial interface (SSI) which transfer data between the ADRV9001 and a baseband processor .
ADRV9001 SSI consists of two receive channels and two transmit channels, the channels are independent and can be configured as
CMOS signals (CSSI) for applications that have narrow RF signal bandwidths and low data rate or as LVDS signals (LSSI) for
applications that require high speed, low noise and longer distance data transfer.
The CSSI supports below two modes of operation and can be operated as either in single data rate (SDR) or double data rate (DDR) data
transfer, the maximum clock frequency is 80 MHz.
• One lane data mode, I/Q data or other format data are serialized onto one single lane.
• Four lanes data mode, which is valid only when ADRV9001 transmit or receive I/Q samples and I/Q samples are 16 bits wide. In
four-lane data mode, each sample is split into 8 bits block of data and sent over one data lane.
The LSSI also supports two modes of operation, the LSSI always operates in DDR data transfer, the maximum clock frequency is up to
491.52MHz.
• I/Q in one lane (one-lane mode)
• With I-Q data samples of 16 bits (total of 32 bits for each transfer)
• I/Q in separate lanes (two-lane mode)
• With I and Q data samples of 16bits
• With I and Q data samples of 12 bits
ADRV9001 SSI has various and flexible work modes to support all kinds of system scenarios, users can choose their appropriate work
modes according to the interface sample/symbol rate and bit width. Table 13 lists the ADRV9001 SSI work modes and the maximum
support I/Q sample rate.
Table 14. ADRV9001 SSI Work Modes
SSI Modes
Data Lanes Per
Channel
Serialization Factor Per
Data Lane
Maximum Data Lane
Rate (MHz)
Maximum Clock
Rate (MHz)
Maximum
Sample Rate
for I/Q (MHz)
Data
Type
CSSI 1-Lane 1 32 80 80 2.5 SDR
CSSI 1-Lane 1 32 160 80 5 DDR
CSSI 1-Lane1 1 16/8/2 80-SDR/160-DDR 80 Not
Applicable
SDR/DDR
CSSI 4-Lane 4 8 80 80 10 SDR
CSSI 4-Lane 4 8 160 80 20 DDR
LSSI 1-Lane 1 32 983.04 491.52 30.72 DDR
LSSI 2-Lane 2 16 983.04 491.52 61.44 DDR
LSSI 2- Lane2 2 12 737.28 368.64 61.44 DDR
1 ADRV9001 data port transmit/receive data symbols, refer CSSI Data Symbols Transmit and Receive.
2 For User’s LVDS data lane rate limitation applications, RX samples are rounded from 16 bits to 12 bits. Tx Sample are extended from 12bits to 16bits.
The following sections explain the details of the signals that make up the SSI and their properties when configured for each mode.
ELECTRICAL SPECIFICATION
ADRV9001 SSI can operate in standard single ended CMOS compatible mode or Low-voltage Differential Signal (LVDS) compatible
mode, CMOS SSI and LVDS SSI share the IO pads of ADRV9001. Figure 24 describes the four channels with their corresponding IOs in
CMOS and LVDS modes.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 46 of 253
N14
PIN CMOS-SSI
1-LANE
Rx
CHANNEL 1
M11 RX1_DCLK_OUT RX1_DCLK_OUT
M12
N13 RX1_STROBE_OUT RX1_STROBE_OUT
N14
M13 RX1_IDATA1_OUT
M14 RX1_DATA_OUT RX1_IDATA0_OUT
N11 RX1_QDATA3_OUT
N12 RX1_QDATA2_OUT
M4 RX2_DCLK_OUT RX2_DCLK_OUT
M3
N2 RX2_STROBE_OUT RX2_STROBE_OUT
N1
M2 RX2_IDATA1_OUT
M1 RX2_DATA_OUT RX2_IDATA0_OUT
N4 RX2_QDATA3_OUT
N3 RX2_QDATA2_OUT
N10 TX1_DCLK_IN TX1_DCLK_IN
N9
P13 TX1_STROBE_IN TX1_STROBE_IN
P12 TX1_DCLK_OUT TX1_DCLK_OUT
P9 TX1_IDATA1_IN
P8 TX1_DATA_IN TX1_IDATA0_IN
P10 TX1_QDATA3_IN
P11 TX1_QDATA2_IN
M10 TX1_DCLK_OUT TX1_DCLK_OUT
M9 TX1_DCLK_OUT TX1_DCLK_OUT
N5 TX2_STROBE_IN TX2_DCLK_IN+
N6
P2 TX2_STROBE_IN TX2_STROBE_IN
P3 TX2_DCLK_OUT TX2_DCLK_OUT
P6 TX2_IDATA1_IN
P7 TX2_DATA_IN TX2_IDATA0_IN
P5 TX2_QDATA3_IN
P4 TX2_QDATA2_IN
M5 TX2_DCLK_OUT TX2_DCLK_OUT
M6 TX2_DCLK_OUT TX2_DCLK_OUT
BALL #
M11
M12
N13
M14
M13
N12
N11
M3
M4
N1
N2
M1
M2
N3
N4
N9
N10
P12
P13
P8
P9
P11
P10
P9
M10
N6
N5
P3
P2
P7
P6
P4
P5
M6
M5
Rx CHANNEL 1
Rx CHANNEL 2
Tx CHANNEL 1
Tx CHANNEL 2
Rx1
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
CMOS/LVDS
Rx2
Tx1
Tx2
Tx
CHANNEL 1
Tx
CHANNEL 2
Rx
CHANNEL 2
CMOS-SSI
4-LANE
LVDS-SSI
RX1_DCLK_OUT+
RX1_DCLK_OUT–
RX1_STROBE_OUT+
RX1_IDATA_OUT+
RX1_IDATA_OUT–
RX1_QDATA_OUT+
RX1_QDATA_OUT–
RX2_DCLK_OUT+
RX2_DCLK_OUT–
RX2_STROBE_OUT+
RX2_STROBE_OUT–
RX2_IDATA_OUT+
RX2_IDATA_OUT–
RX2_QDATA_OUT+
RX2_QDATA_OUT–
TX1_DCLK_IN+
TX1_DCLK_IN–
TX1_STROBE_IN+
TX1_STROBE_IN–
TX1_IDATA_IN+
TX1_IDATA_IN–
TX1_QDATA_IN+
TX1_QDATA_IN–
TX1_DCLK_OUT+
TX1_DCLK_OUT–
TX2_DCLK_IN+
TX2_DCLK_IN–
TX2_STROBE_IN+
TX2_STROBE_IN–
TX2_IDATA_IN+
TX2_IDATA_IN–
TX2_QDATA_IN+
TX2_QDATA_IN–
TX2_DCLK_OUT+
TX2_DCLK_OUT–
RX1_STROBE_OUT–
24159-024
Figure 23. ADRV9001 SSI I/Os Mapping
CMOS SSI electrical specification is shown in Table 14. For good performance, the CMOS outputs should drive minimal capacitive
loads. The CMOS output drive strength can be increased for capacitive loads bigger than 10 pF to increase the edge rate of output signal
during transitional period, the maximum capacitive load can reach to 30 pF at 80 MHz clock data rate.
In LVDS mode, an external 100 Ω differential termination resistor is required for each LVDS pair, and the termination resistors should
be located as close as possible to the LVDS receiver. ADRV9001 LVDS in circuit has optional internal 100 Ω termination resistor which
can be enabled for LSSI, but ADRV9001 LVDS output circuit does not have internal termination resistors, users should develop
appropriate LVDS termination resistors in LVDS receiver. The default LVDS out circuit produces 350 mV peak at 1.2V common mode
level, output swing level can be increased to 450 mV for longer trace. LVDS SSI electrical specification is shown in Table 15.
It is recommended to keep trace lengths of SSI Clock, Strobe, Data signals in one Transmit or Receive channel as equal as possible.
ADRV9001 SSI has configurable delay cells on LVDS/CMOS in and out circuits which can allow users to small adjust the phase
relationship between strobe/data and clock, the adjustable phase delay cell is approximate 90 ps per step for LVD mode and 170 ps per
step for CMOS mode, the maximum adjustable step is 7.
Preliminary Technical Data UG-1828
Rev. PrA | Page 47 of 253
Table 15. CSSI Electrical Specification
Symbol Parameter Min Typ Max Units
VDIGIO_1P8 Interface power supply voltage 1.71 1.8 1.89 V
VIH Input voltage high VDIGIO_1P8 × 0.65 VDIGIO_1P8 + 0.18 V
VIL Input voltage low 0 VDIGIO_1P8 × 0.35 V
VOH Output voltage high VDIGIO_1P8 − 0.45 VDIGIO_1P8 V
VOL Output voltage low 0 0.45 V
fCLK Clock frequency 80 MHz
CL @ 80 MHz Load capacitance supported for
an 80 MHz clock waveform
10 30 pF
Table 16. LSSI Electrical Specification
Symbol Parameter Conditions Min Typ Max Units
VDIGIO_1P8 Interface power supply voltage 1.71 1.8 1.89 V
VI Input voltage range 825 1675 mV
Input Common Mode Voltage 925 1200 1575 mV
VIDTH Input differential threshold −100 +100 mV
RIN Receiver differential input impedance 100 Ω
VOH Output voltage high RLOAD = 100 Ω ± 1% 1390 mV
VOL Output voltage low RLOAD = 100 Ω ± 1% 1000 mV
|VOD| Output differential voltage RLOAD = 100 Ω ± 1% 360 mV
VOS Output offset voltage RLOAD = 100 Ω ± 1% 1150 1200 1250 mV
RO Output impedance, single ended 80 100 120 Ω
ISA, ISB Output current Driver shorted to ground 17 mA
ISAB Output current Drivers shorted together 4.1 mA
Clock signal duty cycle 500 MHz 45 50 55 %
TR,TF Output Rise/Fall Time 300 mVp swing 0.371 nsec
CMOS SYNCHRONOUS SERIAL INTERFACE (CMOS-SSI)
One-Lane Mode CSSI Interface
Receive CSSI Interface
The one-lane mode receive CSSI interfaces of each channel (Rx1 and Rx2) are a 3-wire digital interface consisting of:
• RX_DCLK_OUT: is an output clock synchronizing data and strobe output signals.
• RX_STROBE_OUT: is an output signal indicating the first bit of the serial data sample.
• RX_DATA_OUT: is an output serial data stream.
The I and Q samples are serialized out starting with configurable I or Q first and MSB or LSB first, Figure 25 illustrates the receive CSSI
interface (Rx1 and Rx2) for a 16-bit I/Q data sample with I sample and MSB first configuration.
RX_DATA_OUT
RX_DCLK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
I0_D15 I0_D14 I0_D0 Q0_D15 Q0_D14 I0_Q0 I1_D15
24159-025
Figure 24. Receive CSSI Timing for 16-Bit I/Q Data Sample (I and MSB First)
The RX_STROBE_OUT signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high:
For one clock cycle at start of I and Q sample transmit. In the case a 16-bit data sample, RX_STROBE is high for one clock cycle and low
for 31 clock cycles.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 48 of 253
For I data duration and low for Q data duration. In the case of a 16-bit data sample, RX_STROBE is high for 16 clock cycles (I data
sample) and low for 16 clock cycles (Q data sample).
The Transmit CSSI Interface
The one-lane mode transmit CSSI interface of each channel (Tx1 and Tx2) is a 4-wire digital interface consisting of:
• TX_DCLK_IN: is an input clock synchronized to the data and strobe inputs.
• TX_STROBE_IN: is an input signal indicating the first bit of the serial data sample.
• TX_DATA_IN: is an input serial data stream.
• TX_DCLK_OUT: is an optional output reference clock that is provided to the baseband processor to generate all the above signals,
the baseband processor can also use RX_DCLK_OUT as the reference clock when its clock rate is equal with Transmit SSI clock
rate.
The I and Q samples can be deserialized starting with configurable I or Q first and MSB or LSB first, Figure 26 illustrates the Transmit
CSSI interface (Tx1 and Tx2) for a 16-bit I/Q data sample with I sample and MSB first configuration.
TX_DATA_IN
TX_DCLK_IN
TX_STROBE_IN
OR
TX_STROBE_IN
I0_D15 I0_D14 I0_D0 Q0_D15 Q0_D14 I0_Q0 I1_D15
TX_DCLK_OUT
24159-026
Figure 25. Transmit CSSI Timing for 16-Bit I/Q Data Sample (I and MSB First)
The TX_STROBE_IN signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high:
• For one clock cycle at start of I and Q sample transmit. In the case a 16-bit data sample, the TX_STROBE is high for one clock cycle
and low for 31 clock cycles.
• For I data duration and Low for Q data duration. In the case of a 16-bit data sample, TX_STROBE is high for 16 clock cycles (I data
sample) and low for 16 clock cycles (Q data sample).
CSSI Data Symbols Transmit and Receive
The previous sections described data transfer with I/Q format with 16bit width. When the ADRV9001 internal
modulation/demodulation is enabled (refer to the Transmitter Signal Chain and Rx Demodulator sections), the data transfer between
ADRV9001 and baseband processor would be 2 bits or 16 bits I only data ( denoted as symbol to differentiate with I/Q complex
samples). In a symbol format mode, raw data are transferred through this interface using different data size. The CSSI interface supports
three additional data formats:
• 2 bits of data
• 8 bits of data
• 16 bits of data
Data with a size of two bits could be transferred over a CSSI with an 8-bit data format with six dummy bits. The clock and strobe
behavior are similar to the I/Q format described in previous sections.
Preliminary Technical Data UG-1828
Rev. PrA | Page 49 of 253
Figure 26 illustrates the receive CSSI interface (Rx) for 2-bit data symbols.
RX_DATA_OUT
RX_DCLK_OUT
RX_STROBE_OUT
S0_D1 S0_D0 S1_D1 S1_D0 S2_D1 S2_D0 S3_D1
24159-027
Figure 26. Receive CSSI Timing for 2-Bit Symbols (MSB First)
Figure 27 illustrates the transmit CSSI interface (Tx) for 2-bit data symbols.
TX_DCLK_OUT
TX_DCLK_IN
TX_STROBE_IN
TX_DATA_IN S0_D1 S0_D0 S1_D1 S1_D0 S2_D1 S2_D0 S3_D1
24159-028
Figure 27. Transmit CSSI Timing for 2-Bit Symbols (MSB First)
Figure 28 illustrates the receive CSSI interface (Rx) for 8-bit data symbols.
RX_DATA_OUT
RX_DCLK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
S0_D7 S0_D6 S0_D5 S0_D4 S0_D3 S0_D2 S0_D1 S0_D0 S1_D7
24159-029
Figure 28. Receive CSSI Timing for 8-Bit Symbols (MSB First)
Figure 29 illustrates the transmit CSSI interface (Tx) for a 8-bit data symbols.
TX_DCLK_OUT
TX_DCLK_IN
TX_STROBE_IN
OR
TX_STROBE_IN
TX_DATA_IN S0_D7 S0_D6 S0_D4 S0_D3 S0_D2 S0_D0 S1_D7
24159-030
Figure 29. Transmit CSSI Timing for 8-Bit Symbols (MSB First)
UG-1828 Preliminary Technical Data
Rev. PrA | Page 50 of 253
Figure 31 illustrates the receive CSSI interface (Rx) for 16-bit data symbols.
RX_DATA_OUT
RX_DCLK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
S0_D15 S0_D14 S0_D8 S0_D7 S0_D6 S0_D0 S1_D15
24159-031
Figure 30. Receive CSSI Timing for 16-Bit Symbols (MSB First)
Figure 32 illustrates the transmit CSSI interface (Tx) for a 16-bit data symbols.
TX_DATA_IN
TX_DCLK_IN
TX_STROBE_IN
OR
TX_STROBE_IN
S0_D15 S0_D14 S0_D8 S0_D7 S0_D6 S0_D0 S1_D15
TX_DCLK_OUT
24159-032
Figure 31. Transmit CSSI Timing for 16-Bit Symbols (MSB First)
Receive CSSI Interface with 2×, 4×, and 8× Data Clock Rates
ADRV9001 receive CSSI supports the 2 times, 4 times, or 8 times of the data clock rate for some applications.
Figure 32, Figure 33, and Figure 34 illustrate the receive CSSI interface (Rx1 and Rx2) for 16-bit I/Q data sample with 2×, 4×, and 8×
clock rates. The strobe pulse validates the start of the 32-bit I and Q samples, the remaining data bits are ignored.
RX_DCLK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT
16 CYCLES (I SAMPLE) 16 CYCLES (Q SAMPLE) 32 CYCLES (NO SAMPLE)
I0_D15 I0_D14 I0_D0 Q0_D15 Q0_D14 Q0_D0 I0_D14I1_D15
24159-033
Figure 32. Receive CSSI Timing with 2× Data Clock Rate for 16-Bit I/Q Data Sample (MSB First), 32 Cycles
RX_DCLK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT
16 CYCLES (I SAMPLE) 16 CYCLES (Q SAMPLE) 96 CYCLES (NO SAMPLE)
I0_D15 I0_D14 I0_D0 Q0_D15 Q0_D14 Q0_D0 I0_D14I1_D15
24159-034
Figure 33. Receive CSSI Timing with 4× Data Clock Rate for 16-Bit I/Q Data Sample (MSB First), 96 Cycles
Preliminary Technical Data UG-1828
Rev. PrA | Page 51 of 253
RX_DCLK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT
16 CYCLES (I SAMPLE) 16 CYCLES (Q SAMPLE) 224 CYCLES (NO SAMPLE)
I0_D15 I0_D14 I0_D0 Q0_D15 Q0_D14 Q0_D0 I0_D14I1_D15
24159-035
Figure 34. Receive CSSI timing with 8× Data Clock Rate for 16-Bit I/Q Data Sample (MSB First), 224 Cycles
Figure 35, Figure 36, and Figure 37 illustrate the Receive CSSI interface (Rx1 and Rx2) in frequency deviation mode with 16-bit data
symbol with 2×, 4×, and 8× clock rates. The strobe pulse validates the start of the 16bits data symbol, the remaining data bits are ignored.
RX_CLOCK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT
16 CYCLES (I SAMPLE) 16 CYCLES (NO SAMPLE)
I0_D15 I0_D14 I0_D8 I0_D7 I0_D6 I0_D0 I0_D14I1_D15
24159-036
Figure 35. Receive CSSI Timing with 2× Data Clock Rate for 16-Bit Data Symbol (MSB First)
RX_CLOCK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT
16 CYCLES (I SAMPLE) 48 CYCLES (NO SAMPLE)
I0_D15 I0_D14 I0_D8 I0_D7 I0_D6 I0_D0 I0_D14I1_D15
24159-037
Figure 36. CSSI Receive Timing with 4× Data Clock Rate for 16-Bit Data Symbol (MSB First)
RX_CLOCK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT
16 CYCLES (I SAMPLE) 112 CYCLES (NO SAMPLE)
I0_D15 I0_D14 I0_D8 I0_D7 I0_D6 I0_D0 I0_D14I1_D15
24159-038
Figure 37. Receive CSSI Timing with 8× Data Clock Rate for 16-Bit Data Symbol (MSB First)
Four-Lane Mode CSSI Interface
The four-lane mode receive CSSI interface of each channel (Rx1 and Rx2) are a 6-wire digital interface consisting of:
• RX_DCLK_OUT: is an output clock synchronous data and strobe output signals.
• RX_STROBE_OUT: is an output signal indicating the first bit of the serial data sample.
• RX_IDATA0_OUT: is an output serial data stream of I sample low byte.
• RX_IDATA1_OUT: is an output serial data stream of I sample high byte.
• RX_QDATA2_OUT: is an output serial data stream of Q sample low byte.
• RX_QDATA3_OUT: is an output serial data stream of Q sample high byte.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 52 of 253
Figure 39 illustrates the receive CSSI interface (Rx1 and Rx2) for a four-lane format with MSB first configuration.
RX_IDATA0_OUT
RX_DCLK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_IDATA1_OUT
RX_QDATA2_OUT
RX_QDATA3_OUT
I0_D7 I0_D6 I0_D5 I0_D4 I0_D3 I0_D2 I0_D1 I0_D0 I1_D7
I0_D15 I0_D14 I0_D13 I0_D12 I0_D11 I0_D10 I0_D9 I0_D8 I1_D15
Q0_D7 Q0_D6 Q0_D5 Q0_D4 Q0_D3 Q0_D2 Q0_D1 Q0_D0 Q1_D7
Q0_D15 Q0_D14 Q0_D13 Q0_D12 Q0_D11 Q0_D10 Q0_D9 Q0_D8 Q1_D15
24159-039
Figure 38. Four-Lane Mode Receive CSSI Timing for 16-Bit I/Q Data Sample (MSB First)
The four-lane mode CSSI transmit interface of each channel (Tx1 and Tx2) is a 7-wire digital interface consisting of:
• TX_DCLK_IN: is an input clock synchronized to the data and strobe inputs.
• TX_STROBE_IN: is an input signal indicating the first bit of the serial data sample.
• TX_IDATA0_IN: is an input serial data stream of I sample low byte.
• TX_IDATA1_IN: is an input serial data stream of I sample high byte.
• TX_QDATA2_IN: is an input serial data stream of Q sample low byte.
• TX_QDATA3_IN: is an input serial data stream of Q sample high byte.
• TX_DCLK_OUT: is an optional output reference clock that is provided to the baseband processor to generate all the above signals,
the baseband processor can also RX_DCLK_OUT as the reference clock when its clock rate is equal with transmit SSI clock rate.
Figure 40 illustrates the transmit CSSI interface (Tx1 and Tx2) for a four-lane format with MSB first configuration.
TX_IDATA0_IN
TX_DCLK_IN
TX_DCLK_OUT
T
X_STROBE_IN
OR
T
X_STROBE_IN
I0_D7 I0_D6 I0_D5 I0_D4 I0_D3 I0_D2 I0_D1 I0_D0 I1_D7
TX_IDATA1_IN I0_D15 I0_D14 I0_D13 I0_D12 I0_D11 I0_D10 I0_D9 I0_D8 I1_D15
TX_QDATA2_IN Q0_D7 Q0_D6 Q0_D5 Q0_D4 Q0_D3 Q0_D2 Q0_D1 Q0_D0 Q1_D7
TX_QDATA3_IN Q0_D15 Q0_D14 Q0_D13 Q0_D12 Q0_D11 Q0_D10 Q0_D9 Q0_D8 Q1_D15
24159-040
Figure 39. Four-Lane Mode Transmit CSSI Timing for 16-Bit I/Q Data Sample (MSB First)
Transmit and Receive CSSI Using DDR Clock
Transmit and receive CSSI can be operated in either SDR or DDR data transfer.
Figure 41 illustrates the Rx CMOS SSI interface with DDR clock in relation with strobe/data. Each edge of the clock (positive and
negative) corresponds to a data sample. The RX DDR Clock can be generated in phase with the data/strobe or delayed quarter cycle of
the clock period, the optional delayed clock helps to ease the timing interface of the baseband processor to meet the setup/hold on the
baseband processor).
Preliminary Technical Data UG-1828
Rev. PrA | Page 53 of 253
RX_DCLK_OUT
OR
RX_DCLK_OUT
WIT H QUART E R CLO CK
CYCL E DE LAY
(OPTIONAL)
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_IDATA_IN I0_D15 I0_D14 I0_D8 I0_D7 I0_D6 I0_D0 I1_D15
24159-041
Figure 40. Receive CSSI DDR Clock Relation with Strobe/Data
Figure 41 illustrates the transmit CMOS SSI interface with DDR clock in relation with strobe/data, with respect to ADRV9001. Each edge
of the clock (positive and negative) samples the corresponding strobe/data sample based on the interface setup/hold timing.
When the baseband processor drives out the transmit SSI clock, strobe and data to ADRV9001, the output DDR clock can be in-phase
with the strobe/data or delayed quarter cycle of the clock period, it’s up to the user, but the relation between transmit DDR clock and
strobe/data must meet the ADRV9001 setup and hold timing specification.
TX_DCLK_IN
OR
TX_DCLK_IN
TX_DCLK_OUT
TX_STROBE_IN
OR
TX_STROBE_IN
TX_IDATA_IN I0_D15 I0_D14 I0_D8 I0_D7 I0_D6 I0_D0 I1_D15
24159-042
Figure 41. Transmit CSSI DDR Clock Relation with Strobe/Data
Figure 42 and Figure 43 illustrate the timing diagram example for four-lane mode receive, transmit CSSI with DDR clock, 16-bit I/Q
sample.
RX_IDATA0_IN
RX_DCLK_OUT
OR
RX_DCLK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
I0_D7 I0_D6 I0_D5 I0_D4 I0_D3 I0_D2 I0_D1 I0_D0 I1_D7
RX_IDATA1_IN I0_D15 I0_D14 I0_D13 I0_D12 I0_D11 I0_D10 I0_D9 I0_D8 I1_D15
RX_QDATA2_IN Q0_D7 Q0_D6 Q0_D5 Q0_D4 Q0_D3 Q0_D2 Q0_D1 Q0_D0 Q1_D7
RX_QDATA3_IN Q0_D15 Q0_D14 Q0_D13 Q0_D12 Q0_D11 Q0_D10 Q0_D9 Q0_D8 Q1_D15
24159-043
Figure 42. Four-Lane Mode Receive CSSI DDR Timing for 16-Bit I/Q Data Sample
UG-1828 Preliminary Technical Data
Rev. PrA | Page 54 of 253
TX_IDATA0_IN
TX_DCLK_IN
OR
TX_DCLK_IN
TX_DCLK_OUT
TX_STROBE_IN
OR
TX_STROBE_IN
I0_D7 I0_D6 I0_D5 I0_D4 I0_D3 I0_D2 I0_D1 I0_D0 I1_D7
TX_IDATA1_IN I0_D15 I0_D14 I0_D13 I0_D12 I0_D11 I0_D10 I0_D9 I0_D8 I1_D15
TX_QDATA2_IN Q0_D7 Q0_D6 Q0_D5 Q0_D4 Q0_D3 Q0_D2 Q0_D1 Q0_D0 Q1_D7
TX_QDATA3_IN Q0_D15 Q0_D14 Q0_D13 Q0_D12 Q0_D11 Q0_D10 Q0_D9 Q0_D8 Q1_D15
24159-044
Figure 43. Four-Lane Mode Transmit CSSI DDR Timing for 16-Bit I/Q Data Sample
LVDS SYNCHRONOUS SERIAL INTERFACE (LVDS-SSI)
Receive LSSI Interface
The LSSI receive interfaces of each channel (Rx1 and Rx2) are a 8-wire LVDS interface consisting of:
• RX_DCLK_OUT (±): is a differential output clock.
• RX_STROBE_OUT (±): is a differential output signal indicating the first bit of the serial data sample.
• RX_IDATA_OUT (±): is a differential output serial I data stream.
• RX_QDATA_OUT (±): is a differential output serial Q data stream.
Receive LSSI Interface with Separate Lanes for I and Q
Figure 44 illustrates the receive LSSI interface (Rx1 and Rx2) for a 16-bit I/Q data sample with MSB first configuration. Figure 45
illustrates the receive LSSI interface for a 12-bit I/Q data sample.
RX_IDATA_OUT+/–
RX_DCLK_OUT+
OR
RX_DCLK_OUT+
RX_STROBE_OUT+
OR
RX_STROBE_OUT+
I0_D15
RX_QDATA_OUT+/– Q0_D15 Q0_D7 Q0_D0 Q1_D15 Q1_D14
Q0_D8
I0_D7 I0_D0 I1_D15 I1_D14I0_D8
24159-045
Figure 44. Receive LSSI Timing for 16-Bit I/Q Data Sample over Two Lanes (MSB First)
Preliminary Technical Data UG-1828
Rev. PrA | Page 55 of 253
RX_IDATA_OUT+/–
RX_DCLK_OUT+
OR
RX_DCLK_OUT+
RX_STROBE_OUT+
OR
RX_STROBE_OUT+
I0_D11
RX_QDATA_OUT+/– Q0_D11 Q0_D5 Q0_D0 Q1_D11 Q1_D10
Q0_D6
I0_D5 I0_D0 I1_D11 I1_D10I0_D6
24159-046
Figure 45. Receive LSSI Timing for 12-Bit I/Q Data Sample over Two Lanes (MSB First)
The RX_STROBE signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high:
• For a half clock cycle at start of I and Q sample transmit. In the case of a 16-bit data sample, RX_STROBE is high for a half clock
cycle and low for a half and 15 clock cycles. In the case of a 12-bit data sample, RX_STROBE is high for a half clock cycle and low for
a half and 11 clock cycles.
• For half of I and Q data duration. In the case of a 16-bit data sample, the RX_STROBE is high for 4 clock cycles, and low for 4 clock
cycles (Q data sample). In the case of a 12bit data sample, the RX_STROBE is high for 3 clock cycles and low for 3 clock cycles.
In 12-bit I/Q mode, 16-bit samples from the receive datapath are cut to 12 bits for LSSI, a configurable option for the user to choose the
12-bit is from LSB or MSB of the 16-bit sample data.
Receive LSSI Interface with One Lane for I and Q
In this mode, only one lane is used to transfer I and Q data samples. The I/Q data bits are serialized with configurable I or Q first and
MSB or LSB first. The STROBE signal can be configured to high for a half clock cycle to indicate the start of I and Q symbols or for half
of I and Q data duration to distinguish between I data and Q data.
Figure 46 illustrates the one-lane receive LSSI interface (Rx1 and Rx2) for a 16-bit I/Q data sample with I sample and MSB first
configuration.
RX_IDATA_OUT+/–
RX_DCLK_OUT+
OR
RX_DCLK_OUT+
RX_STROBE_OUT+
OR
RX_STROBE_OUT+
I0_D15
RX_QDATA_OUT+/–
I0_D15 Q0_D0 I1_D15 I1_D14I0_D0
24159-047
Figure 46. Receive LSSI Timing for 16-Bit I/Q Data Sample over One-Lane (I and MSB First)
Transmit LSSI Interface
The transmit LSSI interface of each channel (Tx1 and Tx2) is an 8-wire digital interface consisting of:
• TX_DCLK_IN (±): is a differential input clock synchronized to the data and strobe inputs.
• TX_STROBE_IN (±): is a differential input signal indicating the first bit of the serial data sample.
• TX_IDATA_IN (±): is a differential input serial I data stream.
• TX_QDATA_IN (±): is a differential input serial Q data stream.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 56 of 253
An additional port might be used as a reference clock for the baseband processor to generate above Transmit LSSI clock, Strobe and Data
signal, the user could use RX1_DCLK_OUT or RX2_DCLK_OUT as a reference clock if these clock frequencies are equal to the TX clock
frequency.
An optional LVDS port (alternative function of Digital GPIO) can also be configured as an output LVDS pad used as a reference clock
TX_DCLK_OUT (±) for the baseband processor, the user could use TX_DCLK_OUT to generate above LSSI clock, strobe and data
signal.
Transmit LSSI Interface with Separate Lanes for I and Q
Figure 47 illustrates the transmit LSSI interface (Tx1 and Tx2) for a 16-bit I/Q data sample with MSB first configuration.
TX_IDATA_IN+/–
TX_DCLK_IN+
OR
TX_DCLK_IN+
TX_DCLK_OUT+
TX_STROBE_IN+
OR
TX_STROBE_IN+
I0_D15
TX_QDATA_IN+/– Q0_D15 Q0_D7 Q0_D0 Q1_D15 Q1_D14Q0_D8
I0_D7 I0_D0 I1_D15 I1_D14I0_D8
24159-048
Figure 47. Transmit LSSI Timing for 16-Bit I/Q Data Sample on Separate Lanes
Figure 48 illustrates the Transmit LSSI interface (Tx1 and Tx2) for a 12-bit I/Q data sample with MSB first configuration.
TX_IDATA_IN+/–
TX_DCLK_IN+
OR
TX_DCLK_IN+
TX_DCLK_OUT+
TX_STROBE_IN+
OR
TX_STROBE_IN+
I0_D11
TX_QDATA_IN+/– Q0_D11 Q0_D5 Q0_D0 Q1_D11 Q1_D10Q0_D6
I0_D5 I0_D0 I1_D11 I1_D10I0_D6
24159-049
Figure 48. Transmit LSSI Timing for 12-Bit I/Q Data Sample on Separate Lanes
The TX_STROBE signal is aligned with the first bit of the serialized data (I & Q), and can be configured to be high:
• For a half clock cycle at start of I and Q sample transmit. In the case a 16-bit data sample, the TX_STROBE is high for a half clock
cycle and low for a half and 15 clock cycles. In the case of a 12-bit data sample, the TX_STROBE is high for a half clock cycle and
low for a half and 11 clock cycles.
• For half of I and Q data duration. In the case of a 16-bit data sample, the TX_STROBE is high for 4 clock cycles, and low for 4 clock
cycles (Q data sample). In the case of a 12-bit data sample, the TX_STROBE is high for 3 clock cycles and low for 3 clock cycles.
In 12-bit I/Q mode, 12-bit samples from LSSI are extended to 16 bits by padding four bits zero in LSB for the following transmit datapath
process.
Preliminary Technical Data UG-1828
Rev. PrA | Page 57 of 253
Transmit LSSI Interface with One Lane for I and Q
In this mode, only one lane is used to transfer I and Q data samples. The I/Q data bits can be deserialized with configurable I or Q first
and MSB or LSB first. The STROBE signal can be configured to high for a half clock cycle to indicate the start of I and Q symbols or for
half of I and Q data duration to distinguish when I Data and Q Data.
Figure 49 illustrates the one lane LSSI interface (Tx1 and Tx2) for a 16-bit I/Q data sample with I sample and MSB first configuration.
TX_IDATA_IN+/–
TX_DCLK_IN+
OR
TX_DCLK_IN+
TX_DCLK_OUT+
TX_STROBE_IN+
OR
TX_STROBE_IN+
I0_D15
TX_QDATA_IN+/–
I0_D0 Q0_D15 Q0_D14 I0_Q0 I1_D15I0_D14
24159-050
Figure 49. Transmit LSSI Timing for 16-Bit I/Q Data Sample Sharing One Lane
SSI TIMING PARAMETERS
Receive SSI and transmit SSI timing diagram are shown in Figure 50 and Figure 51. The preliminary timing specification for CMOS SSI
is described in Table 16 and the preliminary timing specification for LVDS SSI is described in Table 17.
DATA
CLOCK PE RIO D
DATA
T
DELAY
RX_DCLK_OUT
RX_STROBE/DATA_OUT
T
DELAY
24159-051
Figure 50. Receive SSI Timing Diagram
DATA
CLOCK PE RIO D
DATA
T
SETUP
T
HOLD
TX_DCLK_IN
TX_SROBE/DATA_IN
T
SETUP
T
HOLD
DATA
24159-052
Figure 51. Transmit SSI Timing Diagram
Table 17. CMOS SSI Timing Specification
CMOS SSI Timing Description
CMOS Rx tDELAY Maximum 5 ns Clock to strobe/data delay
CMOS Tx tSETUP Minimum 2 ns Strobe/data setup to clock
CMOS Tx tHOLD Minimum 2 ns Strobe/data hold after clock
UG-1828 Preliminary Technical Data
Rev. PrA | Page 58 of 253
Table 18. LVDS SSI Timing Specification
LVDS SSI Timing Description
Rx tDELAY (Maximum) 200 ps Clock to strobe/data delay
Tx tSETUP (Minimum) 200 ps Strobe/data setup to clock
Tx tHOLD (Minimum) 300 ps Strobe/data hold after clock
CSSI/LSSI TESTABILITY AND DEBUG
ADRV9001 SSI has built-in test pattern generator and test pattern checker which can help users to quickly test and debug the SSI
interface between the ADRV9001 and the baseband processor. Figure 52 illustrates the ADRV9001 SSI testability and debug diagram
with a baseband processor.
DAC TX1
DATA P ATH T X1 SSI TX1 SSI
TEST
PAT TERN G E N
TEST
PAT TERN G E N
USER T x DATA
BASE BAND PROCESS OR
USER T x DATA
USER Rx DAT A
DEBUG
LOGIC
DAC TX2
DATA P ATH T X2 SSI TX2 SSI
LVDS/
CMOS
SSI
INTERFACE
DEBUG
LOGIC
DEBUG
LOGIC
ADC RX1
DATA P ATH RX1 SSI TX1 SSI
TEST
PAT TERN G E N
USER Rx DAT A
DEBUG
LOGIC
ADC RX2
DATA P ATH RX2 SSI TX2 SSI
24159-053
Figure 52. ADRV9001 SSI Testability and Debug Diagram
ADRV9001 receive SSI can generate ramp or PRBS (LSSI only) pattern and replace the receive channel data to baseband processor when
enable the receive debug function, users can check the specified test pattern at their SSI output to test if the receive SSI works well.
ADRV9001 transmit SSI has ramp and PRBS (LSSI only) pattern checker, users can transmit ramp or PRBS pattern rather than user
transmit data via SSI to ADRV9001 to verify if transmit SSI works well. Moreover, ADRV9001 transmit SSI always monitors the
TX_STROBE_IN signal validity according the SSI work modes and reports the error flag if finds the strobe misalignment.
ADRV9001 transmit SSI data output can be loopback to receive SSI data input when transmit and receive SSI runs at same clock rate,
users can utilize themselves pattern generator and checker to verify if the whole system SSI works well.
As mentioned earier, the SSI clock, strobe and data have programable delay, this helps users to meet the timing spec that described in SSI
Timing Parameters.
Preliminary Technical Data UG-1828
Rev. PrA | Page 59 of 253
API PROGRAMMING
The ADRV9001 SSI configuration is performed in chip initialization stage and based on the following data structure.
typedef struct adi_adrv9001_SsiConfig
{
adi_adrv9001_SsiType_e ssiType;
adi_adrv9001_SsiDataFormat_e ssiDataFormatSel;
adi_adrv9001_SsiNumLane_e numLaneSel;
adi_adrv9001_SsiStrobeType_e strobeType;
uint8_t lsbFirst;
uint8_t qFirst;
bool refClockGpioEn;
uint8_t lvdsBitInversion;
uint8_t lvdsUseLsbIn12bitMode;
bool lvdsTxFullRefClkEn;
bool lvdsRxClkInversionEn;
uint32_t rfLvdsDiv;
bool cmosTxDdrNegStrobeEn;
bool cmosDdrPosClkEn;
bool cmosDdrClkInversionEn;
bool cmosDdrEn;
} adi_adrv9001_SsiConfig_t;
In the data structure, the previously mentioned SSI modes are defined for each Tx/RX channel, users can find the detail data structure
and enumerator description in API doxygen help file.
A set of API commands are provided to set and inspect the SSI test/debug functions, which are summarized in Table 19.
Table 19. SSI Test/Debug API List
SSI Function Name Description
adi_adrv9001_Ssi_Rx_TestMode_Configure Configures the SSI test mode for the specified Rx channel
adi_adrv9001_Ssi_Tx_TestMode_Configure Configures the SSI test mode for the specified Tx channel
adi_adrv9001_Ssi_Tx_TestMode_Status_Inspect Inspects the SSI test mode status for the specified Tx channel
adi_adrv9001_Ssi_Delay_Configure
Programs the SSI delay configuration
adi_adrv9001_Ssi_Delay_Inspect Gets the SSI delay configuration from ADRV9001 device
UG-1828 Preliminary Technical Data
Rev. PrA | Page 60 of 253
MICROPROCESSOR AND SYSTEM CONTROL
ADRV9001 supports quick configuration from idle states to operation and quick transition between receive and transmit states. Those
transitions are handled by internal blocks called stream processors. Stream processor is a processor within the ADRV9001 device
assigned to perform a series of configuration tasks upon an external request. Upon a request from the user, the stream processor
performs a series of actions defined in the image loaded into the ADRV9001 during initialization process.
The stream processor therefore has streams (series of tasks) for:
• Tx1 Enable/Tx1 disable
• Tx2 Enable/Tx2 disable
• Rx1 Enable/Rx1 disable
• Rx2 Enable/Rx2 disable
Enabling and disabling paths is done typically using pins, however can also be controlled over the SPI bus using API command. The
stream is not limited to path enabling events and can react to other events such as a DGPIO input signal.
ADRV9001 is flexible in its configuration, and therefore, the stream is flexible. In the same way as the initialization structures change
with profile, so the stream processor image needs to change with configuration, for example, the stream that enables Rx1 differs
depending on whether a narrowband or a wideband setup is chosen. For this reason, it is necessary to utilize a stream image for each
configuration of the device. In this way, when the user saves configuration files (.c) using the ADRV9001 TES, a stream image is also
saved automatically. This stream file should then be used when using these configuration files.
Figure 53 describes the general ecosystem of ADRV9001. On the right-hand side (data side), ADRV9001 interfaces with the BBIC and on
the left hand side (antenna side), it interfaces with the RF components. The following section describes control of the ADRV9001
datapaths.
Rx1 DATA PATH Rx1 SSI
LNA
Rx2 DATA PATH Rx2 SSI
LNA
Tx1 DATA PAT H Tx1 SSI
PA
Tx2 DATA PAT H
Rx1
STREAM
PROC.
Rx2
STREAM
PROC.
Tx1
STREAM
PROC.
Tx2
STREAM
PROC.
PA
RAMP
CONTROL
SPI
INTERFACE
Tx2 SS I
LNA1_CTRL
LNA2_CTRL
RF_SWITCH1
RF_SWITCH2
PA1_BIAS
PA2_BIAS
Rx1_ENABLE
Rx2_ENABLE
Tx1_ENABLE
Tx2_ENABLE
RAMP1_EN
RAMP2_EN
SPI INT E RFACE
PA
SWITCH
SWITCH
AuxDAC1
AuxDAC1
24159-054
Figure 53. Data Path Control Signals
Preliminary Technical Data UG-1828
Rev. PrA | Page 61 of 253
SYSTEM CONTROL
The datapaths within ADRV9001 can be controlled either through the API or through ENABLE pin controls. In the case of API control,
this is reliant on the SPI communication bus and thus for critical time alignment of powering on/off chains, pin control is recommended.
Each datapath is independently controlled, with the following enable signals defined:
Table 20. Data Path Enable Signals.
Enable Signal Data Path
RX1_ENABLE Rx1 datapath
RX2_ENABLE Rx2 datapath
TX1_ENABLE Tx1 datapath
TX2_ENABLE Tx2 datapath
For ADRV9001 to receive and react to control signals it needs to be moved to the primed state. The primed state indicates that the
system is ready for operation when the transmit and receive channels are enabled by the user. After the channel is primed, in order to
start transmit or reception activities, it needs to be further transitioned from the primed state to the RF_ENABLED state. This can be
accomplished by a set of API calls.
PIN Mode
1. Call adi_adrv9001_Radio_ChannelEnableMode_Set( ) to set the PIN mode
2. Toggle corresponding ENABLE pin to transition the channel to the RF_ENABLED state.
SPI Mode
1. Call adi_adrv9001_Radio_ChannelEnableMode_Set( ) to set the SPI mode
2. Call adi_adrv9001_Radio_Channel_EnableRf( ) to transition the channel to RF_ENABLED state.
After pin or SPI/API mode is executed, the ADRV9001 enables the requested channels. The channels remain active until further
instruction through a pin command or SPI/API command.
TIMING PARAMETERS CONTROL
ADRV9001 has integrated stream processors to handle various external and internal events that are required to be serviced in real time.
Those stream processors coupled with programmable delayed enable modules relieves the system firmware (running on integrated
microprocessor) from managing all those critical events by providing a quick and parallel response to external and internal events. This
configuration allows the 4 channels (Tx1, Tx2, Rx1, and Rx2) to operate independently from each other by using their own dedicated
stream processor.
ADRV9001 can support different applications each with its own unique challenges. A set of programmable timing parameters for both
transmit and receive are provided to users to meet their particular timing requirements in various TDD applications. Understanding the
ADRV9001 timing parameters is crucial to ensure all TDD events taking place at an accurate time order as expected by user. In addition,
configuring timing parameters in an optimal way by taking advantage of the multiple power saving modes ADRV9001 offered could
improve the overall system power consumption performance significantly.
Timing Definition
Transmit Timing Definition
Transmit timing parameters define the events that take place in order from the start of transmission at the ADRV9001 data port to the
end of transmission when the transmit burst is sent through the antenna to the air.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 62 of 253
t
TxEnaRise2On
TX ON: ANTENNA SWI TCH
USER PROVIDES ADRV 9001
ADRV9001 PRO V IDES US E R
HELPER PARAMETERS
FRAM ING ON AIR
FRAM ING AT BBIC
PIN: TX_E NABLE
TX_INTERFACE
TX ANALOG POWER t
TxEnaSetup
t
TxGT
t
TxGT
t
TxPD
t
TxEnaHold
t
TxPD
t
TxPD
VALID DAT A
VALID DAT A
TX
TX
t
TxPD
24159-055
t
TxEnaRise2AnaOn
t
TxEnaFall2Off
Figure 54. Transmitter Timing Parameters (tTxPD > tTxEnaSetup)
As shown in Figure 54, a transmit burst consists a series of valid transmit data with user’s option of padding guard data at the beginning
and end of the valid data. Based on the timing parameters configured by user, it is user’s decision if full or partial of the guard data
should be transmitted to the air and user’s responsibility to make sure that the guard data usage is compliant with the standard
requirement. The transmit enable pin is controlled by user to signal the start and end of a transmit burst at the data port. Based on the
transmitter enable signal and a set of transmit timing parameters configured by user, ADRV9001 further controls the transmitter
interface, transmitter internal analog components, as well as the antenna switch (if it is controlled by ADRV9001 instead of user) to
make sure that the transmit burst is on air at deterministic time as desired by user.
Transmit timing parameters in Figure 54 can be categorized into three types: ADRV9001 parameter (ADRV9001 provides to user), user
parameter (user provides to ADRV9001), and helper parameters (determined by user which are not needed to provide to ADRV9001 but
could be utilized by the user to derive other required timing parameters). Table 21 further explains all these timing parameters. All
bounds specified in Table 21 are suggestions for optimal operation, no hardware or software restrictions prevent users from setting
values that are out of bounds. The maximum programmable parameter value is specified in later sections.
Table 21. Transmit Timing Parameters Description
Tx Timing Parameters Description
Provided
By Bounds Comments
enableSetupDelay
(tTxEnaSetup)
Time taken for ADRV9001 to
power up its analog front end.
This may or may not include
PLL tuning time based on the
use case. (For example, when
Tx and Rx shares the same IO
but at different frequency, PLL
tuning is needed at the frame
boundary.)
ADRV9001
Parameter
Min: N/A
Max: N/A
No PLL retuning @ frame
boundary: 8 μs (analog power-up
time)
PLL tuning @frame boundary:
758 μs (Analog Power-Up time +
PLL Tuning time)
(The PLL tuning time 750 μs refers
to the case when internal LO is
used. When external LO is used,
users should calculate and use
their own PLL tuning time. Note
the time required for PLL tuning is
continuously improving in the
future.)
propagationDelay
(tTxPD)
Delay from ADRV9001 digital
interface to antenna
Helper
Parameter
Min: N/A
Max: N/A
This parameter should be
measured by user and it is
dynamic profile dependent and
board layout dependent. It does
not need to be provided to
ADRV9001. It can be used to
derive other parameters required
by the ADRV9001.
Preliminary Technical Data UG-1828
Rev. PrA | Page 63 of 253
Tx Timing Parameters Description
Provided
By Bounds Comments
enableRiseToOnDelay
(tTxEnaRise2On)
Delay between Tx_enable
rising edge and antenna
switching to Tx channel. It
should align with the desired
time when the first symbol is
on air.
(If ADRV9001 is not controlling
antenna switch, this
parameter is not needed
except to determine other
parameters.)
User
Parameter
Min: 0
Typical: tTxPD
Max: tTxGT+ tTxPD
@ min bound: antenna switch
occurs tTxEnaSetup + some margin
after Tx enable rising edge
@ typical value: all symbols sent
over interface (including guard
symbols) make it onto the air
@ max bound: no guard symbols
are transmitted over the air
enableRiseToAnalogOnDelay
(tTxEnaRise2AnaOn)
Delay between Tx_enable
rising edge and analog power
up begins
User
parameter
Min: 0
Max: tTxEnaRise2On −
tTxEnaSetup
If Tx propagation delay is long, the
analog power up can be delayed
for power saving or to keep Tx
analog powered down during Rx
frame. If Tx propagation delay is
small, this should be set to 0. If this
parameter is greater than its max
bound, the antenna switch time
could be delayed.
enableGuardDelay
(tTxGT)
Guard time at the beginning
of the Tx frame. Reserved for
future use. Should set to 0
currently.
User
parameter
Min: TBD
Max: TBD
TBD
enableHoldDelay
(tTxEnaHold)
Delay between the falling
edge of Tx_enable and the Tx
interface being disabled.
(ADRV9001 forces it to 0
currently. Tx interface is
disabled at the same time
when Tx is disabled.)
User
parameter
Min: 0
Max: None. Must be
optimized to be
minimal.
Tx_enable falling edge should
ideally come as last valid data is
sent over interface. This can be
used to disable Tx algorithms
whose performance may be
degraded if guard symbols are
used. Interface can be kept on
even after Tx_enable falling edge
to allow transmission of user
guard symbols.
enableFallToOffDelay
(tTxEnaFall2Off)
Delay between Tx_enable
falling edge and antenna
switching to Rx channel and
Tx analog powers down. (Even
if ADRV9001 is not controlling
antenna switch, this
parameter is still needed to
delay analog power down.)
User
parameter
Min: tTxEnaHold
Max: None. Must be
optimized to be
minimal.
(Recommended
Max: tTxEnaHold + tTxPD
Note tTxEnaHold is
forced to 0
currently.)
@ min bound: antenna switch
occurs soon after Tx interface is
disabled. It should always occur
prior to powering down of Tx
analog. Not all symbols in the path
make it on air.
@ max bound: antenna is switched
away from Tx channel just as last
user data has propagated to
antenna.
Design Strategies for Transmit Timing Parameters
Use Case 1: tTXPD > tTXENASETUP
In this case, because the propagation delay is larger than the transmit analog set up delay, user may choose to delay powering up analog
front end while the data is propagating through the digital datapath as shown in Figure 54. This could achieve better power saving. For
example, if the user measures the propagation delay as 2.5 ms, whereas the enableSetupDelay provided by ADRV9001 is 8 μs, analog
front end could be off to avoid burning power for the first 2.492 ms of the propagation time. Having the analog front end powered up
early could also be a liability. For example, if the transmit propagation path delay is longer than the guard time between receive and
transmit frames, the transmit enable rising edge may occur in the middle of an receive frame. In this case, the user may want to keep the
analog front end of the transmitter channel powered down until the end of the receive frame. In such a case, the enableRiseToAnalogOnDelay
should be set to some value less than or equal to
propagationDelay – enableSetupDelay
UG-1828 Preliminary Technical Data
Rev. PrA | Page 64 of 253
Set enableRiseToOnDelay equal to the propagationDelay or enableRiseToAnalogOnDelay + enableSetupDelay. The transmit enable
rising edge should occur enableRiseToOnDelay before on air transmit begins. The transmit interface could be set high at the same time
as transmit enable to start transmitting guard symbols.
When the frame ends, the transmit enable falling edge should ideally occur right as the last valid data that must be demodulated by a
receiver sent over interface. Interface can be held on for some time longer to allow guard data to be sent across by setting
enableHoldDelay to a value greater than zero (note currently enableHoldDelay is forced to 0 by ADRV9001). The parameter,
enableFallToOffDelay, determines how much after the transmit enable falling edge, the antenna is switched away from the transmitter
channel. It must always be set to a value greater than equal to enableHoldDelay. If both values are set equal, for example, both are set to
0, the interface turns off first then analog powers down. To ensure that all the data that was sent over the interface makes it onto the air,
enableFallToOffDelay should be set greater than or equal to
enableHoldDelay + propagationDelay
If it is greater, then zeros are transmitted after all the data sent over the interface has been propagated.
Use Case 2: tTxPD < tTxEnaSetup
In this case, as shown in Figure 55, the time taken for data to propagate from the digital interface to antenna is very small, that is, tTxPD is
smaller than the time to setup the analog front end tTxEnaSetup, in such a case, enableRiseToAnalogOnDelay can be set to 0, so that analog
power up begins immediately after TX_ENABLE rising edge. The parameter, enableRiseToOnDelay, could also be set to 0, in this case,
the antenna is switched to a transmit channel, as soon as analog power up completes. For a more deterministic delay between transmit
enable rising edge and antenna switch time, enableRiseToOnDelay should be set to a value greater than or equal to
enableRiseToAnalogOnDelay + enableSetupDelay
In such a case, after raising Tx_enable, some guard data must be sent over the interface to make sure all valid Tx data is transmitted on
air. Based on the length of the user guard time and Tx timing parameter configurations, only a part or none of the guard data is
transmitted to the air.
When the frame ends, enableFallToOffDelay could be set in a similar way as discussed in Use Case 1.
Note ADRV9001 currently is not controlling the antenna switch, therefore it is the user’s responsibility to switch the antenna on and off
at the accurate time. As a recommendation, the antenna should be switched on after analog power up and switched off before analog
power down.
USER PROVIDES ADRV 9001
ADRV9001 PRO V IDES US E R
HELPER PARAMETERS
TX ON: ANTENNA SWI TCH
FRAM ING ON AIR
FRAM ING AT BBIC
PIN: TX_E NABLE
TX_INTERFACE
TX ANALOG POWER
t
TxGT
t
TxEnaFall2Off
t
TxEnaHold
t
TxPD
t
TxEnaRise2AnaOn
=0
t
TxEnaRise2On
VALID DAT A
VALID DAT A
t
TxPD
t
TxPD
24159-056
t
TxEnaSetup
Figure 55. Transmit Timing Parameters (tTxPD < tTxEnaSetup)
Receive Timing Definition
Receive timing parameters define the events that take place in order from the start of reception at the air to the end of reception when the
receive burst is sent through the ADRV9001 data port to the BBIC.
Preliminary Technical Data UG-1828
Rev. PrA | Page 65 of 253
USER PROVIDES NAVASSA
ADRV9001 PRO V IDES US E R
HELPER PARAMETERS
RX_INTERFACE
FRAM ING ON AIR
FRAM ING AT BBI C
PIN: RX_ENABLE
RX ON: LNA P OW ER OUT
RX ANAL O G POWE R
t
RxPD
t
RxPD
t
RxGT
t
RxPD
t
RxGT2
24159-057
t
RxEnaHold
t
RxEnaFall2Off
RX
RX
VALID DATA
t
RxEnaRise2On
t
RxPD
t
RxEnaSetup
t
RxEnaRise2On
t
RxPD
Figure 56. Receive Timing Parameters
As shown in Figure 56, similarly, a receive burst is composed of a series of valid Rx data with user’s option of padding guard data at the
beginning and end of the valid data. Similar to transmit, based on the timing parameters configured by the user, it is the user’s decision if
full or partial of the guard data should be received and it is the user’s responsibility to make sure that the guard data usage is compliant
with the standard requirement. The RX_ENABLE pin is controlled by the user to signal ADRV9001 the start and end of a receive burst at
the air (Note RX_ENABLE should rise before the start of the receive burst at air to allow powering up analog front end.). Based on the
RX_ENABLE signal and a set of receive timing parameters configured by user, ADRV9001 further controls receive analog components,
receive interface, and the external LNA (if it is controlled by ADRV9001 instead of user) to make sure that the received Rx burst is sent to
BBIC at the deterministic time as desired by user.
Similar to transmit timing parameters, as shown in Figure 56, receive timing parameters can be categorized into three types: ADRV9001
parameter (ADRV9001 provides to user), user parameter (user provides to ADRV9001) and helper parameters (determined by user
which are not needed to provide to ADRV9001 but could be utilized by the user to derive other required timing parameters).
All the parameters used in Figure 56 are explained further in Table 22. All bounds specified in Table 22 are suggestions for optimal
operation, no hardware or software restrictions prevent customer from setting values that are out of bounds. The maximum
programmable parameter value is specified in later sections.
Table 22. Receive Timing Parameters Description
Delay Description
Provided
By Bounds Comments
enableSetupDelay
(tRxEnaSetup)
Time taken for ADRV9001
to power up Rx analog
front end. This may or may
not include PLL tuning
time based on the use
case. (For example, when
Tx and Rx shares the same
LO but at different
frequency, PLL tuning is
needed at the frame
boundary.)
ADRV9001
Parameter
Min: N/A
Max: N/A
No PLL tuning @ frame boundary:
8 μs (analog power-up time)
PLL tuning @frame boundary:
758 μs (Analog Power-Up Time +
PLL Tuning Time)
(The PLL tuning time 750 μs refers
to the case when internal LO is
used. When external LO is used,
users should calculate and use their
own PLL tuning time. Note the time
required for PLL tuning is
continuously improving in the
future.)
UG-1828 Preliminary Technical Data
Rev. PrA | Page 66 of 253
Delay Description
Provided
By Bounds Comments
propagationDelay
(tRxPD)
Propagation delay from
antenna to Rx interface
Helper
Parameter
Min: N/A
Max: N/A
This parameter should be measured
by user and it is profile dependent
and board layout dependent. It
does not need to be provided to
ADRV9001, however, it can be used
to derive other values for other
parameters required by ADRV9001.
enableRiseToAnalogOnDelay
(tRxEnaRise2AnaOn)
Delay between RX_ENABLE
rising edge to start of Rx
analog power up
User
Parameter
Min: 0
Max: duration of power
up tasks in power
savings or frequency
hopping modes
Will only be set to non-zero values if
using power savings or frequency
hopping. See later sections to
determine how to choose a non-
zero value.
enableRiseToOnDelay
(tRxEnaRise2On)
Delay between RX_ENABLE
rising edge and LNA power
up.
If ADRV9001 does not
controlling LNA power, this
parameter is not needed
User
Parameter
Min: tRxEnaRise2AnaOn
Typ: tRxEnaRise2AnaOn +
tRxEnaSetup
Max: None. Must be
optimized to be
minimal.
If set to tRxEnaRise2AnaOn, the actual
delay is tRxEnaRise2AnaOn + tRxEnaSetup.
enableGuardDelay
(tRxGT)
Guard time at the
beginning of the Rx frame.
Reserved for future use.
Should set to 0 currently.
User
Parameter
Min: TBD
Max: TBD
TBD
enableFallToOffDelay
(tRxEnaFall2Off)
Delay between RX_ENABLE
falling edge and the
powering down the LNA.
(If ADRV9001 not
controlling LNA power, this
parameter can still be used
to delay analog power
down. ADRV9001 forces it
to 0 currently. LNA is
disabled at the same time
when Rx is disabled.)
User
Parameter
Min: 0
Max: None. Must be
optimized to be
minimal.
Ideally, RX_ENABLE falling edge
arrives when the last valid data is
received over the air. By setting this
value greater than 0, ADRV9001 can
continue receiving guard symbols,
while signaling to certain
algorithms or other systems that
the valid data for the frame has
already been received.
enableHoldDelay
(tRxEnaHold)
Delay between RX_ENABLE
falling edge and masking
off datapath data sent over
interface.
User
Parameter
Min: tRxEnaFall2Off
Max: None. Must be
optimized to be
minimal.
(Recommended Max:
tRxEnaFall2Off + tRxPD Note
tRxEnaFall2Off is forced to 0
currently.)
The interface is disabled only after
analog power down has completed.
@ min bound: Some of the data
received at the antenna may not
make it over the interface.
@ max bound: Digital datapath and
Rx SSI interface remains enabled
until last received data is
propagated to the interface.
Design Strategy for Receive Timing Parameters
As described in Table 22, ADRV9001 provides user enableSetupDelay which is the time required to power up the Rx front end. By
knowing that, user could set the RX_ENABLE pin high at least enableRiseToOnDelay in advance as shown in Figure 56. In regular TDD
mode, that is, no power savings or frequency hopping, enableRiseToAnalogOnDelay should always be set to 0, so that analog power up
begins immediately after receive enable rising edge (Note Figure 56 describes receive timing parameters in a general case with
enableRiseToAnalogOnDelay not equal to 0.). The parameter enableRiseToOnDelay could also be set to 0, in this case, the LNA is
powered up as soon as analog power up completes. For a more deterministic delay between RX_ENABLE rising edge and LNA power up
time, enableRiseToOnDelay can be set to a value greater than or equal to
enableRiseToAnalogOnDelay + enableSetupDelay
Once timing on air is established, the user may choose to raise RX_ENABLE, sometime before the start of the actual frame. As soon as
the Rx analog power up completes, the digital interface turns on , however, if the path has a long propagation delay, the initial data
coming off the interface are not the data received over the air.
When the frame ends, user may wish to continue receiving for a while, however, ADRV9001 may wish to stop all the tracking algorithms
to avoid any performance degradation. This can be achieved by bringing the RX_ENABLE signal low as soon as the frame ends but
Preliminary Technical Data UG-1828
Rev. PrA | Page 67 of 253
setting the enableFallToOffDelay equal to the time user wish to continue receiving data (Note enableFallToOffDelay is forced to 0
currently by ADRV9001.). This time should be no larger than the guard time before the next frame. The longer this value, the later the
next Rx_enable rising edge can occur. In cases where the receive path has a large propagation delay, user may wish to turn off the
receiver analog front end, so that user may commence a transmit frame, but still leave the digital datapath and interface on so that data
already received over the air may be sent over the interface. The enableHoldDelay parameter is used for this purpose. It must always be
set at least the enableFallToOffDelay. In order to receive all the data already received over the air, it should be set to
enableFallToOffDelay + propagationDelay
Guard/Hold Times Between Edges of TX_ENABLE and RX_ENABLE
By understanding the transmit and receive timing parameters discussed separately in the previous sections, the minimum guard/hold
time design between the rising and falling edges of TX_ENABLE and RX_ENABLE in a TDD system are further discussed in this section.
Six scenarios are considered, as follows:
• Guard time between TX_ENABLE falling edge and RX_ENABLE rising edge
• Guard time between RX_ENABLE falling edge and TX_ENABLE rising edge
• Guard time between TX_ENABLE falling edge and TX_ENABLE rising edge
• Guard time between RX_ENABLE falling edge and RX_ENABLE rising edge
• Hold time between TX_ENABLE rising edge and TX_ENABLE falling edge
• Hold time between RX_ENABLE rising edge and RX_ENABLE falling edge
User should always set the guard/hold timer greater than the minimum requirement. Note no hardware or software restriction prevents
user from raising TX_ENABLE/RX_ENABLE at any time. Correct operation cannot be guaranteed if rules described in the following
sections are violated.
Guard Time Between TX_ENABLE Falling Edge and RX_ENABLE Rising Edge
The guard time between TX_ENABLE falling edge and RX_ENABLE rising edge is for making sure that the transmitter analog front end
and the receiver analog front end are not powered up simultaneously. As discussed in previous sections, after TX_ENABLE falling edge,
it takes tTxEnaFall2Off to power off the transmitter analog front end. Therefore, the earliest time the receiver analog front end can be powered
up is tTxEnaFall2Off after the TX_ENABLE falling edge. Because it takes tRxEnaRise2On to power up the receiver analog front end starting from the
RX_ENABLE rising edge, the minimum guard time is tTxEnaFall2Off − tRxEnaRise2On if tTxEnaFall2Off is greater than tRxEnaRise2On. In the case of tTxEnaFall2Off
is less than tRxEnaRise2On (this could be possible when power saving modes are enabled as discussed in later sections), RX_ENABLE rising
edge could happen tRxEnaRise2On − tTxEnaFall2Off before TX_ENABLE falling edge. Figure 57 describes both cases.
Tx_ENABLE
Rx_ENABLE
t
TxEnaFall2Off
– t
RxEnaRise2On
Tx_ENABLE
Rx_ENABLE
t
RxEnaRise2On
– t
TxEnaFall2Off
t
TxEnaFall2Off
> t
RxEnaRise2On
t
TxEnaFall2Off
< t
RxEnaRise2On
24159-058
Figure 57. Minimum Guard Time Between TX_ENABLE Falling Edge and RX_ENABLE Rising Edge
Guard Time Between RX_ENABLE Falling Edge and TX_ENABLE Rising Edge
Similarly, the guard time between RX_ENABLE falling edge and TX_ENABLE rising edge is for making sure that the Rx analog front
end and the Tx analog front end are not powered up simultaneously. As discussed in previous sections, after RX_ENABLE falling edge, it
takes tRxEnaFall2Off to power off the Rx analog front end. Therefore the earliest time Tx analog front end can be powered up is tRxEnaFall2Off after
the RX_ENABLE falling edge. Because it takes tTxEnaRise2On to power up the transmitter analog front end starting from the TX_ENABLE
rising edge, the minimum guard time is tRxEnaFall2Off – tTxEnaRise2On if tRxEnaFall2Off is greater than tTxEnaRise2On. In the case of tRxEnaFall2Off is less than
tTxEnaRise2On, TX_ENABLE rising edge could happen tTxEnaRise2On − tRxEnaFall2Off before TX_ENABLE falling edge. Figure 58 describes both cases.
Rx_ENABLE
Tx_ENABLE
t
RxEnaFall2Off
– t
TxEnaRise2On
Rx_ENABLE
Tx_ENABLE
t
TxEnaRise2On
– t
RxEnaFall2Off
t
RxEnaFall2Off
> t
TxEnaRise2On
t
RxEnaFall2Off
< t
TxEnaRise2On
24159-059
Figure 58. Minimum Guard Time Between RX_ENABLE Falling Edge and TX_ENABLE Rising Edge
UG-1828 Preliminary Technical Data
Rev. PrA | Page 68 of 253
Guard Time Between TX_ENABLE Falling Edge and Tx_enable Rising Edge
The guard time between TX_ENABLE falling edge and TX_ENABLE rising edge is for making sure that the interface is turned off at the
end of the previous frame before it turns on again for the next frame. In addition, it must also make sure that the analog front end has
been powered off in the previous frame prior to powering up again in the new frame. Because it takes tTxEnaHold to turn off the transmit
interface after the TX_ENABLE falling edge, the next TX_ENABLE rising edge must come after a delay of at least tTxEnaHold. This ensures
that the interface is turned off at the end of the previous frame before it turns on again for the next frame. Since it takes tTxEnaFall2Off to
power down the transmitter analog front end after the TX_ENABLE falling edge, the next TX_ENABLE rising edge must come after a
delay of at least equal to tTxEnaFall2Off − tTxEnaRise2AnaOn. This ensures that the analog front end has been powered off in the previous frame prior
to powering up again in the new frame. If the timing parameters are set appropriately, these two conditions are almost identical. If they
are not identical for some reason, the guard time should be set as the maximum (tTxEnaHold, tTxEnaFall2Off − tTxEnaRise2AnaOn). Figure 59 describes
this scenario.
Tx_ENABLE
MAX (tTxEnaHold, tTxEnaFall2Off – tTxEnaRise2On)
24159-060
Figure 59. Minimum Guard Time Between TX_ENABLE Falling Edge and TX_ENABLE Rising Edge
Guard Time Between RX_ENABLE Falling Edge and RX_ENABLE Rising Edge
The guard time between the RX_ENABLE falling edge and RX_ENABLE rising edge is for making sure that the interface is turned off at
the end of the previous frame before it turns on again for the next frame. Because it takes tRxEnaHold to turn off the receive interface after the
RX_ENABLE falling edge, the next RX_ENABLE rising edge must come after a delay of at least tRxEnaHold. This ensures that the interface is
turned off at the end of the previous frame before it turns on again for the next frame. Because the analog powers down before the
interface, the analog front end is guaranteed to power down prior to being powered up at the start of the next frame if this condition is
met. Figure 60 describes this scenario.
Rx_ENABLE
t
RxEnaHold
24159-061
Figure 60. Minimum Guard Time Between RX_ENABLE Falling Edge and RX_ENABLE Rising Edge
Hold Time Between TX_ENABLE Rising Edge and TX_ENABLE Falling Edge
After a TX_ENABLE rising edge, its falling edge must come after a delay of at least tTxEnaRise2AnaOn or tTxEnaRise2On (if controlling antenna
switch). In order to actually transmit, the channel must be on for a duration longer than its propagation delay. This can be achieved,
either by making sure TX_ENABLE is high for longer than the propagation delay, or by ensuring the tTxEnaHold and tTxEnaFall2Off are longer
than tTxPD. Figure 61 describes this scenario.
Tx_ENABLE
tTxPD
24159-062
Figure 61. Minimum Hold Time between TX_ENABLE Rising Edge and TX_ENABLE Falling Edge
Hold Time Between RX_ENABLE Rising Edge and RX_ENABLE Falling Edge
After a RX_ENABLE rising edge, its falling edge must come after a delay of at least tRxEnaRise2AnaOn or tRxEnaRise2On (if controlling LNA power).
In order to actually receive data, the channel must be on for a duration longer than its propagation delay. This can be achieved, either by
making sure RX_ENABLE is high for longer than the propagation delay or by ensuring the tRxEnaHold is longer than tRxPD. Figure 62
describes this scenario.
Rx_ENABLE
t
RxPD
t
RxEnaRise2On
24159-063
Figure 62. Minimum Hold Time Between RX_ENABLE Rising Edge and RX_ENABLE Falling Edge
Timing Parameters with Power Savings Modes
ADRV9001 offers several channel power savings modes (Power Saving Mode 0, Power Saving Mode 1, and Power Saving Mode 2) that
trade off better power savings with longer transition time to turn on and turn off a transmit or receive channel. Please refer to the Power
Saving and Monitor Mode section in this User Guide for more details about power saving modes. In order to take advantage of these
power saving modes, the timing parameters must be set appropriately.
Preliminary Technical Data UG-1828
Rev. PrA | Page 69 of 253
Note the minimum guard time discussed above does not consider the time takes to power down transmit or receive analog by assuming
it is insignificant. But it is highly recommended to allow extra time to make sure analog power up happens only after analog power down
is fully completed. The analog power down time is usually much less than the analog power up time.
PIN: CH_ENABL E
CH ANALOG
POWER SAVINGS MODE 2
POWER SAVINGS MODE 1
POWER SAVINGS MODE 0
LDO POWER UP / DOWN
PLL POWER UP / DOWN
PLL TUNING
t
PowerUpPSM2
t
PowerDnPSM2
t
PowerDnPSM1
t
chEnaRise2AnaOn
t
chEnaSetup
t
chEnaFall2Off
IDLE
Tx CHANNE L ANALOG POW E R UP / DOWN
t
PowerUpPSM1
24159-064
Figure 63. Channel Power-Up and Power-Down Sequences in Different Power Savings Modes
Figure 63 shows the sequence of events taken to power up or power down a transmit or receive channel in the various channel power
savings modes. It can be seen in Power Savings Mode 1 and Power Savings Mode 2, the enableRiseToAnalogOnDelay is used to power
up additional entities that may have been powered down at the end of the previous frame. (Note in Power Savings Mode 1 and Power
Savings Mode 2, PLL is powered down at the end of the previous frame. Therefore, when it is turned on at the start of the new frame, PLL
tuning is required.) Thus, the enableRiseToAnalogOnDelay must be set long enough to allow these power up procedures to complete. If
the additional power-up procedures in Power Savings Mode 2 takes tPowerUpPSM2 to complete, the ADRV9001 prevents the system from
entering Power Savings Mode 2, unless enableRiseToAnalogOnDelay is set greater than tPowerUpPSM2. Refer to the Impact of Power Savings
on Timing Parameter Selection section for more details on hardware and software restrictions. Similarly, the same is true for Power
Savings Mode 1, the ADRV9001 prevents the system from entering Power Savings Mode 1, unless enableRiseToAnalogOnDelay is set
greater than tPowerUpPSM1. In Power Savings Mode 0, which is the default mode, there are no additional power up procedures, thus there is
no additional restrictions on enableRiseToAnalogOnDelay other than those already specified in earlier sections.
If switching dynamically between several power savings modes, user should set the enableRiseToAnalogOnDelay to satisfy the
restrictions of the highest power savings mode. Figure 63 shows that there is a longer idle time when switching to a lower power savings
mode. The parameter enableRiseToAnalogOnDelay cannot be changed dynamically, thus the timing of the TX_ENABLE/RX_ENABLE
rising edge relative to the on air time should also remain the same even when dynamically switching between different power savings
modes.
In certain use cases, when transmit and receive are using the same LO but at different frequencies, if the transition times between
transmit and receive frames are always long enough, PLL tuning is performed at the start of the frame. This is not related to any specific
power saving mode and PLL tuning happens even in Power Saving Mode 0. The timing diagram looks like Figure 64.
PI N: CH_E NABLE
CH ANALOG
POWER SAVINGS MODE 2
POWER SAVINGS MODE 1
POWER SAVINGS MODE 0
LDO POWER UP / DOWN
PLL POWER UP / DOWN
PLL TUNING
tPowerUpPSM2 tPowerDnPSM2
tPowerDnPSM1
tchEnaRise2AnaOn tchEnaFall2Off
IDLE
Tx CHANNE L ANAL OG P OW E R UP / DO WN
tPowerUpPSM1
tchEnaSetup
24159-065
Figure 64. Channel Power-Up and Power-Down Sequence in Different Power Savings Modes (PLL Retune @ Frame Boundary Case)
UG-1828 Preliminary Technical Data
Rev. PrA | Page 70 of 253
In this case, in all power saving modes, the PLL tuning is performed during enableSetupDelay instead of enableRiseToAnalogOnDelay.
Therefore, enableSetupDelay is much longer as it needs to allow time to tune the PLL. This means that the additional power up durations
tPowerUpPSM are much shorter and thus higher power savings can be achieved while setting the enableRiseToAnalogOnDelay to a much
smaller value.
Impact of Power Savings on Timing Parameter Selection
As explained in the previous section, certain power savings modes cannot be entered if the enableRiseToAnalogOnDelay for that channel
is not greater than the duration of the additional power up procedures needed in that mode.
For transmit channels, if the propagation delay is quite large, the enableRiseToAnalogOnDelay chosen may already be larger than the
longest power up procedure duration, that is, tPowerUpPSM2. In this case, there is no impact to the selection of the timing parameters.
For receive channels, or transmit channels with short propagation delays, the enableRiseToAnalogOnDelay must be chosen larger than
tPowerUpPSM1 to enter Power Savings Mode 1 and larger than tPowerUpPSM2 to enter Power Savings Mode 2 and higher. The
enableRiseToOnDelay, if it is being used, must also increase as it must always be larger than enableRiseToAnalogOnDelay. However,
none of the other timing parameters are affected by the power savings mode.
At the end of the frame, the power-down procedures take some small but finite time. For receiver channels with large propagation delay,
this may have no impact because the digital datapath might be on for a long time after the analog has powered down.
For transmit channels or receive channels with short propagation delays, the minimum period between the channel enable falling edge
and the next rising edge needs to be enableHoldDelay plus the additional time needed for the extra power-down procedures (tPowerUpPSM1,
tPowerUpPSM2). This prevents PLL or LDO from beginning power up in the new frame even before it has finished powering down in the old
one.
Hardware and Software Restrictions for Timing Parameters
As previously mentioned, the bounds provided for each of these timing parameters and the guard times between rising and falling edges
of the receiver and transmitter enable signals are only guidelines. There are almost no hardware or software restrictions preventing user
from setting these parameters anyway they like including harmful or useless ways. There are in place a few restrictions, however, which
are outlined as follows:
• All timing parameters that must be provided by user have to be within the range of 0 ms to 91 ms. These bounds are specified,
assuming the delay generation blocks run at 184.32 MHz (system clock). If operating at a different frequency, the maximum bound
scales accordingly. For example, if using a 160 MHz clock, the max delay is 91 ms/184.32 × 160 = 79 ms).
• For all channels the enableRiseToOnDelay must be greater than or equal to the enableRiseToAnalogOnDelay, provided the
enableRiseToOnDelay parameter is being used, that is, ADRV9001 is controlling antenna switch and/or LNA power.
• For transmitter channels, the enableHoldDelay must be less than or equal to the enableFallToOffDelay.
• For receiver channels, the enableFallToOffDelay must be less than or equal to the enableHoldDelay.
• For a specific channel, Power Savings Mode 2 or higher is disallowed when the enableRiseToAnalogOnDelay is less than tPowerUpPSM2.
• For a specific channel, Power Savings Mode 1 or higher is disallowed when the enableRiseToAnalogOnDelay is less than tPowerUpPSM1.
API Programming and Default Values for Timing Parameters
A set of API commands are provided to user to configure timing parameters. Because the timing parameters are related to the channel
power saving mode, user should set the channel power saving mode first before configuring the timing parameters. API Command
adi_adrv9001_arm_ChannelPowerSaving_Configure( ) is provided to the user to set the channel power saving mode for a specified
channel when the channel is in the calibrated, primed, or RF_ENABLED state. After that, user could use API Command
adi_adrv9001_Radio_ChannelEnablementDelays_Configure( ) to configure the timing parameters for the selected channel. The
following data structure holds all the ADRV9001 required timing parameters:
API Programming and Default Values for Timing Parameters
A set of API commands are provided to user to configure timing parameters. Because the timing parameters are related to the channel
power saving mode, user should set the channel power saving mode first before configuring the timing parameters. API Command
adi_adrv9001_arm_ChannelPowerSaving_Configure( ) is provided to user to set the channel power saving mode for a specified channel
when the channel is in the calibrated, primed, or RF_ENABLED state. After that, user could use API Command
adi_adrv9001_Radio_ChannelEnablementDelays_Configure( ) to configure the timing parameters for the selected channel. The
following data structure holds all the ADRV9001 required timing parameters:
Preliminary Technical Data UG-1828
Rev. PrA | Page 71 of 253
typedef struct adi_adrv9001_ChannelEnablementDelays
{
uint32_t riseToOnDelay; /* Delay from rising edge until antenna switch (Tx) or LNA
(Rx) is powered up */
uint32_t riseToAnalogOnDelay; /* Delay from rising edge until Tx/Rx analog power up
procedure commences */
uint32_t fallToOffDelay; /* Delay from falling edge until antenna switch (Tx) or LNA
(Rx) is powered down */
uint32_t guardDelay; /* Reserved for future use*/
uint32_t holdDelay; /* Delay from falling edge until the Tx/Rx interface is
disabled */
} adi_adrv9001_ChannelEnablementDelays_t
Note guardDelay is reserved for future use and forced to 0 by ADRV9001 for both transmitter and receiver channels. In addition to that,
for the transmitter channel, holdDelay is also reserved for future use and forced to 0. For the receiver channel, fallToOffDelay is also
reserved for future use and forced to 0. API Command adi_adrv9001_Radio_ChannelEnablementDelays_Configure( ) should be called
when the channel is in the standby or calibrated state.
To set all those timing parameters properly, user should have prior knowledge about ADRV9001 timing parameters (ADRV9001
provides to user) as well as helping parameters such as the transmit and receive propagation delay. The prior timing parameters include
enableSetupDelay, propagationDelay, and maximum intended power savings mode, tPowerUpPSM1 and tPowerUpPSM2.
Table 23 summarizes all these timing parameters for both transmit and receive. Note all timing parameters specified in units of time
assume a system clock frequency of 184.32 MHz. If using a different system clock frequency, it must be adjusted by
scaleFactor = 184.32 (MHz)/system clock Frequency
Table 23. Prior Tx/Rx Timing Parameters
No PLL Retuning at Frame Boundary
(Use Case in Figure 63)
PLL Retuning at frame boundary
(Use Case in Figure 64)
enableSetupDelay Analog Power-Up*scaleFactor PLL Tuning + Analog Power-Up *scaleFactor
propagationDelay From user’s own measurement Same as No PLL tuning case
tPowerUpPSM1 PLL Tuning + PLL Power-Up *scaleFactor PLL Power-Up *scaleFactor
tPowerUpPSM2 PLL Tuning + LDO Tuning + PLL Power-Up *scaleFactor LDO Tuning + PLL Power-Up *scaleFactor
The system clock Freq depends on the profile and user could find the corresponding value under TDD Enablement Delays tab in TES.
In addition to that, TES also displays the timing parameters provided by ADRV9001 to help determine the prior transmit/receive timing
parameters as described in Table 23. Figure 65 shows the picture of TES where those timing parameters and the system clock for the
current user selected profile are located.
24159-066
Figure 65. ADRV9001 Provided Timing Parameters and the System Clock for the Selected Profile in TES
Based on the information provided in Table 23 or Figure 65, user can further configure the ADRV9001 required timing parameters.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 72 of 253
Default Timing Parameters for Transmitter Channels
Figure 66 shows the ADRV9001 transmitter required timing parameters and their minimum, maximum, and default values as well as
some recommendations are summarized in Table 24.
TX_INTERFACE
PIN: TX_E NABLE
TX ANALOG POWER
TX ON: ANTENNA POW E R
t
RxGT
VALID DAT A
t
RxEnaRise2On
t
RxEnaRise2On
t
RxEnaHold
t
RxEnaFall2Off
t
RxEnaFall2Off
24159-067
Figure 66. Transmit Timing Parameters
Table 24. ADRV9001 User Provided Transmit Timing Parameters
Timing Parameter Min Value Max Value Comment
enableRiseToAnalogOnDelay
(tTxEnaRise2AnaOn)
Max of the following values: 0
propagationDelay –
enableSetupDelay
tPowerUpPSM (for the maximum
intended power savings mode)
91 ms/scaleFactor Default = min
enableRiseToOnDelay
(tTxEnaRise2On)
enableRiseToAnalogOnDelay +
enableSetupDelay
91 ms/scaleFactor Default = min
Not needed if not controlling LNA power
enableGuardDelay
(tTxGT)
(Not Used Currently)
0 91 ms/scaleFactor Default = min
Can increase to non-zero if performance
degradation is observed and the channel
is transmitting for some time before the
start of the actual frame
(Forced to be 0 currently by ADRV9001)
enableHoldDelay
(tTxEnaHold)
(Not Used Currently)
0 91 ms/scaleFactor Default = min
Can increase if performance degradation is
observed and the channel is transmitting
for some time after the end of the actual
frame
(Forced to be 0 currently by ADRV9001)
enableFallToOffDelay
(tTxEnaFall2Off)
enableHoldDelay enableHoldDelay +
propagationDelay
Default = max
Can decrease if not all data sent through
interface needs to be transmitted.
Default Timing Parameters for Receiver Channels
Figure 67 shows the ADRV9001 receiver required timing parameters and their minimum, maximum, and default values as well as some
recommendations are summarized in Table 25.
RX ON: LNA POWE R OUT
PIN: RX _E NABLE
RX ANALOG P OWE R
RX_INTERFACE
t
RxGT
t
RxEnaRise2On
t
RxEnaRise2On
t
RxEnaHold
t
RxEnaFall2Off
t
RxEnaFall2Off
24159-068
Figure 67. Receiver Timing Parameters
Preliminary Technical Data UG-1828
Rev. PrA | Page 73 of 253
Table 25. User Provided Receiver Timing Parameters
Timing Parameter Min Value Max Value Comment
enableRiseToAnalogOnDelay
(tRxEnaRise2AnaOn)
Max of the following values: 0
tPowerUpPSM (for the maximum
intended power savings mode)
91 ms/scaleFactor Default = min
enableRiseToOnDelay
(tRxEnaRise2On)
enableRiseToAnalogOnDelay +
enableSetupDelay
91 ms/scaleFactor Default = min
Not needed if not controlling LNA power
enableGuardDelay
(tRxGT)
(not used currently)
0 91 ms/scaleFactor Default = min
Can increase if performance degradation
is observed and the channel is receiving
for some time before the start of the
actual frame
(Forced to be 0 currently by ADRV9001)
enableFallToOffDelay
(tRxEnaFall2Off)
(Not Used Currently)
0 91 ms/scaleFactor Default = min
Can increase if performance degradation
is observed and the channel is receiving
for some time after the end of the actual
frame. Can still be used if not controlling
LNA power down.
(Forced to be 0 currently by ADRV9001)
enableHoldDelay
(tRxEnaHold)
enableFallToOffDelay enableFallToOffDelay +
propagationDelay
Default = max
Can decrease if not all data received on
air needs to be sent over interface.
When ADRV9001 calculates the default values, it utilizes the transmit/receive propagation delay internally characterized for different
profiles. User should measure the propagation delay in their application to help determine all the required timing parameters. During the
measurement, user could set all the timing parameters to be the default values for simplification and also it is important to use the same
profile and configurations as the actual application being deployed.
After calculating all the timing parameters required by ADRV9001, user could configure them through TES as shown in Figure 68.
24159-069
Figure 68. Timing Parameters Configuration in TES
As shown in Figure 68, only relevant channels are enabled for timing parameters configuration. User should enter all the values in ns.
The propagation delay is a helper parameter, which is not needed by ADRV9001. It helps to set other timing parameters ADRV9001
requires.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 74 of 253
As aforementioned, API Command adi_adrv9001_Radio_ChannelEnablementDelays_Configure( ) can also be used to set the timing
parameters. As a summary, all the APIs provided for timing parameters are listed in Table 26. Refer to the API doxygen document for
more details.
Table 26. A List of Timing Parameters Related APIs
API Function Name Description
adi_adrv9001_arm_ChannelPowerSaving_Configure Configures the channel power saving settings for the specified channel.
adi_adrv9001_arm_ChannelPowerSaving_Inspect Inspects the channel power saving settings for the specified channel.
adi_adrv9001_Radio_ChannelEnablementDelays_Configure Configures channel enable delays for the specified channel.
adi_adrv9001_Radio_ChannelEnablementDelays_Inspect Inspects channel enable delays for the specified channel.
Preliminary Technical Data UG-1828
Rev. PrA | Page 75 of 253
CLOCK GENERATION AND MULTICHIP SYNCHRONIZATION
CLOCK GENERATION
In ADRV9001 all clocks for the converters and main digital are generated by CLKGEN. CLKGEN receives from two clocks, a high
performance (HP) clock PLL and a low power (LP) PLL. The high performance clock PLL has a programmable frequency range of
7.2 GHz to 8.8 GHz. The low power clock PLL can generate a programmable range of 3.3 GHz to 5 GHz frequency. CLKGEN also has
the clocks be divided and retimed with reset pulses from the clock PLLs.
CLK P LL AND
PHASE SYNC
7200 TO
8847.36MHz CLK GEN
TO MAIN
DIGITAL
/1,/2,/3,/4 /2 TO /31
/2 TO /31
/2 TO /31
LP CLK PLL AND
PHASE SYNC
3300 TO
5000MHz
24159-070
Figure 69. ADRV9001 Clock Generation
CONFIGURABLE
DECIMATORS
HP BBPLL
8.8G TO 7.2G
HP BBPLL
3.3G TO 5G
DESIRED
SAMPLE RATE
HP ADC
LP ADC
/4
/12
/8
/6
24159-071
Figure 70. CLKPLL Can Be Programmed to Provide Arbitrary Clock Speed
Low Power Clock PLL (LP CLKPLL)
By default, LP CLKPLL works at a fixed frequency at 4423.68 MHz. However, the user can set it to have a tuning operation range. The
operating frequency range of LP CLKPLL is from 3.3 GHz to 5 GHz. User only needs to provide their final sampling frequency at the
interface, and the final frequency of LP CLKPLL are determined internally. This is all done before the chip is programmed. A profile is
generated based on the user’s provided sampling frequency.
Note LP CLKPLL uses less power than HP CLKPLL but has worse performance in terms of jitter noise. User needs to take this trade-off
into consideration for their end application.
Table 27 lists the supported data sample rate with different standards. The LTE 40 MHz at 16-bit, this is not supported by the
LP CLKPLL.
Table 27. Sample Rate Supported By LP CLKPLL
Standard Sample Rate
DMR I/Q 2.40E + 04
TETRA 1.44E + 05
TETRA 2.88E + 05
LTE 1.5 1.92E + 06
LTE 3 3.84E + 06
LTE 5 7.68E + 06
LTE 10 1.54E + 07
LTE 15 2.30E + 07
LTE 20 3.07E + 07
LTE 40 @12 bits 6.14E + 07
UG-1828 Preliminary Technical Data
Rev. PrA | Page 76 of 253
Table 28. Supported Data Lane Rate By LP CLKPLL
Standard Serialization Factor Per Data Lane Data Lane Rate
DMR/P25 Direct Modulation 2 9.60E +03
P25 Direct Modulation 2 1.20E +04
FM Direct Modulation 16 1.28E +05
DMR I/Q 32 7.68E + 05
8 1.92E + 05
16 3.84E + 05
FM Direct Modulation 16 1.54E + 06
TETRA 32 4.61E + 06
8 1.15E + 06
16 2.30E + 06
TETRA 32 9.22E + 06
8 2.30E + 06
16 4.61E + 06
LTE 1.5 32 6.14E + 07
8 1.54E + 07
16 3.07E + 07
LTE 3 8 3.07E + 07
16 6.14E + 07
LTE 5 8 6.14E + 07
16 1.23E + 08
LTE 10 16 2.46E + 08
LTE 15 16 3.69E + 08
LTE 20 16 4.92E + 08
LTE 40 @12 bits 12 7.37E +08
MULTICHIP SYNCHRONIZATION
Systems with MIMO configuration, where multiple ADRV900x devices are used to implement multiple inputs and outputs channels,
require a common device clock (DEV_CLK) and synchronization signal (MCS).
Figure 71 illustrates the synchronization between multiple ADRV900x devices using a shared input pin, MCS. The MCS signal is
generated by the external clock chip (for example, AD9528) using device clock DEV_CLK and captured by each ADRV900x device using
negative or positive edge of DEV_CLK to meet setup and hold time with good margins. Each ADRV900x device uses this sampled MCS
to synchronize all internally generated clocks which make them aligned between all devices internal clocks.
To use MCS for clock synchronization, multiple MCS pulses are required to sequentially synchronize clock dividers inside ADRV900x
devices, 4 for analog clock divider synchronization, 2 for digital clock divider synchronization. Figure 72 illustrates MCS pulse sequence
for MCS synchronization. The MCS pulse width has be at least one device clock (DEV_CLK) cycle. The wait times between MCS pulses
are TBD.
After multiple ADRV900x devices are synchronized, it is possible to perform digital clock divider synchronization only, without
resynchronizing analog clock dividers, that is, after the initial four analog MCS pulses, all remaining MCS pulses go straight to the digital
with affecting the state of synchronization of analog circuitry.
Preliminary Technical Data UG-1828
Rev. PrA | Page 77 of 253
MCS
SAMPLING
CLK PLL
DEV_CLK MCS
MCS
SAMPLING
DIGITAL CLOCK MCS
DIGITAL CLOCK
RX L VDS CLO CK M CS
RX L VDS CLO CK
CLKGEN
DIVIDERS
MCS
SAMPLING
DIGITAL
MCS
SAMPLING
ANALOG
ADRV900x (2)
MCS
SAMPLING
CLK PLL
DEV_CLK
MCS_2
MCS_1
CLK_2
CLK_1
MCS
CLOCK GE NE RATION
CLOCK CHIP
MCS GENERATION
MCS
SAMPLING
DIGITAL CLOCK MCS
DIGITAL CLOCK
RX L VDS CLO CK M CS
RX L VDS CLO CK
CLKGEN
DIVIDERS
MCS
SAMPLING
DIGITAL
MCS
SAMPLING
ANALOG
ADRV900x (1)
24159-072
Figure 71. Block Diagram For Multichip Synchronization (MCS)
FIRST MCS
ANALOG
MCS
MCS
DEVI CE CLO CK
DIVIDER
SYNCHRONIZATION
SECO ND M CS
ANALOG
PL L REF E RE NCE
CLOCK DIV IDER
SYNCHRONIZATION
THIRD MCS
ANALOG
PLL STATE
MACHINE
SYNCHRONIZATION
FOURTH M CS
ANALOG
CLKGEN DI V IDER
SYNCHRONIZATION
FIRST MCS
DIGITAL
DIGITAL CLOCK
DIVIDER
SYNCHRONIZATION
SECO ND M CS
DIGITAL
RX DAT A
INTERFACE
SYNCHRONIZATION
24159-073
Figure 72. Illustration of MCS Pulse Sequence for MCS Synchronization
ADRV9001 COMMUNICATION WITH BBIC
ADRV9001 sleeps during MCS. BBIC is responsible to inform ARM before MCS operation and wake it afterwards.
The ARM must wait for MCS signals in the following situations:
• During system initialization: the ARM is not yet enabled and no action is required from the firmware.
• During and/or after initial calibration stage, MCS may be required due to changed datapath configuration: if required, the ARM
informs the BBIC what kind of MCS it needs, then sleep automatically and wait for an interrupt from the BBIC.
• Any time MCS is repeated: the BBIC must notify the ARM, which then sleeps and waits for interrupt.
At these times, sleep the ARM using wait for interrupt (WFI) to ensure it is not doing anything that MCS might interfere with. The ARM
always notifies the BBIC before it sleeps by sending one of the ARM ready for MCS signals.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 78 of 253
Device Profile
The device profile shall contain a uint8_t parameter called sysConfig.externalMcsSupported. Zero means only internal MCS is possible,
non-zero means internal and external MCS are both available for the ARM to request.
Request MCS from BBIC to ARM
This signal is raised by the BBIC when it needs to do an unscheduled MCS. It should not be raised at startup or when rerunning
initialization calibrations. It may only be raised when in standby or idle state. BBIC sends a mailbox command to ARM with opcode
CMD_MCS. If ARM is in standby or idle state, it acknowledges the mailbox command and proceeds to the next step, else it rejects the
mailbox command
Signal ARM Ready For MCS
This signal is given by the ARM if MCS is required after/during initialization calibrations, or if requested as above. Then the ARM
prepares for sleep (shuts down interrupt sources, puts watchdog on hold, and so forth). When the ARM is ready to sleep, it raises an
interrupt to the BBIC and executes WFI, which puts it to sleep.
Signal MCS Complete—Wake Up ARM
This signal is raised by the BBIC when MCS is complete, in order to generate an interrupt on the ARM, which wakes it. The BBIC sends
an interrupt to the ARM using CORE_SOFTWARE_INTERRUPT_REGISTERS_SW_INTERRUPT_4, meaning wake up.
The ARM resumes normal operation (reactivates interrupts and running processes).
Preliminary Technical Data UG-1828
Rev. PrA | Page 79 of 253
SYNTHESIZER CONFIGURATION AND LO OPERATION
The ADRV9001 family devices employ four phase-locked loop (PLL) synthesizers: clock, RF (×2), and auxiliary. Each PLL is based on a
fractional-N architecture and consists of a common block made up of a reference clock divider, phase frequency detector, charge pump,
loop filter, feedback divider, and digital control block, and either a 1 or 4 core voltage-controlled oscillator (VCO). The VCO has a
tuning range of 6.5 GHz to 13 GHz. Each PLL drives its own local oscillator (LO) generator: RF LOGEN, aux LOGEN, and CLKGEN.
The output of the LOGEN block is a divided version of the VCO frequency. No external components are required to cover the entire
frequency range of the device. The reference frequency for the PLL is scaled from the reference clock applied to the device. Figure 73
illustrates synthesizer interconnection and clock/LO distribution block diagram.
CLOCK
SYNTHESIZER
RF 1
SYNTHESIZER
RF 2
SYNTHESIZER
AUXILLARY
SYNTHESIZER
BB CLOCK
GENERATOR
RF LO1
GENERATOR
RF LO2
GENERATOR
AUX L O
GENERATOR
DIG IT AL, ADCs,
DACs, LVDS
TX1
RX2
RX1
TX2
CALIBRATION
CLK P LL
REF
CLK PLL1
REF
CLK PLL2
REF
REFCLK
GEN
REF CLK IN±
AUX PL L
REF
24159-074
Figure 73. Synthesizer Interconnection and Clock/LO Distribution Block Diagram
Each receiver channel can be used as an observation receiver (ORx) for transmitter channels as shown in Figure 74.
CLOCK
SYNTHESIZER
RF1
SYNTHESIZER
RF2
SYNTHESIZER
AUXILLARY
SYNTHESIZER
BB CLOCK
GENERATOR
RF LO1
GENERATOR
RF LO2
GENERATOR
AUX L O
GENERATOR
DIG IT AL, ADCs,
DACs, LVDS
TX1
RX2/ORX2
RX1/ORX1
TX2
CALIBRATION
CLK P LL
REF
CLK PLL1
REF
CLK PLL2
REF
REFCLK
GEN
REF CLK IN±
AUX PL L
REF
24159-075
Figure 74. Synthesizer Interconnection and Clock/LO Distribution Diagram (Receiver Channels Configured as Observation Receivers for Transmitter Channels)
CLOCK SYNTHESIZER
The clock synthesizer is used to generate all the clocking signals necessary to run the device. The synthesizer uses a single core VCO
block. The reference frequency for the clock PLL is scaled from the device clock by the reference clock generator. Reconfiguration of the
clock synthesizer is typically not necessary after initialization. The most direct approach to configuration is to follow the recommended
programming sequence and utilize provided API functions to set the clock synthesizer to the desired mode of operation. The clock
generation block of the clock synthesizer provides clock signals for the high speed digital clock, receiver ADC sample and interface
clocks, transmitter DAC sample and interface clocks, and LVDS interface clocks.
RF SYNTHESIZER
The device contains two RF PLLs. Each RF PLL uses the PLL block common to all synthesizers in the device and employ a 4 core VCO
block which provides a 6 dB phase noise improvement over the single core VCO. As with the other synthesizers in the device, the
reference for RF PLL 1 and RF PLL 2 are sourced from the reference generation block of the device. The RF PLLs are also fractional-N
architectures with a programmable modulus. The default modulus of 8,388,473 is programmed to provide an exact frequency on at least
a 5 kHz raster using certain reference clocks which are integer multiples of 38.40 Hz. The RF LO frequency is derived by dividing down
the VCO output in the LOGEN block. The tunable range of the RF LO is 30 MHz to 6000 MHz.
A switching network is implemented in the device to provide flexibility in LO assignment for the two RF LO sources. The switching
network is shown in Figure 75 and Figure 76.
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RX2
RX2 MUX
RX1
RX1 MUX
TX2
TX2 MUX
TX1
EXT
LO1 RF
LO1
TX1 MUX
RFLO1 M UX
EXT
LO2
RF
LO2
RFLO2 M UX
24159-076
Figure 75. LO Switching Network
RX2/ORX2
RX2 MUX
RX1/ORX1
RX1 MUX
TX2
TX2 MUX
TX1
EXT
LO1 RF
LO1
TX1 MUX
RFLO1 M UX
EXT
LO2
RF
LO2
RFLO2 M UX
AUX
LO
24159-077
Figure 76. LO Switching Network (Receiver Channels Configured as Observation Receivers for Transmitter Channels)
Note depending on the application, user has the ability to select best phase noise or best power saving options for better optimization.
The option, best phase noise, only works for LO frequency under 1 GHz.
AUXILIARY SYNTHESIZER
An auxiliary synthesizer is integrated to generate the signals necessary to calibrate the device. This synthesizer utilizes a single core VCO.
The reference frequency for the auxiliary synthesizer is scaled from the device clock via the reference clock generation system. The
output signal is connected to a switching network and injected into the various circuits to calibrate filter bandwidth corners, or into the
receive signal chain as an offset LO. Calibrations are executed during the initialization sequence at startup. There should be no signal
present at the receiver/observation receiver input during tone calibration time. Calibrations are fully autonomous. During the
calibration, the auxiliary synthesizer is controlled solely by the internal ARM microprocessor and does not require any user interactions.
The auxiliary LO signal is also available as an LO source for the observation receiver mixers.
EXTERNAL LO
The device is provisioned with two external LO ports. These ports are available as a pair of balls and are configured to be input for
external LO signals.
External LO can receive a signal between 60 MHz and 12 GHz through a matched differential impedance of 100Ω and delivers a
programmable signal between 30 MHz and 6 GHz as the LO for transmitters and receivers in the device. Amplitude must be maintained
between ±6 dBm. For more information refer to External LO Port Impedance Matching Network paragraph.
Singled-ended external LO in is also supported. The matched singled-ended impedance is 50 Ω. On-chip duty cycle correction circuit
can correct limited range of external LO duty cycle error if it is not 50%.
Single-Ended vs. Differential External LO
Note the current eval board only supports differential external LO, however user is not restricted to use single-ended LO in their end
system. User must change clocks.ext1LoType and clocks.ext2LoType from 0 to 1. This can be found in the Enum below
enum adi_adrv9001_ExtLoType { ADI_ADRV9001_EXT_LO_DIFFERENTIAL = 0,
ADI_ADRV9001_EXT_LO_SINGLE_ENDED = 1}
Note only frequencies from 500 MHz to 1000 MHz are supported for single-ended mode. Figure 77 shows the RF LO generation
diagram.
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DIFFERENTIAL
EXT LO
/1, /2n,
n = 1,2,3,...255
/2 RF LO
SINGLE-ENDED
EXT LO
EXT LO IN±
/1, /2n,
n = 1,2,3,...255
RF
VCO
24159-078
Figure 77. RF LO Generation Diagram
RF PLL Loop Filter Recommendations
For optimal phase noise and EVM performance, a lookup table of RF PLL loop filter bandwidth settings is implemented in ADRV9001
firmware. ADRV9001 automatically selects best RF PLL loop filter configuration based on LO frequency. Alternatively, user can program
its own RF PLL loop filter bandwidth following instruction outlined in Loop Filter Configuration paragraph.
PLL Phase Noise
The Figure 78 shows the typical PLL phase noise contributors. For low offset frequencies reference clock dominates the phase noise, and
for high offset frequencies, VCO noise dominates the phase noise. User can optimize the phase noise by:
• Provide better reference clock source
• Provide higher reference clock frequency (PFD)
• Adjust loop filter bandwidth to trade-off between close-in band and far-out band noise
When changing the loop filter bandwidth, typically consideration is the wider the bandwidth, the better close-in band noise, but the
worse the far-out band noise. User should trade-off between the two to find the optimal setting for the specific application.
F
LOOP
INPUT
REFERENCE
PHASE DETECTOR
AND CHARGE P UM P
AMPLITUDE
NOISE
VCO
–20dB/dec
SPUR
LOG F
OFFSET
PHASE NOISE
FREQUENCY OFFSET
INPUT REFERENCE NOI S E
PHASE DE TECTOR AND
CHARGE P UM P NOI S E
VCO NOISE
AMPLITUDE NOISE
OVERALL PLL NOISE
24159-079
Figure 78. PLL Phase Noise Contributors
Following is an example that PLL phase noise is highly dependent on the PFD frequency (REF_CLK). With a higher PFD frequency, a
better phase noise can be achieved.
UG-1828 Preliminary Technical Data
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24159-080
Figure 79. Effect of PFD (REF_CLK) Frequency on PLL Phase Noise
Another example is shown below where a trade-off can be made between close-in phase noise and far-end phase noise by adjusting the
loop filter bandwidth. As stated previously the higher the loop filter bandwidth, the better the close-in noise but with the scarification of
the far-end noise, and vice versa.
24159-081
Figure 80. Effect of Loop Filter Bandwidth on PLL Phase Noise
API OPERATION
Data Structure and Enums
Table 29. Data Structures Related to LO Operation
Data Structure Description
adi_adrv9001_Device_t Data structure to hold ADRV9001 device instance settings.
adi_adrv9001_Carrier_t Carrier structure for carrier configuration
adi_common_Port_e Enumeration of port types.
adi_common_ChannelNumber_e Enumeration of channel numbers.
adrv9001_PllCalMode_e Enum of PLL calibration mode.
adi_adrv9001_LoGenOptimization_e Enum of LO Optimization
adi_adrv9001_PllCalibration_e Enum for PLL calibration mode
adi_adrv9001_PllName_e Enum of PLL selections.
adi_adrv9001_PllLoopFilterCfg_t Data structure to hold Synthesizer PLL Loop filter settings
Preliminary Technical Data UG-1828
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API Commands
More detailed information including parameters, return values is provided in the doxygen document supplied with SDK package.
Table 30. API Commands Related with LO Configuration Settings
API Function Description
adi_adrv9001_Channel_EnableRf() Enable or disable RF channel
adi_adrv9001_Radio_PllStatus_Get() Checks if the PLLs are locked.
adi_adrv9001_Radio_PllLoopFilter_Set() Configures the loop filter for the specified PLL.
adi_adrv9001_Radio_PllLoopFilter_Get() Gets the loop filter configuration for the specified PLL.
adi_adrv9001_Radio_Carrier_Configure() Sets the carrier configuration for the given channel.
adi_adrv9001_Radio_Carrier_Inspect() Inspects carrier configuration
LO Change Procedure
To set the LO frequency to a particular channel, user needs to
1. Verify the internal ARM microprocessor has been initialized
2. If device is on RF_ENABLED state, user needs to set it to PRIMED state by calling adi_adrv9001_EnableRf()
3. Once device is in PRIMED state, Set the LO frequency by calling adi_adrv9001_Radio_Carrier_Configure(). User can specify a
Normal or a Fast calibration by setting pllCalibration argument.
4. Lastly set turn the device to RF_ENABLED state by calling adi_adrv9001_EnableRf()
User does not have specific control over CLK_PLL. Configuration of CLK_PLL is done by calling initAnalog function. initAnalog
function programs the CLK_PLL based on information set in the device profile. This is done at initialization time
POWER_UP
STANDBY
STANDBY
STANDBY
UNPRIME
PRIME
AUTO
CALIBRATE FAL L
CALIBRATE
ADDITIONAL
CALIBRATIONS
PRIMED
MONITORING
MONITOR
DISABLE
MONITOR
ENABLE
RF
ENABLED
RF E NABLE
RF DI S ABLE
CALIBRATED
24159-082
Figure 81. Device State Machine
Loop Filter Configuration
Currently the loop filter is hard-coded in adrv9001_RadioCtrlInit. This function is called at initialization time. However user does have
access to a public API, adi_adrv9001_Radio_PllLoopFilter_Set to manually change the loop filter settings. This function needs to be
called at PRIMED state, similar to setting the LO frequency.
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FREQUENCY HOPPING
Before delving into the frequency hopping feature details, user is recommended to read the Synthesizer Configuration and LO Operation
section and the Timing Parameters Control section of this document.
Frequency hopping allows the user to quickly switch radio signals among different frequency channels. For ADRV9001, this is achieved
by retuning the PLL before switching to the frequency channel. There are two local oscillators (LO) inside ADRV9001, therefore we can
“ping-pong” between the two LOs. This means while one LO is being used for on-air signal transmitting for one frequency, the other LO
can be utilized to prepare for the next frequency. This makes very fast frequency hopping possible.
This document explains the key parameters of frequency hopping, namely HOP signal and Tx and Rx Setup signals. They play a key role
in understanding more complicated timing configurations. Then a brief explanation of how frequency hopping is achieved internally
inside ADRV9001 is provided. User does not need interaction with the internal process. Then the frequency table concept is introduced
and the procedure of its configuration is also explained.
Next, the modes of operation for frequency hopping are also shown. These proposed modes of operation are based on the allowed time
for the PLLs to retune. The number of LOs, number of allowed channels, and calibration modes are different depending on the different
modes of operation.
Besides the mode of operation, the user also needs to specify other parameters to ADRV9001. This document lists the parameters the
user needs to provide to use frequency hopping properly. The next section Configuration and User Information is shown for the
necessary parameters. This also includes timing parameters and the user should refer to Timing Parameters Control section for detailed
parameter description.
Next, it describes the initial calibration and how it works with frequency hopping. Initial calibration is done in the chip initialization step,
not at the hop time. This section also lists the necessary parameters needed for calibration provided by the user.
Finally, an example is presented for the frequency hopping operation. This is presented based on the key signals: Hop and Tx and Rx
Setups. At each rising and falling edge of these key signals, a description of the hardware and software component is shown. This should
help the user understand how the chip works internally as well as with the BBIC at each step.
This document is still under development since not all features have been implemented. API details are updated as the design and
implementation are finalized.
KEY SIGNALS
The frequency hopping framework involves reconfiguring the analog and digital components to hop to different frequencies during the
TDD operation.
Figure 82 shows a typical frequency hopping timing diagram. In this diagram, we have the HOP signal and the Tx and Rx setup signals,
frequency select, and the frames on the air.
FRAM E NO 7
CHANNEL
FREQUENCY TX
F4
LO LO2
6RX
F3
LO1
5TX
F2
LO2
4RX
F1
LO1
3TX
F4
LO2
2RX
F3
LO1
1TX
F2
LO2
0RX
F1
LO1
–
–
–
–
–
–
FREQUENCY
SELECT (MSG)
HOP 0 6 754321
Tx SE TUP
Rx SET UP
BBIC
BBIC
BBIC
BBIC
24159-083
F1
LO1 F4
LO2
F3
LO1
F2
LO2
F1
LO1
F4
LO2
F3
LO1
F2
LO2
Figure 82. Typical Timing Diagram for Frequency Hopping
Tx and Rx setup signals, essentially are the Tx and Rx enable signals coming from the BBIC. They are the DGPIO pins of Tx_Enable and
Rx_Enable. In frequency hopping, they are repurposed as signals to indicate which channel (Tx or Rx) the upcoming hop frame is going
to operate on. The HOP signal rising or falling edge marks the actual frame (indicated in the diagram in the green box). Rx and Tx setup
signals, on the other hand, do not. In this example, Rx setup rising edge (indicated in the diagram in the red box) simply indicates that
the next hop frame operates on the Rx.
Note if operating in TDD 2T2R non-diversity mode, frequency hopping is supported but needs two HOP signals for the two channels. If
operating in 1T1R or 2T2R diversity mode, then one HOP pin is supported.
Preliminary Technical Data UG-1828
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The frequency information comes from the BBIC. Before each Tx or Rx setup, we expect to get some message (this may come in various
forms which is discussed later in the document) which indicates a frequency. Prior to each hop, the channel (Tx or Rx) information and
the frequency information are obtained.
The table in blue indicates the frames on the air. This shows one frame delay, which is required for all the setup information (frequency
and channel). This gives the time for PLL to be retuned and channel to be set up before bringing the data frame on the air.
The hop frame consists of the transition time and dwell time. Transition time (shown as a black box) is the allowed setup time before the
actual frame starts. Dwell time (actual Tx or Rx frame) is the time at which the actual frame starts and operates in that specific frequency.
In this example, each frame works on a different frequency from F1 to F4, and two LOs are being used.
FRAMEWORK
This section briefly describes the interaction of different hardware components both internally and externally with BBIC to achieve
frequency hopping, specifically ADRV9001 ARM, Stream processor, DMA, and BBIC. Note DMA is an internal component for quick
memory access. DMA and stream processor are used internally and do not require user interaction. We mention these only for a more
complete description of how different components work together for ADRV9001. From the user point of view, everything should work
seamlessly.
ARM accepts the communication from the BBIC. During setup time, ARM is going to generate DMA tables to program the PLL and at
hop time these tables can be triggered by stream processor to program the PLL.
Stream processor responds to the signals (Hop signal, Tx setup, and Rx setup) in a deterministic manner so that when a hop signal comes
in from BBIC, the analog and digital components can be properly set up.
DMA allows the ARM to update it before each hop frame so that it can configure the PLL to a new frequency. At hop time, the stream
processor enables the DMA.
CHANNEL USE CASES
Depending on the user’s application, the channel can be configured in two ways, TRX and TX only and Rx only. If the propagation delay
is less than the allowed hop duration length, then the user can choose either mode. However, for the case that propagation delay is longer
than the hop duration, only Tx only or Rx only can be supported. The propagation delay parameter, in this case, needs to be set up
properly to guarantee that the data is ready at the antenna at the right time.
Table 31. Channel Use Cases and Timing Considerations
Channel Use Case Timing Considerations
TRX Supports profiles where propagation delay and setup time are within the allowed hop duration of the frequency
hopping mode.
Does not support profiles where the propagation delay is greater than the allowed hop duration.
TX Only and RX
only
Supports profiles where propagation delay and setup time are within the allowed hop duration of the frequency
hopping mode.
Supports profiles where the propagation delay is greater than the allowed hop duration.
FREQUENCY TABLE INDEXING
The user has the option of providing a frequency hopping table before the system bootup. Besides the frequency table, there are other
ways to provide frequency information, which is discussed later in this document. If the user wants to provide a frequency table, we have
three selection modes for indexing a frequency table: PIN, API, and AUTO modes.
In PIN mode, DGPIO pins can be utilized by user to indicate a frequency index. 6 DGPIO pins can be used to indicate a max of 64
frequencies in the frequency table and 3 DGPIO pins can be used to indicate a max of 8 gain levels. Note the frequencies do not need to
be in order.
API mode works similarly, instead of DGPIO pins, two 8-bit registers can be used to provide a frequency and gain index. The user just
needs to provide the frequency and gain index and API call are used to write the frequency and gain values in the hardware.
UG-1828 Preliminary Technical Data
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Automatic mode simply auto-increments in the frequency table.
Table 32. Frequency and Gain Index Selection Modes
Selection mode Notes
PIN Uses DGPIO pins for the user to provide a frequency and gain index.
The number of frequencies or gain levels which can be indexed are restricted to the number of available DGPIOs.
6 DGPIOs are required to index a maximum of 64 operating frequencies.
3 DGPIOs would be required to index, for example, 8 gain levels.
API The user is asked to provide frequency and gain index and they are loaded via API
AUTO Autoincrements through a frequency hopping table.
When the end has been reached, it loops back to start.
MODES OF OPERATION
The following are the four proposed modes of operation that are defined to support different timing, performance, and application
requirements. The main difference between the four modes is the transition time and dwell time allowed.
Table 33. Frequency Hopping Modes of Operation
FH Mode
Transition
Time
Dwell
Time PLLs
PLL Retune
Time
PLL Cal
Mode
Gain
Selection
Frequency
Selection Channel
Very Fast
FH (VFFH)
Short (< 10 μs) Short (<
10 μs)
2 LO
Mux
2 transitions +
1 dwell
Coarse Cal
mode (20us
lock)
FIXED Table based (PIN,
AUTO, API)
Single (1T1R)
Fast FH
(FFH)
Short (< 10 μs) Long (>
500 μs)
2 LO
Mux
1 transitions +
sub 1 dwell
Fine Cal
mode (250us
lock)
API/PIN Table based (PIN,
AUTO, API)
or on-the-fly (High
priority mailbox)
Single (1T1R)
Normal FH
(NFH)
Medium (60 μs
- ~250 μs)
Long (>
500 μs)
1 LO Sub 1
transitions
Coarse Cal
mode (20us
lock)
API/PIN Table based (PIN,
AUTO, API)
or on-the-fly
(High priority
mailbox)
Single/Dual
(1T1R or 2T2R)
Slow FH
(SFH)
Long
(> ~250 μs)
Long (>
500 μs)
1 LO Sub 1
transitions
Fine Cal
mode (250us
lock)
API/PIN Table based (PIN,
AUTO, API)
or on-the-fly
(High priority
mailbox)
Single/Dual
(1T1R or 2T2R)
The number of LOs is shown in these modes. For VFFH and FFH modes 2 LOs are required and for NFH and SFH only 1 LO is
required. Depending on the time allowed in each mode, PLL cal mode can be either in coarse cal mode or fine cal mode. In the 2-LO
modes, which are VFFH and FFH, the PLL can be retuned within 2 transitions + 1 dwell time. In contrast in the 1-LO modes, the PLL
must be retuned within 1 transition time. For this reason, in NFH mode, we use coarse cal mode for PLL and not fine cal mode.
The gain selection must be in fixed mode in the VFFH mode and does not change during the transition time. However, user can provide
a table of frequencies and their associated gain values before setup time and the information can be utilized so that each frequency can
have a specific gain value associated with it.
Frequency selection can be in the format of a frequency table or “on-the-fly”.
The frequency table is loaded by BBIC to ARM memory, there are up to 64 frequencies in the table. This allows ARM to precompute the
DMA tables, and at hop time the frequency and any configuration associated with it is loaded.
On-the-fly means that the user does not need to provide the frequency table prior to setup time. Instead, the user can provide a new
frequency in Hz before the next hop frame. ARM obtains the new frequency and generates a new DMA table and get ready. This,
however, is not supported in the VFFH mode where there is simply not enough time to do so.
Note, the mode of operation for frequency hopping is set during the boot-up time, currently, we do not allow changing of the mode of
operation in the operation time.
Note also, PLL retune time depends on the reference clock frequency and it is not absolute.
Preliminary Technical Data UG-1828
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CONFIGURATION AND USER INFORMATION
We ask the user to provide the following information to ADRV9001 for frequency hopping.
• Mode of Operation
• Channel Mask for Hop 1
• Channel Select Mode
• Frequency Select Mode
• Gain Select Mode
The following parameters are not implemented yet, only an indication of what is needed.
Table 34. Parameters for Frequency Hopping Configuration
Parameter Notes
Mode Very fast, fast,
normal, slow.
Indicates to software what mode to prepare for.
Channel mask
Hop 1
[3:0] = TX2, TX1,
RX2, RX1
Indicates which channels are operating in FH mode on the hop 1 pin.
1T1R or 2T2R diversity can be supported using one hop pin.
Channel select
mode
PIN or API Indicates how the user selects an upcoming channel, typically PIN
Frequency
select mode
PIN, API,
HIGH-PRIORITY
MAILBOX,
AUTO
Indicates how the user selects an upcoming frequency. Either by PIN/SPI indicating a table index,
or high priority mailbox indicating frequency. AUTO means auto-increment through the table.
Gain select
mode
PIN, API,
HIGH PRIORITY
MAILBOX
Indicates how the user selects gain for the next operating frequency.
Timing Parameters
In the case of Tx only or Rx only mode, there is a possibility of propagation delay longer than the hop frame. For Tx, ensure that the data
is on the antenna at the right time. Similarly, for Rx we need to make sure that receiving data should be waited for the right amount of
time so that at the interface there is no loss of data. Therefore, the following timing parameters need to be properly set up to guarantee
the data frames at Tx and Rx are properly set up at the right time.
Details of timing parameters are explained in the Timing Parameters Control section of this document.
Frequency Hopping Table
User has the option of using a frequency hopping table. If it is used, the parameters in this table need to be provided.
The hop frequency list contains the list of operating frequencies to be hopped over.
The band index list provides a mapping of each frequency in the hop frequency list to a frequency region. This is used to help firmware
load the appropriate calibration coefficients for each hop frame. This is discussed more in the next section.
The following parameters are not implemented yet, and serve only as an indication of what is forthcoming. The table is updated as
parameters become available.
Table 35. Parameters for Frequency Hopping Tables
Parameter Notes
Number of hop
frequencies
0 to 64 The number of hop frequencies. 0 if no table is used.
Hop frequency list List of hop frequencies. Ignored if the number of hop frequencies is 0.
Band index list List of frequency to band/region
mapping
List to map frequencies in hop frequency list to specific
bands/regions.
CALIBRATION
Initial Calibration
Calibration is done at the initialization stage rather than the hop stage. During initialization, utilize the frequency table to do the
calibration. Calibration results or coefficients are saved in ARM memory and reloaded later at hop time.
UG-1828 Preliminary Technical Data
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BBIC L OADS
DEVICE PROFILE
FH DATA
ARM IMAGE ...
INI T RADI O
SWITCH TO
NEXT FREQUENCY
ID FREQUENCY
INIT CAL FREQ TABLE
65.4GHz
54.2GHz
43.3GHz
32.5GHz
21.2GHz
10.5GHz
RUN INI T CAL .
ALGORITHMS
STORE RESULTS.
MORE
FRE Q UE NCY TO
CALIBRATE?
INIT
DONE
Y
N
ID ITEMS
FH CONFIG
3FREQUENCY SELECT MODE
2CHANNEL SE LECT MO DE
1FH M ODE
ID ITEMS
FH INIT CAL INFORMATION
3NUMBER O F G AINS
2INIT CAL FREQUENCY LIST
1NUM I NIT CAL F RE QUECI E S
ID ITEMS
FH HO P TABL E S
3FREQUENCY RANGE L IST
2FREQUENCY HOP L IST
1NUM HO P FREQ UE CIES
24159-084
Figure 83. Initialization and Calibration for Frequency Hopping
Frequency Region
During characterization of the PLL, frequency regions are determined. The calibration algorithms determine the frequency region that
the specific algorithm will be done in.
When user provides the frequency table, which indicates the frequencies are going to be used in hopping, the firmware maps those
frequencies into frequency regions. “Initial calibration frequency list” in this table is the list of the center frequency for each region. For
example, it is possible the user wants to hop in 20 different frequencies but this might only cover 5 regions. Therefore, calibration can be
done for just those 5 regions. This relates to the band index in the previous section. At hop time when there is a new frequency, this
frequency is mapped into a region, then the calibration coefficients are loaded for that region.
In the case the users do not want to/cannot provide a frequency table, they do however need to provide the minimum and maximum
frequency for frequency hopping operation. Once the min and max frequencies are provided, the frequency regions are determined
internally and calibration is done for those regions. However, this is not ideal for the reason that the number of regions might be large
and calibration therefore might take a longer time.
Initial Calibration Frequency Information (API)
Following parameters are not implemented yet, only an indication of what is forthcoming. The table is updated as parameters become
available.
Table 36. Parameters for Initialization and Calibration
Parameter Notes
Number of
bands/regions
0 to 64 Number of initial calibration frequencies.
Initial calibration
frequency list
List of frequencies to be used for
initial calibrations.
Depending on characterization results. Could be, for example, centre
frequency of each frequency band used.
Number of gains
Number of gains levels to calibrate over.
This may or may not be needed if we have gain range?
TX gain range Range of MIN and MAX gain levels
which TX operates on
Gain levels specified in dB.
RX gain range Range of MIN and MAX gain levels
which RX operates on
Gain levels specified in dB.
Preliminary Technical Data UG-1828
Rev. PrA | Page 89 of 253
HOP TIME EXAMPLE
FRAM E NO 7
CHANNEL
FREQUENCY TX
F4
LO LO2
6RX
F3
LO1
5TX
F2
LO2
4RX
F1
LO1
3TX
F4
LO2
2RX
F3
LO1
1TX
F2
LO2
0RX
F1
LO1
–
–
–
–
–
–
FREQUENCY
SELECT (MSG)
HOP 0 6 754321
Tx S ETUP
RET UNE P LL
Rx SET UP
BBIC
BBIC
BBIC
BBIC
F1 F4F3F2
F1
F4F3F2
PL L READY
24159-085
Figure 84. Frequency Hopping (Fast Frequency Hopping Mode) Timing Diagram
1. This example shows a frequency diagram for a 2-LO case for the Fast frequency hopping mode. The hop is occurring on Tx and Rx
frames. We will demonstrate how ARM and stream processor will operate in each time. In this example, there is a one-frame delay
between the HOP signal and the frame on the air. There are two sets of registers A and B for the algorithm coefficients. These
register sets work similarly as RF LO1 and RF LO2 so that one can be used while the other one is being prepared.
2. First, the Rx setup is sent from BBIC to indicate to ARM that the upcoming frame (frame #0) will be operating on Rx. At this point,
the frequency information has been indicated by the BBIC through API. ARM gets this frequency information (F1) and prepares
DMA to update RF LO1 to F1. ARM also prepares algorithm coefficients generated in initialization time for frequency F1. At this
point, the coefficients are not applied, they are simply being prepared. Streams take no action.
3. Next, at the first rising edge of the HOP signal, the main stream processor triggers DMA to tune RF LO1 to F1. ARM is interrupted
by the stream and prepares the DMA to power up RF LO1 for the next frame. ARM writes Rx algorithm coefficients to, in this case,
B registers for the next hop frame.
4. At the falling edge of the Rx setup signal, the main stream processor takes no action, ARM takes no action, Rx stream processor
reads the upcoming frame is Rx and starts to power up the digital and analog components for Rx.
5. The rising edge of the Tx setup signal indicates the upcoming frame (frame #1) will operate on Tx. ARM gets the next frequency and
gain information (F2) and prepares DMA to update RF LO2 to F2. ARM prepares algorithm coefficients for frequency F2. Streams
take no action.
6. At HOP signal falling edge, the main stream processor triggers DMA to tune RF LO2 to F2. DMA powers up the RF LO1. It also
toggles the HOP register to switch to B registers. ARM is interrupted by the stream to update DMA so that RF LO2 is powered up
next frame and LO1 is powered down. RX stream processor reads that RX is active in this frame. The falling edge of Rx has already
powered up the digital and analog components. At this point, the stream processor just powers up the Rx LO mux buffer and
unmasks the ADC output. ARM writes Tx algorithm coefficients to the next A registers for the next hop frame (frame #1).
7. At the falling edge of the Tx setup signal, the main stream processor takes no action. ARM takes no action. Tx stream processor
reads that the next frame is Tx and starts powering up digital and analog components.
8. Finally, at the next rising edge of the HOP signal (start of frame#2), the main stream processor triggers DMA to power down RF
LO1, tune RF LO1 to F3, and DMA to power up the RF LO2. ARM is interrupted by stream to update DMA so that LO1 is powered
up next frame and LO2 is powered down. Tx stream processor reads that Tx is active in this frame. The falling edge of the Tx setup
has already powered up the digital and analog components. At this point, the stream processor just powers up the Tx LO mux buffer
and unmasks the DAC output. ARM saves updated Rx algorithm coefficients from previous B registers (for just completed hop
frame, frame #0). ARM writes Rx algorithm coefficients to the next B registers for the next hop frame (frame #2).
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TRANSMITTER SIGNAL CHAIN
The ADRV9001 device integrates dual direct-conversion (Zero-IF) transmitters. It supports both time division duplexing (TDD) and
frequency division duplexing (FDD) modes and is capable of transmitting both narrowband (NB) and wideband (WB) signals. It
supports a wide range of applications such as DMR, P25 and TETRA as examples of NB standards and LTE as an example of WB
standards.
In general, each transmitter consists of an independent I and Q signal path with separate digital filters, DACs, analog Tx low pass filters
(LPF) and upconversion mixers. After mixers, an analog attenuator is employed to control the Tx output signal power.
Data from baseband processor is input to the Tx signal path via synchronous serial interface (SSI). The serial data is converted to parallel
format through the deframer and then the data is processed by interpolation filters. There are several signal conditioning functions, such
as Tx gain control, power amplifier protection, power amplifier digital pre-distortion (DPD), Tx quadrature error correction (QEC) and
Tx LO leakage (LOL) handling, before the data is passed on to the DACs. The DAC outputs are filtered by LPF, upconverted to RF via
the mixer and attenuated through the analog attenuator to prepare for RF transmission. The ADRV9001 device also supports FM/FSK
modulation for some NB applications which will be discussed later.
The high level block diagram of the Tx signal path is shown in Figure 85.
DAC
LPF
MIXER
ANALOG
ATTENUATOR
TX1/2
MIXER DAC
LPF
90°
0°
INTERPOLATION
TX GAIN CONTROL
PA PROTECTION
DPD
TX LOL
TX QEC
FM MODUTATION
SERIAL
INTERFACE
TX1/2_IDATA_IN±
TX1/2_DCLK_OUT±
TX1/2_STROBE±
TX1/2_CLK_IN±
TX1/2_QDATA_IN±
24159-086
Figure 85. High Level Block Diagram of TX Signal Chain
DATA INTERFACE
The Tx data interface supports several different interface rates and configurations. It has a total of 5 differential pairs (i.e. a total of 10
wires). The interface is operated single-ended in CMOS synchronous serial interface (CSSI) mode and differential in LVDS synchronous
serial interface (LSSI) mode.
The CSSI interface has one or four data wires as well as one strobe, input and output clock wire. Depending on the number of data wires,
the data interface is referred to as CSSI one-lane or CSSI four-lane, respectively. The output clock is passed to the baseband processor to
generate the data, strobe and clock signals.
In one-lane operation, the I- and Q-symbols are interleaved and sequentially transmitted over the CSSI interface. Each symbol can
consist of 2, 8, or 16 bits. The four-lane interface only supports 16-bit symbols. They are separated into two 8-bit words for each I and Q
stream, and then sent over the 4 data wires of the CSSI four-lane interface.
For the LSSI interface there is a separate data lane for the I- and Q-data. There is also a mode where the I-data and Q-data can be
interleaved and transferred over a single data lane. The bit-width of the data symbols can be 12 or 16 bits. In addition to the data lanes,
the interface has a strobe, an input clock and an optional output clock signal. The output clock signal can be used by the baseband
processor to generate the above data, clock and strobe signals.
As mentioned earlier, the ADRV9001 supports many NB and WB standards. Depending on the selected standard and the specific symbol
rate chosen via the API profile, the interface clock rate can vary significantly. For the currently supported use cases the interface rate can
range from 9.6 kHz to 983.04 MHz. Please note that the CMOS SSI interface is a slow-speed interface and is not able to cover this entire
frequency range. Please refer to
Data Interface section in this User Guide for more information.
DATAPATH
The high level datapath is shown in Figure 86, which is composed of an analog front end (AFE) and a digital front end (DFE).
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INTERNAL
OBSERVATION
DAC
Tx1/Tx2
Tx1+,
Tx2+
Tx1+,
Tx2– DAC
90°
0°
INTERPOLATION
STAGE 2
INTERPOLATION
DFEAFE
INTERPOLATION
STAGE 1 PROGRAMMABLE
128 TAP FIR FILTER
NCO
SYMBOL
MAPPING/
INTERPOLATION DATA
PORT
TX1/2_DCLK_OUT±
PA
PROTECTION
TX
ATTENUATION
FREQUENCY
DEVIATION MAPPER
FOR DIRECT
LO MODULATION
RF PLL LOOPBACKLO
QUADRATURE
ERROR
CORRECTION
LO LEAKAGE
SUPPRESSION DIGITAL
PRE-DISTORTION
I/Q
FM/FSK
DIGITAL
UPCONVERTER
LPF
LPF
2
TX1/2_QDATA_IN±
2TX1/2_IDATA_IN±
2TX1/2_STROBE_IN±
2TX1/2_DCLK_IN±
2
24159-087
Figure 86. Tx Datapath Block Diagram
In the DFE subsystem, the SSI interface passes data to the Tx preprocessing blocks including a symbol mapping/interpolation and a 128-
tap programmable FIR filter (PFIR). The symbol mapping/interpolation is used to perform interpolation and/or symbol mapping
necessary for certain NB standards. Please note that if the it is configured as an interpolator, proper filtering of the interpolation images
will be ensured in the PFIR. The PFIR is followed by 2 interpolation stages through a flexible combination of interpolation filters. The
interpolation ratios and filters are controlled by the profiles. By design, the interpolation images are rejected by more than 110dB.
Between the 2 interpolation stages, there is an optional FM/FSK modulator named IQ FM/FSK and a digital upconverter (DUC) which
could both be bypassed. Finally, for IQ data, the signal is interpolated to the DAC sample rate.
As shown in Figure 86, the DFE subsystem also includes various signal conditioning algorithms, such as LO leakage (LOL) suppression
and quadrature error correction (QEC). Besides those, it also provides power amplifier protection and Tx attenuation control blocks.
The output of DFE will first go through the DAC in the AFE subsystem. The DAC standard clock rate can be programmed to be 184.32,
368.64, or 552.96 MHz, which is set by the profile. (Note other sample rates could also be supported when arbitrary sample rate is
employed.) Then, the DAC output is filtered by the LPF and input to the upconversion mixer.
As shown in Figure 86, the ADRV9001 device also supports another method of FM/FSK modulation named Direct FM/FSK modulation.
In this mode, the DUC, IQ FM/FSK, the interpolation stage 2, power amplifier protection and Tx attenuation blocks (digital part) are all
bypassed. RFPLL is utilized to generate a constant envelope phase-modulated signal by modulating the Sigma-Delta Modulator (SDM)
with the data stream. In Direct FM/FSK, both DAC and LPF can be powered down.
In the following subsections, major Tx functionalities will be discussed.
DIGITAL FRONT END
Programmable FIR Filter (PFIR)
The PFIR has 128 taps with 24-bit coefficients. There are 2 FIR filters, which are PFIR_I and PFIR_Q as shown in Figure 87. It can be
configured to operate in parallel, one for I data and one for Q data in digital IQ modulation applications such as LTE. It can also be
configured to use PFIR_I or PFIR_Q only or to operate both filters sequentially for FM/FSK applications. For WB applications, user
could optionally use PFIR as a channel compensation filter, while for NB applications, user could optionally use PFIR as a pulse-shaping
filter. Currently, PFIR is not enabled in the datapath and will be provided to user in the future.
TO NARROWBAND
INTERPOLATOR AFTER TX
PREPROCESSING
PFIR_Q
{I,Q} PFIR_I
I
I,Q
Q
I
24159-088
Figure 87. Programmable FIR Filters
Transmit Attenuation Control
Transmit Gain Table
The Tx attenuation block controls the Tx output power. A Tx gain table with 960 entries is loaded into the ADRV9001’s memory during
initialization. (Currently only the first 840 entries are used and the remaining 120 entries are reserved for future use.) Each entry equals a
0.05dB gain step. Therefore, there is a total gain range of 42dB. The total Tx attenuation is distributed into two portions, an analog
attenuation portion and a digital attenuation portion. In the analog attenuation, there is a digitally controlled step attenuator (DSA) with
64 unit steps on a linear scale. The gaps between the analog gain steps are interpolated by a 12-bit digital multiplier to 0.05dB steps. The
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maximum analog attenuation is 36 dB and the maximum digital attenuation is 6 dB. Note in direct FM/FSK mode, the maximum Tx
attenuation is 12 dB with 0.5 dB step size.
Table 37 shows the first 5 rows of the Tx gain table.
Table 37. Sample Rows from the Tx Gain Table
Tx
Attenuation
Index
Total Tx
Attenuation
(dB)
Analog
Attenuation
Control Word[5:0]
Analog
Attenuation
(dB)
Digital
Attenuation
(dB)
Digital
Attenuation
(Linear)
Digital
Attenuation
Control
Word[11:0]
0 0 0 0.00 0.00 1.00 4095
1 0.05 0 0.00 0.05 0.9943 4072
2 0.10 0 0.00 0.10 0.9886 4049
3 0.15 1 0.14 0.01 1.00 4090
4 0.20 1 0.14 0.06 0.9928 4066
… … … … … … …
As shown in Table 37, the 1st column is the Tx attenuation index. The 2nd column shows the total Tx attenuation in dB for the
corresponding index. Note the attenuation step size for adjacent index is 0.05dB. The 3rd column is the control word used to calculate
the analog gain shown in the 4th column. The equation used for this calculation is:
Analog Gain (dB) = 20 × log10(1 − Analog Attenuation Control Word/64)
The 5th and 6th column show the required digital attenuation in dB and linear domain respectively to achieve the total attenuation in the
2nd column. The last column stands for the digital attenuation control word which is used to calculate the linear digital gain in 6th
column based on the following algorithm:
If Digital Attenuation Control Word = 4095
Digital Attenuation = 4096/2^12
else
Digital Attenuation = Digital Attenuation Control Word/2^12
Note only the 3rd column and the 7th column (in grey) are actually stored in memory. Other columns shown in Table 37 are only for
explanation purpose.
The user is allowed to read and write the table through the following API command “adi_adrv9001_Tx_AttenuationTable_Read()” and
“adi_adrv9001_Tx_AttenuationTable_Write()”. Please refer to the doxygen document for more details about API functions.
Note the table content is defined by the data structure “adi_adrv9001_TxAttenTableRow_t” as the following:
typedef struct adi_adrv9001_TxAttenTableRow
{
uint16_t txAttenMult;
uint8_t txAttenHp;
uint8_t Reserve;
} adi_adrv9001_TxAttenTableRow_t
where “txAttenMult” denotes the “Digital Attenuation Control Word” (in the range of 0 to 4095) and the “txAttenHp” denotes the
“Analog Attenuation Control Word” (in the range of 0 to 63) as shown in Table 37.
Tx Attenuation Mode
There are 3 modes to control the Tx attenuation block, which are bypass mode, SPI mode and GPIO mode. The API command
“adi_adrv9001_Tx_AttenuationMode_Set()” is provided to user to set the Tx attenuation mode.
Besides that, another API “adi_adrv9001_Tx_Attenuation_Configure()” is provided to the user to set more configurations for Tx
attenuation block such as the Tx attenuation step size.
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Three Tx attenuation modes are provided as defined by the enum “adi_adrv9001_TxAttenuationControlMode_e”:
typedef enum adi_adrv9001_TxAttenuationControlMode
{
ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_BYPASS = 0,
ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_SPI = 1,
ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_PIN = 3,
} adi_adrv9001_TxAttenuationControlMode_e
BYPASS MODE
Bypass mode is selected when the Tx attenuation mode is set as
“ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_BYPASS”. In this mode, the Tx attenuation functionality is not used
which means 0dB total Tx attenuation.
SPI MODE
SPI mode is selected when the Tx attenuation mode is set as “ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_SPI”. In this
mode, the user could set the Tx attenuation value via the API command “adi_adrv9001_Tx_Attenuation_Set()”.
SPI mode consists of two options, the TDD ramp mode and the constant-step size mode. The TDD ramp mode was designed for power
ramping in TDD systems. Note it is not supported in the current release. The constant-step size mode allows to control an exact constant
gain step size to reach the targeted attenuation level.
TDD RAMP MODE
The TDD ramp mode was designed for use in TDD systems. The user could program an “On power” and “Off power” for the next time
slot. The ramp rate can be controlled via a step size (tdd_ramp_step_size) and wait duration (tdd_ramp_wait_duration) between steps.
The ramp up or down could be initiated through API commands. Note those user interactions are currently not supported but will be
provided in the future. A typical TDD ramp is depicted in Figure 88.
TDD_RAMP_STEP_SIZE
TDD SLOT
DESI RE D Tx
ATTENUATION
IN RAM P UP
DESI RE D Tx
ATTENUATION
IN RAM P DOW N
Tx ON POWER
FULL-SCALE OUTPUT POWER
Tx OUTPUT POWER
Tx OFF POWER
TDD_RAMP_WAIT_DURATION
ATTEN_RAMP_UP
ATTEN_RAMP_DOWN
24159-089
Figure 88. TDD Ramp Profile
Constant-Step Size Mode
In constant-step size mode, the Tx attenuation controller ramps to the new Tx attenuation value immediately after it is set through API
command. Again the slope can be controlled via a step size (const_step_mode_step_size) and wait duration
(const_step_mode_wait_duration) between steps. A typical output power transient for this mode is shown in Figure 89.
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CONST_STEP_MODE_STEP_SIZE
DESI RE D Tx
ATTENUATION
FULL-SCALE OUTPUT POWER
Tx OUTPUT POWER
CONST_STEP_MODE_WAIT_DURATION
TX_ATTENUATION<9:0>
24159-090
Figure 89. Constant Step Mode
GPIO MODE
Another method to control the Tx attenuation block is through GPIO mode. In this mode, two GPIO pins are used to increment or
decrement the current attenuation value. An API command “adi_adrv9001_Tx_Attenuation_PinControl_Configure()” is provided to
user to configure the GPIO pins and set the step size. A typical output power transient is shown in Figure 90.
TX_INCR_DECR_WORD
TX_INCR_GPIO
TX_DECR_GPIO
Tx OUTPUT POWER
24159-091
Figure 90. GPIO Incr/Decr Mode
Power Amplifier Protection
In the Tx signal chain, two power amplifier protection mechanisms are provided to protect the power amplifier from excessive peak or
average power excursions. Note these features are not fully supported in the current release.
Power Monitor
Power monitor is one of the power amplifier protection methods and it utilizes the Tx attenuation block to adjust the power by
continuously monitoring the output power of the Tx datapath.
Through API commands, the user can enable power amplifier protection and set configuration parameters such as average and peak
power thresholds. The average power is accumulated over a specified integration time and an error flag is asserted if it exceeds the
threshold. In addition, the instantaneous or peak power is detected and the error flag is asserted if a specified number of peaks is
exceeded. The power amplifier error flag can be read via an API command. The power delivered to the power amplifier is automatically
reduced if the error flag is asserted. In the scenario depicted in Figure 91, the error flag is asserted after two power peaks were detected.
The power amplifier power is automatically ramped down to max attenuation. Note that the average power did also exceed its threshold
but not for long enough.
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Tx OUTPUT POWER
PA_PROTECTION_RAMP_MAX_ATTENUATION
PA_PROTECTION_RAMP_STEP_SIZE
PA_PROTECTION_ERROR_FLAG
PA_PROTECTION_AVG_DUR PE AK THRES HOLD
AVERAG E THRES HOLD
PA_PROTECTION_RAMP_STEP_DURATION
TX_ATTENUATION
24159-092
Figure 91. Power Amplifier Monitor
Slew Rate Limiter (SRL)
The slew rate limiter is the other method for power amplifier protection. It essentially limits the rate of change of a waveform by
continuously monitoring the difference between the input and output of the block and limiting the amount the output that can change
during one cycle. As a result, sudden changes in the input will be applied to the output over several cycles or symbols. Through API
commands, the user can control this slew limit as a fraction of full-scale which can be varied from very strong slew limiting to no slew
limiting at all. For example, if the slew limit is set to 10% of full-scale, a full-scale step input to the step limiter results in a ramp which
spreads over the next 10 clock cycles. The basic block diagram of the implemented slew rate limiter is shown in Figure 92. As shown in
this figure, the output sample is looped back to subtract from the input sample to decide the slew rate. Based on the slew limit selection, a
proper scaling factor is applied to reduce the slew rate to the desired level.
SLEW LIMIT
(10, 20, 30, 50) % OF FUL L SCAL E
IN –OUT
24159-093
Figure 92. Basic Block Diagram of the Slew Rate Limiter
Tx QEC
In the analog circuitry of a direct-conversion transmitter, there are 3 major non-idealities which are gain variation between I and Q
datapath, phase imbalance (non-90 degree between LO driving I and Q mixers) and differences in the LPF such as group-delay
variations. Without properly correcting them, the output spectrum of the transmitter could be significantly degraded due to the
undesired images.
Tx QEC is designed to estimate and correct those non-idealities through initial and tracking calibrations. The initial calibration is
performed by generating a tone through the NCO and inserting it to the Tx datapath. Note this tone is visible at the Tx output therefore
user needs to ensure that antenna is isolated from Tx (power amplifier is off) during Tx initial calibration. Internally in the device, the
output from the Tx up-converter is looped to the observation Rx (ORx) through internal loopback (ILB) path. The ORx output and the
transmitted tone are utilized to estimate the mismatches. Tables are generated to record the initial calibration results, which could be
further refined through tracking calibrations on-the-fly. During signal transmission, the mismatch estimations are applied in the Tx
datapath so that the non-idealities could be compensated. For more detailed information, please refer to the
Transmitter/Receiver/Observation Receiver Signal Chain Calibrations section.
Tx LOL
In the transmitter, any coupling of the LO to the RF output or baseband DC offset could generate an undesired tone at the LO frequency.
Without properly correcting it, it could cause a negative impact on the system performance.
Tx LOL is designed in the Tx signal chain to handle this problem. Similarly, it estimates the DC offset through initial and tracking
calibrations and then apply the estimation in the baseband to cancel the undesired tone. For more detailed information, please refer to
the Transmitter/Receiver/Observation Receiver Signal Chain Calibrations section.
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DPD
DPD is an optional feature available in the ADRV9001 device to enable users to achieve higher power amplifier efficiency while still meet
Error Vector Magnitude (EVM) and adjacent channel leakage ratio (ACLR) requirements in their Tx signal chain for compliance with
the standards requirements. DPD works on the principle of pre-distorting the Tx data to cancel distortion caused by power amplifier
compression. It utilizes the tracking calibration to capture the transmitted data samples and the data samples looped back through ORx
to estimate the distortion parameters. By applying the estimations in the real time, the transmitted signal is pre-distorted to compensate
for the power amplifier nonlinearity.
For more detailed information, please refer to the Digital Predistortion section in the User Guide.
TX NCO Internal Signal Source
The ADRV9001 has an internal quadrature NCO which serves several purposes. First, it could be used to generate the calibration tone
for the initial calibrations such as the Tx QEC. Second, it can be used to verify the functionality of the datapath. In both cases, as shown
in Figure 86, the Tx preprocessor takes the input data from NCO instead of data interface.
The NCO has a 32-bit phase accumulator. The NCO clock frequency for the phase accumulator is programmable. It is either set by the
profile to the interface rate or overwritten by the calibration task. To test the datapath, the user can generate a tone with a frequency
resolution of Fclk/232 up to Nyquist frequency through the API command “adi_adrv9001_Tx_NcoFrequency_Set()”.
FM/FSK Modulation
The ADRV9001 provides a FM/FSK modulation for standards which use constant-envelope frequency modulation scheme, such as
DMR, Analog FM, P25 Phase 1 and Phase 2. It also provides an optional capability to perform symbol mapping and interpolation
operation on the Tx data received from baseband processor for FM/FSK modulation. This capability provides user more flexibility when
preparing Tx data for transmission. User has an option to send either pre mapped and interpolated Tx data by enabling this functionality
or send post mapped and interpolated data by bypassing this functionality in ADRV9001. For example, for the Digital Mobile Radio
(DMR) standard which uses 4.8ksps symbol data. baseband processor could send the symbol data directly to ADRV9001 and let
ADRV9001 map the symbol data and then interpolate the data to generate frequency deviation data. Note this functionality is currently
not enabled in the datapath and will be provided to user in the future.
Currently, to utilize the FM/FSK modulation capability of ADRV9001, user should perform symbol mapping, interpolating and pulse
shaping filtering in baseband processor to generate frequency deviation data before sending to ADRV9001. Two different options of
FM/FSK modulation are deployed in the ADRV9001 which are Direct FM/FSK and IQ FM/FSK as shown in Figure 86. They are briefly
discussed in the following subsections.
Direct FM/FSK
Frequency modulation is implemented by modulating the Tx RF PLL directly in Direct FM/FSK option. The Tx datapath with Direct
FM/FSK is shown in Figure 93.
IN ANALOG
ATTENUATOR FREQ_DEV
MAPPER NARROWBAND
INTERPOLATORS
FRAC–N
PLL (TX)
FM MOD. PROGRAMMABLE
128 TAP FI R
SYMBOL
MAPPING/
INTERPOLATION CSSI TX_DATA
24159-094
Figure 93. Direct FM/FSK Data Path Block Diagram
As shown in Figure 93, the baseband processor TX_DATA can optionally go through the symbol mapping/interpolation and
programmable FIR, and after interpolation and frequency deviation mapping, the Frac-N PLL implements the FM/FSK modulation at
the desired RF output frequency. Finally, the PLL output is attenuated before feeding to the TX RF interface. The programmable 128-tap
FIR works as the pulse shaping filter in this scenario, customer could optionally load their filter coefficients according to the standard
requirement through API commands. Note this feature is currently not available but will be provided in future releases. In Direct
FM/FSK modulation, the DAC and LPF could both be powered down and some digital blocks such as the common interpolators, power
amplifier protection and Tx attenuation control could all be bypassed. Therefore, it could result in a significant power saving.
IQ FM/FSK
IQ FM/FSK modulation is implemented by modulating the digital NCO as shown in Figure 86. The modulated IQ data goes through
interpolator, DAC, LPF, and then be upconverted to RF frequency by mixer. The previous processing stages before the digital FM/FSK
modulator are similar to Direct FM/FSK option, which also contains optional symbol mapping/interpolation and pulse shaping
functions. The selection between direct FM/FSK and IQ FM/FSK is determined by profile.
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ANALOG FRONT END (AFE)
DAC
The ADRV9001 integrates a 16-bit DAC which can be operated at standard rate of 184.32, 368.64, or 552.96 MHz (Note when arbitrary
sample rate is supported, DAC can operate at other different rates as well.). The sampling rate is set by the selected profile. The DAC is
auto-tuned to remove mismatches in the DAC units which improves the linearity of the DAC. The nominal full-scale current of the DAC
can be boosted by 3dB through API command “adi_adrv9001_Tx_DacFullScaleBoost_Set()”. The increased signal swing throughout the
entire analog signal chain will result in better AM noise performance. By default, the 3dB boost is disabled.
LPF
The analog LPF is used to attenuate the sampling images of the DAC. The frequency response has 2nd-order Butterworth shape. The
corner frequency is auto-tuned to compensate for process and temperature variation. The operating corner frequency is set by the API
profile.
Upconversion Mixer
The upconversion mixer translates the baseband signal to RF. It is an IQ modulator which receives a quadrature baseband and LO signal.
Due to the image rejection property of IQ modulators, it produces an output only on one side of the LO, i.e. the image is rejected. The
LO leakage and quadrature errors of the mixer are calibrated at startup and continually tracked by Tx LOL and Tx QEC as discussed
earlier.
RF Attenuator
Following the mixer is a digitally controlled step attenuator with 64 linear gain steps. This results in a total gain range of 42dB. Please
note that the analog gain steps are not linear-in-dB. However, as pointed out in the previous section the analog gain steps are
interpolated by a digital multiplier to achieve 0.05dB gain steps. Note in Direct FM/FSK mode, the total gain is 12 dB with 0.5dB step
size.
LPF
The analog LPF is used to attenuate the sampling images of the DAC. The frequency response has 2nd-order Butterworth shape. The
corner frequency is auto-tuned to compensate for process and temperature variation. The operating corner frequency is set by the API
profile.
Upconversion Mixer
The upconversion mixer translates the baseband signal to RF. It is an IQ modulator which receives a quadrature baseband and LO signal.
Due to the image rejection property of IQ modulators, it produces an output only on one side of the LO, i.e. the image is rejected. The
LO leakage and quadrature errors of the mixer are calibrated at startup and continually tracked by Tx LOL and Tx QEC as discussed
earlier.
RF Attenuator
Following the mixer is a digitally controlled step attenuator with 64 linear gain steps. This results in a total gain range of 42dB. Please
note that the analog gain steps are not linear-in-dB. However, as pointed out in the previous section the analog gain steps are
interpolated by a digital multiplier to achieve 0.05dB gain steps. Note in Direct FM/FSK mode, the total gain is 12 dB with 0.5dB step
size.
TRANSMIT DATA CHAIN API PROGRAMMING
A set of Tx data chain APIs are provided for user interaction with the ADRV9001 device transmit datapath. Some of them have been
discussed in the previous sections. The following table summarizes the list of API functions currently available with a brief description
for each one. For more up-to-dated information and detailed descriptions, please refer to API doxygen document. Note more details
about Tx power amplifier ramp functionality can be found in this User Guide in the future.
Table 38. A List of Tx Data Chain APIs
Rx Gain API Function Name Description
adi_adrv9001_Tx_Attenuation_Configure Configures the Tx attenuation for the specified channel
adi_adrv9001_Tx_Attenuation_Inspect Inspects the Tx attenuation for the specified channel
adi_adrv9001_Tx_AttenuationMode_Set
Sets the attenuation control mode
adi_adrv9001_Tx_AttenuationMode_Get Gets the attenuation control mode
adi_adrv9001_Tx_Attenuation_Set Sets the Tx attenuation for the specified channel
adi_adrv9001_Tx_Attenuation_Get Gets the Tx attenuation for the specified channel
adi_adrv9001_Tx_DacFullScaleBoost_Set Sets the DAC full scale current boost
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Rx Gain API Function Name Description
adi_adrv9001_Tx_DacFullScaleBoost_Get Gets the DAC full scale current boost
adi_adrv9001_Tx_AttenuationTable_Write Writes the attenuation table for the specified Tx channels
adi_adrv9001_Tx_AttenuationTable_Read Reads the attenuation table for the specified Tx channels
adi_adrv9001_Tx_NcoFrequency_Set Sets the Tx NCO test tone frequency for the specified Tx channel
adi_adrv9001_Tx_NcoFrequency_Get Gets the Tx NCO test tone frequency for the specified Tx channel
adi_adrv9001_Tx_PaProtection_Configure Configures power amplifier Protection for the specified Tx channel
adi_adrv9001_Tx_PaProtection_Inspect Inspects power amplifier Protection for the specified Tx channel
adi_adrv9001_Tx_SlewRateLimiter_Configure Configures the slew rate limiter for the specified Tx channel
adi_adrv9001_Tx_SlewRateLimiter_Inspect Inspects the slew rate limiter for the specified Tx channel
adi_adrv9001_Tx_PaRamp_Configure Configures the power amplifier ramp for the specified Tx channel
adi_adrv9001_Tx_PaRamp_Inspect Inspects the power amplifier ramp for the specified Tx channel
adi_adrv9001_Tx_Attenuation_PinControl_Configure Configures the Tx attenuation PIN mode for the specified Tx channel
adi_adrv9001_Tx_Attenuation_PinControl_Inspect Inspects the Tx attenuation PIN mode for the specified Tx channel
Preliminary Technical Data UG-1828
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RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN
The ADRV9001 offers dual receive channels. With a minimum number of external components, each receive channel could build a
complete RF-to-bits signal chain which serves as RF front end for a wide range of applications. It supports both time division duplexing
(TDD) and frequency division duplexing (FDD) modes and reception of both narrowband (NB) and wideband (WB) signals up to 40
MHz. NB applications include DMR, P25 and TETRA, while WB applications are geared towards LTE transmissions. For example,
ADRV9001 supports standard sample rates of 24 kHz (typically for FM waveforms), 144 KHz and 288 KHz (typically for TETRA
signals), and 1.92 MHz, 3.84 MHz, 7.68 MHz, 15.36 MHz, 23.04 MHz, 30.72 MHz, and 61.44 MHz (typically for LTE signals). Besides
those standard rates, the ADRV9001 is also capable of supporting an almost continuous range of sample rates between 24 KHz and 61.44
MHz. Some sample rates could not be supported due to internal clocking constraints.
Rx2
HP ADC
AFE
RX1A+
RX1A–
RX1B+
RX1B–
Rx1 DFE
DIGITAL SIGNAL PROCESSING:
– NARROW/ WI DE BAND DE CIMATION
– DC OF FSE T CORRE CTI ON (DC)
– QUADRAT URE E RROR CO RRE CTION (QEC)
– NUMERICALLY CO NTRO LLE D OSCILLAT OR (NCO )
– PROGRAMMABLE FIR FILTER (pFIR)
– RECEI V E R S IG NAL ST RE NGT H INDICATO R ( RS S I)
– FREQUENCY OFFSET CORRECTION
– PHASE OFFSET CORRECTION
– OVE RLO AD DE TECT ORS
DATA PORT
CMOS-SSI
OR
LVDS-SSI TO
BBP
LP ADC
LP ADC
HP ADC
INTERNAL
OBSERVATION
LPF
LO1
LO2
LPF
90°
0°
24159-095
Figure 94. Top Level Structure of ADRV9001 Dual Receiver
Figure 94 describes the top-level structure of the ADRV9001 receivers. As shown in Figure 94, each receive path Rx1 or Rx2 contains 2
major subsystems, the Analog Front End (AFE) and the Digital Front End (DFE). The AFE subsystem contains 4 major components,
which are programmable front end attenuator, matched I and Q mixer, low pass filter (LPF) and analog-to-digital converter (ADC). The
attenuators are utilized to control the signal gain to avoid overloading the datapath when a strong interfering signal presents. It is
followed by the mixers to down convert the received signals for digitization. The output current of the mixers is further converted to
voltage and filtered by LPFs before passing to ADCs. The ADRV9001 provides two pairs of ADCs, a pair of high performance (HP)
ADCs to achieve high linearity performance and a pair of low power (LP) ADCs with slightly less linearity performance but significant
lower power consumption. This design allows for a flexible trade-off between power consumption and linearity performance.
The DFE subsystem contains a series of digital signal processing components such as sample rate decimation (DEC), dc offset correction
(DC), quadrature error correction (QEC), digital down conversion (DDC) with numerically controlled oscillator (NCO), a
programmable 128-tap FIR filter (PFIR), receiver signal strength indicator (RSSI), frequency offset correction (FOC), phase offset
correction (POC) and overload detectors. DEC is used to decimate the ADC sample rate to the desired output sample rate. DC, QEC,
PFIR, FOC and POC are used to condition the digital signals at different stages of the datapath for optimal performance. Overload
detectors are used for gain control in the datapath. RSSI provides signal power measurement to control the bit-width of the output signal.
In addition, it could be used to detect the presence of a signal in a desired frequency band. At the end of the signal chain, through
CMOS-SSI or LVDS-SSI data port, the output signal is delivered to based band processor for further processing.
The ADRV9001 supports a RF local oscillator (LO) range from 30MHz to 6GHz. RF LOs can be generated via two internal phase lock
loops (PLL) or applied externally to the part. The digital subsystem contains an optional digital mixer that is driven by a programmable
NCO. Rx LO can offset from the frequency of the desired channel and then make use of the digital mixer to down convert the signal to
baseband before being processed by baseband processor. There are several advantages to offset the Rx LO from the frequency of the
desired channel: Impairments that exist around the Rx LO, such as LO-leakage, can be avoided. The effect of flicker noise from baseband
circuits can be mitigated since the received signal is offset from dc in the analog signal path. Also, image rejection can be improved if the
Rx LO is offset enough from the desired channel, such that the image frequency lies in the attenuation region of the user’s external RF
filter. IF operation could work with both NB and WB applications. Typically, when the receiver is operating in NB mode, the sensitivity
requirements for these applications demand very low noise performance, therefore, the intermediate frequency (IF) approach is
preferred. The device is capable of receiving signals offset from the carrier, as well as an IF down conversion scheme. When the receiver
is operating on a WB signal, it could utilize direct down conversion or zero IF (ZIF) (although IF approach is also available for WB
signal). In this mode the DDC will be bypassed.
Figure 95 describes the simplified transmit and receive signal path between the antenna and the ADRV9001 device. The components
between the antenna and the ADRV9001 device are external components. In the transmit path, typically, the output signal from the
UG-1828 Preliminary Technical Data
Rev. PrA | Page 100 of 253
device goes through a variable gain amplifier (VGA), a low pass filter (LPF) and a power amplifier before transmitting through antenna.
In the receive path, typically, the RF signal receiving from antenna goes through a low noise amplifier (LNA) and a band pass filter (BPF)
before sending to the device. The duplexer is for supporting both FDD and TDD modes, which could stand for a frequency duplexer in
FDD mode and a RF switch in TDD mode.
As shown in Figure 95, for each Rx, besides acting as a primary data channel for receiving RF signals, it could also serve as an observation
channel, which receives loopback signals from Tx. There are 3 loopback paths, which are internal loopback (ILB), external loopback type
1 (ELB1) and external loopback type 2 (ELB2) as shown in Figure 95. When users are in full control of the loopback channel for running
their own algorithms, we rename the Rx as observation Rx (ORx). In such a case, user can use either ELB1 or ELB2 depending on the
algorithm requirements. For example, if running an external DPD, user should utilize the ELB2 path.
PA
ELB2
ELB1
VGA
LNA
DUPLEXER
(TDD,FDD)
LPF TX1TX1
ILB
RX1/ ORX1
Rx1A
ILB INP UT
Rx1B
BPF
ANTE NNA A
ADRV9001
PA
ELB2
ELB1
VGA
LNA
DUPLEXER
(TDD,FDD)
LPF TX2TX2
ILB
RX2/ ORX2
Rx2A
ILB INP UT
Rx2B
BPF
ANTE NNA B
24159-096
Figure 95. ADRV9001 Rx/ORx/Loopback Diagram
The 3 loopback paths could also be used internally by ADRV9001 for two major purposes: Tx init calibrations and Tx tracking
calibrations including the integrated digital pre-distortion (DPD) operation. Tx init calibrations is to configure the device properly based
on system configurations during the initialization time. It can be done through either ILB, ELB1 or ELB2. The major advantage of using
ELB1 comparing with ILB is to observe common mode voltage. In addition, during Tx init calibrations procedure, test tones are
generated and present at Tx output. Therefore, user needs to ensure appropriate level of isolation from ADRV9001 Tx output to antenna
to ensure that test tones are not transmitted by the system. This isolation could be achieved by disabling power amplifier during Tx init
calibration in ELB1. For ELB2, the calibration signal might be transmitted out through the antenna. Although the power level of
calibration signal is set as low as possible, the user should make sure that this will not cause any problem when using this option. See the
Transmitter/Receiver/Observation Receiver Signal Chain Calibrations section for more information.
Tx tracking calibrations is to tweak the system on the fly during its normal operations for optimal performance. Similarly, it could utilize
ILB, ELB1 or ELB2. ILB and ELB1 are used when DPD is not required while ELB2 is used when DPD is required, in which the Tx
transmit signal is looped back to the receiver after power amplifier. Note ELB1 and ELB2 shares the same Rx input, so they can’t be used
simultaneously.
No matter used by user or internally by the device, the observation channel shares the same datapath as the regular Rx, therefore the
observation can only be performed when no regular Rx reception is required at the same time. This is the case for Tx init calibrations and
the user should aware that Rx might not be idle since it works as observation channel during the time period of initialization internally
by the device. Different from Tx init calibrations, Tx tracking calibrations are performed on the fly, so they have to time share with the
regular Rx operations. For example, in a TDD system, when Tx is transmitting Rx should not be receiving, therefore, it could be used for
observation for Tx tracking calibrations. For a system where Rx is fully occupied all the time for receiving RF signals, such as a 2Tx2Rx
FDD system, it is not possible to perform Tx tracking calibrations including DPD operations in such a system. However, in a 1Tx1Rx
FDD system, since 1 Rx is always idle, it can be used as an observation channel. For example, if Tx1 is transmitting, then Rx1 can be used
for observation by receiving loop back signals from Tx1 and Rx2 can be used as the main receive path. Note it is required that the
observation must be at the same side of the Tx it observes so observation Channel 1 is always for Tx1 and observation Channel 2 is
Preliminary Technical Data UG-1828
Rev. PrA | Page 101 of 253
always for Tx2. When users are in control of the observation channel, they will be allowed to configure the ORx based on their
requirements such as the ORx gain. When the ADRV9001 device is control of the observation channel, it is responsible to configure the
observation channel properly without any user intervention.
As shown in Figure 95, each Rx has 3 inputs, one is the ILB input dedicated for receiving ILB signal. The others are Rx1A/Rx2A and
Rx1B/Rx2B inputs, one could be configured to receive RF signals and the other one to receive ELB signals.
Due to the support of a wide range of applications, user interaction with the Rx signal chain is mainly done through configuration
profiles. Based on the channel profile which includes key parameters such as bandwidth, sample rate and AGC settings, initial calibration
is performed in the device to set up the receive chain properly. When DPD is performed internally in the device, the switch between Rx
and ORx is fully determined without user interaction. Therefore, the device could support rapid switching between different RF channel
profiles with different modulation schemes and bandwidths requirements. When DPD is performed externally by baseband processor,
then baseband processor owns the entire ORx channel. It is user’s responsibility to make sure there is no conflict between the DPD
operations and the Tx tracking calibrations in the device.
In the ADRV9001, a specialized “Monitor mode” exists that allows the device to autonomously poll a region of the spectrum for the
presence of a signal, while in a low power state. In this mode, the chip continuously cycles through sleep-detect-sleep states controlled by
an internal state machine. Power savings are achieved by ensuring that the sleep duty cycle is greater than the “detect” duty cycle. In the
“sleep” state, the chip is in a minimal power consumption configuration where few functions are enabled. After a pre-determined period,
the chip enters the “detect” state. In this state, the chip enables a receiver and performs a signal detect over a bandwidth and at a Rx LO
frequency determined by the user. If a signal is detected, the “Monitor Mode” state machine exits its cycle and normal signal reception
will resume. If no signal is detected, the chip resumes its sleep-detect-sleep cycle. The sleep-detect duty cycle and durations, power
measurement threshold, and Rx LO are user-programmable, and are set before enabling “Monitor Mode”. Please refer to the Rx Monitor
Mode section in the User Guide for more details.
The ADRV9001 provides users with various levels of power control. Power scaling on individual analog signal path blocks can be
performed to trade-off power and performance. In addition, enabling and disabling various blocks in TDD Rx and Tx frames to reduce
power could be customized, at the expense of Rx/Tx or Tx/Rx turn-around time. See the Power Saving and Monitor Mode section for
more information.
Receive Data Chain, AFE Components, Digital Front End Components, and Receive Data Chain API Programming
The following sections provide topical information regarding:
• Receive data chain: this section describes how the analog and digital components are used at the different stages of the receiver chain
to convert RF signals to bits at the desired sample rate for further baseband processor processing.
• Analog front-end components: this section discusses each major AFE component and its functionality.
• Digital front-end components: this section discusses each major DFE component and its functionality.
• Receive data chain API programming: this section outlines the API programming capabilities of Rx data chain for user interactions.
RECEIVE DATA CHAIN
The ADRV9001 supports both NB and WB applications in a common design. Figure 96 describes the block diagram of the entire Rx data
chain, which is composed of AFE and DFE. As mentioned earlier, the AFE includes a front end attenuator which controls the received
RF signal level, mixer for RF to baseband (or IF) down-conversion, low pass filter and a pair of HP and LP ADCs. The LPF has a
programmable bandwidth from about 5MHz to 50MHz depending on the profile. Its configuration and filter characteristics are
automatically tuned internally to achieve optimal performance for different applications. In principle, the AFE design is based on WB
architecture with a very high dynamic range to absorb both desired signal and interference without distortion. Therefore, in such a
design, very little channelization or blocker filtering is needed through LPF since the HP and LP ADC can simultaneously absorb weak
signals and large blockers. Blocker suppression and channelization are then achieved efficiently in the digital signal path. After ADC, the
digital output signal will be further processed through multiple stages in DFE.
HP ADC
RX1A+,
RX2A+
RX1A–,
RX2A–
RX1B+,
RX2B+
RX1B–,
RX2B–
Rx1
LP ADC
LP ADC
HP ADC
INTERNAL
OBSERVATION LO LOOPBACK
LPF
LPF
90°
0°
DECIMATION
STAGE 1
OVERLOAD
DETECTORS MANUAL AND
AUTOMATIC
GAIN CO NTROL
DC OFFSET
CORRECTION QUADRATURE
ERROR
CORRECTION
DECIMATION
AFE DFE
DECIMATION
STAGE 2 FREQUENCY
OFFSET
CORRECTION
PROGRAMMABLE
CHANNEL FILTER
(128 TAP F IR) GAIN
COMPENSATION PHASE
OFFSET
CORRECTION DATA
PORT
INTERFACE
GAIN
RECEIVE R S IGNAL
STRENGTH
INDICATOR
NARROW
BAND FSK
DISCRIMINATION
DMR SYNC
DETECTION
DIGITAL
DOWN
CONVERTER
RX1/2_QDATA_OUT±
2RX1/2_IDATA_OUT±
2RX1/2_STROBE_OUT±
2RX1/2_DCLK_OUT±
2
24159-097
Figure 96. Rx Signal Chain Block Diagram
UG-1828 Preliminary Technical Data
Rev. PrA | Page 102 of 253
The ADRV9001 supports 3 standard ADC clocks which are ADC-H clock 2211.84MHz, ADC-M clock 1474.56MHz and ADC-L clock
1105.92MHz for both HP ADC and LP ADC (Note ADC clock could vary with arbitrary sample rate.). In the DFE subsystem, the ADC
output signal at 3 different sample rates will go through 2 decimation stages as shown in Figure 96 to convert to the desired sample rate
by using a flexible combination of decimators. Between the 2 decimation stages, there is an optional DDC which is employed in the
applications which adopts IF reception scheme.
At different decimation stages, several signal conditioning algorithms are performed, which are overload detection for gain control, DC
offset correction (DC) and quadrature error correction (QEC) as shown in Figure 96. The overload detection result is utilized by
automatic gain control (AGC) or manual gain control (MGC) algorithms to properly control both analog and digital gain through a Rx
gain table. The analog gain is applied at the front end attenuator to avoid overload/underload situations. The digital gain is applied at the
gain compensation block in the Rx datapath and it has 2 major functionalities: one is to correct the small step size inaccuracy of the front
end analog gain and the other is to compensate for the front end gain change completely so that it is transparent to users. Different Rx
gain tables are loaded for either correction or compensation based on user’s configuration during the device initialization. In
ADRV9001, a sophisticated gain control mechanism (AGC/MGC) is provided, please see Rx Gain Control section for more details. DC
and QEC are used to correct the DC offset and quadrature error so that the signal distortion could be minimized to achieve an optimal
performance before sending data to baseband processor. To achieve best performance for different applications, QEC algorithm is
designed differently for WB and NB applications.
After decimation stage 2, the ADRV9001 provides an option to correct small carrier frequency offset through API commands, followed
by a 128-tap programmable PFIR as a channel selection filter. In the future, API commands will be provided for PFIR for more user
interactions.
After PFIR, besides applying the digital gain as discussed earlier, an interface gain could be optionally applied by utilizing the signal
strength measurement from RSSI. The interface gain is applied through a “Slicer” by properly shifting the signal. When the signal is
large, it could be used to avoid saturate the data port due to a limited bit-width and when the signal is small, it could be used to avoid lose
sensitivity. An API command is provided to user to read the signal strength measurement. The interface gain can be applied
automatically in the device or manually by the user through API commands. This is beneficial when saturation is observed in baseband
processor. Please see Rx Gain Control section for more details.
The RSSI could also be utilized as the signal detector in Rx Monitor Mode. In NB applications, at the end of the datapath, the device
provides an optional capability to discriminate the FSK frequency shift and in addition, detect the DMR sync patterns, which is critical
for Rx Monitor Mode. Note phase offset correction capability is also provided at the end of the Rx datapath to ensure the signal fidelity.
In the future, API command will be provided to allow user interaction. Finally, the output signal is sent through CMOS-SSI/LVDS-SSI
data port to baseband processor for further processing.
ANALOG FRONT-END COMPONENTS
Analog Front Attenuator
The analog front attenuator is a PI resistive network that in conjunction with the passive mixer provides a constant 100 Ohm differential
input impedance. It is controlled by the gain control functionality in the receive datapath to adjust the signal gain to avoid overload the
datapath through overload detectors. When a strong interferer presents, the gain will be decreased and when the interferer disappears,
the gain will be increased so that the desired signal level could be adjusted back to the proper level.
The attenuator has 256 gain settings providing an Rx attenuation range from 0 to 20*log(1/256) = -48dB. Typically, only a subset of this
range will be used. In ADRV9001, the range of the attenuation is from 0 to -36dB with a 0.5dB resolution. The gain of the attenuator is
calculated by the following equation:
The fe_gain_cw[7:0] is a 8 bit control word defined in the Rx gain table. Based on the information from the signal detectors, the gain
control algorithm will find the index of this gain table so that the corresponding gain control word at this index could be used to
calculate the gain at the front end attenuator. Please see Rx Gain Control section for more details.
Mixer
Following the RF attenuator is the passive down converting mixer. It is used to down convert the RF signal to IF or baseband. The
passive mixer uses non-overlapping ¼ duty cycle local oscillator generated by the 4 phase 50% duty cycle LO. The non-overlapping time
is controlled by the duty cycle distortion (DCD) circuit. The DCD is implemented by delaying the rising edge of the 50% duty cycle LO.
Preliminary Technical Data UG-1828
Rev. PrA | Page 103 of 253
LPF
In the Rx data chain, the LPF sits between the mixer and the ADC as a Rx baseband filter, supporting a baseband bandwidth of 5-
50MHz. It also converts the baseband signal current to voltage. The capacitor arrays are implemented to program the various cut-off
frequencies based on the system requirements. In addition, along with other AFE components, it provides a static gain of about 20dB
which is independent of the gain control functionality through the Rx data chain.
The LPF could be configured in transimpedance amplifier (TIA) mode with single pole or in bi-quad (BIQ) mode with 2 complex poles
in the transfer function (Note currently, only TIA mode is supported.). While the in-band performance of both modes is similar, the BIQ
mode offers additional advantages comparing with the TIA mode, such as improving anti-alias filtering which might be necessary while
using LP ADC. However, the use of the BIQ mode consumes about twice the power than the TIA mode.
The LPF is calibrated during device initialization to ensure a consistent frequency corner across all devices. The 3dB bandwidth is set
within the device data structure and is profile dependent.
ADC
As mentioned earlier, the ADRV9001 provides a pair of HP ADCs and a pair of LP ADCs to achieve a flexible trade-off between power
consumption and linearity performance. The HP ADC is based on Continuous Time Delta Sigma (CTDS) architecture and is 5-bits
wide. The LP ADC is based on voltage-controlled oscillator (VCO) architecture and is 16-bits wide. Each type of ADC is capable of
accepting the same input voltage, but the output bus width is different due to the different modulator orders and presence of linearity
correction in the LP ADC.
HP and LP ADCs provide similar level of noise and dynamic range (full scale to thermal noise) performance. Therefore, the noise figure
(NF) performance is similar at the input. (Even with slight NF difference at the device input, the difference at antenna input would be
smaller as a result of the LNA gain in the front end.) The major difference between HP and LP ADC is the linearity performance and
power consumption. The intermodulation distortion (IMD) performance of HP ADC is slightly better than LP ADC, at the expense of
higher power consumption. Please refer to the data sheet for detailed information.
Given the high dynamic range of both the HP and LP ADC, very little channelization or blocker filtering occur in the analog signal chain
since the HP ADC can simultaneously absorb weak signals and large blockers. Blocker suppression and channelization are then achieved
efficiently in the digital signal path.
Therefore, HP ADC provides the maximum interferer tolerance performance and LP ADC provides the best power consumption
performance under slightly relaxed interferer condition. Based on the application, user is allowed to select between HP and LP ADC for
linearity and power consumption performance trade-off. In addition, user is allowed to dynamically switch HP ADC and LP ADC on the
fly through API commands adi_adrv9001_Rx_AdcSwitchEnable_Set( ) and adi_adrv9001_Rx_AdcSwitch_Configure( ). The first API
function is used to enable the ADC switching feature and it should be called at STANDBY state before initial calibrations. When
dynamic ADC switch is enabled, both HP ADC and LP ADC initial calibrations will be performed. The second API configures the ADC
switching functionality for a specified Rx channel to operate in different modes. It should be called at CALIBRATED state after
performing initial calibrations.
When Rx Monitor Mode (not supported currently) is enabled, the device might switch between the HP ADC and LP ADC to reduce
power consumption. Additional algorithms are employed in ADRV9001 to compensate for the gain and delay differences while
operating with different type of ADCs so any internal switch is transparent to users.
DIGITAL FRONT END COMPONENTS
DEC
In Rx data chain, a series of decimators (organized into 2 different decimation stages) are employed to convert the ADC sample rate to a
desired sample rate in both NB and WB modes. The following diagram shows how the standard sampling rates for different standards
are achieved through a flexible combination of decimators in the data chain. For simplicity, any other non-DEC blocks are skipped in the
diagram.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 104 of 253
LP
ADC
LP
ADC
16 BIT S
LPF OUTPUT
LPF OUTPUT
LPADC
HPADC
2p2G
1p47G
1p1G
16 BIT S
HP
ADC
HP
ADC
ADC_H
ADC_L
ADC CLK
MUX
WB RX M UX
ADC_M
2211.84M
1105.92M
1474.56M
5 BITS
5 BITS
DEC/8
DEC/12
DEC/6
DEC/3 DEC/8
DEC/16
DEC/32
DEC/2
DEC/4
184.32MHz 61.44MHz
30.72MHz
46.08MHz
DEC/2 23.04MHz
46.08MHz
DEC/40 DEC/40
DEC/24
DEC/8
DEC/6
DEC/4
1152kHz
15.36MHz
7.68MHz
3.84MHz
192kHz
144kHz
48kHz
288kHz
24kHz
1.92MHz
61.44MHz LTE20M
LTE40M_1
LTE15M
LTE10M
LTE5M
LTE3M
LTE1.4M
LTE40M_2
NB RX MUX
DMR48K
TETRA_1
TETRA_192K
DMR_R0
DMR_R1
P25_1_R1
FM_R1
TETRA_2
DEC/4
24159-098
Figure 97. Decimation Schemes in Receiver Data Chain to Support Various Standards
As shown in Figure 97, in NB and WB mode, 3 different ADC output sample rates are first decimated to a fix rate of 184.32MHz. Then, it
is further converted to 2 different rates, one is 61.44 for WB mode only and the other is 46.08MHz for both NB and WB modes. All LTE
standard modes are considered WB and the desired sample rate is further generated from both 61.44MHz and 46.08MHz through a
decimation rate of 2 to 32. DMR, FM, P25 and Tetra are NB modes and the desired sample rate is further generated from 46.08MHz with
a decimation rate of 160-1920.
For each decimator show in Figure 97, it could consist a combination of lower rate decimation filters. For example, DEC/40 could be
implemented as a cascade of DEC/10 and 2 DEC/2 decimators. In addition, the different decimation rates are achieved by strategically
enabling and disabling some lower rate decimators. For example, in WB mode, with an initial sample rate of 61.44MHz, if all lower rate
decimators are used, it can achieve a decimation rate of 32. If two of the DEC/2 are disabled, a decimation rate of 8 can be achieved. All
the decimation filters are carefully designed to satisfy the system performance requirements.
With arbitrary sample rate, the user could get an almost continuous range of sample rates from 24KHz to 61.44MHz except for some
“dead zones” due to internal clocking constraints. This is achieved through adjusting the internal CLK PLL frequency as well as a flexible
arrangement of decimators.
DC OFFSET
The ADRV9001 receiver supports both IF down conversion and ZIF down conversion. The source of the dc offset is mainly from the Rx
LO leakage caused by the finite isolation between the LO and RF ports of a mixer, which is typical for silicon-based ICs. It could generate
a high dc component at the center of desired signal band especially for ZIF operation. Through the datapath, the induced dc offset is
amplified and could reduce the ADC dynamic range significantly. In addition to Rx LO leakage, the device mismatch in LPF and ADC
also contributes to the dc offset problem. Without properly correcting the dc offset, it could cause a negative impact on the system
performance.
In ADRV9001, a two-step approach is taken to estimate and correct the dc offset. The first step comprises of an dc estimation step in
digital domain and a correction procedure in the analog domain. The second step is an all-digital dc offset estimation and correction
technique that estimates and corrects for any residual dc offset after the first step.
QEC
In an ideal analog mixer, the in-phase (I) and quadrature-phase (Q) sinusoidal signals are orthogonal. In addition, the I and Q path of
LPF and ADC should have identical frequency responses. However, in reality, IQ imbalance always exists in the mixer, LPF and ADC,
resulting in quadrature errors. Without properly handling it, it seriously degrades the reception performance. For IF reception, the
respective image mixes partially onto the desired signal during the IF down conversion. In direct conversion reception, IQ-imbalance
leads to a distortion of the IQ-signals themselves within the respective desired baseband channel.
In general, quadrature error can be classified as frequency independent error (FIE) and frequency dependent error (FDE). FIE is mainly
caused by the mixer I/Q sinusoid mismatch in both gain and phase, while FDE is mainly caused by the inconsistent filter responses.
Preliminary Technical Data UG-1828
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Since ADRV9001 supports both NB and WB modes, NBQEC and WBQEC algorithms are developed accordingly to handle quadrature
error in these 2 modes effectively. NBQEC employs a time-domain adaptive algorithm to estimate both gain and phase mismatch. Then,
the estimations are applied to correct the distorted input signal in real-time before passing to DDC. WBQEC designs a correction filter to
cancel the effect of the mismatch filter by modeling the quadrature error generation as a mismatch filtering process. The correction filter
parameters are obtained through the initial calibration by injecting RF tones into the mixer at selected frequencies and then on-the-fly
adjustment by processing the Rx data in real-time.
DDC
DDC is only used when IF reception is employed. By using a programmable NCO configurable from 45KHz to 21MHz, it further
converts the IF signal to the baseband.
FREQUENCY OFFSET CORRECTION
In a communication system, a desired signal is transmitted by the transmitter at RF over the air. Since the clock reference at the
transmitter or the receiver are independent to each other, this may result in the RF carrier frequency offset between the transmitter and
the receiver. This frequency difference is named as the carrier frequency offset (CFO). In the Rx data chain, a frequency offset correction
block is provided as an option to further correct small carrier frequency offset in both NB and WB modes through an API command.
The correction value needs to be estimated and provided by the BBIC. The correction may occur immediately or relative to Rx frame
boundary. Another programmable NCO is employed with a configurable frequency -12KHz to +12KHz and FTW 32 bits wide.
The API command adi_adrv9001_Rx_FrequencyCorrection_Set( ) is used to correct small deviations in Rx LO frequency. The user
needs to provide the frequency deviation value in Hz and specify if the correction should take place immediately or at the start of next
available frame. Note the device employs the digital NCO in the datapath to correct the frequency deviation instead of RF PLL retuning.
PFIR
PFIR is an optional 128-tap programmable FIR used in both NB and WB modes. 4 sets of customized FIR profiles can be stored at the
initialization phase. One of the 4 stored FIR profiles can be switched to be loaded on the fly under the control of the baseband processor.
The PFIR can be loaded a customized lowpass filter profile to stop the adjacent channel interference, which is helpful to achieve better
channel selectivity. Please refer to Rx Demodulator section for more details.
RSSI
RSSI measures the receive signal power over a period of time, which could be employed to calculate the interface gain to avoid saturate
the data port. In addition, in Monitor Mode, it performs signal detection in WB applications and works together with FSK
Discrimination block to detect NB signals in NB applications.
The measured signal level could be retrieved by user through an API command adi_adrv9001_Rx_Rssi_Read( ). The API function reads
back the RSSI status for the given Rx channel and may be called any time after the device is fully initialized. The following data structure
is used to retrieve the power measurement in both milli-dBFS and linear format:
typedef struct adi_adrv9001_RxRssiStatus
{
uint16_t power_mdB; /* Power in milli dB */
/* Linear power is calculated by this formula: linear power = (mantissa * 2^-15) * 2^-
exponent */
uint16_t linearPower_mantissa; /* Mantissa of Linear Power */
uint16_t linearPower_exponent; /* Exponent of Linear Power */
} adi_adrv9001_RxRssiStatus_t;
Interface Gain
Due to the bit-width limitation of the data port, an interface gain is applied by shifting the signal properly so as not to clip the output
upon saturation. It could also increase the signal level for small signals to avoid losing sensitivity. The interface gain could be
automatically adjusted internally inside the device by utilizing the RSSI measurement or by user through API commands. The user could
also optionally retrieve the signal level measured by RSSI through an API command to control the interface gain. Please see Rx Gain
Control section or more details.
Phase Offset Correction
In both NB and WB modes, a phase offset correction block is provided as an option to adjust the sampling phase offset on IQ data or
frequency deviation data. It resamples the incoming received signal, by reconstructing intermediate samples between every 2 inputs
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samples according to the phase parameter configured by user through an API command. Currently, it is only programmable by the
device. More user interaction will be provided in the future.
NB FSK Discrimination
In NB applications, the ADRV9001 device provides the capability of demodulating and detecting FSK/FM signals. This block has 2
operation modes, one is detecting mode and the other is detected mode. The detecting mode is only used when Monitor Mode is
enabled. It is employed to detect the FSK/FM signals. As mentioned earlier, the signal detection could be accomplished by RSSI only.
However, this block could be further utilized in NB mode to achieve more accurate signal detection. After FSK/FM signal is detected, this
block will operate in the detected mode. Some components in the datapath will be reconfigured to operate differently from the detecting
mode. In case no FSK/FM signal is detected, TRx will move to sleep mode.
It is well known that DMR and FM radio has an about 90% idle time, during which, both RF front end and baseband processor are put to
sleep to save power. As a traditional solution, both baseband processor and TRx have to power up to do the carrier detection and TRx
only passes through the data. With the equipped capability of the ADRV9001, it detects the DMR and FM signal independent of the
baseband processor during its idle state, so that the baseband processor could sleep at the whole idle state to extent the battery life. Please
refer to Rx Demodulator section for more details.
RECEIVE DATA CHAIN API PROGRAMMING
A set of Rx data chain APIs are provided for user interaction with the ADRV9001 device receive datapath. Some of them have been
briefly discussed in the previous sections. This set of APIs could be classified into 3 categories: Rx Gain APIs, Interface Gain APIs and
Miscellaneous APIs as shown in Table 39, Table 40, and Table 41 respectively. Each table summarizes the list of API functions with a
brief description for each one. More APIs will be provided to user in the future to allow more programmability of the receiver datapath.
Please refer to the ADRV9001 Device API doxygen document for more details.
Table 39. A List of Rx Gain APIs
Rx Gain API Function Name Description
adi_adrv9001_Rx_GainTable_Write Programs the gain table settings for Rx channels.
adi_adrv9001_Rx_MinMaxGainIndex_Set Updates the minimum and maximum gain indices for a requested Rx/ORx Channel in the
device data structure
adi_adrv9001_Rx_GainTable_Read Reads the gain table entries for Rx channels requested.
adi_adrv9001_Rx_Gain_Set Sets the Manual Gain Index for the given Rx channel.
adi_adrv9001_Rx_Gain_Get Reads the Rx Gain Index for the requested Rx channel
Table 40. A List of Interface Gain APIs
Rx Gain API Function Name Description
adi_adrv9001_Rx_InterfaceGain_Configure Sets the Rx interface gain control configuration parameters for the given Rx channel.
adi_adrv9001_Rx_InterfaceGain_Set Sets the Rx interface gain for the given Rx channel.
adi_adrv9001_Rx_InterfaceGain_Inspect Gets the Rx interface gain control configuration parameters for the given Rx channel.
adi_adrv9001_Rx_InterfaceGain_Get Gets the Rx interface gain for the given Rx channel.
adi_adrv9001_Rx_DecimatedPower_Get Gets the decimated power at configurable locations for the specified channel.
Table 41. A List of Rx Miscellaneous APIs
Rx Miscellaneous API Function Name Description
adi_adrv9001_Rx_Rssi_Read Reads the received signal power measurement in both linear and dB format.
adi_adrv9001_Rx_FrequencyCorrection_Set Corrects for small deviations in Rx LO frequency offset.
adi_adrv9001_Rx_AdcSwitchEnable_Set Sets the readiness of dynamic switch between Low Power and High Performance ADCs.
adi_adrv9001_Rx_AdcSwitchEnable_Get Gets the readiness of dynamic switch between Low Power and High Performance ADCs.
adi_adrv9001_Rx_AdcSwitch_Configure Configures ADC dynamic switch settings for the specified channel.
adi_adrv9001_Rx_AdcSwitch_Inspect Inspects the current ADC dynamic switch settings for the specified channel.
adi_adrv9001_Rx_AdcType_Get Gets the current ADC type for the specified channel.
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TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS
In ADRV9001, to achieve optimal performance, an ARM performs calibrations which can be classified into two categories: initial
calibrations performed at the initialization time before the device is operational; and tracking calibrations performed regularly while the
device is operational.
Initial calibrations are considered as a part of the device initialization which moves the device from “STANDBY” state to
“CALIBRATED” state to prepare for transmit/receive operations. Tracking calibrations are performed regularly on-the-fly while the
device is operational to track the changes such as attenuation, temperature and etc. As discussed in Rx Signal Chain Section of this User
Guide, ADRV9001 includes 2 Tx and 2 Rx. for each Rx, besides acting as a primary data channel for receiving RF signals, it could also
serve as an observation channel, which receives Tx signals through loopback paths. The observation channel could be controlled fully by
user (ORx) or internally controlled by the device for some Tx initial and tracking calibrations. Note for some systems such as FDD 2T2R,
the Tx tracking calibrations requiring loopback paths could not be performed since the observation channel is not available. (Please refer
to ADRV9001 Example Use Cases section for more details.)
Most initial calibrations utilize internally generated tones or wideband signals for calibration which need user to satisfy external system
requirements. This topic will be discussed in more details in later sections. Different from initial calibrations, tracking calibrations
usually utilize the real-time traffic data for calibration. Therefore, tracking calibrations are transparent to users which do not require any
user intervention. Both initial and tracking calibrations are scheduled and performed by the ARM.
INITIAL CALIBRATIONS
There are three types of initial calibrations, which are
• System (non-channel related) initial calibrations
• Initial calibrations for RF PLLs to calibrate the RF PLL for very fast frequency hopping mode (currently not available),
• Aux PLL initial calibration (currently not available).
• Tx initial calibrations
• Quadrature Error Correction (QEC),
• Local Oscillator (LO) Leakage,
• Loop Back Path Delay (LB PD),
• Duty Cycle Correction (DCC),
• Baseband Analog Filter (BBAF),
• Baseband Analog Filter-Group Delay (BBAF GD),
• Attenuation Delay (ATTEN DELAY),
• Digital to Analog Converter (DAC),
• Path Delay.
• Rx initial calibrations
• High Power ADC Resistor/Capacitor (HP ADC RC),
• High Power ADC Flash offset (HP ADC Flash),
• High Power ADC DAC (HP ADC DAC) (currently not available),
• Duty Cycle Correction (DCC), Low Power ADC (LP ADC),
• Transimpedance Amplifier
• 3-dB Cutoff Frequency (TIA Cutoff),
• Transimpedance Amplifier Group Delay,
• Wideband Quadrature Error,
• Frequency Independent Quadrature Error,
• Internal Loop Back LOD (ILB LOD) (currently not available), DC Offset (RF DC),
• Gain Path Delay.
Note Rx initial calibrations are also required to be performed on loopback paths to prepare for Tx initial and tracking calibrations.
To successfully perform all the initial calibrations, the ADRV9001 device should be configured properly. This is fully controlled by the
ADRV9001 ARM therefore no user interaction is required. However, besides the internal configurations, there are also requirements for
the external system. For example, during some Tx initial calibrations, tones are generated and present at Tx output. Therefore, user
should ensure appropriate level of isolation from ADRV9001 Tx output to antenna to make sure that test tones are not transmitted by
the system. This isolation could be achieved by disabling power amplifier during Tx initial calibration.
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Initial Calibrations API Programming
The ADRV9001 ARM in the device is tasked with scheduling/performing initial calibrations to optimize the performance of the device
prior to device operation. Initial calibrations is performed using the top-level API function adi_adrv9001_cals_InitCals_Run( ).
The initial calibration performed is based on the initial calibration configuration defined by the following data structure:
typedef struct adi_adrv9001_InitCals
{
uint32_t sysInitCalMask;
uint32_t chanInitCalMask[ADI_ADRV9001_MAX_RX_ONLY];
adi_adrv9001_InitCalMode_e calMode;
} adi_adrv9001_InitCals_t
In this structure, sysInitCalMask is the initial calibration mask for system calibrations, chanInitCalMask[] is an array containing
calibration bit mask for channel related initial calibrations (chanInitCalMask[0] is the mask for Rx1/Tx1 channels and
chanInitCalMask[1] is the mask for Rx2/Tx2 channels ) and calMode specifies the mode to run the desired initial calibration algorithms.
The following enumerator type defines all the initial calibrations:
typedef enum adi_adrv9001_InitCalibrations
{
ADI_ADRV9001_INIT_CAL_TX_QEC = 0x00000001,
ADI_ADRV9001_INIT_CAL_TX_LO_LEAKAGE = 0x00000002,
ADI_ADRV9001_INIT_CAL_TX_LB_PD = 0x00000004,
ADI_ADRV9001_INIT_CAL_TX_DCC = 0x00000008,
ADI_ADRV9001_INIT_CAL_TX_BBAF = 0x00000010,
ADI_ADRV9001_INIT_CAL_TX_BBAF_GD = 0x00000020,
ADI_ADRV9001_INIT_CAL_TX_ATTEN_DELAY = 0x00000040,
ADI_ADRV9001_INIT_CAL_TX_DAC = 0x00000080,
ADI_ADRV9001_INIT_CAL_TX_PATH_DELAY = 0x00000100,
ADI_ADRV9001_INIT_CAL_RX_HPADC_RC = 0x00000200,
ADI_ADRV9001_INIT_CAL_RX_HPADC_FLASH = 0x00000400,
ADI_ADRV9001_INIT_CAL_RX_HPADC_DAC = 0x00000800,
ADI_ADRV9001_INIT_CAL_RX_DCC = 0x00001000,
ADI_ADRV9001_INIT_CAL_RX_LPADC = 0x00002000,
ADI_ADRV9001_INIT_CAL_RX_TIA_CUTOFF = 0x00004000,
ADI_ADRV9001_INIT_CAL_RX_GROUP_DELAY = 0x00008000,
ADI_ADRV9001_INIT_CAL_RX_QEC_TCAL = 0x00010000,
ADI_ADRV9001_INIT_CAL_RX_QEC_FIC = 0x00020000,
ADI_ADRV9001_INIT_CAL_RX_QEC_ILB_LO_DELAY = 0x00040000,
ADI_ADRV9001_INIT_CAL_RX_RF_DC_OFFSET = 0x00080000,
ADI_ADRV9001_INIT_CAL_RX_GAIN_PATH_DELAY = 0x00100000,
ADI_ADRV9001_INIT_CAL_PLL = 0x00200000,
ADI_ADRV9001_INIT_CAL_AUX_PLL = 0x00400000,
ADI_ADRV9001_INIT_CAL_TX_ALL = 0x000001FF,
ADI_ADRV9001_INIT_CAL_RX_ALL = 0x001FFE00,
ADI_ADRV9001_INIT_CAL_RX_TX_ALL = 0x001FFFFF,
ADI_ADRV9001_INIT_CAL_SYSTEM_ALL = 0x00600000,
} adi_adrv9001_InitCalibrations_e
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The following enumerator type defines the operating modes for initial calibrations:
typedef enum adi_adrv9001_InitCalMode
{
ADI_ADRV9001_INIT_CAL_MODE_ALL = 0,
ADI_ADRV9001_INIT_CAL_MODE_RX = 1,
ADI_ADRV9001_INIT_CAL_MODE_TX = 2,
ADI_ADRV9001_INIT_CAL_MODE_ELB_ONLY = 3
} adi_adrv9001_InitCalMode_e
in which ADI_ADRV9001_INIT_CAL_MODE_ALL is for running all the selected initial calibrations including both Rx (non-loopback
and loopback paths) and Tx initial calibrations. ADI_ADRV9001_INIT_CAL_MODE_RX is for running the selected Rx initial
calibrations (non-loopback paths) and ADI_ADRV9001_INIT_CAL_MODE_TX is for running the selected Rx calibrations on loopback
paths (both internal and external loopback paths) and the selected Tx initial calibrations. When using external LO for both Rx and Tx
and when Rx LO and Tx LO are at different frequencies, it takes time for user to change LO frequency, therefore, instead of running all
the initial calibrations (select mode 0), the user could first set Rx LO and run Rx initial calibrations (non-loopback path) (select mode 1)
and then change to Tx LO and run the Rx initial calibrations (loopback path) and Tx initial calibrations (select mode 2).
ADI_ADRV9001_INIT_CAL_MODE_ELB_ONLY is for running all the initial calibrations on external loopback paths only. Usually
user should not explicitly use this mode. It is used when user calls the adi_adrv9001_cals_ExternalPathDelay_Run()API command to get
the external loopback path delay which can be used as an input to adi_adrv9001_cals_ExternalPathDelay_Set() for characterization.
Note non-channel related initial calibrations run implicitly, which are fully controlled by the ADRV9001 ARM.
Table 42 describes the mask bit assignment for initial calibrations in adi_adrv9001_InitCalibrations_e. It also explains the functionality
of each initial calibration. Note it is possible to select a different mask for Channel 1 (Tx1/Rx1) and Channel 2 (Tx2/Rx2).
Table 42. Initial Calibration Mask Bit Assignments
Bits Corresponding Enum Calibration Description
D0 ADI_ADRV9001_INIT_CAL_TX_QEC Tx QEC Initial
Calibration
This performs an initial QEC calibration for frequency
independent errors for the Tx path. It estimates the gain
and phase mismatch and apply the gain mismatch in the
digital domain. Currently it utilizes the Tx path and an ILB
path. If transmitted data is quadrature modulated, this
initial calibration is performed, but it is not used if the data
modulation is direct modulation (DM).
D1 ADI_ADRV9001_INIT_CAL_TX_LO_LEAKAGE Tx LOL Initial
Calibration
This performs an initial LOL calibration. It estimates the
LOL and applies the cancellation in the digital domain.
Currently it utilizes the Tx path and an ILB path. If
transmitted data is quadrature modulated, this initial
calibration is performed, but it is not used if the data
modulation is direct modulation (DM).
D2 ADI_ADRV9001_INIT_CAL_TX_LB_PD Tx Loop Back
Path Delay
Calibration
This is used to calibrate the Tx Loop Back Path Delay
(could be for either ILB or ELB). This information is
required for QEC and LOL calibration. Currently it utilizes
the Tx path and an ILB path.
D3 ADI_ADRV9001_INIT_CAL_TX_DCC Tx DCC Initial
Calibration
This corrects the 50% duty cycle for external LO when the
divisor is 2.
D4 ADI_ADRV9001_INIT_CAL_TX_BBAF Tx BBAF Initial
Calibration
This is used to tune the low-pass corner frequency and the
pass-band flatness of the Tx baseband analog filter.
D5 ADI_ADRV9001_INIT_CAL_TX_BBAF_GD Tx BBAF-GD
Initial Calibration
This is used to estimate and correct the filter group delay
to remove frequency dependent quadrature error
between the I and Q channels in each transmitter.
D6 ADI_ADRV9001_INIT_CAL_TX_ATTEN_DELAY Tx ATTD Initial
Calibration
This is used to estimate the delay between the Tx analog
attenuation and digital attenuation. The delay will be the
same for all dynamic datapath profiles, gain indices
and frequency regions etc. The calibration need only be
performed on a single channel.
D7 ADI_ADRV9001_INIT_CAL_TX_DAC Tx DAC Initial
Calibration
This is used to calibrate the DAC for the required profile
bandwidth.
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Bits Corresponding Enum Calibration Description
D8 ADI_ADRV9001_INIT_CAL_TX_PATH_DELAY Tx Path Delay
Initial Calibration
This is used to estimate the delay between the Tx input
and the Tx output.
D9 ADI_ADRV9001_INIT_CAL_RX_HPADC_RC Rx HP ADC RC
Initial Calibration
This is used to determine how much the unit R and C vary
from ideal and then tune the HP ADC’s programmable Rs
and Cs to obtain their desired values. Without this
calibration, the HP ADC’s noise performance will be
negatively impacted. The HP ADC could also become
unstable. It is not used when only LP ADC is used.
D10 ADI_ADRV9001_INIT_CAL_RX_HPADC_FLASH Rx HP ADC Flash
Offset Initial
Calibration
This is used to optimize the HP ADC output noise by
correcting comparators offsets in the backend flash. It is
not used when only LP ADC is used.
D11 ADI_ADRV9001_INIT_CAL_RX_HPADC_DAC Rx HP ADC DAC
Initial Calibration
It corrects for element mismatch HP ADC current. It is not
used when only LP ADC is used. This is disabled by default
– uncalibrated performance sufficient.
D12 ADI_ADRV9001_INIT_CAL_RX_DCC Rx HP ADC
Stability Initial
Calibration
This corrects the 50% duty cycle for external LO when the
divisor is 2.
D13 ADI_ADRV9001_INIT_CAL_RX_LPADC Rx LP ADC Initial
Calibration
This is used to calibrate the LP ADC. The major purpose of
using the LP ADC instead of the HP ADC is to reduce
power consumption. It is not used when only HP ADC is
used.
D14 ADI_ADRV9001_INIT_CAL_RX_TIA_CUTOFF
Rx TIA Cutoff
Initial Calibration
This is used to tune the 3dB cut-off frequency of the TIA
filter.
D15 ADI_ADRV9001_INIT_CAL_RX_GROUP_DELAY Rx TIA Fine Initial
Calibration
This is used to compensate the mismatch in 3dB cutoff
frequency between I and Q path. It helps to correct
quadrature error in analog domain, which simplifies the
correction in the digital domain.
D16 ADI_ADRV9001_INIT_CAL_RX_QEC_TCAL Rx Tone Initial
Calibration
This performs an initial QEC calibration in wideband
systems for frequency dependent quadrature errors.
D17 ADI_ADRV9001_INIT_CAL_RX_QEC_FIC Rx Frequency
Independent
Error Initial
Calibration
This performs an initial QEC calibration for frequency
independent errors for both narrowband and wideband
systems.
D18 ADI_ADRV9001_INIT_CAL_RX_QEC_ILB_LO_DELAY Rx ILB LO Delay
Initial Calibration
This is used to adjust the analog delay between the
inphase and quadrature LO components at the mixer on
the internal loopback path. This is not enabled currently.
D19 ADI_ADRV9001_INIT_CAL_RX_RF_DC_OFFSET Rx RFDC Offset
Initial Calibration
This is used to mitigate the RFDC offset added due to LO
self-mixing.
D20 ADI_ADRV9001_INIT_CAL_RX_GAIN_PATH_DELAY Rx Gain Path
Delay Initial
Calibration
This is used to calculate the path delay between the Rx
analog and digital attenuation blocks. This delay is then
used to offset the onset of Rx analog and digital
attenuations relative to each other to compensate for the
path delay between these blocks. It is independent of gain
index and frequency region. The calibration needs only be
performed on a single channel.
D21 ADI_ADRV9001_INIT_CAL_PLL PLL Initial
Calibration
This is used to perform VCO frequency calibration, VCO
real-time temperature/aging calibration and charge pump
calibration to make RF PLL ready for operation. It is only
used for very fast frequency hopping mode. This is not
enabled currently.
D22 ADI_ADRV9001_INIT_CAL_AUX_PLL AUX PLL Initial
Calibration
This is used to perform VCO frequency calibration, VCO
real-time temperature/aging calibration and charge pump
calibration to make aux PLL ready for operation. This is
not enabled currently.
The ADRV9001 ARM proceeds through the calibrations in the required sequential order. The system initial calibrations are performed
first followed by Rx initial calibrations and then Tx initial calibrations. The Rx initial calibration order and the Tx initial calibration order
are shown in Table 43 and Table 44, respectively.
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Table 43. Rx Initial Calibration Order
Order Rx Initial Calibrations
1 RX_HPADC_RC
2 RX_HPADC_FLASH
3 RX_HPADC_DAC
4 RX_LPADC
5 RX_TIA_CUTOFF
6 RX_DCC
7 RX_GROUP_DELAY
8 RX_RF_DC_OFFSET
9 RX_GAIN_PATH_DELAY
10 RX_QEC_ILB_LO_DELAY
11 RX_QEC_TCAL
12 RX_QEC_FIC
Table 44. Tx Initial Calibration Order
Order Tx Initial Calibrations
1 TX_DCC
2
TX_BBAF
3 TX_DAC
4 TX_LB_PD
5 TX_LO_LEAKAGE
6 TX_QEC
7 TX_BBAF_GD
8 TX_ATTEN_DELAY
9 TX_PATH_DELAY
The calibration order is mostly determined by the algorithm dependency. It is important that the users wait for these calibrations to
complete successfully before continuing with other steps of initialization for the device.
NOTE: Table 42 provides a full list of initialization calibrations for the device. Not all of these calibrations have been implemented at this
time and are expected with future software updates.
System Considerations for Tx Initial Calibrations
In this section, high level block diagrams are used to show the device configurations and external system requirements for some Tx
initial calibrations. In all the diagrams, grayed-out lines and blocks are not active in the calibration. Blue blocks are the related
calibrations. It should be noted that as the ADRV9001 ARM performs each of the calibrations, it is tasked with configuring the
ADRV9001 device as per the diagrams below, with respect to enabling/disabling paths, etc. No user input is required in this regard.
However, it is important that the user ensures that external system conditions are met, such as having the power amplifier off for all
calibrations except for some initialization calibration utilizing ELB2.
Among 9 Tx initial calibrations, except for TX_DAC, all other 8 calibrations require to insert Tone/wideband signal into the Tx datapath
from an internal signal generator. Therefore, the internal microprocessor will disable the data port to avoid interference. Some
calibration algorithms, such as TX_LB_PD, TX_QEC, TX_LOL, TX_DCC and TX_ATTEN_DELAY further require the use of
observation datapath through ILB or ELB to receive the transmitted signal so that a joint analysis can be performed by observing the
relationship between the transmitted signal and received signal. As aforementioned, currently, only ILB feedback path is supported for
initial calibrations.
Transmitter Initial Calibrations Utilizing Internal Signal Generation Without Loopback
Figure 98 shows a high level block diagram of system configurations for Tx initial calibrations requiring inserting signals into the Tx
datapath without using loopback path.
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DAC
DATA PORT
CMOS-SSI
OR
LVDS-SSI FROM
BBP
DAC
LPF
LO1
LO2
LPF
PA
PA SWITCH OFF
24159-099
TX_PATH
DELAY
90°
0°
TX_BBAF
TX_BBAF_GD SIGNAL
GENERATOR
Figure 98. Transmitter Initial Calibration System Configuration with Signal Generation Without Loop Back
As shown in Figure 98, an internal signal generator inserts calibration signals into the transmitter datapath. The data port is disabled
during initial calibrations to avoid producing interference. TX_PATH_DELAY is performed in the digital domain whereas TX_BBAF
and TX_BBAF_GD are performed in the analog domain. All of them utilize the signal generator to insert tones for calibration. During all
these calibrations, test signals inserted into the transmitter datapath can appear at the transmitter output, so it is important that the
power amplifier connected to the device output be switched off, which also prevents signals from the antenna reaching the transmitter
during calibrations. 50 Ω termination is also needed to prevent tone signals bouncing back from power amplifier input and reaching the
device transmitter output, thereby confusing internal calibrations. The following paragraph summarizes the external system
requirement.
External system requirement: for transmitter initial calibrations utilizing internal signal generation without loopback, the power
amplifier in the transmitter path should be powered off during these calibrations. When the power amplifier is disabled, the load seen at
the transmitter output should be 50 Ω.
Transmitter Initial Calibrations Utilizing Internal Signal Generation and ILB
Figure 99 shows a high level block diagram of system configurations for transmitter initial calibrations utilizing internal signal
generation and ILB path.
DAC
FROM
BBP
DAC
LPF
LO1
LO2
LPF
90°
0°
TX_LB_PD
TX_QEC
TX_LO_LEAKAGE
TX_DCC
TX_ATTEN_DELAY
TO
BBP
PA
PA SWITCH OFF
ILB
LNA SWITCH OFF
HP ADC
LP ADC
LP ADC
HP ADC
LPF
LO1
LO2
LPF
90°
0°
ADRV9001
LNA
DUPLEXER
(TDD,FDD)
24159-100
DATA PORT
CMOS-SSI
OR
LVDS-SSI
SIGNAL
GENERATOR
Figure 99. Tx Initial Calibration System Configuration with Signal Generation and Internal Loop Back
As shown in Figure 99, TX_LB_PD, TX_QEC, TX_LO_LEAKAGE, TX_DCC, and TX_ATTEN_DELAY utilize the ILB for calibrations.
TX_LO_LEAKAGE and TX_QEC calculate the initial correction parameters. TX_LB_PD provides a measurement of the loop back path
delay for TX_LO_LEAKAGE and TX_QEC algorithms. Both TX_LO_LEAKAGE and TX_QEC calibrations sweep through a series of
attenuation values, creating a table of initial calibration values. Then, during operation and upon application of a new transmitter
attenuation setting, the corresponding QEC and LO_LEAKAGE correction values are applied to the transmitter channel by the
ADRV9001 ARM. TX_DCC estimates the duty cycle error in the digital domain but applies the correction in the analog domain.
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TX_ATTEN_DELAY measures the delay between the transmitter digital attenuation block and transmitter analog attenuation block and
it utilizes the ILB for delay observation and estimation.
During all these calibrations, similarly, the power amplifier connected to the device output should be switched off and 50Ω termination
is needed. In addition, it is important to switch off the LNA (or RF switch if no LNA presented externally) external to the Rx datapath to
avoid the interference from the RF port into Rx input utilized for data traffic. The following paragraph summarizes the external system
requirement.
External system requirement: for Tx initial calibrations using ILB, the power amplifier in the Tx path should be powered off during these
calibrations. When the power amplifier is disabled, the load seen at the Tx output should be 50Ω. The LNA (or RF switch if no LNA
presented externally) for the loopback path should also be switched off to avoid receiving signals from RF port.
Initial Transmitter Calibration Utilizing Internal Signal Generation and ELB
Although not currently supported, it is also possible to perform some Tx initial calibrations using ELB. As mentioned in
Receiver/Observation Receiver Signal Chain section, using ELB1 for initial calibrations provides the advantage of observing common
mode voltage. When ELB1 is used, it has the same external system requirements as using ILB. Figure 100 shows the high level block
diagram of initial Tx calibrations using internal signal generation and ELB1.
0°
90° To BBP
LNA
ADRV9001
From BBP
TX_LB_PD
TX_QEC
TX _LO_ LEAKAGE
TX_ATTEN_DELAY
PA
PA SWITCH OFF
LNA SWITCH OFF
ELB1
LPF
LO1
LO2
LPF
24159-101
DAC
HP
ADC
HP
ADC
SIGNAL
GENERATOR
LP
ADC
LP
ADC
DAC
LPF
LPF
LO1
LO2
0°
90°
DUPLEXER
(T DD, FDD)
COUPLER
DATA P O RT
CMOS-SSI OR
LVDS-SSI
Figure 100. Transmitter Initial Calibration System Configuration with Signal Generation and External Loop Back Type 1
For TX_LO_LEAKAGE, another option is to use ELB2. Figure 101 shows the high level block diagram of system configurations for
TX_LO_LEAKAGE initial calibrations using ELB2 (Note TX_LB_PD initial calibration using ELB2 is required for TX_LO_LEAKAGE).
DATA P O RT
CMOS-SSI OR
LVDS-SSI
0°
90° To BBP
LNA
ADRV9001
From BBP
TX_LB_PD
TX _LO_ LEAKAG E
PA SW IT CH ON
COUPLER
ATTENUATOR
LNA SWITCH OFF
ELB2
LPF
LO1
LO2
LPF
24159-102
DAC
HP
ADC
HP
ADC
SIGNAL
GENERATOR
LP
ADC
LP
ADC
DAC
LPF
LPF
LO1
LO2
0°
90°
DUPLEXER
(T DD, FDD)
PA
Figure 101. Tx Initial Calibration System Configuration with Signal Generation and External Loop Back Type 2
When ELB2 feedback path is utilized, it requires that the power amplifier be enabled such that a full external loop is made between the
Tx outputs and the observation channel inputs. The advantage of this calibration is to obtain a good estimate (gain/phase) of the external
loop channel conditions prior to operation. The device configuration is shown in Figure 101. Note in this case, the calibration signal
might be transmitted out through the antenna. Although the power level of calibration signal is set as low as possible, user should make
sure that this will not cause any problem when using this option.
UG-1828 Preliminary Technical Data
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It is important that a suitable attenuator be chosen between the power amplifier output and the observation channel input. This is to
prevent Tx data from saturating the observation channel input. The following paragraph summarizes the external system requirement.
External system requirement: a suitable attenuator must be chosen between the power amplifier output and the observation channel
input to prevent Tx data from saturating the observation channel input. The LNA (or RF switch if no LNA presented externally) for the
loopback path should be switched off to avoid receiving signals from RF port.
System Considerations for Receiver Initial Calibrations
In this section, similarly, high level block diagrams are used to show the device configurations and external system requirements for
receiver initial calibrations. In all the diagrams, grayed-out lines and blocks are not active in the calibration. Blue blocks are related
calibrations. It should be noted that the ADRV9001 ARM performs each of the calibrations. It is tasked with configuring the ADRV9001
device as per the diagrams below, with respect to enabling/disabling paths, etc. No user input is required in this regard. However, it is
important that the user ensures that external system conditions are met, such as having the Rx input properly terminated for Rx
initialization calibrations.
Among 11 different Rx initial calibrations, RX_HPADC_RC, RX_HPADC_FLASH, RX_HPADC_DAC (not enabled) and RX_LPADC
calibration are performed in the analog domain and the corrections are applied to HP ADC or LP ADC (based on which one is utilized),
while all other Rx initial calibrations are performed in the digital domain. For RX_QEC_FIC and RX_QEC_TCAL, the calibration results
are applied in digital domain for correction. For RX_DCC, RX_RF_DC_OFFSET, RX_TIA_CUTOFF, RX_GROUP_DELAY and
RX_QEC_ILB_LO_DELAY, the calibration results are applied in the analog domain for correction. Figure 102 shows the high level block
diagram of system configurations for Rx initial calibrations. Note different calibration performs at different locations in the Rx datapath
which is simplified in Figure 102.
DATA P O RT
CMOS-SSI OR
LVDS-SSI
0°
90°
To BBP
LNA
ADRV9001 Rx
RX_QEC_FIC
RX_QEC_TCAL
RX_RF_DC_OFFSET
RX_TIA_CUTOFF
RX_GROUP_DELAY
RX_DCC
RX_QEC_ILB_LO_DELAY
LNA SWITCH OFF
LPF
LO1
LO2
LPF
24159-103
HP
ADC
HP
ADC
CAL
PLL
HPADC_RC
HPADC_FLASH
LPADC
LP
ADC
LP
ADC
Figure 102. Receiver Initial Calibration System Configuration
During receiver initial calibration, as shown in Figure 102, the data port is disabled to avoid sending data to baseband processor. This is
controlled by ADRV9001 ARM which requires no user interaction. Except for RX_RF_DC_OFFSET calibration, all other digital domain
calibration algorithms require injecting calibration tones generated internal by calibration PLL and injected internally at the Rx input.
For example, the RX_QEC_TCAL calibration routine sweeps a number of internally generated test tones across the desired frequency
band and then measures quadrature performance and calculates correction coefficients. Therefore, during Rx calibration, it is required to
not receiving any incoming signals from RF port which could interfere with the calibration tones. To ensure that, it is important to
isolate the device Rx input port from incoming signals by disabling LNA (or by switching off the external RF switch if no LNA presented
externally). This also prevents the calibrations tones from reaching antenna through RF coupling. 50Ω termination is needed to prevent
tone signals bouncing back from external LNA output and reaching Rx input confusing internal calibrations. The following paragraph
summarizes the external system requirement.
External system requirement: for optimal performance, and lower calibration duration, during Rx initial calibrations, the device Rx input
port should be isolated from incoming signals. For many Rx calibrations, the calibration tones will appear on the Rx pins, therefore, must
be prevented from reaching the antenna through the Rx port being properly terminated. This also prevents the calibrations tones from
reaching antenna through RF coupling. 50Ω termination is needed to prevent tone signals bouncing back from external LNA output and
reaching Rx input confusing internal calibrations.
Configure the Initial Calibrations Through TES
To achieve optimal performance, all initial calibrations should be enabled. However, the TES provides the capability to allow user to
disable some initial calibrations, mainly for debugging purpose. Table 45 summarizes a comparison for all initial calibrations in terms of
“User Override Capability”, “Run at Boot”, “Signal Utilized by Calibration”, “External Termination Needed” and “Dependency”. Some
initial calibrations need to be rerun after “LO changes more than a certain range (e.g. 100MHz) or divide by 2 boundary change”. The
information is currently not available and will be provided in the future after characterization.
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Table 45. Initial Calibration Comparison Summary
Initial Calibrations
Bits Enum
User
Override
Capability
Run at
Boot
Run After LO
Change <100
MHz and Run
when Not ÷2
Boundary
Change
Run after LO
Change
>100 MHz or
Run After ÷2
Boundary
Change
Signal Used
by Calibration
(Tones, Wide-
band, None)
External
Termination
Needed
Dependent on Which
Init Cals to be Run First
D0 TX_QEC Yes Yes TBD TBD Tone Yes TX_DAC, TX_BBAF, all RX
Init Cals on ILB, TX_LB_PD
D1 TX_LO_
LEAKAGE
Yes Yes TBD TBD Wideband Yes TX_DAC, TX_BBAF, all RX
Init Cals on ILB and ELB,
TX_LB_PD
D2 TX_LB_PD Yes Yes TBD TBD Wideband Yes TX_DAC, TX_BBAF,
RX_HPADC_RC,
RX_HPADC_FLASH,
RX_LPADC,
RX_TIA_CUTOFF,
RX_RF_DC_OFFSET
D3 TX_DDC No Yes TBD TBD Tone Yes None
D4 TX_BBAF No Yes TBD TBD Tone Yes None
D5 TX_BBAF_GD No Yes TBD TBD Tone Yes TX_BBAF, TX_QEC
D6 TX_ATTEN_
DELAY
No Yes TBD TBD Tone Yes TX_DAC, RX_HPADC_RC,
RX_HPADC_FLASH,
RX_LPADC
D7 TX_DAC No Yes TBD TBD None No None
D8 TX_PATH_DELAY Yes Yes TBD TBD Tone Yes TX_ATTEN_DELAY
D9 RX_HPADC_RC No Yes TBD TBD None No None
D10 RX_HPADC_
FLASH
No Yes TBD TBD None No None
D11 RX_HPADC_DAC Not
enabled
Not
enabled
Not enabled Not enabled Not enabled Not enabled Not enabled
D12 RX_DDC No Yes TBD TBD Tone Yes RX_TIA_CUTOFF
D13 RX_LPADC No Yes TBD TBD None No None
D14 RX_TIA_CUTOFF No Yes TBD TBD Tone Yes RX_HPADC_RC,
RX_HPADC_FLASH,
RX_LPADC
D15 RX_GROUP_DELAY No Yes TBD TBD Tone Yes RX_HPADC_RC,
RX_HPADC_FLASH,
RX_LPADC,
RX_TIA_CUTOFF
D16 RX_QEC_TCAL No Yes TBD TBD Tone Yes RX_HPADC_RC,
RX_HPADC_FLASH,
RX_LPADC,
RX_RF_DC_OFFSET,
RX_TIA_CUTOFF,
RX_GROUP_DELAY
D17 RX_QEC_FIC Yes Yes TBD TBD Tone Yes RX_HPADC_RC,
RX_HPADC_FLASH,
RX_LPADC,
RX_RF_DC_OFFSET,
RX_TIA_CUTOFF,
RX_GROUP_DELAY
D18 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
D19 RX_RF_DC_
OFFSET
Yes Yes TBD TBD None No RX_HPADC_RC,
RX_HPADC_FLASH,
RX_LPADC
D20 RX_GAIN_PATH_
DELAY
No Yes TBD TBD Tone Yes RX_HPADC_RC,
RX_HPADC_FLASH,
RX_LPADC
D21 PLL Not
enabled
Not
enabled
TBD TBD Not enabled Not enabled Not enabled
D22 AUXPLL Not
enabled
Not
Enabled
TBD TBD Not enabled Not enabled Not enabled
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For the optional initial calibrations, the TES provides the option to enable or disable those calibrations as shown in Figure 103. Note in
the current release, the configurable Tx initial calibrations are LO Leakage (TX_LO_LEAKAGE), Loop Path Delay (TX_LB_PD), QEC
(TX_QEC) and Duty Cycle Correction (external LO only) (TX_DDC). When TX_LO_LEAKAGE or TX_QEC is enabled, TX_LB_PD
must be enabled too. When “Tx Direct FM/FSK” mode is selected in DMR or AnalogFM profiles, TX_LO_LEAKAGE, TX_QEC and
TX_LB_PD calibrations are not used. Those options become unconfigurable in TES. TX_DDC is only applicable when external LO is
used for Tx. The configurable Rx initial calibrations are QEC frequency independent (RX_QEC_FIC), RFDC (RX_RF_DC_OFFSET)
and Duty Cycle Correction (external LO only) (RX_DDC). Similarly, RX_DDC is only applicable when external LO is used for Rx.
The initial calibrations are performed when user clicks “Program” button in TES. It takes some time to complete all the calibrations (The
calibration time is still under optimization.). When it is successful, the TES will show a status as “Programmed”. If not, it will show
“Programming Failed”. When “Programming Failed” happens, the user could try the “Program” again. If it continues to fail after
multiple attempts, as the next step, the user could enable/disable the optional initial calibrations to see if the problem could be related to
some calibrations. Similarly, when performance issues are observed during the test, the user could play with the optional initial
calibrations as a preliminary debug method. In the future TES releases, more configurable calibration options will be provided.
24159-104
Figure 103. Initial Tx/Rx Calibration Configuration through TES
TRACKING CALIBRATIONS
There are 14 different types of tracking calibrations, which can be classified into transmitter tracking calibrations and
receiver/observation receiver tracking calibrations:
• Transmitter tracking calibrations
• Quadrature Error Correction tracking calibration (QEC)
• Local Oscillator Leakage tracking calibration (LOL)
• Loopback path delay tracking calibration (LB PD) (currently not available)
• Power Amplifier Correction tracking calibration (PAC) (currently not available)
• Digital Pre-distortion tracking calibration (DPD)
• Close Loop Gain Control (CLGC) (currently not available)
• Receiver/observation receiver tracking calibrations
• Harmonic Distortion (2nd order) tracking calibration (HD2)
• Rx Quadrature Error Correction Wideband Poly tracking calibration (Rx QEC WBPLOY)
• ORx Quadrature Error Correction Wideband Poly tracking calibration (ORx QEC WBPLOY) (currently not available)
• Baseband DC offset tracking calibration (BBDC)
• RF DC tracking calibration (RFDC)
• Quadrature Error Correction Narrowband FIC tracking calibration (QEC FIC)
• Automatic Gain Control tracking calibration (AGC)
• RSSI tracking calibration (currently not available)
All the tracking calibrations are fully controlled by the ADRV9001ARM therefore no user interaction is required.
Tracking Calibrations API Programming
The ADRV9001 ARM in the device is tasked with scheduling/performing tracking calibrations to optimize the performance of the device
during its operation. Tracking calibrations are performed using the top-level API function adi_adrv9001_cals_Tracking_Set( ).
The tracking calibrations performed is based on the tracking calibration configuration defined by the following data structure:
typedef struct adi_adrv9001_TrackingCals
{
uint32_t chanTrackingCalMask[ADI_ADRV9001_MAX_RX_ONLY];
} adi_adrv9001_TrackingCals_t
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In this structure, chanTrackingCalMask[] is an array containing calibration bit mask for channel related tracking calibrations
(chanTrackingCalMask[0] is the mask for Rx1/Tx1 channels and chanTrackingCalMask[1] is the mask for Rx2/Tx2 channels ).
The following enumerator type defines all the initial calibrations:
typedef enum adi_adrv9001_TrackingCalibrations
{
ADI_ADRV9001_TRACKING_CAL_TX_QEC = 0x00000001,
ADI_ADRV9001_TRACKING_CAL_TX_LO_LEAKAGE = 0x00000002,
ADI_ADRV9001_TRACKING_CAL_TX_LB_PD = 0x00000004,
ADI_ADRV9001_TRACKING_CAL_TX_PAC = 0x00000008,
ADI_ADRV9001_TRACKING_CAL_TX_DPD = 0x00000010,
ADI_ADRV9001_TRACKING_CAL_TX_CLGC = 0x00000020,
/* Bit 6-7: Not used (Reserved for future purpose) */
ADI_ADRV9001_TRACKING_CAL_RX_HD2 = 0x00000100,
ADI_ADRV9001_TRACKING_CAL_RX_QEC_WBPOLY = 0x00000200,
/* Bit 10-11: Not used (Reserved for future purpose) */
ADI_ADRV9001_TRACKING_CAL_ORX_QEC_WBPOLY = 0x00001000,
/* Bit 13-18: Not used (Reserved for future purpose) */
ADI_ADRV9001_TRACKING_CAL_RX_BBDC = 0x00080000,
ADI_ADRV9001_TRACKING_CAL_RX_RFDC = 0x00100000,
ADI_ADRV9001_TRACKING_CAL_RX_QEC_FIC = 0x00200000,
ADI_ADRV9001_TRACKING_CAL_RX_AGC = 0x00400000,
ADI_ADRV9001_TRACKING_CAL_RX_RSSI = 0x00800000
/* Bit 24-31: Not used */
} adi_adrv9001_TrackingCalibrations_e
Table 46 describes the mask bit assignment for tracking calibrations in the “adi_adrv9001_TrackingCalibrations_e”. It also explains the
functionality of each tracking calibration. Note it is possible to select different mask for Channel 1 (Tx1/Rx1) and Channel 2 (Tx2/Rx2).
Table 46. Tracking Calibration Mask Bit Assignments
Bits Corresponding Enum Calibration Description
D0 ADI_ADRV9001_TRACKING_CAL_TX_QEC Tx QEC
Tracking
Calibration
This performs tracking QEC calibration for frequency
independent errors for the Tx path. It estimates the gain
and phase mismatch on-the-fly using the real-time traffic
data and apply the gain mismatch in the digital domain.
Similar as the initial calibration, currently it utilizes the Tx
path and an ILB path. If transmitted data is quadrature
modulated, this tracking calibration is performed, but it is
not used if the data modulation is direct modulation
(DM).
D1 ADI_ADRV9001_TRACKING_CAL_TX_LO_LEAKAGE Tx LOL
Tracking
Calibration
This performs tracking LOL calibration. It estimates the
LOL on-the-fly and applies the cancellation in the digital
domain. It utilizes the Tx path and an loopback path
(external loopback path preferred if available). If
transmitted data is quadrature modulated, this calibration
is performed, but it is not used if the data modulation is
direct modulation (DM).
D2 ADI_ADRV9001_TRACKING_CAL_TX_LB_PD
Tx Loop Back
Path Delay
Tracking
Calibration
This is used to track the Tx Loop Back Path Delay (could
be for either ILB or ELB) on-the-fly. This information is
required for QEC, LOL and DPD tracking calibrations.
Currently this tracking calibration is not available. QEC,
LOL and DPD tracking calibration utilize the delay
measurement obtained from Tx loopback path delay
initial calibration.
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Bits Corresponding Enum Calibration Description
D3 ADI_ADRV9001_TRACKING_CAL_TX_PAC Tx PAC
Tracking
Calibration
This is used to perform power amplifier correction.
Currently this tracking calibration in not available.
D4 ADI_ADRV9001_TRACKING_CAL_TX_DPD Tx DPD
Tracking
Calibration
This is used to pre-distort the transmit signal in real-time
to compensate for the power amplifier nonlinearity for
achieving higher power efficiency. Please refer to the
Digital Predistortion section in the User Guide for more
details.
D5 ADI_ADRV9001_TRACKING_CAL_TX_CLGC Tx CLGC
Tracking
Calibration
This is used to compensate for the power variation in
power amplifier. Currently this tracking calibration in not
available.
D6 Reserved
D7 Reserved
D8 ADI_ADRV9001_TRACKING_CAL_RX_HD2 Tx Path Delay
Initial
Calibration
This is used to correct the Rx 2nd order harmonic
distortion.
D9 ADI_ADRV9001_TRACKING_CAL_RX_QEC_WBPOLY Rx QEC WB
PLOY Tracking
Calibration
This is used to correct Rx frequency dependent
quadrature error for WB applications.
D10 Reserved
D11 Reserved
D12 ADI_ADRV9001_TRACKING_CAL_ORX_QEC_WBPOLY ORx QEC WB
Tracking
Calibration
This is used to correct ORx frequency dependent
quadrature error for WB applications. Currently this
tracking calibration in not available.
D13 Reserved
D14 Reserved
D15 Reserved
D16 Reserved
D17 Reserved
D18 Reserved
D19 ADI_ADRV9001_TRACKING_CAL_RX_BBDC Rx BBDC
Tracking
Calibration
This is used to mitigate the Rx DC offset at baseband on-
the-fly.
D20 ADI_ADRV9001_TRACKING_CAL_RX_RFDC Rx RFDC
Tracking
Calibration
This is used to mitigate the Rx DC offset at RF (analog) on-
the-fly.
D21 ADI_ADRV9001_TRACKING_CAL_RX_QEC_FIC Rx QEC FIC
Tracking
Calibration
This is used to correct Rx frequency independent
quadrature error for both NB and WB applications.
D22 ADI_ADRV9001_TRACKING_CAL_RX_AGC Rx AGC
Tracking
Calibration
This is used to enable/disable automatic Rx gain control
operation on-the-fly. By disabling it, AGC stops
responding to changes in the input signal and will instead
hold its last gain index.
D23 ADI_ADRV9001_TRACKING_CAL_RX_RSSI Rx RSSI
Tracking
Calibration
This is used to enable/disable Rx signal strength
measurement on-the-fly. Currently this tracking
calibration in not available.
External System Requirements for Tracking Calibrations
Different from initial calibrations, tracking calibrations are performed on-the-fly with real-time traffic data. Therefore, it is mostly
transparent to the users and fully controlled by the internal micro-processor. The external system requirements for users are as the
following:
• Make sure external paths are available when running some tracking calibrations on external loopback paths.
• When external loopback path after power amplifier is used (ELB2), a suitable attenuator must be chosen between the power
amplifier output and the observation channel input to prevent Tx output data from saturating the observation channel input.
• When external DPD is employed in the system, it should time share with other Tx tracking calibrations to avoid conflicts.
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For tracking calibrations, the TES provides the option to enable or disable those calibrations as shown in Figure 104. Note in the current
release, the configurable Tx tracking calibrations are digital pre-distortion (TX_DPD), LO Leakage (TX_LO_LEAKAGE) and QEC
(TX_QEC). When “Tx Direct FM/FSK” mode is selected in DMR or AnalogFM profiles, TX_LO_LEAKAGE and TX_QEC calibrations
are not applicable. Those options become unconfigurable in TES. The configurable Rx tracking calibrations are automatic gain control
(RX_AGC), baseband DC offset (RX_BBDC), (2nd order) harmonic distortion (RX_HD2), frequency independent QEC (RX_QEC_FIC)
and frequency dependent QEC for WB (RX_QEC_WBPOLY).
The tracking calibrations can be enabled or disabled on-the-fly when the device is operational.
24159-105
Figure 104. Tracking Tx/Rx Calibration Configuration Through TES
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RX GAIN CONTROL
The ADRV9001 receivers (Rx1/Rx2) feature automatic and manual gain control modes for flexible gain control in a wide array of
applications. It controls the gain at various stages of the Rx datapath to avoid overloading during the onset of a strong interferer. In
addition, it could ensure that the Rx digital output data is representative of the RMS power of the Rx input signal so that any internal
front-end gain changes to avoid overloading are transparent to the baseband processor.
In ADRV9001, the two gain control modes are named Automatic Gain Control (AGC) and Manual Gain Control (MGC). AGC allows
for receivers to autonomously adjust the receiver gain depending on variations of the input signal. It controls the gain of the device based
on the information from a number of signal detectors named peak detector and power detector. The receivers are also capable of
operating in MGC mode where changes in gain are initiated by the baseband processor through API commands or Digital GPIO
(DGPIO) pins. In the MGC mode, by enabling the signal detectors, baseband processor could optionally utilize the information provided
from signal detectors through Digital GPIO (DGPIO) pins to properly control the gain.
The gain control is highly flexible and can be configured differently in various scenarios. For example, for BTS receivers, the received
signal is a multi-carrier signal in most cases. A gain change should be performed only under large over range or under range conditions
and gain changes should not occur very often for typical 3G/4G operations. In such a case, it might be sufficient to use peak detectors.
Nevertheless, if an asynchronous blocker does appear, a “fast attack” mode exists which could reduce the gain at a fast rate. As another
example, to support GSM blockers and radar pulses which have fast rise and rapid fall times, a “fast attack and fast recovery” mode can
be employed. This mode is capable of fast recovery in addition to the fast attack as mentioned earlier.
Section Topics
The list of topics reviewed in detail are found in the following sections:
• Receiver Data Path: This section outlines the gain control and signal observation elements of the receiver chain, followed by a
description of the receiver gain table concept.
• Gain Control Modes: This section advises how to select between AGC and MGC mode, followed by a detailed description of how to
operate in each mode. In AGC mode, peak detect mode and peak/power detect mode will be further discussed and compared.
• Gain Control Detectors: This section outlines the operation and configuration of various gain control detectors in the device.
• AGC Clock and Gain Block Timing: This section describes the speed of the AGC clock and the various gain event and delay timers.
• Analog Gain Control API Programming: This section outlines how to configure the analog gain control using API commands,
explaining each parameter of the API structures. It also provides a summary of all API functions currently supported.
• Digital Gain Control and Interface Gain (Slicer): This section outlines the various forms of digital gain control available in the
ADRV9001.
• Digital Gain Control and Interface Gain API Programming: This section outlines how to configure the digital gain control and
interface gain using API commands, explaining each parameter of the API structures. It also provides a summary of all API
functions currently supported.
• Usage Recommendations: This section provides a list of recommended gain control configurations to achieve optimal performance.
• TES Configuration and Debug Information: This section advises user how to configure Rx gain control functionality through TES
and perform simple debugging when some gain control performance problems are encountered.
Important Terminology
A list of important terms used in following sections are summarized below:
Manual Gain Control (MGC)
This term is used to refer to a use case when the user is in control of the currently applied gain settings in the receiver chain.
Automatic Gain Control (AGC)
This term is used to refer to the device’s own internal AGC, where the device is in control of the receiver gain settings. If the user does
not use the internal AGC, then it is expected that an AGC would run in the baseband processor. However, in this document such a case
would be referred to as MGC because the gain of the receive path is under user’s control.
Gain Attack
This term is used to indicate the reduction of the receiver gain due to an overloaded signal path.
Gain Recovery
This term is used the indicate the increase of the receiver gain due to a reduction in the power of the signal being received.
Preliminary Technical Data UG-1828
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Gain Compensation
The process of compensating for the analog attenuation in the device (prior to the ADC) with a corresponding amount of digital gain
before the digital signal is sent to the user.
High Threshold
This threshold is used to trigger gain attack event. Some detectors could have multiple high thresholds.
Low Threshold
This threshold is used to trigger gain recovery event. Some detectors could have multiple low thresholds.
Threshold Overload
When a threshold is exceeded in a signal detector, this is referred to as an overload.
Threshold Underload
When a threshold is not exceeded in a signal detector, this is referred to as an underload.
Overrange Condition
An overrange condition exists when the AGC is required to reduce the gain. This can either be a peak condition, where a programmable
number of individual overloads of a high threshold have occurred within a defined period of time, or a power condition, where the
measured power exceeds a high power threshold.
Underrange Condition
An underrange condition exists when the AGC is required to increase the gain. This can either be a peak condition, where a lower
threshold is not exceeded a programmable number of times within a defined period of time, or a power condition, where the measured
power does not exceed a low power threshold.
RECEIVER DATAPATH
Figure 105 shows the simplified Rx datapath and gain control blocks. The receivers have front end attenuators prior to the mixer stage
that are used to attenuate the signal in the analog domain to ensure the signal does not overload the receiver chain. Note ADRV9001
provides about 20dB gain so the front end gain attenuator further attenuates signal from that level. In the digital domain, there is also
digital gain control capability.
As shown in this figure, the receiver chain has a number of observation elements that can monitor the incoming signal. These can be
used in either MGC or AGC mode. Firstly, an Analog Peak Detector (APD) exists prior to ADC. Being in the analog baseband, this peak
detector will see signals first, and will also have visibility of interfering signals which can overload the ADC but could be filtered as they
progress through the digital chain. The second peak detector is called the HB Peak Detector since it monitors the data at the output of the
Half Band (HB) Filtering block in the receiver chain.
A power measurement detection block is also provided at the same output of HB Filtering block which takes the RMS power of the
received signal over a configurable period of time.
Besides the front end gain control, this device could also control an external gain element through analog GPIO (AGPIO) pins (currently
not supported). In the digital domain, this device can further control the digital gain in both wideband (WB) and narrowband (NB)
modes. To avoid saturate the output signal due to the limitation of the bit width of data port, an optional interface gain (slicer) is applied
at the end of the datapath by properly shifting the data. The interface gain could be automatically controlled internally inside the device
by utilizing the information provided from the Receiver Signal Strength Indicator (RSSI) block or manually controlled by users through
API command.
The gain control block is shown with multiple inputs providing information shown in purple solid lines. Peak detectors are shown in
brown and the power detector is shown in blue. The gain control block controls the gain of the signal chain using a predefined gain table.
Note the default gain table is loaded into the device during initialization. An API function adi_adrv9001_Rx_GainTable_Write() can be
called by the user to load a custom gain table or reconfigure the gain table. Note this operation should be done before performing initial
calibrations.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 122 of 253
WB/NB DECI M ATION
(DECIMATION
STAGE 2)
HB FILTERING
(DECIMATION
STAGE 1) INTERFACE
GAIN
(SLICER)
LVDS/CMOS
API
API DGPIO(S)
RSSI
HB PEAK
DETECTOR POWER
DETECTOR
ANALOG
PEAK
DETECTOR
GAIN CONTROL BLOCK
(AG C, MGC)
FRO NT END
ATTENUATOR
MUX
DIGITAL
GAI N CONT ROL
ADC
TIA
GAIN
EXTERNAL
GAIN
GAIN
24159-106
Figure 105. Rx Data Path and Gain Control Blocks
In this gain table, each row provides a unique combination of 6 fields including Front-end Attenuator, TIA Control, ADC Control,
External Gain Control, Phase Offset and Digital Gain/Attenuator. Among them, the TIA Control which sets the TIA gain, the ADC
Control which sets the ADC gain and the Phase Offset which compensates for the phase discontinuity during gain change are reserved
for future use.
Based on the row of this table selected, either by the user in MGC mode, or automatically by the device in AGC mode, the gain control
block updates the variable gain elements depicted by the orange dash lines. In the MGC mode, the user can control the gain control block
using the API commands and DGPIOs.
Table 47 shows the first three and last three rows in a sample gain table.
Table 47. Sample Rows from the Default Rx Gain Table
Gain Table
Index
Front-End Attenuator
Control Word [7:0]
TIA
Control
ADC
Control
External Gain
Control [1:0]
Phase
Offset
Digital Gain/Attenuator
Control Word
[10:0]
183 252 0 0 0 0 25
184 252 0 0 0 0 35
185 251 0 0 0 0 -7
… … … … … … …
253 28 0 0 0 0 -2
254 14 0 0 0 0 -1
255 0 0 0 0 0 0
The gain table index is the reference for each unique combination of gain settings in the programmable gain table. The possible range of
the gain table is 183 to 255. The gain index region is user configurable. An API function adi_adrv9001_Rx_MinMaxGainIndex_Set()
could be called by the user right after loading the gain table to load multiple gain table regions and switch between multiple gain table
regions during runtime.
Note the External Gain Control which sets the external gain is not supported currently. It is used to control two AGPIO pins for each Rx.
Depending on the hardware register setting, the AGPIO pins for Rx1 and Rx2 can be selected from AGPIO[3:0], AGPIO[7:4] and
AGPIO[11:8]. Table 48 shows an example of Rx1 and Rx2 external gain element control when AGPIO[0:3] is selected (Note it is also
possible to use AGPIO[1:0] for Rx2 and AGPIO[3:2] for Rx1. Please refer to GPIO section in the User Guide for more information.).
Table 48. An Example of Analog GPIOs for External Gain Element Control
Receiver AGPIO Pins to Control External Gain Element
Rx1 AGPIO[1:0]
Rx2 AGPIO[3:2]
These AGPIOs must be enabled as outputs and set for external gain functionality. The 2-bit value programmed is directly related to the
status of these AGPIO pins, for example if the external gain word of the Rx1 gain table is programmed to 3 in selected gain index, then
AGPIO[0] and AGPIO[1] will be high if AGPIO[1:0] is used to control external gain element as the example show in Figure 106.
Preliminary Technical Data UG-1828
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EXTERNAL
ATTENUATOR
Rx1
AGPIO[0]
AGPIO[1]
24159-107
Figure 106. AGPIO Control of an External Gain Element to Rx1
The 2 fields which are used in the gain table are the Front-end Attenuator and the Digital Gain/Attenuator. The Front-end Attenuator is
an 8-bit control word. The amount of attenuation applied depends on the value set in this column of the selected gain table index. The
following equation provides an approximate relationship between the internal attenuator and the front-end attenuation value
programmed in the gain table, N:
The Digital Gain/Attenuator column is used to apply gain or attenuation digitally. The 11-bit signed word defines the digital gain
applied, which equals to the control word times 0.05 in dB. As shown in Table 47, for gain index 253, the digital gain can be calculated as
-2*0.05 = -0.1dB.
2 Types of Rx gain tables are provided. One is for gain correction in which the digital gain is for correcting the small step size inaccuracy
in the Front-end Attenuator. The other is for gain compensation which compensates the entire front-end attenuation. The example
shown in Table 47 stands for a Rx gain correction table. In the Receiver/Observation Receiver Signal Chain Section of this User Guide, it
mentions that Rx can also be used as ORx for signal observation. Note another gain table exists for ORx gain control. However, for ORx
gain control, there is no AGC mechanism but only MGC. In addition, the digital gain is only for gain correction.
GAIN CONTROL MODES
The gain control mode is selected through the API function adi_adrv9001_Rx_GainControl_Mode_Set() for a specified channel. Please
refer to API doxygen document for more details.
adi_adrv9001_RxGainControlMode_e is an enum for selecting the gain mode. The possible options are shown in Table 49.
Table 49. Definition of adi_adrv9001_RxGainControlMode_e
ENUM Gain Mode
ADI_ADRV9001_RX_GAIN_CONTROL_MODE_SPI Manual Gain Control SPI Mode
ADI_ADRV9001_RX_GAIN_CONTROL_MODE_PIN Manual Gain Control PIN Mode
ADI_ADRV9001_RX_GAIN_CONTROL_MODE_AUTO
Automatic Gain Control Mode
adi_common_ChannelNumber_e is an enum which indicates which Rx channel is used:
Table 50. Definition of adi_common_ChannelNumber_e
ENUM Rx channel
ADI_CHANNEL_1 Rx1
ADI_CHANNEL_2 Rx2
Automatic Gain Control (AGC)
In Automatic Gain Control (AGC) mode, a built-in state machine automatically controls the gain based on user defined configuration.
The AGC can be configured to one of two modes:
• Peak Detect mode, where only the peak detectors are used to make gain changes.
• Peak/Power Detect mode, where information from both the power detector and the peak detectors are used jointly to make gain
changes.
Peak Detect Mode
In this mode, the peak detectors alone are used to inform the AGC to make gain changes. This section explains the basic premise of the
operation, while more explicit details of configuring the peak detectors is covered in subsequent sections.
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The APD and HB detector both have a high threshold and a low threshold, apdHighTresh, apdLowThresh, hbHighTresh and
hbUnderRangeHighThresh, respectively. These levels are user programmable, as well as the number of times a threshold needs to be
exceeded for an over range condition to be flagged.
The high thresholds are used as limits on the incoming signal level and will principally be set based on the maximum input of the ADC.
When an over range condition occurs, the AGC will reduce the gain (gain attack). The low thresholds are used as lower limits on signal
level. When an under range condition occurs, the AGC will increase the gain (gain recovery). The AGC stable state (where it will not
adjust gain) occurs when neither an under range nor over range condition is occurring.
Each overrange/underrange condition has its own attack and recovery gain step as shown in Table 51.
Table 51. Peak Detector Gain Steps
Over Range/Under Range Gain Step
apdHighThresh over range Reduce gain by apdGainStepAttack
apdLowThresh under range Increase gain by apdGainStepRecovery
hbHighThresh over range Reduce gain by hbGainStepAttack
hbUnderRangeHighThresh under range Increase gain by hbGainStepHighRecovery
An overrange condition occurs when the high thresholds have been exceeded a configurable number of times within a configurable
period. An underrange condition occurs when the low thresholds have not been exceeded a configurable number of times within the
same configurable period. These counters make the AGC less sensitive to occasional peaks in the input signal, ensuring that a single peak
exceeding a threshold does not necessarily cause the AGC to react. Table 52 outlines the counter parameters for the individual
overload/under range conditions.
Table 52. Peak Detector Counter Values
Over Range/Under Range Counter
apdHighTresh over range apdUpperThreshPeakExceededCnt
apdLowThresh under range apdLowerThreshPeakExceededCnt
hbHighThresh over range hbUpperThreshPeakExceededCnt
hbUnderRangeHighThresh under range hbUnderRangeHighThreshExceededCnt
The AGC uses a gain update counter to time gain changes, with gain changes made when the counter expires. The counter value, and
therefore the time spacing between possible gain changes, is user programmable through the agcGainUpdateCounter parameter. The
user specifies the period, in AGC clock cycles, that gain changes can be made. Typically, this might be set to frame or sub-frame
boundary periods.
Once the gain update counter expires all the peak threshold counters are reset. The gain update period is therefore a decision period. The
overload thresholds and counters are therefore set based on the number of overloads considered acceptable for the application within the
gain update period.
Figure 107 shows an example of the AGC response to a signal versus the APD or HB peak detector threshold levels. APD and HB
detector works in the same fashion in this mode. For ease of explanation, only APD is mentioned in the following discussions. The green
line is representative of the peaks of the signal. Initially the peaks of the signal are within the apdHighThresh and apdLowThresh. No
gain changes are made. An interferer suddenly appears whose peaks now exceed apdHighThresh. On the next expiry of the gain update
counter (assuming a sufficient number of peaks occurred to exceed the counter), the AGC decrements the gain index (reduces the gain)
by apdGainStepAttack. This isn’t sufficient to get the signal peaks within the threshold levels, and hence the gain is decremented once
more, with the peaks now between the two thresholds. The gain is stable in this current gain level until the interferer is removed, and the
peaks of the desired signal are now below the apdLowThresh which results in an under range condition. Hence the AGC increases gain
by the apdGainStepRecovery at the next expiry of the gain update counter, continuing to do so until the peaks of the signal are within the
two thresholds once more.
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SIGNAL
LEVEL
apdHighThresh/
hbHighTresh
INTERFERER
PRESENT
INTERFERER
REMOVED
GAIN DECREMENT
(apdGainStepAttack/
hbGainStepAttack)
GAIN UPDATE
PERIOD
GAIN INCREM ENT
(apdGainStepRecovery/
hbGainStepHighRecovery)
GAIN INCREM ENT
(apdGainStepRecovery/
hbGainStepHighRecovery)
GAIN DECREMENT
(apdGainStepAttack/
hbGainStepAttack)
apdLowThresh/
hbUnderRangeHighTresh
24159-108
Figure 107. APD/HB Thresholds and Gain Changes Associated with Underrange and Overrange Conditions
It is possible to enable a fast attack mode whereby the AGC is instructed to reduce gain immediately when an over range condition
occurs, instead of waiting until the next expiry of the gain update counter using changeGainIfThreshHigh. This parameter has
independent controls for the APD and HB detectors. Values from 0-3 are valid as shown in Table 53.
Table 53. changeGainIfThreshHigh Settings
changeGainIfThreshHigh[1:0] Gain Change following APD Over range Gain Change following HB Overrange
00 After expiry of gainUpdateCounter After expiry of gainUpdateCounter
01 After expiry of gainUpdateCounter Immediately
10 Immediately After expiry of gainUpdateCounter
11 Immediately Immediately
Figure 108 shows how the AGC reacts when the changeGainIfThreshHigh is set for APD or HB detector. In this case when the interferer
appears, the gain is updated as soon as the number of peaks exceed the peak counter. It does not wait for the next expiry of the gain
update counter. Hence a number of gain changes can be made in quick succession providing a much faster attack than the default
operation. The assumption here is that if the ADC is overloaded then it is best to decrease the gain quickly rather than wait for a suitable
moment in the received signal in order to change the gain. This mode is referred as “fast attack” mode.
SIGNAL
LEVEL
apdHighThresh/
hbHighTresh
INTERFERER
PRESENT
INTERFERER
REMOVED
GAIN INCREM ENT
(apdGainStepRecovery/
hbGainStepHighRecovery)
GAIN INCREM ENT
(apdGainStepRecovery/
hbGainStepHighRecovery)
GAIN DECREMENT
(apdGainStepAttack/
hbGainStepAttack)
GAIN DECREMENT
(apdGainStepAttack/
hbGainStepAttack)
GAIN UPDATE
PERIOD
apdLowThresh/
hbUnderRangeHighTresh
24159-109
Figure 108. APD/HB Gain Changes with Fast Attack Enabled
Besides the “fast attack” mode, it is also possible to enable a “fast recovery” mode. This functionality is enabled with the
enableFastRecoveryLoop parameter.
This “fast recovery” mode only works with the HB detector. The operation is illustrated in Figure 109. In this mode, the “fast recovery” is
achieved by utilizing multiple low thresholds and step sizes as well as the update periods. When the signal level falls below
hbUnderRangeLowThresh, the lowest threshold, the gain is incremented the most by hbGainStepLowRecovery following the expiry of a
gain update period. Note that in the “fast recovery” mode the agcUnderRangeLowInterval is used instead of the gain update counter to
set the gain update period (This also applies to the APD.). After sufficient gain increases to bring the signal level above
hbUnderRangeLowThresh, the gain is incremented by hbGainStepMidRecovery after the expiry of agcUnderRangeMidInterval, which is
a multiple of agcUnderRangeLowInterval. Finally, when the signal level is increased above hbUnderRangeMidThresh, the gain is
UG-1828 Preliminary Technical Data
Rev. PrA | Page 126 of 253
incremented by hbGainStepHighRecovery following the expiry of agcUnderRangeHighInterval, which is a multiple of
agcUnderRangeMidInterval.
The multiple thresholds and interval parameters allow for faster gain recovery. Typically, agcUnderRangeHighInterval could be set to
gain update counter as shown in Figure 109. Therefore, when the signal level is below the mid and low thresholds, the recovery could
happen multiple times within a single gain update counter, which makes the recovery much faster. Note in “fast recovery” mode, gain
recovery might not always happen at the expiry of the gain update counter, which is different from the mode without “fast recovery”. If
the gain update counter is set to align with the frame or subframe boundary, it is possible that a fast recovery could happen in the middle
of a frame or subframe. Therefore, it is recommended to not use “fast recovery” mode when there is a stringent requirement for keeping
a constant gain for an entire frame or subframe.
SIGNAL
LEVEL hbHighTresh
hbUnderRangeHighTresh
hbUnderRangeMidTresh
hbUnderRangeLowTresh
INTERFERER
PRESENT
INTERFERER
REMOVED
GAIN INCREM ENT
(hbGainStepHighRecovery)
GAIN INCREM ENT
(hbGainStepLowRecovery)
agcUnderRangeLowInterval
agcUnderRangeMidInterval
agcUnderRangeHighInterval
GAIN INCREM ENT
(hbGainStepMidRecovery)
24159-110
Figure 109. AGC operation with HB Detector in Fast Recovery Mode
It is highly recommended that the apdHighThresh and hbHighThresh are set to an equivalent dBFS value. Likewise, it is highly
recommended that the apdLowThresh and the hbUnderRangeHighThresh are set to equivalent values. This equivalence will be
approximate, as these thresholds have unique threshold settings and will not be exactly equal. This section discusses the relevant
priorities between the detectors and how the AGC reacts when multiple threshold detectors have been exceeded. Table 55 shows the
priorities between the detectors when multiple overranges occur.
Table 54. Priorities of Attack Gain Steps
apdHighThresh Over Range hbHighThresh Over Range Gain Change
No No No Gain Change
No Yes Gain Change by hbGainStepAttack
Yes No Gain Change by apdGainStepAttack
Yes Yes Gain Change by apdGainStepAttack
For recovery, the number of thresholds is dependent on whether fast recovery is enabled or not. Considering the fast recovery scenario,
the priority of the thresholds is:
1. hbUnderRangeLowThresh Underrange Condition
2. hbUnderRangeMidThresh Underrange Condition
3. hbUnderRangeHighThresh Underrange Condition
4. apdLowThresh Underrange Condition
Upon one underrange condition, the AGC changes the gain by the corresponding gain step size of this condition. However, if multiple
conditions occur simultaneously, then the AGC prioritizes based on the priorities indicated; that is, if hbUnderRangeLowThresh is
reporting an under range condition then the AGC will adjust the gain by hbGainStepLowRecovery with two exceptions.
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The apdLowThresh has priority in terms of preventing recovery. If apdLowThresh reports an over range condition (sufficient signal
peaks have exceeded its threshold in a gain update counter period), then no further recovery is allowed. apdLowThresh and
hbUnderRangeHighThresh should be configured to be as close to the same value of dBFS, but assuming some small difference between
the thresholds, then as soon as apdLowThresh is exceeded recovery will no longer occur. The reverse is not true,
hbUnderRangeHighThresh will not prevent the gain recovery towards the apdLowThresh. Given the strong recommendation that
apdLowThresh and hbUnderRangeHighThresh being set equally, then a condition whereby apdLowThresh was at a lower dBFS level to
hbUnderRangeLowThresh or hbUnderRangeMidThresh should not occur.
Another exception is if the recovery step size for a detector is set to zero. If so, the AGC makes the gain change of the highest priority
detector with a non-zero recovery step. Figure 110 provides a flow diagram of the decisions of the AGC when recovering the gain in peak
detect mode.
GAI N RE COVE RY
IF
apdLowThresh
under-range
IF
hbUnderRangeLowThresh
under- rang e AND
hbGainStepLowRecovery
NOT 0
IF
hbUnderRangeMidThresh
under- rang e AND
hbGainStepMidRecovery
NOT 0
IF
hbUnderRangeHighThresh
under- rang e AND
hbGainStepHighRecovery
NOT 0
IF
apdLowThresh under-range
AND apdGain S t epRecovery
NOT 0
END
RECOV E RY GAI N BY
hbGainStepLowRecovery
RECOV E RY GAI N BY
hbGainStepMidRecovery
RECOV E RY GAI N BY
hbGainStepHighRecovery
RECOV E R GAI N BY
apdGainStepRecovery
NY
Y
Y
Y
Y
N
N
N
N
24159-111
Figure 110. Flow Diagram for AGC Recovery in Peak Detect AGC Mode
Peak/Power Detect Mode
In this mode, the peak and power detect work jointly to control the gain of the Rx chain. In the event of an over-range condition, then
both the peak and the power detect can instantiate a gain decrement. In the event of an under-range, only the power detect can
increment the gain. The power detector will change gain solely at the expiry of the gain update counter. As previously mentioned, the
peak detect can be set in one of two modes (depending on the setting of gainChangeIfThreshHigh) whereby the AGC: 1) waits for the
gain update counter to expire before initiating a gain change; or 2) immediately updates the gain as soon as the overrange condition
occurs (see Figure 107 and Figure 108). Therefore, in the peak/power detect mode, if the gain attack is instantiated by peak detectors, it is
possible to perform fast attack.
The power detect provides the RMS power measurement of the receiver data at the output of HB Filtering block. In power detect mode,
the AGC compares the measured signal level to programmable thresholds which provide a 2nd order control loop, whereby gain can be
UG-1828 Preliminary Technical Data
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changed by larger amounts when the signal level is farther from the target level while make smaller gain changes when the signal is closer
to the target level. This could allow the gain change faster when the level is farther away from the targeted range.
Figure 111 shows the operation of the AGC when using the power detect. Considering the power detect in isolation from the peak
detectors, the AGC will not modify the gain when the signal level is between overRangeLowPowerThresh and
underRangeHighPowerThresh. This range is the target range for the power measurement. The associated thresholds are also called inner
thresholds.
When the signal level goes below underRangeLowPowerThresh, the AGC waits for the next gain update counter expiry and then
increments the gain by underRangeLowPowerGainStepRecovery. When the signal level is greater than underRangeLowPowerThresh but
below underRangeHighPowerThresh, the AGC will increment the gain by underRangeHighPowerGainStepRecovery. Likewise, when the
signal level goes above overRangeHighPowerThresh, the AGC decreases the gain by overRangeHighPowerGainStepAttack, and when the
signal level is between overRangeHighPowerThresh and overRangeLowPowerThresh, the AGC will decrease the gain by
overRangeLowPowerGainStepAttack. underRangeLowPowerThresh and overRangeHighPowerThresh are also called outer thresholds.
SIGNAL
LEVEL
NO GAIN CHANG E
GAIN
DECREMENT
GAIN
DECREMENT
GAIN UPDATE
PERIOD
GAIN
INCREMENT
RECEIVED
SIGNAL LEVEL
CHANGE
POWER
MEASUREMENT
DURATION
GAIN
INCREMENT
underRangeHighPowerTresh
underRangeLowPowerTresh
overRangeHighPowerTresh
overRangeLowPowerTresh
INCREMENT GAIN BY
underRangeHighPowerGainStepAttack
INCREMENT GAIN BY
underRangeLowPowerGainStepAttack
DECREME NT GAIN BY
overRangeLowPowerGainStepAttack
DECREME NT GAIN BY
overRangeHighPowerGainStepAttack
RECEIVED
SIGNAL LEVEL
CHANGE
24159-112
Figure 111. PMD Thresholds and Gain Changes for Under-range and Over-range Conditions
It is possible for the AGC to get contrasting requests from the power and peak detectors. An example would be an interferer that is
visible to the analog peak detector but is significantly attenuated at the power detector. In this case the APD could be requesting a gain
decrement, while the power detector could be requesting a gain increment. The AGC has the following priority scheme in peak/power
detect mode:
1. APD Overrange
2. HB Overrange
3. APD lower level peak exceeded
4. HB lower level peak exceeded
5. Power Measurement
In this example, the gain would be decremented because the APD over-range has a higher priority than the power measurement.
However, APD and HB lower level overloads act differently in peak detect and peak/power detect mode. In peak detect mode, the lower
level thresholds for these detectors are used to indicate an under-range condition which caused the AGC to increase the gain. In
peak/power detect mode, these detectors are not used for gain recovery, but used to control gain recovery by setting the API parameter,
lowThreshPreventGainInc. If this parameter is set, and if the signal level is exceeding a lower level threshold, the AGC is prevented from
increasing the gain regardless of the power measurement.
When a signal has higher than expected Peak to Average Power Ratio (PAR), the power detector could indicate a gain increase while the
peak detector low threshold could still be exceeded. In such a case, gain increase will be prevented to avoid an overloading possibility. In
addition, this could prevent an oscillation condition that could otherwise occur to an interferer visible to APD but filtered before the
power detect. In such a case, the peak detect could cause the AGC to decrease gain. It would do this until the interferer is no longer
exceeding the defined threshold. At this point, the power detect could request an increase in gain and would do so until the detector’s
peak threshold is exceeded. This might cause an oscillation condition. By using these lower level thresholds of peak detect, the AGC is
prevented from increasing gain as the signal level approaches an overload condition, providing a stable gain level for the Rx chain under
such a condition.
Preliminary Technical Data UG-1828
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Peak Detect and Peak/Power Detect Mode Comparison
Among the two detect modes, peak detect offers the quickest response time to overload signals by employing “fast attack” mode. It allows
the AGC to respond within hundreds of nanoseconds in overload scenarios. In addition, the peak detect also provides “fast recovery”
option to increase the gain of the desired signal quickly when an interferer disappears. It can also avoid the possible gain index oscillation
issue of peak/power detect when the signal has higher than expected PAR.
With power detect, the gain change can only happen at the expiration of gain update counter, which is typically set at the order of
hundreds of microseconds or milliseconds. However, the power detector is usually more stable and will not likely cause frequent gain
changes. In addition, it can provide a tighter control of signal level by utilizing a set of inner and outer thersholds comparing with peak
detect.
It is highly recommended to use peak detect especially when fast gain control is desired.
Manual Gain Control (MGC)
The gain control block applies the settings from the selected gain index in the gain table. In MGC mode, the baseband processor is in
control of selecting the gain index. There are two options: 1) API commands (ADI_ADRV9001_RX_GAIN_CONTROL_MODE_SPI);
and 2) pin control (ADI_ADRV9001_RX_GAIN_CONTROL_MODE_PIN). By default, if MGC is chosen the part is configured for API
commands.
In API command mode, the user selects a gain index in the gain table through the API function adi_adrv9001_Rx_Gain_Set(). The gain
index selected for a channel can be read back through the API function adi_adrv9001_Rx_Gain_Get().
The pin control MGC mode is useful when real time control of gain is required. API command
adi_adrv9001_Rx_GainControl_PinMode_Configure() can be used to properly configure this mode. In this mode, out of 16 digital
DGPIO pins, 2 pins per receiver are used, one increasing and the other decreasing the gain table index. The user specifies both the max
and min gain index as well as the increment and decrement step size (in the range of 0 to 7 gain table indices). A pulse is applied to the
relevant DGPIO pin to trigger an increment or decrement in gain as shown in Figure 112. This pulse must be held high for at least 2
AGC clock cycles for a reliable detection of the rising edge to trigger the gain change (see AGC clock section for details). The
configuration data structure for this mode is defined as the following:
typedef struct adi_adrv9001_RxGainControlPinCfg
{
uint8_t minGainIndex; //Minimum gain index. Must be >= gainTableMinGainIndex and <
maxGainIndex
uint8_t maxGainIndex; //Maximum gain index. Must be > minGainIndex and <=
gainTableMaxGainIndex
uint8_t incrementStepSize; //Number of indices to increase gain on rising edge on
incrementPin (Range: 0 to 7)
uint8_t decrementStepSize; //Number of indices to decrease gain on rising edge on
decrementPin (Range: 0 to 7)
adi_adrv9001_GpioPin_e incrementPin;// A rising edge on this pin will increment gain by
incrementStepSize.
adi_adrv9001_GpioPin_e decrementPin; //A rising edge on this pin will decrement gain by
decrementStepSize.
} adi_adrv9001_RxGainControlPinCfg_t
Rx1
Rx1
Rx2
DGPIO[a]
DGPIO[b]
DGPIO[c]
DGPIO[d]Rx2
24159-113
Figure 112. MGC PIN Mode: DGPIO (a to d) Represent Any of DGPIO[0:15]
In the MGC mode, to properly control the gain, user could optionally retrieve the status of peak detectors and power detector in the
device through a set of DGPIO pins (this could also be done in the AGC mode for observation). In order to make sure that the status
information from the signal detectors are meaningful, it is important that the user should first enable and configure the signal detectors
UG-1828 Preliminary Technical Data
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properly, which can be done through API command. The feedback information can be configured into 2 modes, the peak detect mode
and peak and power detect mode. In peak detect mode, the over-range and under-range conditions of both APD and HB detectors will
be provided through DGPIO pins to user. In peak and power detect mode, over-range and under-range conditions of power detector,
over-range and under-range condition of APD will be provided through DGPIO pins to user.
Table 55 describes feedback configuration and the bitfield definition and position. For example, when it is configured in peak mode, the
user could connect to a set of DGPIO pins to retrieve all the APD and HB detector status. Note the DGPIO pins could be selected from
pin 0 to pin 15 and 2 consecutive DGPIO pins should always be configured as a pair to retrieve 2 consecutive bitfields (bit 0&1 or bit 2&3
in both modes). DGPIO pin selection is defined by the following enum type:
typedef enum adi_adrv9001_GpioPinCrumbSel
{
ADI_ADRV9001_GPIO_PIN_CRUMB_UNASSIGNED,
ADI_ADRV9001_GPIO_PIN_CRUMB_01_00,
ADI_ADRV9001_GPIO_PIN_CRUMB_03_02,
ADI_ADRV9001_GPIO_PIN_CRUMB_05_04,
ADI_ADRV9001_GPIO_PIN_CRUMB_07_06,
ADI_ADRV9001_GPIO_PIN_CRUMB_09_08,
ADI_ADRV9001_GPIO_PIN_CRUMB_11_10,
ADI_ADRV9001_GPIO_PIN_CRUMB_13_12,
ADI_ADRV9001_GPIO_PIN_CRUMB_15_14,
} adi_adrv9001_GpioPinCrumbSel_e
In both peak mode and peak and power mode, a pair of bits (bit 0&1 or bit 2&3) can choose any one pair of GPIO pins defined in
“adi_adrv9001_GpioPinCrumbSel_e”. If “ADI_ADRV9001_GPIO_PIN_CRUMB_UNASSIGNED” is selected, it means no GPIO pins
assigned so the corresponding bitfields cannot be observed by user. The DGPIO pins can be associated with either one of the receivers
Rx1 or Rx2.
Table 55. DGPIO Configuration for Retrieving Signal Detector Information
Mode Bit Field Definition
Feedback Mask Bit
Position
Peak Mode hb_low_threshold_counter_exceeded (low threshold has been exceeded counter times, no
under load condition)
0
apd_low_threshold_counter_exceeded
(low threshold has been exceeded counter times, no under load condition)
1
hb_high_threshold_counter_exceeded
(high threshold has been exceeded counter times, over load condition)
2
apd_high_threshold_counter_exceeded
(high threshold has been exceeded counter times, over load condition)
3
Peak and Power
Mode
power_inner_low_threshold_exceeded (inner low threshold exceeded, no under load
condition)
0
power_inner_high_threshold_exceeded
(inner high threshold exceeded, over load condition)
1
apd_low_threshold_counter_exceeded
(low threshold has been exceeded counter times, no under load condition)
2
apd_high_threshold_counter_exceeded
(high threshold has been exceeded counter times, over load condition)
3
Preliminary Technical Data UG-1828
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GAIN CONTROL DETECTORS
In this section, three gain control detectors will be discussed in more details.
Analog Peak Detector (APD)
The analog peak detector is located in the analog domain following the TIA filter and prior to the ADC input (see Figure 105). It
functions by comparing the signal level to programmable thresholds. When a threshold has been exceeded a programmable number of
times in a gain update period, then the detector flags that the threshold has been overloaded.
apdLowThresh (mV)
apdHighThresh (mV)
t
24159-114
Figure 113. Analog Peak Detector Thresholds
There are two APD thresholds as shown in Figure 113. These thresholds are contained in the agcPeak API structure, apdHighThresh and
apdLowThresh, respectively. The thresholds are typically considered relative to full scale voltage of the ADC, which is 850mVpeak. The
mV setting of the APD thresholds can be determined using the following equations:
To determine the setting of the APD thresholds in terms of the closest possible setting in terms of dBFS of the ADC assuming
apdHighdBFS and apdLowdBFS for apdHighThresh and apdLowThresh, respectively, the following equations can be used:
The APD threshold must be exceeded a programmable number of times within a gain update counter period before an over range
condition occurs. Both the upper and lower thresholds have a programmable counter in the API structure, as indicated in Table 56.
Table 56. APD Programmable Threshold Counters
Threshold Counter
Upper Threshold
(apdHighThresh)
apdUpperThreshPeakExceededCnt
Lower Threshold
(apdLowThresh)
apdLowerThreshPeakExceededCnt
As described in the earlier section on AGC control, the APD is used for both gain attack and gain recovery in peak detect mode. In
peak/power detect mode, the APD could be used for gain attack, and is used to prevent overloading during gain recovery. For more
details, refer to the relevant sections.
In AGC mode, the APD has programmable gain attack and gain recovery step sizes as shown in Table 57.
UG-1828 Preliminary Technical Data
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Table 57. APD Attack and Recovery Step Sizes
Gain Change Step Size
Gain Attack apdGainStepAttack
Gain Recovery apdGainStepRecovery
Step size refers to the number of indices of the gain table the gain is changed. As explained earlier, the gain table is programmed with the
largest gain in the Max Gain Index (typically index 255), with ever decreasing gain for decreasing gain index. Thus, if the APD gain
attack step size was programmed to 6, then this means that the gain index is reduced by 6 when the apdHighThresh has been exceeded
more than apdUpperThreshPeakExceededCnt times. For example, if the gain index had been 255 before this over range condition, then
the gain index would be reduced to 249. The amount of gain reduction this equates to is dependent on the gain table in use. The default
table has 0.5dB steps which in this example would equate to a 3dB gain reduction upon an APD over range condition.
The APD is held in reset for a configurable amount of time following a gain change to ensure that the receiver path is settled at the new
gain setting.
Half-Band Peak Detector
The HB peak detector is located in the digital domain at the output of the HB Filtering block. It can therefore also be referred to as the
Decimated Data Overload Detector because it works on decimated data. Like the APD detector, it functions by comparing the signal
level to programmable thresholds. It monitors the signal level by observing individual samples (I2 + Q2 or peak I/peak Q) over a period
of time and compares these samples to the threshold. If a sufficient number of samples exceed the threshold in the period of time, then
the threshold is noted as exceeded by the detector. The duration of the HB measurement is controlled by hbOverloadDurationCnt, while
the number of samples that should exceed the threshold in that period is controlled by hbOverloadThreshCnt.
Once the required number of samples exceed the threshold in the duration required, then the detector records that the threshold was
exceeded. Like the APD detector, the HB detector requires a programmable number of times for the threshold to be exceeded in a gain
update period before it will flag an over-range condition.
Figure 114 shows the two-level approach which is different from APD. It shows the gain update counter period, with the time being
broken into subsets of time based on the setting of hbOverloadDurationCount. Each of these periods of time is considered separately,
and hbOverloadThreshCount individual samples must exceed the threshold within hbOverloadDurationCount for an overload to be
declared. These individual samples greater than the threshold are shown in purple, while those less than the threshold are shown in
green. Two examples are shown, one where the number of samples exceeding the threshold is sufficient for the HB peak detector to
declare an overload (this time period is shown as yellow in the gain update counter timeline), and a second example where the number of
samples exceeding the threshold is not sufficient to declare an overload (this time period is shown as blue in the gain update counter
timeline). The number of overloads is counted, and if the number of overloads of the hbHighThresh exceed
hbUpperThreshPeakExceededCount in a gain update counter period, then an over-range condition is called. Likewise, if the number of
overloads of the hbUnderRangeHighThresh does not exceed hbUnderRangeHighThreshExceededCount, then an under-range condition
is called. Note that if hbOverloadDurationCount is set to equal to the time duration of 1 sample and hbOverloadThreshCount is set to 1,
the HB two-level approach becomes similar to the APD algorithm.
hbOverloadDurationCnt hbOverloadDurationCnt
hbOverloadThreshCnt
EXCEEDED hbOverloadThreshCnt
NOT EXCEEDED
agcGainUpdateCounter
24159-115
Figure 114. HB Detector, Two-Level Approach for an Overload Condition
Preliminary Technical Data UG-1828
Rev. PrA | Page 133 of 253
The HB detector has a number of programmable thresholds. Some of these thresholds are only used in the fast recovery mode of the peak
detect AGC configuration, as summarized in Table 58.
Table 58. HB Overload Thresholds
HB Threshold Usage
hbHighThresh Used for gain attack in both peak and peak/power detect AGC modes.
hbUnderRangeHighThresh Used for gain recovery in peak detect AGC mode. In peak/power detect AGC mode it is used to prevent
overloads during gain recovery.
hbUnderRangeMidThresh Used only when the fast recovery option of the peak detect AGC mode is being utilized.
hbUnderRangeLowThresh Used only when the fast recovery option of the peak detect AGC mode is being utilized.
For more details of how these thresholds are used by the AGC, refer to the relevant sections in this document.
The thresholds are related to an ADC dBFS value using the following equations:
Each threshold has an associated counter such that an over-range condition is not flagged until the threshold has been exceeded this
amount of times in a gain update period.
Table 59. Gain Steps for HB Overrange and Underrange Conditions
HB Threshold Counter
hbHighThresh hbUpperThreshPeakExceededCount
hbUnderRangeHighThresh hbUnderRangeHighThreshExceededCount
hbUnderRangeMidThresh hbUnderRangeMidThreshExceededCount
hbUnderRangeLowThresh hbUnderRangeLowThreshExceededCount
In AGC mode, the HB peak detector has programmable gain attack and gain recovery step sizes.
Table 60. HB Attack and Recovery Step Sizes
Gain Change Step Size
Gain Attack hbGainStepAttack
Gain Recovery (hbUnderRangeHighThresh) hbGainStepHighRecovery
Gain Recovery (hbUnderRangeMidThresh) hbGainStepMidRecovery
Gain Recovery (hbUnderRangeLowThresh) hbGainStepLowRecovery
The HB peak detector is held in reset for a configurable amount of time following a gain change to ensure that the receiver path is settled
at the new gain setting.
Power Detector
The power measurement block measures the RMS power of the incoming signal at the output of HB Filtering block. The number of
samples that are used in the power measurement calculation is configurable using the powerMeasurementDuration API parameter:
Power Meas Duration (Rx Sample Clocks) = 8 × 2powerMeasurementDuration
where Rx Sample Clocks is the number of clocks at the power measurement location.
It is important that this duration not exceed the gain update counter. The gain update counter resets the power measurement block and
therefore a valid power measurement must be available before this event. In the case of multiple power measurements occurring in a gain
update period, the AGC will use the last fully completed power measurement, any partial measurements being discarded.
The power measurement block has a dynamic range of 60dB. Signals lower than −60 dBFS may not be measured accurately. The power
measurement could be read through the API function adi_adrv9001_Rx_DecimatedPower_Get().
UG-1828 Preliminary Technical Data
Rev. PrA | Page 134 of 253
AGC CLOCK AND GAIN BLOCK TIMING
The AGC clock is the clock which drives the AGC state machine. In ADRV9001 device, the default AGC clock (to support a set of
standard sample rates) is at 184.32 MHz. When arbitrary sample rate is adopted in Rx, the AGC clock could vary.
The AGC state machine contains 3 states: Gain Update Counter, followed by the Slow Loop Settling (SLS) Delay, and 5 AGC clock cycles
delay. The total time between gain updates (gain update period) is a combination of slowLoopSettlingDelay and 5 AGC clock cycles.
GAI N UP DATE COUNTE R
5 AGC
CLOCK
CYCLE
IMMEDIATE
GAIN
ATTACK
GAIN
ATTACK
TYPE 1
SLOW
LOOP
SETTLING
DELAY
SLOW
LOOP
SETTLING
DELAY
SLOW
LOOP
SETTLING
DELAY
5 AGC
CLOCK
CYCLE GAI N UP DATE CO UNTER
GAIN
ATTACK
TYPE 2
YES
GAIN
RECOVERY
DELAYED
GAIN
RECOVERY
GAIN
RECOVERY
YES
24159-116
Figure 115. Delayed Gain Attack for Nondelayed Gain Recovery
Figure 115 outlines the operation of the AGC state machine. The diagram outlines possible gain change scenarios rather than a practical
example of AGC operation. The possible gain change scenarios are described below:
• AGC Gain Attack within gain update counter, but more than an SLS delay before the gain update counter expiry – Because slow
loop settling (SLS) is typically several orders of magnitude smaller than gain update counter, this is the most common gain
decrement scenario. This type of AGC Gain Attack is named as Gain Attack Type 1 as shown in Figure 115.
• AGC Gain Attack within gain update counter, but within a SLS delay before the gain update counter expiry – This is a special case,
which will rarely occur in applications per the reasoning in 1). This type of AGC Gain Attack is named as Gain Attack Type 2 as
shown in Figure 115.
• AGC Gain Recovery at the end of the gain update counter – Note that when fast recovery is enabled, the gain update counter is
substituted with the low under range interval, per Figure 109. A gain attack may occur within the gain update counter when fast
attack is enabled. A gain recovery event may only occur at the end of gain update counter (or low under range interval in “fast
recovery” mode) as previously discussed. This is mainly for aligning the gain recovery (for desired signal) with the frame or
subframe boundary. After a gain attack, a gain change counter with a value equal to the SLS delay is started. No further gain attacks
are allowed while this counter is running. This allows the minimum time to be set between gain changes.
However the gain change counter also prevents the AGC from moving from the gain update counter state to the slow loop settling delay
state since it needs to wait until the expiry of the SLS delay. Therefore if a gain attack occurred very close to end of the gain update
counter state, the gain change counter would delay the start of the SLS state and shift the gain recovery event as shown in Figure 116
Whereas in Figure 115, gain recovery event is always aligned with the vertical dash lines.
Preliminary Technical Data UG-1828
Rev. PrA | Page 135 of 253
GAI N UP DATE COUNTE R
5 AGC
CLOCK
CYCLE
IMMEDIATE
GAIN
ATTACK
GAIN
ATTACK
TYPE 2
SLOW
LOOP
SETTLING
DELAY
SLOW
LOOP
SETTLING
DELAY
SLOW
LOOP
SETTLING
DELAY
5 AGC
CLOCK
CYCLE GAI N UP DATE CO UNTER
YES
24159-117
DELAYED
GAIN
RECOVERY
DELAYED
GAIN
RECOVERY
Figure 116. Immediate Gain Attack Causing Delayed Gain Recovery
To prevent this happening and maintain a perfectly periodic gain recovery event, gain attacks are prevented from happening towards the
end of gain update counter state as shown in Figure 115. If a gain attack would happen in this period, it is delayed until the start of the
next gain update counter state. This can cause gain attacks to be held off for up to 2× SLS + 5 delay, therefore it is recommended to keep
SLS delay as short as possible to minimize the gain attack delay. Note that it is possible to disable this blocking feature, thus allowing gain
attacks to occur anywhere within the gain update counter state, however the periodicity of the gain recovery event is no longer
guaranteed as gain attacks towards the end of the gain update counter state will cause the gain recovery event to be delayed as shown in
Figure 116.
At the expiry of the gain update counter (or low under range interval in “fast recovery” mode), all measurement blocks are reset and any
peak detector counts will be reset back to zero. When the Rx is enabled, the counter begins. This might mean that its expiry is at an
arbitrary phase to the slot boundaries of the signal. The expiry of the counter can be aligned to the slot boundaries by setting the
parameter enableSyncPulseForGainCounter. While this bit is set, the AGC will monitor a DGPIO pin to find a synchronization pulse.
This pulse will cause the reset of the counter at this point of time, hence if the user supplies a DGPIO pulse time aligned to these slot
boundaries then the expiry of the counter will be aligned to slot boundaries. Any of DGPIO pin 0-15 can be used for this purpose.
For example, considering 100us gain update period and a 184.32 MHz AGC clock, a total of 18,432 AGC clocks will exist in the gain
update period:
Gain Update Period (AGC Clocks) = 184.32 MHz × 100 μs = 18,432
As noted, the full gain update period is the sum of the gainUpdateCounter, the slowLoopSettlingDelay and a number of AGC clock
cycles. If the slowLoopSettlingDelay is set to 4, the gain update counter must be set to 18,423 from the following calculation:
Gain Update Period (AGC Clocks) = gainUpdateCounter + slowLoopSettlingDelay +5
Gain Update Period (AGC Clocks) = 18,423 + 4 + 5 = 18,432
When Rx is enabled, the AGC can be kept inactive for a number of AGC clock cycles by using attackDelay_us. This means the user can
specify one delay for AGC reaction when entering Rx mode, and another for after a gain change occurs (slowLoopSettlingDelay).
ANALOG GAIN CONTROL API PROGRAMMING
As mentioned earlier, the Rx gain control mode could be configured as MGC or AGC mode. In both modes, the API function
adi_adrv9001_Rx_GainControl_Configure() is used to configure the gain control blocks, such as the peak detectors and the power
detector for a specific channel. Those detectors are utilized not only in the AGC mode but also could be utilized in MGC mode to feed
user important information. This API function also configures the DGPIO pins for retrieving the signal detectors information. Note
although signal detectors information is critical for MGC mode, it can also be obtained in AGC mode for observation and debugging
purpose.
The composition of the gain control configuration structure adi_adrv9001_GainControlCfg_t will be discussed in details in the next
section. Once it is configured, the desired gain control mode can be enabled by using adi_adrv9001_Rx_GainControl_Mode_Set()API
function.
If MGC mode is selected, as previously discussed, the gain could be manually controlled through API commands or DGPIO pins. In API
command mode, the user selects a gain index in the gain table through the API function adi_adrv9001_Rx_Gain_Set(). The gain index
selected for a channel can be read back through the API function adi_adrv9001_Rx_Gain_Get().
UG-1828 Preliminary Technical Data
Rev. PrA | Page 136 of 253
Figure 117 describes a high level flow chart of Rx gain control programming. Note the final step is to configure any GPIOs as necessary
such as GPIO inputs which allow the AGC gain update counter to be synchronized to a slot boundary, or DGPIOs to directly control the
gain index. Note the configure of the DGPIO pins for retrieving signal detectors information is included in the API command
adi_adrv9001_Rx_GainControl_Configure(). The operation of these has been described earlier.
GAI N CONT ROL
SETUP START
CONFIGURE G AIN T ABLE,
AGC STRUCT URE S
RUN
adi _adrv9001_Rx_G ainCon t rol _Conf ig ure( )
RUN
adi _adrv9001_Rx_G ainCon t rol _M ode_S et ( )
CONFIGURE GAIN
CONTROL GPIOS
GAIN CONTROL SETUP
COMPLETE
24159-118
Figure 117. Gain Control Programming Flowchart
Gain Control Data Structures
Figure 118 shows the member structure of adi_adrv9001_GainControlCfg_t, and its substructures, adi_adrv9001_PeakDetector_t,
adi_adrv9001_PowerDetector_t and adi_adrv9001_ExtLna_t. Each of the parameters are briefly explained in Table 61 to Table 64, the
wider context of these parameter settings being outlined in the previous relevant sections.
Preliminary Technical Data UG-1828
Rev. PrA | Page 137 of 253
adi_adrv9001_GainControlCfg_t
+peakWaitTime
+maxGainIndex
+minGainIndex
+gainUpdateCounter
+attackDelay_us
+slowLoopSettlingDelay
+lowThreshPreventGainInc
+changeGainIfThreshHigh
+agcMode
+resetOnRxon
+resetOnRxonGainIndex
+enableSyncPulseForGainCounter
+enableFastRecoveryLoop
adi_adrv9001_PeakDetector_t
+agcUnderRangeLowInterval
+agcUnderRangeMidInterval
+agcUnderRangeHighInterval
+apdHighThresh
+apdLowThresh
+apdUpperThreshPeakExceededCount
+apdLowerThreshPeakExceededCount
+apdGainStepAttack
+apdGainStepRecovery
+enableHbOverload
+hbOverloadDurationCount
+hbOverloadThreshCount
+hbHighThresh
+hbUnderRangeLowThresh
+hbUnderRangeMidThresh
+hbUnderRangeHighThresh
+hbUpperThreshPeakExceededCount
+hbUnderRangeHighThreshExceededCount
+hbGainStepHighRecovery
+hbGainStepLowRecovery
+hbGainStepMidRecovery
+hbGainStepAttack
+hbOverloadPowerMode
+hbUnderRangeMidThreshExceededCount
+hbUnderRangeLowThreshExceededCount
+feedback_low_threshold_counter_exceeded
+feedback_high_threshold_counter_exceeded
adi_adrv9001_PowerDetector_t
+powerEnableMeasurement
+underRangeHighPowerThresh
+underRangeLowPowerThresh
+underRangeHighPowerGainStepRecovery
+underRangeLowPowerGainStepRecovery
+powerMeasurementDuration
+powerMeasurementDelay
+rxTddPowerMeasDuration
+rxTddPowerMeasDelay
+overRangeHighPowerThresh
+overRangeLowPowerThresh
+overRangeHighPowerGainStepAttack
+overRangeLowPowerGainStepAttack
+feedback_lowThreshold_gainChange
+feedback_high_threshold_exceeded
adi_adrv9001_ExtLna_t
+gpio
+powerDown
+settlingDelay
+peak
+power +extLna
24159-119
Figure 118. Member Listing of adi_adrv9001_GainControlCfg_t Data Structure
Table 61. adi_adrv9001_GainControlCfg_t Structure Definition
Parameter Description Min Value
Max
Value
Default
Value
peakWaitTime Number of gain control clock cycles to wait before enabling
peak detectors after a gain change.
0 31 4
maxGainIndex Maximum gain index allowed. Must be greater than
minGainIndex and be a valid gain index.
183 255 255
minGainIndex Minimum gain index allowed. Must be less than maxGainIndex
and be a valid gain index.
183 255 183
gainUpdateCounter Is used as a decision period, with the detectors reset on this
period. Gain changes in AGC mode can also be synchronized to
this period (the expiry of this counter). The full period is a
combination of the gainUpdateCounter and
slowLoopSettlingDelay and a number of AGC cycles.
Depends on
Overload
Detector
Settings
4194303
AGC_CLK
Cycles
11520
attackDelay_us The duration the AGC should be held in reset when the Rx path
is enabled.
0 63 10
slowLoopSettlingDelay Number of AGC clock cycles to wait after a gain change before
the AGC will change gain again.
0 127 16
lowThreshPreventGainInc Only relevant in Peak and Power Detect AGC operation.
1: If AGC is in Peak and Power Detect Mode, then gain
increments requested by the power detector are prevented if
there are sufficient peaks (APD/HB Low Threshold Exceeded
Count) above the apdLowThresh or hbUnderRangeHighThresh.
0: apdLowThresh and hbUnderRangeHighThresh are don’t
cares for gain recovery.
0 1 0
UG-1828 Preliminary Technical Data
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Parameter Description Min Value
Max
Value
Default
Value
changeGainIfThreshHigh Applicable in both peak and peak and power detect modes.
0: Gain changes will wait for the expiry of the gain update
counter if a high threshold count has been exceeded on either
the APD or HB detector.
1: Gain changes will occur immediately when initiated by HB.
Gain changes initiated by the APD will wait for the gain update
to expire.
2: Gain changes will occur immediately when initiated by APD.
Gain changes initiated by HB will wait for the gain update to
expire.
3: Gain changes will occur immediately when initiated by APD
or HB detectors.
0 3 3
agcMode 1: AGC in Peak AGC mode, power-based gain changes are
disabled.
0: AGC in Peak and Power AGC mode where both Peak
Detectors and Power Detectors are utilized.
0 1 1
resetOnRxon 1: AGC state machine is reset when Rx is disabled. The AGC gain
setting will use the “resetOnRxonGainIndex” after resuming the
operation.
0: AGC state machine maintains its state when Rx is disabled
and the last AGC gain index will be used after resuming the
operation.
0 1 0
resetOnRxonGainIndex The AGC index to start with when “resetOnRxon” is set as 1. 183 255 255
enableSyncPulseForGainCounter 1: Allows synchronization of AGC Gain Update Counter to the
time-slot boundary. GPIO setup required.
0: AGC Gain Update Counter free runs.
0 1 0
enableFastRecoveryLoop 1: Enables the fast recovery AGC functionality using the HB
overload detector. Only applicable in Peak Detect Mode.
0: AGC fast recovery is not enabled.
0 1 0
power Structure containing all the power detector settings. N/A N/A N/A
peak Structure containing all the peak detector settings. N/A N/A N/A
extLna Structure containing all external LNA settings N/A N/A N/A
Table 62. adi_adrv9001_PowerDetector_t Structure Definition
Parameter Description
Min
Value
Max
Value
Default
Value
powerEnableMeasurement 1: Power Measurement block enabled.
0: Power Measurement block disabled.
0 1 1
underRangeHighPowerThresh Threshold (negative sign assumed) which defines the lower
boundary on the stable region of the power detect gain
control mode.
0 127 10
underRangeLowPowerThresh Offset (negative sign assumed) from
underRangeHighPowerThresh which defines the outer
boundary of the power based AGC convergence. Typically,
recovery would be set to be larger steps than when the
power measurement is less than this threshold.
0 15 4
underRangeHighPowerGainStep
Recovery
The number of indices that the gain index pointer should be
increased (gain increase) in the event of the power
measurement being less than underRangeHighPowerThresh
but greater than underRangeLowPowerThresh.
0 31 2
underRangeLowPowerGainStep
Recovery
The number of indices that the gain index pointer should be
increased (gain increase) in the event of the power
measurement being less than underRangeLowPowerThresh.
0 31 4
powerMeasurementDuration Number of IQ samples on which to perform the power
measurement. The number of samples corresponding to the
4-bit word is 8 × 2^(pmdMeasDuration[3:0]). This value must
be less than AGC Gain Update Counter.
0 31 10
Preliminary Technical Data UG-1828
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Parameter Description
Min
Value
Max
Value
Default
Value
powerMeasurementDelay Measurement delay to detect power for specific slice of gain
update counter
0 255
AGC
clock
cycles
2
rxTddPowerMeasDuration Following an Rx Enable, the power measurement block can
be requested to perform a power measurement for a specific
period of a frame. This is applicable in TDD modes. This
parameter sets the duration of this power measurement. A
value of 0 causes the power measurement to run until the
next gain update counter expiry.
0 65535
AGC
clock
cycles
0
rxTddPowerMeasDelay Following an Rx Enable, the power measurement block can
be requested to perform a power measurement for a specific
period of a frame. This is applicable in TDD modes. This
parameter sets the delay between the Rx Enable and the
power measurement starting on Rx.
0 65535
AGC
clock
cycles
0
overRangeHighPowerThresh Offset (positive sign assumed) from threshold
overRangeLowPowerThresh which defines the outer
boundary on the stable region of the power detect gain
control mode. Typically attack would be set to be larger steps
than when the power measurement is greater than this
threshold.
0 15 0
overRangeLowPowerThresh Threshold (negative sign assumed) which defines the upper
boundary on the stable region of the power detect gain
control mode.
0 127 7
overRangeHighPowerGainStep
Attack
The number of indices that the gain index pointer should be
decreased (gain reduction) in the event of the power
measurement being greater than
overRangeHighPowerThresh.
0 31 4
overRangeLowPowerGainStep
Attack
The number of indices that the gain index pointer should be
decreased (gain decrease) in the event of the power
measurement being less than OverRangeHighPowerThresh
but greater than OverRangeLowPowerThresh.
0 31 4
feedback_lowThreshold_gainChange
A pair of DGPIO pins to retrieve the gain change information
and power detector inner low threshold not exceeded status
0
(not
assigned)
9
(Select
DGPIO
pins 14
and 15)
0
(not
assigned)
feedback_high_threshold_exceeded A pair of DGPIO pins to retrieve the power detector inner
high threshold exceeded status and apd high threshold
counter exceeded status
0
(not
assigned)
9
(Select
DGPIO
pins 14
and 15)
0
(not
assigned)
Table 63. adi_adrv9001_PeakDetector_t Structure Definition
Parameter Description Min Value
Max
Value
Default
Value
(TBD)
agcUnderRangeLowInterval This sets the time constant (in AGC clock cycles) that
the AGC will recover when the signal peaks are less
than hbUnderRangeLowThresh. Only applicable when
the fast recovery option is enabled in Peak Detect AGC
mode.
Depends
on hb
detector
settings
65535 50
agcUnderRangeMidInterval This sets the time constant (in AGC clock cycles) that
the AGC will recover when the signal peaks are less
than hbUnderRangeMidThresh. Calculated as
(underRangeMidInterval+1) ×
underRangeLowInterval. Only applicable when the
fast recovery option is enabled in Peak Detect AGC
mode.
0 63 2
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Parameter Description Min Value
Max
Value
Default
Value
(TBD)
agcUnderRangeHighInterval This sets the time constant (in AGC clock cycles) that
the AGC will recover when the signal peaks are less
than hbUnderRangeHighThresh. Calculated as
(underRangeHighInterval+1) *
underRangeMidInterval.
Only applicable when the fast recovery option is
enabled in Peak Detect AGC mode.
0 63 4
apdHighThresh This sets the upper threshold of the analog peak
detector. When the input signal exceeds this
threshold a programmable number of times (set by its
corresponding overload counter) within a gain update
period, the overload detector flags. In AGC modes, the
gain will be reduced when this overload occurs.
apdLow
Thresh
63 21
apdLowThresh This sets the lower threshold of the analog peak
detector. When the input signal exceeds this
threshold a programmable number of times (set by its
corresponding overload counter) within a gain update
period, the overload detector flags. In Peak AGC
mode, the gain is increased when this overload is not
occurring. In Power AGC mode, this threshold can be
used to prevent further gain increases if the
lowThreshPreventGainInc bit is set.
0 apdHigh
Thresh
12
apdUpperThreshPeakExceededCount
Sets number of peaks to detect above apdHighThresh
to cause an APD High Over Range Event. In AGC
modes, this will result in a gain decrement set by
apdGainStepAttack.
0 255 6
apdLowerThreshPeakExceededCount Sets number of peaks to detect above apdLowThresh
to cause an APD Low Overload Event. In Peak Detect
AGC mode, if an APD Low Overload Event is not
occurring then this will result in a gain increment set
by apdGainStepRecovery.
0 255 3
apdGainStepAttack The number of indices that the gain index pointer
should be decreased in the event of an APD High Over
Range in AGC modes. The step size in dB depends on
the gain step resolution of the gain table (default
0.5dB per index step).
0 31 2
apdGainStepRecovery The number of indices that the gain index pointer
should be increased in the event of an APD Under
range event occurring in Peak Detect AGC mode. The
step size in dB depends on the gain step resolution of
the gain table (default 0.5dB per index step).
0 31 0
enableHbOverload 1: HB Overload Detector enabled
0: HB Overload Detector disabled
0 1 1
hbOverloadDurationCount The number of clock cycles (at the HB output rate)
within which hbOverloadThreshCnt must be
exceeded for an overload to occur. A HB overload flag
is only raised when the number of these overloads
exceeds hbUpperThreshPeakExceededCnt or
hbLowerThreshPeakExceededCnt within a gain
update period.
0 7 1
hbOverloadThreshCount Sets the number of individual samples exceeding
hbHighThresh or hbLowThresh necessary within
hbOverloadDurationCnt for an overload to occur. The
HB overload flag will only be raised when the number
of these overloads exceeds
hbUpperThreshPeakExceededCnt or
hbLowerThreshPeakExceededCnt within a gain
update period.
1 15 1
Preliminary Technical Data UG-1828
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Parameter Description Min Value
Max
Value
Default
Value
(TBD)
hbHighThresh This sets the upper threshold of the HB detector. 0 16383 13044
hbUnderRangeLowThresh This sets the lower threshold of the HB under range
threshold detectors. Used only when the fast recovery
option of the peak detect AGC mode is being utilized.
0 16383 5826
hbUnderRangeMidThresh This sets the middle threshold of the HB under range
threshold detectors. Used only when the fast recovery
option of the peak detect AGC mode is being utilized.
0 16383 8230
hbUnderRangeHighThresh Peak Detect Mode: Threshold used for gain recovery.
Peak Detect with Fast Recovery Mode: This sets the
highest threshold of the HB under range threshold
detectors.
Power Detect Mode: Threshold used to prevent
further gain increases if lowThreshPreventGainInc is
set.
0 16383 7335
hbUpperThreshPeakExceededCount Sets number of individual overloads above
hbHighThresh (number of times
hbOverloadThreshCount was exceeded in
hbOverloadDuractionCount) to cause an HB High
Over Range event. In AGC modes, this will result in a
gain decrement set by hbGainStepAttack.
0 255 6
hbUnderRangeHighThreshExceededCount Sets number of individual overloads above
hbUnderRangeHighThresh (number of times
hbOverloadThreshCount was exceeded in
hbOverloadDurationCount) to cause an HB Under
Range High Threshold Overload Event. In Peak Detect
AGC mode, not having sufficient peaks to cause the
overload is flagged as an under-range event and the
gain is recovered by hbGainStepHighRecovery.
0 255 3
hbGainStepHighRecovery The number of indices that the gain index pointer
should be increased in the event of an HB Under
Range High Threshold Under Range Event.
0 31 2
hbGainStepLowRecovery Only applicable in fast recovery mode of peak detect
AGC. This sets the number of indices that the gain
index pointer should be increased in the event of an
HB Under Range Low Threshold Under Range Event.
0 31 6
hbGainStepMidRecovery Only applicable in fast recovery mode of peak detect
AGC. This sets the number of indices that the gain
index pointer should be increased in the event of an
HB Under Range Mid Threshold Under Range Event.
0 31 4
hbGainStepAttack The number of indices that the gain index pointer
should be decreased in the event of an HB High
Threshold Over Range event in AGC modes. The step
size in dB depends on the gain step resolution of the
gain table (default 0.5dB per index step).
0 31 2
hbOverloadPowerMode Sets the measurement mode of the HB detector. HB
uses I^2+Q^2 when set to 1. Otherwise the HB uses
max(I, Q) per sample.
0 1 0
hbUnderRangeMidThresh
ExceededCount
Only applicable in fast recovery mode of peak detect
AGC. Sets number of individual overloads above
hbUnderRangeMidThresh (number of times
hbOverloadThreshCount was exceeded in
hbOverloadDurationCount) to cause an HB Under
Range Mid Threshold Overload Event. In Peak Detect
AGC mode, not having sufficient peaks to cause the
overload is flagged as an under-range event and the
gain is recovered by hbGainStepMidRecovery.
0 255 3
hbUnderRangeLowThresh
ExceededCount
Only applicable in fast recovery mode of peak detect
AGC. Sets number of individual overloads above
hbUnderRangeLowThresh (number of times
0 255 3
UG-1828 Preliminary Technical Data
Rev. PrA | Page 142 of 253
Parameter Description Min Value
Max
Value
Default
Value
(TBD)
hbOverloadThreshCount was exceeded in
hbOverloadDurationCount) to cause an HB Under
Range Low Threshold Overload Event. In Peak Detect
AGC mode, not having sufficient peaks to cause the
overload is flagged as an under-range event and the
gain is recovered by hbGainStepLowRecovery.
feedback_
low_threshold_counter_exceeded
A pair of DGPIO pins to retrieve the hb low threshold
counter exceeded status and apd low threshold
counter exceeded status
0
(not
assigned)
9
(Select
DGPIO
pins 14
and 15)
0
(not
assigned)
feedback_
high_threshold_counter_exceeded
A pair of DGPIO pins to retrieve the hb high threshold
counter exceeded status and apd high threshold
counter exceeded status
0
(not
assigned)
9
(Select
DGPIO
pins 14
and 15)
0
(not
assigned)
Table 64. adi_adrv9001_ExtLna_t Structure Definition
Parameter Description Min Value
Max
Value
Default
Value
gpio TBD TBD TBD 0
powerDown TBD TBD TBD 0
settlingDelay External LNA Settling Delay TBD TBD 0
A set of Rx gain control APIs are provided for user interaction with the ADRV9001 device. Some of them have been mentioned in the
previous sections. The following table summarizes the list of API functions currently available with a brief description for each one. For
more up-to-dated information and detailed descriptions, please refer to API doxygen document.
Table 65. A List of Rx Gain Control APIs
Rx Gain API Function Name Description
adi_adrv9001_Rx_GainControl_Mode_Set Configures the Rx gain control mode for a specific channel
adi_adrv9001_Rx_GainControl_Mode_Get Retrieves the currently configured Rx gain control mode
adi_adrv9001_Rx_Gain_Get Reads the Rx Gain Index for the requested Rx channel
adi_adrv9001_Rx_Gain_Set Sets the current AGC Gain Index for the requested Rx channel
adi_adrv9001_Rx_GainTable_Write Programs the gain table settings for Rx channels
adi_adrv9001_Rx_MinMaxGainIndex_Set
Set the minimum and maximum gain indices in the device data structure
adi_adrv9001_Rx_GainTable_Read Reads the gain table entries for Rx channels requested
adi_adrv9001_Rx_DecimatedPower_Get Gets the decimated power for the specified channel
adi_adrv9001_Rx_GainControl_Configure Sets up the device Rx Gain Control for a specified channel
adi_adrv9001_Rx_GainControl_Inspect Inspects the device Rx Gain Control for a specified channel
adi_adrv9001_Rx_GainControl_MinMaxGainIndex_Set Sets the min/max gain indexes for gain control operation for the specified
channel
adi_adrv9001_Rx_GainControl_MinMaxGainIndex_Get Gets the min/max gain indexes for gain control for the specified channel
adi_adrv9001_Rx_GainControl_Reset Resets all state machines within the gain control block
adi_adrv9001_Rx_GainControl_PinMode_Configure Configures gain control for MGC PIN mode
adi_adrv9001_Rx_GainControl_PinMode_Inspect Inspects gain control configurations for MGC PIN mode
DIGITAL GAIN CONTROL AND INTERFACE GAIN (SLICER)
The digital gain control has two major purposes, one for gain correction which is to correct the small step size inaccuracy in analog
front-end attenuation and the other for gain compensation which is to compensate for the entire analog front-end attenuation. In the
gain compensation mode, for example, if 5dB analog attenuation is applied at the front end of the device then 5dB of digital gain will be
applied. This ensures that the digital data is representative of the RMS power of the signal at the Rx input port (plus the nominal Rx
analog gain) so that any internal front-end attenuation changes in device for preventing ADC overloading are transparent to the
baseband processor. In this way, the device’s AGC can be used to react quickly to incoming blockers without the need for the baseband
processor to track the current gain index for the level of the received signal at the input to the device for signal strength measurements.
Preliminary Technical Data UG-1828
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The digital gain block is controlled by the Rx gain table as mentioned earlier. Note different digital gain will be applied when configured
in gain correction or gain compensation mode. The Rx gain table has a unique front-end attenuator setting, with a corresponding
amount of digital gain, programmed at each index of the table, as shown in Table 47.
For the gain compensation mode, it can be used in either AGC or MGC mode. The digital gain allows for compensation of both the
internal analog attenuator and an external gain component (such as a DSA or LNA). After the digital gain compensation, the signal
power should only depend on the input signal power.
Around the end of the Rx datapath, Rx interface gain could be further applied by using a “Slicer” block for 2 major purposes. One is to
avoid digital saturation due to the bit-width limitation of the data port in gain compensation mode. The other one is to ensure the overall
SNR is limited only by analog noise and unaffected by quantization noise. When gain compensation mode is used, any analog
attenuation is compensated by a corresponding digital gain, such that the sum of the analog and digital gain is always equal to the
nominal Rx analog gain of 20dB. At the ADC input, the full scale input signal is approximately 8.6 dBm. This value translates to 0 dBFS
in the digital datapath for either the I or Q channel. As an example, assuming a 5dBm signal is applied at Rx input port, at the Rx output,
the signal power will be 5+20 = 25dBm or 25-8.6= 16.4dBFS. This will cause clipping in 16-bit output signal. Therefore, interface gain
(less than 0 in this case) could be applied to attenuate the signal to avoid clipping. On the other hand, for a very low signal level, at Rx
input, within the RF bandwidth of interest, it must be assured that the analog noise dominates the quantization noise. In the Rx datapath,
the final 16-bit quantizer could become the dominant noise source as a result of the final interface quantization. This quantization noise
as a result of the final 16-bit quantizer will be spread over a bandwidth equivalent to its output sampling frequency. For NB applications
where the output sampling frequency is low, the total quantization noise per Hz could be larger than the analog noise per Hz. By
applying interface gain (greater than 0 in this case), prior to the final quantizer, the signal level and analog noise level are both increased.
Therefore, the analog noise dominates over the quantization noise so that SNR is dominated by analog front-end noise in the RF
bandwidth of interest. For WB applications, since the sampling frequency is higher, the total quantization noise becomes much smaller.
In such a case, the analog noise could be way above the quantization noise, therefore, interface gain is not required.
Figure 119 is a block diagram of the digital gain control portion of the Rx chain, showing the locations of the various blocks in the
simplified datapath.
WB/NB
DECIMATION
INTERFACE
GAIN
(SLICER)
LVDS/CMOS
MUX
API
RSSI
SIGNAL AFTER
HB FILTERING
DIGITAL
GAI N CONT ROL
24159-120
Figure 119. Gain Control and Slicer Section of the Receiver Data Path
It can be seen from Figure 119 that digital gain control is performed in the WB/NB Decimation block. In NB and WB applications, the
digital gain control is actually performed at different stages of the Rx data chain to achieve optimal performance, which is simplified in
Figure 119. The slicer must be dependent on the desired signal power alone and must be done only when all the interfering signals have
been filtered out, i.e. close to the end of the datapath. The Slicer operation can either be controlled automatically by the device internally
or by user externally through API commands. When controlled internally the RSSI block is used to determine the amount of interface
gain.
The following sections describe four different digital gain control modes in the device.
Mode 1: No Digital Gain Compensation with Internal Interface Gain Control
In this mode the digital gain block is used for gain correction. It applies a small amount of digital gain/attenuation to provide consistent
gain steps in a gain table. The premise is that because the analog attenuator does not have consistent steps in dB across its range then the
digital gain block can be utilized to even out the steps for consistency (the default table utilizes the digital gain block to provide consistent
0.5dB steps).
With internal control, the device automatically applies the interface gain determined by RSSI, which measures the input signal power
right before the slicer. Note in the gain correction mode, interface gain less than 0 is not needed since the Rx output level should not
exceed 0dBFS through either AGC or MGC. When in NB applications, the interface gain range could be from 0 to 18dB in 6 dB step size
(0,6,12,18) for improving the sensitivity. In WB applications, as discussed earlier, the sensitivity is already satisfied by the high sampling
rate so the interface gain is always 0.
UG-1828 Preliminary Technical Data
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After applying the interface gain, the signal is provided to the data port in 16-bit format. The baseband processor could retrieve the
interface gain through API commands to scale the power of the received signal to determine the power at the input to the device (or at
the input to an external gain element if considered part of the digital gain compensation).
Mode 2: No Digital Gain Compensation with External Interface Gain Control
This mode is similar to mode 1 except that user controls the interface gain manually. Similarly, when in NB applications, the interface
gain range could be selected from 0 to 18dB in 6 dB step size while in WB applications the interface gain is fixed at 0dB.
Mode 3: Digital Gain Compensation with Internal Interface Gain Control
In this mode gain compensation is used and the interface gain is determined internally. The device should be loaded with gain tables that
compensate for the analog front-end attenuation applied. Thus, as the analog front-end attenuation is increased, and equal amount of
digital gain is applied. The interface gain is determined by RSSI. If the power level is too high, the Slicer will shift the signal properly
before sending to the data port to avoid saturation.
As an example of how slicer works (note the following plots are only for showing the concepts which do not represent the actual
implementation), considering 3 different input signal power levels. The Power Level 1 fits a data length of 16 bit-width. The Power Level
2 is 0-6dB higher than Power Level 1which increases the bit-width by 1. The Power Level 3 is 6-12dB higher than Power Level 1 which
further increases bit-width by 1. Figure 120 outlines this effect, with gray boxes indicating the valid (used) bits in each case.
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D20
D21
D22
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D20
D21D22
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D20
D21D22
INPUT POWER LEVEL 1
INPUT POWER LEVEL 2
INPUT POWER LEVEL 3
24159-121
Figure 120. Bit Width of Input Signal with Increasing Power Levels
The slicer is used to attenuate the data such that it can fit into the resolution of the data port. Since the output is a shifted version of the
input, the slicer can only handle gains that are in ±6 dB steps.
Figure 121 explains the slicer operation. For Power Level 1, the slicer shift value is calculated as 0 so the 16-bit output data is taken from
D15 – D0. As the power level increases, the bit-width of the signal has increased. For Power Level 2, now the bit-width is 17. The slicer
shift value becomes 1 so the 16-bit output data is taken from D16 – D1. This is equivalent to apply 6dB of attenuation by slicer which
ensures that the bit-width of the signal is 16 once more; that is, the 16 MSBs have been selected (sliced) with the LSB dropped. When the
power level further increases as Power Level 2, the signal bit-width becomes 18-bit. The slicer shift value becomes 2 so the 16-bit output
data is taken from D17 – D2, which is equivalent to apply 12 dB of attenuation by slicer or slice the 16 MSBs dropping the 2 LSBs.
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D20D21D22
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D20D21D22
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D20D21D22
SLICER SHIFT VALUE
0
1
2
INPUT POWER LEVEL 1
INPUT POWER LEVEL 2
INPUT POWER LEVEL 3
24159-122
Figure 121. Slicer Bit Selection with Different Input Power Levels
The slicer algorithm assumes a max PAR of 15dB and it adjusts the interface gain such that the measured signal power + 15 dB is less
than 0 dBFS. For NB applications, the interface gain is from -36dB to 18dB and for WB applications, the interface gain is from −36 dB to
0dB in 6 dB step size.
Similarly, the baseband processor could retrieve the interface gain through API commands to scale the power of the received signal to
determine the power at the input to the device (or at the input to an external gain element if considered part of the digital gain
compensation).
Mode 4: Digital Gain Compensation with External Interface Gain Control
This mode is similar to mode 3 except that user controls interface gain by selecting a proper value. The baseband processor could
measure the input signal power or utilize the power measurement done by RSSI in the device to determine the interface gain. Then
through API commands and the Slicer will operate in the same way as mentioned in mode 3. For NB applications, the interface gain is
Preliminary Technical Data UG-1828
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from -36dB to 18dB and for WB applications, the interface gain is from −36 dB to 0 dB in 6 dB step size. This mode could be utilized
especially when baseband processor input signal clipping is observed by the user.
DIGITAL GAIN CONTROL AND INTERFACE GAIN API PROGRAMMING
The API function adi_adrv9001_Rx_InterfaceGain_Configure() is provided to configure the interface gain. The configuration structure
adrv9001_RxInterfaceGainCtrl_t is defined as the following:
typedef struct adrv9001_RxInterfaceGainCtrl
{
adi_adrv9001_RxInterfaceGainUpdateTiming_e updateInstance; /* Time at which Rx interface
gain control has to be updated. 0: To be updated at start of next frame 1: To be updated
immediately */
adi_adrv9001_RxInterfaceGainCtrlMode_e controlMode; /* 0: Uses internal Rx interface gain
value 1: Uses external Rx interface gain value. Gain value has to be provided in this case. */
adi_adrv9001_RxGainTableType_e gainTableType; /* 0: Gain Correction table 1: Gain
Compensation table
adi_adrv9001_RxInterfaceGain_e gain; /* a value between 0 and 9 (0x0 =
18dB, 0x1 = 12dB, 0x2 = 6dB, 0x3 = 0dB, 0x4 = -6dB, 0x5 = -12dB, 0x6 = -18dB, 0x7 = -24dB, 0x8 =
-30dB, 0x9 = -36dB). */
} adrv9001_RxInterfaceGainCtrl_t
It is clear from the above that there are 2 interface gain control modes, which are internal (automatic) control and external control. In
addition, there are 2 options to apply the interface gain. The first option is to apply it at the start of the next frame and the second option
is to apply it immediately. The interface gain could be selected from -36dB to 18dB in 6dB step size, a total of 10 options, which is defined
by “adi_adrv9001_RxInterfaceGain_e” as the following:
typedef enum adi_adrv9001_RxInterfaceGain
{
ADI_ADRV9001_RX_INTERFACE_GAIN_18_DB = 0, /*!< 18 dB */
ADI_ADRV9001_RX_INTERFACE_GAIN_12_DB, /*!< 12 dB */
ADI_ADRV9001_RX_INTERFACE_GAIN_6_DB, /*!< 6 dB */
ADI_ADRV9001_RX_INTERFACE_GAIN_0_DB, /*!< 0 dB */
ADI_ADRV9001_RX_INTERFACE_GAIN_NEGATIVE_6_DB, /*!< -6 dB */
ADI_ADRV9001_RX_INTERFACE_GAIN_NEGATIVE_12_DB, /*!< -12 dB */
ADI_ADRV9001_RX_INTERFACE_GAIN_NEGATIVE_18_DB, /*!< -18 dB */
ADI_ADRV9001_RX_INTERFACE_GAIN_NEGATIVE_24_DB, /*!< -24 dB */
ADI_ADRV9001_RX_INTERFACE_GAIN_NEGATIVE_30_DB, /*!< -30 dB */
ADI_ADRV9001_RX_INTERFACE_GAIN_NEGATIVE_36_DB, /*!< -36 dB */
} adi_adrv9001_RxInterfaceGain_e
Note as discussed before, depending on the gain table type and the bandwidth of the application, the interface gain could be limited to a
subset of the 10 options. This API must be called in the “CALIBRATED” state.
To change the interface gain on the fly while the channels are operation, the API function adi_adrv9001_Rx_InterfaceGain_Set() could
be used. The gain should be selected from one of the 10 options.
The following table summarizes the list of API functions currently available for digital gain control and interface gain. For more up-to-
dated information and detailed descriptions, please refer to API doxygen document.
Table 66. A List of Rx Interface Gain Control APIs
Rx Gain API Function Name Description
adi_adrv9001_Rx_Rssi_Read Reads back the RSS status for the given channel
adi_adrv9001_Rx_InterfaceGain_Configure Sets the Rx interface gain control configuration parameters for the given Rx channel
adi_adrv9001_Rx_InterfaceGain_Set Sets the Rx interface gain for the given Rx channel
adi_adrv9001_Rx_InterfaceGain_Inspect Gets the Rx interface gain control configuration parameters for the given Rx channel
adi_adrv9001_Rx_InterfaceGain_Get Gets the Rx interface gain for the given Rx channel
UG-1828 Preliminary Technical Data
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USAGE RECOMMENDATIONS
In this section, a list of recommendations is summarized for achieving optimal gain control performance:
It is recommended to start with AGC and default configurations.
• When changing the default configurations is needed, it is better to change parameters one by one.
• The high thresholds are used as limits on the incoming signal level and should be set based on the maximum input of the ADC. The
high thresholds should be set at least 3-6dB lower than the full input scale of the ADC.
• The apdHighThresh and hbHighThresh are set to an equivalent dBFS value. Likewise, the apdLowThresh and the
hbUnderRangeHighThresh are set to equivalent values.
• The apdUpperThreshPeakExceededCount and hbUpperThreshPeakExceededCount should be set properly to achieve a desired level
of AGC sensitivity to input signal peaks.
• The gain change period should typically be aligned to the frame or subframe boundary periods.
• Peak detect can achieve faster response time comparing with peak/power detect. For applications requiring “fast attack” and “fast
recovery”, peak detect provides better performance.
• “Fast recovery” mode should not be used when it is required to increase gain only at the frame or subframe boundary.
• For applications requiring “fast attack” and “fast recovery”, SLS delay should be set as short as possible to minimize the delay while
allowing sufficient time to set the gain changes.
TES CONFIGURATION AND DEBUG INFORMATION
User could interact with the Rx gain control functionality through API commands as discussed in previous sections or through
ADRV9001 Transceiver Evaluation Software (TES). While using TES, user should first configure the Rx gain control operation mode
and the signal detector operation mode as shown in Figure 122. (Note TES design could continuously change, see the ADRV9001
Evaluation System section for updated information.)
This configuration page is under GPIO Configurations tab in TES. Gain Control Mode provides user three options which are
Automatic, Manual Pin, and Manual SPI, which are corresponding to the AGC, MGC with pin control and MGC with SPI control. By
default, it is set as Manual SPI. When Manual Pin is selected, user should further select the GPIO pins for gain increment and
decrement. After selecting the gain control mode, user can further configure the Detection Mode which has two options “Peak Only”
and Peak and Power. By default, it is set as Peak Only mode. The Detection Mode indicates which AGC mode is configured when the
Gain Control Mode is selected as Automatic. When the Gain Control Mode is selected as Manual Pin or Manual SPI, it further
enables the ADRV9001 internal signal detectors in either Peak Only or Peak and Power mode. By configuring the GPIO pins, user is
allowed to retrieve the signal detector status which could be used to control Rx gain in Manual mode. Note the signal detector status
could also be retrieved in AGC mode.
24159-123
Figure 122. TES Configuration for Rx Gain Control Mode and Signal Detector Operation Mode
After configuring Gain Control Mode and Detection Mode, user could further configure signal detector parameters, interface gain and
manual control parameters under the Gain Control tab in TES as shown in Figure 123 and Figure 124. In Figure 123, AGC mode is
selected and in Figure 124, MGC Pin mode is selected. As shown in both figures, TES provides three sections for user configurations.
The first section is Rx Interface Gain. User can choose Manual or Automatic receiver interface gain control. When Manual is selected,
user can further enter the desired interface gain value and when the gain update should take effective (note interface gain configuration
Preliminary Technical Data UG-1828
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relates to the selection of gain table. User should first select Rx gain table type at the bottom of this configuration page in TES.) The
second section displays the current gain control mode. If AGC is configured as shown in Figure 123, users are not allowed to enter the
other parameters in this section. If MGC is configured as shown in Figure 124, user should further configure other parameters. With
MGC Pin mode, user should configure the targeted Manual Gain Index as well as the step sizes. The third section displays the detection
mode user selected and it allows user to configure the signal detector related operating parameters, such as Peak Overload threshold and
Peak Underload Threshold (they apply to both APD and HB detectors), Gain Refresh Period, Max Gain Index, and Min Gain Index
when Peak Only mode is selected. Note some selections are greyed out either because they are not configurable due to current software
limitation or not applicable in the selected modes. TES provides sanity checks for the parameter user enters so when the value is out of
range, the user input is not allowed.
24159-124
Figure 123. TES Configuration for Rx Interface Gain, Signal Detection Parameters and Manual Control Mode Parameters (when AGC is Configured)
UG-1828 Preliminary Technical Data
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24159-125
Figure 124. TES Configuration for Rx Interface Gain, Signal Detection Parameters and Manual Control Mode Parameters (when MGC Pin is Configured)
After finishing all the configurations, user could start the receive operations and observe the Rx gain changes. It is recommended to start
from the default settings and change the parameters one by one as needed. “Reset AGC settings to defaults” can be used to reset all the
parameters to their default values.
When the Rx gain control is not working as expected, the user could perform the following simple self-debugging:
• Check if the gain control mode is set as AGC or MGC.
• Check if the MAX and MIN index is set properly. When set improperly, the gain control capability could be significantly impacted.
• If detectors are not working, check if the gain step is set as 0, which will disable gain attack or gain recovery.
• When signal saturation is observed, adjust the slicer/interface gain could help.
Preliminary Technical Data UG-1828
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RX DEMODULATOR
RX NARROW-BAND DEMODULATOR SUBSYSTEM
ADRV9001 Rx narrow-band demodulator subsystem, denoted by rxnbdem, is the digital baseband backend partition of ADRV9001 Rx
channel. Note that narrow band, commonly for a wireless communication system, if the channel spacing, also known as channel
bandwidth, is no more than 1 MHz, we call it “Narrowband System”. Otherwise, we call “Wideband System”. Figure 125 illustrates the
rxnbdem subsystem, incorporating signal buffering, carrier frequency offset correction, programmable channel filtering, frequency
discrimination, narrowband programmable pulse shaping, and resampling function. The input of rxnbdem, driven by the RX decimation
filters, is the ZIF digital baseband IQ signal. Programmability exists to bypass each block in the rxnbdem subsystem. The output of
rxnbdem, is directly sent to the RX SSI interface. Depending on the programmed functionality, the output can be Frequency
Deviation(I)-only or IQ.
RESAMPLER
NB
PROGRAMMABLE
FIR
NB
PROGRAMMABLE
FIR
Rx
PROGRAMMABLE
FIR
Rx
PROGRAMMABLE
FIR
FREQUENCY
DISCRIMINATOR
RESAMPLER
SIGNAL
FIFO SIN
DDS
COS
DECIMATION
FILTERS
I
Q
I
Q O R M ag
I OR FD
Q O R M ag
I OR FD
Q
I OR FD
Rx SSI
INTERFACE
Q
rxnb_dem
ROUND
I
Q
24159-126
Figure 125. Functional Diagram of rxnbdem
Signal FIFO
Signal FIFO is to buffer the input IQ data stream, and it is applicable only in the CMOS SSI operation mode. The Signal FIFO depth is
2048. As a result, it can store for more than 85 ms at the sampling rate of 24KHz
SIGNAL FIFO
FIFO (I+Q)
I+Q CARRIER
FREQUENCY
CORRECTOR
I
Q
rxnb_dem
DECIMATION
FILTERS
Q
IBYPASS
FIFO
WRENA RDENA
24159-127
Figure 126. Functional Diagram of Signal FIFO
The Signal FIFO can be disabled or enabled based on the users’ requirement. As the Signal FIFO is disabled, this block is bypassed and
cannot be written or read. As the Signal FIFO is enabled, the writing control and reading control of the Signal FIFO can be manipulated
separately. The FIFO reading clock is configurable, can be 1x, 2x, 4x, or 8x of the FIFO writing clock. For wideband modes, only 1x and
2x are supported and the reading clock rate cannot be above 61.44 MHz.
In the Signal FIFO, as shown in Figure 126 there is an output mux, which has 2 inputs: one input, denoted as “Bypass”, is driven by the
input IQ stream to the FIFO; the other, denoted as “FIFO”, is driven by the output IQ stream from the FIFO. The mux inputs can be
switched on demand to drive the following modules in rxnbdem.
Below is an example explaining how to use the Signal FIFO.
During the signal capturing phase before the wireless data link is established, the mux should be kept at “Bypass”, and the FIFO writing
control is enabled, and the FIFO reading control is disabled. Through the Rx SSI port, the BBIC can keep on detecting the received
signal. Meanwhile, the Signal FIFO keeps on buffering the IQ stream. The FIFO writing overflow may or may not happen. If happen, the
FIFO always stores the latest 2048 IQ data.
As the BBIC detects the wanted Rx frame from the input data stream and estimates the right starting point of the wanted Rx frame,
further the synchronous parameters, the BBIC may switch the mux from “Bypass” to “FIFO”, then enable the reading control of the
FIFO, to process the stored data stream and the following data stream seamlessly.
Carrier Frequency Corrector (CFC)
Carrier Frequency Corrector in rxnbdem is to remove the carrier frequency offset. This module can be bypassed.
In a communication system, a desired signal is transmitted by the transmitter at RF over the air. Since the clock reference at the
transmitter and the receiver are independent, this may result in the RF carrier frequency offset between the transmitter and the receiver.
UG-1828 Preliminary Technical Data
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This frequency difference is named by the carrier frequency offset (CFO). The CFC in rxnbdem enables the BBIC to remove the CFO
before the channel selection filtering at the receiver side. The correction value applied to the CFC, needs to be estimated and further
input by the BBIC. The change of the correction value may occur immediately or relative to RX frame boundary.
The CFC is implemented as a Digital Down Converter (DDC), which consists of an NCO and a complex multiplier in the datapath. As
the correction value, the NCO frequency word should be in the range of min (±20k,20% of sample rate).
0
–20
–40
–60
–100
–80
–120
–30 –20 –10 010 20 30
dBc
MHz
0
–20
–40
–60
–100
–80
–120
–30 –20 –10 010 20 30
dBc
MHz
–20MHz CW Fs/16 CW
0
–20
–40
–60
–100
–80
–120
–30 –20 –10 010 20 30
dBc
MHz
0
–20
–40
–60
–100
–80
–120
–30 –20 –10 010 20 30
dBc
MHz
Fs/8 CW Fs/4 CW
X = –22
Y = –2.388
24159-128
Figure 127. Output Spectrum of the CFC/NCO as Fs = 61.44 MHz
Figure 127 presents the spectrum of desired tone and the generated NCO spurs levels relative to desired tone for the CFC NCO at 61.44
MHz sampling frequency. The outlined plots show a typical case and some worst cases. As shown in Figure 127, the NCO output spurs
are -100 dBc below desired tone across the range of [-fs/2, fs/2]:
• −20 MHz CW,
• CW,
• CW, and
• CW.
Please note these are not within the range defined above.
Rx Programmable FIR Filter
Rx Programmable FIR Filter in rxnbdem is multi-functional and customizable. This module can be bypassed.
The Rx Programmable FIR supports up to 128 taps. Each tap is 24 bits width with the signed bit included. 4 sets of customized FIR
profiles can be stored at the initialization phase. One of the 4 stored FIR profiles can be switched to be loaded on the fly under the control
of the BBIC.
The Rx programmable FIR can be loaded a customized lowpass filter profile to stop the adjacent channel interference, which is helpful to
achieve better channel selectivity. For example, as shown in Figure 128, before the CFO is corrected, the BBIC may program a loose filter
Preliminary Technical Data UG-1828
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profile onto the Rx Programmable FIR to perform common filtering. However, after the CFO is corrected via Carrier Frequency
Corrector block, a tight filter profile can be loaded to perform the deep channel selection filtering. The change in the filter profile can be
initiated by the BBIC on demand in the RF_Enabled State.
CFO
THE WANT E D CHANNE L
BEFORE CFO I S CORRECTED. THE WANT E D CHANNE L
AFTER CFO IS CORRECTED.
DC DC
LOOSE FILTER PROFILE TIGHT FILTER PROFILE
24159-129
Figure 128. Loose Filter Profile vs. Tight Filter Profile
Frequency Discriminator
Frequency Discriminator in rxnbdem is to translate the IQ signal into Frequency Deviation (FD) signal, performing the frequency
demodulation in the digital domain. This module can be bypassed.
D
D
I
Q
–
ATAN2 FREQUENCY
DEVIATION
(FD)
SQUARED
MAGNITUDE
(Mag2)
X
Y
24159-130
Figure 129. Functional Diagram of Frequency Discriminator
Illustrated by Figure 129, the Frequency Discriminator outputs the transient frequency deviation (FD) and the transient squared
magnitude (Mag2) sample by sample. The output FD and the output Mag2 are defined as followed:
where atan2 is same as the function in Octave, and D is the programmable delay. Typically, D is chosen as ‘1’, which means 1
sampling clock delay.
Assuming the input IQ signal is the complex single tone, given by
where A is the signal magnitude, ft is the tone frequency, fS is the sampling frequency. The output of the frequency discriminator (FD) is
D × 2ft/fS while the output Mag2 is A2.
NB Programmable FIR
NB Programmable FIR in rxnbdem is to perform the pulse shaping filtering or the low pass filtering at the output of the Frequency
Discriminator. This module can be bypassed.
The NB Programmable FIR supports up to 128 taps. Each tap is 24 bits width including the sign-bit, and only 1 set of customized FIR
profiles can be loaded.
Resampler
Resampler in rxnbdem adjusts the sampling phase of the IQ signal or that of the FD signal. This module can be bypassed.
UG-1828 Preliminary Technical Data
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Figure 130 illustrates the functional diagram of the Resampler, the Resampler resamples the incoming received signal, by reconstructing
intermediate samples between every 2 inputs samples according to the re-sample phase parameter, .
In the frequency domain, the ideal digital Resampler has the transfer function as below:
where Bx is the maximum bandwidth of the input signal. Filtered by the ideal resampling filter, the input signal, x(kTS), is converted to
the output signal y(kTS) = x((k + μ) × TS
SUB-FIR3 SUB-FIR2 SUB-FIR1 SUB-FIR0
µ
16: S1. 15
I, Q
I, Q
24159-131
Figure 130. Functional diagram of the Resampler
Scanning the sampling phase μ from 0 to 0.5, the maximum magnitude difference of the frequency transfer function between the
Resampler and the ideal digital resampler is collected and plotted at the upside of Figure 131. The maximum phase error is collected and
plotted at the downside of Figure 131.
The Resampler can be used in both the wideband and narrowband modes.
50
40
30
20
10
0
0.5
0.4
0.3
0.2
0.1
0
MAX M AGNITUDE E RROR (d B)MAX P HASE E RROR (S ample)
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
NORM ALIZED FREQ UE NCY ( × Rad/Sample)
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
NORM ALIZED FREQ UE NCY ( × Rad/Sample)
MAX M AGNITUDE E RROR FOR µ= [ 0: 0.001:0.5]
MAX P HASE E RROR F OR µ= [ 0: 0.001:0.5]
X = 0.9
Y = 8.558
X = 0.2
Y = 0.00081 X = 0.4
Y = 0.01989 X = 0.6
Y = 0.0407 X = 0.7
Y = 1.302 X = 0.8
Y = 3.459
X = 0.3
Y = 0.004165
X = 0.1
Y = 5.189e-05 X = 0.5
Y = 0.09938
X = 0.9
Y = 0.1648
X = 0.2
Y = 4.893e-05 X = 0.4
Y = 0.0007297 X = 0.6
Y = 0.01102 X = 0.7
Y = 0.03144
X = 0.8
Y = 0.07514
X = 0.3
Y = 0.0002133
X = 0.1
Y = 1.589e-05 X = 0.5
Y = 0.02958
24159-132
Figure 131. Maximum Magnitude/Phase Error of the Resampler
Note: The resampler configuration is not supported by current ADRV9001 software release yet.
Round Module
Round in rxnbdem is to map the ADRV9001 internal datapath bit-width to the Rx SSI output. This module cannot be bypassed.
The Round module outputs 16-bit I data and 16-bit Q data to the Rx SSI output. If required, the Round module can output 16-bit I data
to the Rx SSI output with the 16-bit output Q data set as ‘0’.
NORMAL IQ OUTPUT MODE
The Normal IQ Output mode is applicable for both wideband and narrow band as the frequency discriminator bypassed. Except the
Rounding, all other modules can be bypassed. See Figure 132 ADRV9001 Rx narrow-band demodulator can be the common output stage
of Rx channel.
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RESAMPLER
NB
PROGRAMMABLE
FIR
NB
PROGRAMMABLE
FIR
Rx
PROGRAMMABLE
FIR
Rx
PROGRAMMABLE
FIR
FREQUENCY
DISCRIMINATOR
RESAMPLER
SIGNAL
FIFO SIN
DDS
COS
DECIMATION
FILTERS
I
Q
I
Q
I
Q
I
Q
I
Q
IRx SSI
INTERFACE
Q
rxnb_dem
ROUND
24159-133
Figure 132. Rxnbdem in Normal IQ output mode
In the Normal IQ output mode, the rxnbdem can provide the signal processing resources as followed:
• a spur-free carrier frequency offset correction,
• a profile-switchable channel filter, and
• a precise IQ resampler (not supported by software yet).
All above resources can be manually enabled and controlled by the BBIC by API (will provide the support in the later software releases).
FREQUENCY DEVIATION OUTPUT MODE
The Frequency Deviation Output mode is only applicable for the narrowband modes. Except the Round and the Frequency
Discriminator, all other modules can be bypassed. See Figure 133 ADRV9001 Rx narrowband demodulator contains a frequency
discriminator hardware block. Cooperating with other hardware blocks, for example, the CFC/DDC, and programmable FIR filters, etc.,
ADRV9001 Rx narrowband demodulator can perform FSK and FM demodulation under the control of the BBIC.
RESAMPLER
NB
PROGRAMMABLE
FIR
NB
PROGRAMMABLE
FIR
Rx
PROGRAMMABLE
FIR
Rx
PROGRAMMABLE
FIR
FREQUENCY
DISCRIMINATOR
RESAMPLER
SIGNAL
FIFO SIN
DDS
COS
DECIMATION
FILTERS
I
Q
I
Mag
FD
Mag
FD
Q
FD Rx SSI
INTERFACE
Q
rxnb_dem
ROUND
I
Q
24159-134
Figure 133. Rxnbdem in Frequency Deviation Output mode
The FSK/FM demodulation can cover the standards listed as followed:
• Analog FM with 12.5 KHz channel bandwidth
• Analog FM with 20 KHz channel bandwidth
• Analog FM with 25 KHz channel bandwidth
• P25 Phase I with 12.5 KHz channel bandwidth
• DMR with 12.5 kHz channel bandwidth
Regarding to each standard at above, Table 67 lists the usage suggestion of each modules in the Frequency Deviation Output mode.
Table 67. Suggestion of rxnbdem Usages in the Frequency Deviation Output Mode
FM, 12.5KHz FM, 20KHz FM, 25KHz P25 I, 12.5KHz
DMR,
12.5KHz
Input Sampling Clock 24 KHz or 48 kHz 48 KHz 24 KHz or 48 KHz
Signal FIFO Optional
CFC/DDC Enable for manual control
Rx Prog. FIR Enabled for channel filtering with 2 sets of FIR profiles
Freq. Discriminator Enabled with D = 1
NB Prog. FIR Low-pass filtering for smoothing the output FD signal Pulse Shaping
Resampler Disable Enable for manual control
Contact an Analog Devices Application Engineer for the specific filter profiles of Rx Programmable FIR and NB Programmable FIR.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 154 of 253
In summary, in the frequency deviation output mode, the rxnbdem can provide more important resources as followed:
• A 2k-depth FIFO,
• A spur-free carrier frequency offset correction,
• A profile-switchable channel filter,
• An accurate digital frequency discriminator,
• A low-pass filter or a pulse shaping filter for the frequency deviation, and
• A precise frequency deviation resampler.
All above resources can be manually enabled and controlled by the BBIC.
API PROGRAMMING
Configuration for blocks in rxnbdem subsystem is profile related on so far, all relative blocks are enabled or bypassed in profile by
selecting Rx “IQ” mode or “Frequency Deviation” mode, more user configurable capability will be added in later software release.
Carrier Frequency Corrector API programming
The API function adi_adrv9001_Rx_FrequencyCorrection_Set() is provided to set CFC frequency word, as mentioned earlier, the
frequency correction word should be in the range of min (±20k,20% of sample rate) (will change the limitation in later software). And
the frequency correct operation can take effect immediately or at the start of next available frame by set the parameter “immediate” to
“Ture” or “False”.
Rx Programmable FIR Filter API Programming
Profile Pre-defined Rx PFIR coefficients (customized Rx PFIR coefficients will be supported in the later software release) are atomically
loaded during chip initialization, there is no need for baseband processor to call any PFIR coefficients loading API function.
The configuration structure adi_adrv9001_PfirWbNbBuffer_t is defined as the following for the programming FIR filter coefficients.
typedef struct adi_adrv9001_PfirWbNbBuffer
{
uint8_t numCoeff; /* number of coefficients */
adi_adrv9001_PfirSymmetric_e symmetricSel; /* symmetric selection */
adi_adrv9001_PfirNumTaps_e tapsSel; /* taps selection */
adi_adrv9001_PfirGain_e gainSel; /* gain selection */
int32_t coefficients[ADI_ADRV9001_WB_NB_PFIR_COEFS_MAX_SIZE]; /* coefficients */
} adi_adrv9001_PfirWbNbBuffer_t;
Baseband processor can prepare new FPIR coefficients in one or more adi_adrv9001_PfirWbNbBuffer_t instances and call the API
function adi_adrv9001_arm_NextPfir_Set() in “PRIMED” or “RF_ENABLED” state to load each required instance into ADRV9001
hardware. Multiple PFIRs using the same coefficients can be loaded in a single call. However, note that the old coefficients remain in
effect until adi_adrv9001_arm_Profile_Switch() is called.
The API function adi_adrv9001_arm_NextRxChannelFilter_Set() calls adi_adrv9001_arm_NextPfir_Set() once or twice as needed to
update channel filter coefficients for Rx1, Rx2, or both. Either PFIR pointer may be NULL to prevent modifying the corresponding PFIR
but it is an error if both PFIR pointers are NULL.
The ADRV9001 performs the PFIR coefficients switch for all channels that have new coefficients prepared and waiting when the API
command adi_adrv9001_arm_Profile_Switch() is called. If ADRV9001 is in PRIMED state, the new coefficients will take effect on the
next transition to RF_ENABLED. If it is in RF_ENABLED, they take effect immediately.
An example python code for the RX PFIR coefficients switch is in below:
pfir_dmr_12p5k_coeff = [1,4,10,14,10,-8,-36,-56,-43,18,110,176,140,-36,-296,\
-477,-385,65,717,1164,945,-116,-1630,-2655,-2161,224,3612,5917,4823,-660,-8930,\
-15835,-16492,-8267,6681,21178,26054,15428,-8503,-34452,-46572,-33192,4645,50326,\
77802,65235,9575,-66663,-122526,-118715,-41686,81623,189288,211654,109809,-93600,\
-309489,-411032,-287232,101328,691337,1327974,1817574,2001178,1817574,1327974,\
691337,101328,-287232,-411032,-309489,-93600,109809,211654,189288,81623,-41686,\
-118715,-122526,-66663,9575,65235,77802,50326,4645,-33192,-46572,-34452,-8503,\
15428,26054,21178,6681,-8267,-16492,-15835,-8930,-660,4823,5917,3612,224,-2161,\
Preliminary Technical Data UG-1828
Rev. PrA | Page 155 of 253
-2655,-1630,-116,945,1164,717,65,-385,-477,-296,-36,140,176,110,18,-43,-56,-36,\
-8,10,14,10,4,1,0]
pfir_dmr_12p5k = adi_adrv9001_PfirWbNbBuffer_t()
pfir_dmr_12p5k.numCoeff = 128
pfir_dmr_12p5k.symmetricSel = adi_adrv9001_PfirSymmetric_e.ADI_ADRV9001_PFIR_COEF_NON_SYMMETRIC
pfir_dmr_12p5k.tapsSel = adi_adrv9001_PfirNumTaps_e.ADI_ADRV9001_PFIR_128_TAPS # PFIR_128_TAPS
pfir_dmr_12p5k.gainSel = adi_adrv9001_PfirGain_e.ADI_ADRV9001_PFIR_GAIN_ZERO_DB # PFIR_GAIN_0DB
for i in range(pfir_dmr_12p5k.numCoeff):
pfir_dmr_12p5k.coefficients[i] = pfir_dmr_12p5k_coeff[i]
Adrv9001.arm.NextPfir_Set(1, pfir_fm_12p5k) # put in the right filter object
Adrv9001.arm.Profile_Switch()
NB Programmable FIR API Programming
Same with Rx PFIR, a profile pre-defined set of NB PFIR coefficients (customized NB PFIR coefficients will be supported in the later
software release) are automatically loaded during chip initialization, there is no need for baseband processor to call any PFIR coefficients
loading API function.
UG-1828 Preliminary Technical Data
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POWER SAVING AND MONITOR MODE
ADRV9001 is a high-performance integrated transceiver with low power considerations. To accommodate different user cases,
ADRV9001 provides flexibility for users to trade-off between power consumption and performance with some static configuration
options, such as:
• Clock PLL option of high performance and low power;
• ADC option of high performance or low power;
• ADC clock rate option of high, medium and low;
• RF PLL LOGEN optimization option of best phase noise and best power consumption.
• RF PLL power option of high, medium and low
• ARM clock rate option of divided by 1, 2, 4
These static options are chosen and configured in chip initialization stage and are not allowed to dynamically change except the ADC
option, high performance ADC, and low power ADC can be dynamically switched after chip has been initialized. Users can refer the
relative sections for above options detail in the User Guide.
For TDD applications, ADRV9001 defines different power saving modes to meet the power saving requirement in various user cases.
Some standards like DMR (Digital Mobile Radio) require the radio enter periodical sleep and carrier detection cycles in order to save
power (Monitor Mode) when radio is not in use. ADRV9001 has dedicated hardware to meet this Monitor Mode requirement, and
ADRV9001 software adds additionally static and dynamic power saving schemes in order to extend the power saving feature to a broader
market beyond DMR.
ADRV9001 defines five extra power down modes that provides from low to high power saving but short to long recovery time, details
will be introduced in the following section.
Three power saving schemes are designed for different power saving applications.
• Temporarily powering up/down the unused Tx/Rx channel in Calibrated state
• Dynamic interframe power saving is running automatically during all regular TDD TX/RX operations. DGPIO pins could be
configured to support additional power savings. All configurations can be set by API via fast messages on the fly. Power saving
software will smartly handle powering up/down HW components based on PLL mapping and selected power saving mode. There
are two power saving choices in interframe operations:
• Channel power saving. This is to power down a channel (both TX and RX) based on power down mode 0-2.
• System power saving. This is to power down the whole chip by power down mode 3-5
• Monitor Mode. This can allow baseband processor move into sleep state after it configures and moves ADRV9001 into Monitor
mode, ADRV9001 software will control the dedicated hardware and timers for periodical sleeping and detecting. Only power down
modes 3-5 are allowed in Monitor Mode.
Users can choose proper power down modes and power saving schemes according to their application scenarios. The following sections
explain the detail power saving schemes.
POWER-DOWN MODES
Power down modes are defined to dynamically power down and up different level of ADRV9001 components. Five extra power down
modes are defined from low power saving but short recover time to high power saving but long recover time as shown in Table 68. Each
higher power down mode would power down additional components than the lower mode, power down mode 3 is the exception.
Table 68. Power-Down Modes and Related Power-Down Components
Power Down Modes 0 (default) 1 2 3 4 5
Components TX Analog and Digital Data Path x x x x x x
TX Internal PLLs
x
x
x
x
x
TX LDOs
x x x
RX
Analog and Digital Data Path
x
x
x
x
x
x
RX Internal PLLs
x x x x x
RX LDOs
x
x
x
System CLK PLL
x x x
Converter and CLKPLL LDOs
x
x
ARM (+ memories)
x
Approximate Power-Up Time (μs)1 TBD TBD TBD TBD TBD TBD
1 Based on 38.4M device clock.
Preliminary Technical Data UG-1828
Rev. PrA | Page 157 of 253
• Power down mode 0 is the default power saving if power saving API is not called to set other values. In this mode, TX/RX enable pin
will automatically trigger powering up/down the TX/RX analog and digital datapath components such as Mixer, A/D, filters, etc.
The transition time is very short around TBD us.
• Power down mode 1 would power down internal RF PLLs in addition to mode 0 power down. After powering up, PLL requires
parameters restoration (TBD) or re-calibration, so it takes more time to power up.
• Power down mode 2 would power down some LDOs related to channels and RF PLLs in addition to mode 1 power down.
• Power down mode 3 powers down the TX/RX channels and PLLs (clock PLL, RF PLLs) only. No LDOs are powered down.
• Power down mode 4 powers down Clock PLL and system LDOs related to TX/RX channels in addition to mode 3 power down.
• Power down mode 5 powers down almost the whole ADRV9001 chip including ARM and memory except some wake up circuits.
POWER-DOWN/POWER-UP CHANNEL IN CALIBRATED STATE
User could power down/up individual channel (TX1/TX2/RX1/RX2) dynamically in Calibrated State if these channels are statically
enabled in device profile. adi_adrv9001_Radio_Channel_PowerDown() can be called to power down the specified channel, it will power
down the channel related LDOs and PLL for the channel in in additional to datapath power down.
adi_adrv9001_Radio_Channel_PowerUp() is used for power up the specified channel. User should be noticed that these two APIs can
only be called in Calibrated state.
Figure 134 shows a DMR radio switch from TX only frames into TX/RX alternate frames, ADRV9001 is initialized with Tx and Rx
enabled, at the beginning of TX only frames, baseband processor can bring the RX channel into Calibrated State and power it down.
Then before the transition of TX/RX alternate frames, baseband processor can power up RX and move RX into Primed state. The power
saving of TX channel in the green area would be addressed by power down modes in the following sections.
RX ON
(15ms)
TX ON
(30ms) SLEEP
(30ms) SLEEP
(30ms)
TX ON
(30ms) TX ON
(30ms) TX ON
(30ms)
ACTIVE TX STATE TRX ACTIVE TX
REVERSE
STATE
24159-135
Figure 134. DMR Typical State Transition
Another use case example, if 4 channels ((TX1/TX2/RX1/RX2) are enabled in the profile, user can power down the channels not used
temporarily after moving those channels to Calibrated state.
DYNAMIC INTERFRAME POWER SAVING
Dynamic inter-frame power saving is running automatically during all regular TDD TX/RX operations, higher level power down mode
can be configured to get more power saving if the application has longer TX/RX transition time. DGPIO pins could be configured to
support additional power savings.
There are two power saving choices that can be applied for various TDD interframe scenarios, one is Channel Power Saving and another
one is System Power Saving, users can configure either or both of these two options according to their system specification.
Channel Power Saving (CPS)
Channel power saving is to save power on channel granularity for dynamic TDD inter-frame operations. There are two kinds of power
saving events triggered by either TX/RX Enable pins or DGPIO pins respectively. The configuration selects power saving modes for both
kinds of events. Only power down mode 0-2 can be configured for CPS.
TX_ENABLE/RX_ENABLE Pin Triggers Power Saving
Power saving triggered by TX_ENABLE/RX_ENABLE pin powers up/down based on TX_ENABLE/RX_ENABLE rising or falling edges.
TX_ENABLE/RX_ENABLE rising edge powers up the components based on power down mode and falling edge powers down them.
Figure 135 shows TX/RX Enable pin powers up/down channels. If Tx/Rx Enable Pin power down mode is set to mode 1, TX1/RX1
Enable falling edge powers down TX1/RX1 PLL and TX1/RX1 datapath, rising edge powers them up. As mentioned earlier, the higher
power down mode, the longer recovery time, users should make sure their system has enough transition time between the power down
and power up of the same component if users set a high power down mode. For example in Figure 135, if TX1 and RX1 uses the same
internal PLL and there is very short transition time between TX enable falling edge and RX enable rising edge, then mode 1 and 2 should
not be selected because the same PLL and LDOs are always used.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 158 of 253
TX 1 ENABLE
TX ENABLE OFF
POWERING DOWN
COMPONENTS BASED ON
POWER SAVING MO DE
TX ENABLE ON
POWERING ON
COMPONENTS BASED ON
POWER SAVING MO DE
RX ENABLE O F F
POWERING DOWN
COMPONENTS BASED ON
POWER SAVING MO DE
RX ENABLE O N
POWERING ON
COMPONENTS BASED ON
POWER SAVING MO DE
RX1 ENABL E
TRX1 TX ON RX ON TX ON
24159-136
Figure 135. TX/RX Enable Pin triggers Power Saving
DGPIO Triggers Power Saving
DGPIO pin triggered Channel Power Saving can provide additional power saving than the TX/RX Enable pin when it is enabled,
therefore if enabled, the power down mode triggered by DGPIO should be larger than TX/RX enable pin triggered power down mode.
Both TX and RX channel would be powered down at the DGPIO rising edge and powered up at the DGPIO falling edge, this is because
only one DGPIO is assigned for TX and RX channel. Users should be noticed, the DGPIO can only be allowed to pull up when both TX
Enable and Rx Enable is low.
CH1
RX ENABL E
RX ENABL E
GPIO
TIME SLOTSTIME SLOTS
1
TX 234
RX 1
TX 234
RX
24159-137
Figure 136. TX/RX Pin Triggers Power Saving and DGPIO Triggers Power-Down Saving
Figure 136 shows an example that both TX/RX enable and DGPIO pin trigger power saving is enabled. The green time slots are the ones
TX/RX needs to be active. If TX and RX transition time is not long enough to allow power down mode 1 or 2, then users have to select
TX/RX Enable pin power down mode to 0. DGPIO power saving can be engaged during time slots 2 and 3 by selecting power down
mode 2 to power down both TX/RX LDOs and PLLs in the brown areas which neither TX nor RX is active.
The API command adi_adrv9001_arm_ChannelPowerSaving_Configure() is used to configure Channel Power Saving modes for a
specified channel. It can be called in Calibrated, Primed or RF Enabled state. The new setting would not take effect immediately after
mailbox acknowledgment but start at the power down pin edge (Enable falling edge and DGPIO rising edge). baseband processor should
leave enough time to send this command and receive acknowledgebefore the next power down event.
The channel power saving trigger modes are defined in following data structure:
typedef struct adi_adrv9001_ChannelPowerSavingCfg
{
adi_adrv9001_ChannelPowerDownMode_e channelDisabledPowerDownMode;
adi_adrv9001_ChannelPowerDownMode_e gpioPinPowerDownMode;
} adi_adrv9001_ChannelPowerSavingCfg_t;
The enumerator adi_adrv9001_ChannelPowerDownMode_e defines three power down modes that has been described in Table 68.
typedef enum adi_adrv9001_ChannelPowerDownMode
{
ADI_ADRV9001_CHANNEL_POWER_DOWN_MODE_DISABLED = 0, /*!< Default radio operation, no extra
power down */
ADI_ADRV9001_CHANNEL_POWER_DOWN_MODE_RFPLL = 1, /*!< RF PLL power down */
ADI_ADRV9001_CHANNEL_POWER_DOWN_MODE_LDO = 2, /*!< Channel LDO power down */
} adi_adrv9001_ChannelPowerDownMode_e;
adi_adrv9001_arm_ChannelPowerSaving_Inspect() is used to insect the channel power saving settings for the specified channel.
Preliminary Technical Data UG-1828
Rev. PrA | Page 159 of 253
System Power Saving (SPS)
More power saving can be achieved by System Power Saving but longer transition time. System Power Saving mode will use additional
DGPIO pin to trigger the whole ADRV9001 chip into sleep in power saving mode 3-5.
RX ON
(30ms) RX O N
(30ms)
GPIO PIN
POWER
SAVING/
SLEEP (Nm s )
TX TX
TX ON
(15ms)
ACTIVE RX WITH
INVERSE TX STATE ACTIVE TX STATE
24159-138
Figure 137. Combined CPS and SPS for Power Saving
Figure 137 shows an example how CPS and SPS combined to achieve the best power savings. User can select channel power saving to
TX/RX Enable pin power down mode 2, so TX/RX enable falling edge powers down channel LDOs and TX/RX PLL and rising edge can
power them up. After switching to TX only state, although RX channel can be powered down by command
adi_adrv9001_Radio_Channel_PowerDown() in Calibrated state, the dark green area will only have TX LDOs and PLL powered down
by TX enable falling edge. Another option is user can power down more by using System Power Saving if the dark gray area is very long.
User can set power down mode 3 to 5 to power down most of ADRV9001 components to save power and wake them up by DGPIO
falling edge early enough before TX enable rising edge.
Similar with the DPIO usage in Chanel Power Saving mode, the DPGIO in System Power Mode can only be pulled up when both Tx
Enable and Rx Enable is low.
adi_adrv9001_arm_SystemPowerSavingMode_Set() is used to set the System Power Saving modes. The enumerator
adi_adrv9001_SystemPowerDownMode_e defines three power down modes that described in Table 68:
typedef enum adi_adrv9001_SystemPowerDownMode
{
ADI_ADRV9001_SYSTEM_POWER_DOWN_MODE_CLKPLL = 3, /*!< CLK PLL power down */
ADI_ADRV9001_SYSTEM_POWER_DOWN_MODE_LDO = 4, /*!< LDO power down */
ADI_ADRV9001_SYSTEM_POWER_DOWN_MODE_ARM = 5 /*!< ARM power down */
} adi_adrv9001_SystemPowerDownMode_e;
MONITOR MODE
ADRV9001 Monitor mode is designed to do detection and sleep autonomously in idle state which can allow baseband processor to sleep
during the whole Idle cycle to get the highest system level power saving. The detection process checks the assigned channel to ascertain if
there is a valid signal on the channel of interest to commence communication with other Radios. ADRV9001 provides multiple modes of
detection processes.
Figure 138 shows a typical Monitor Mode operation, baseband processor fully controls Monitor mode operation before it enables
ADRV9001 into Monitor Mode. First, baseband processor sets the Monitor Mode configuration through an API command. then,
baseband processor asserts the Monitor Enable pin (specified by a DGPIO) to move ADRV9001 into Monitor Mode and baseband
processor itself can go into sleep sate until it’s waked up by ADRV9001 or other system interrupt. During the Monitor mode, ADRV9001
fully controls itself to perform the Sleep-Detection cycling, the Sleep/Detection cycle of the ADRV9001 is continuous unless a valid signal
is detected via the configured detection method or it is terminated by baseband processor pulling down the Monitor Enable pin.
ADRV9001 will trigger the wake-up pin to wake up baseband processor once the carrier is detected in any detection cycle.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 160 of 253
MO NI TO R M ODE ENABLE
(HIGHER PRIORITY)
TX_ENABLE
(HIGHER PRIORITY)
RX_ENABLE
(HIGHER PRIORITY)
BBIC/DSP
TRX
TIME
UP TIME
UP TIME
UP
WAKE UP
PIN ON MONITOR MODE
PIN OFF
TIME
UP
RX_ENABLE
ON
WAKE UPSLEEPING RECEIVES
RX DATA
SPI WRITE OR MONITOR
MO DE P IN O N TO E NABLE
MONITOR MODE
CARRIER
DETECTED
BUFFER
RX DATA
DETECT UNTIL
“DETECT TIM E R”
UP
DETECT UNTIL
“DETECT TIM E R”
UP
ENTER
RX_ENABLE ST ATE
TRANSM ITS RX DAT A
DETECT UNIT “ BATT ERY SAVE
MODE DELAY TIM ER”
IME-UP
SLEEP UNTIL
“SLEEP TI MER”
UP
SLEEP UNTIL
“SLEEP TI MER”
UP
24159-139
Figure 138. Monitor Mode: Baseband Processor in Sleep and ADRV9001 in Alternate Sleep and Carrier Detection
API command adi_adrv9001_arm_SystemPowerSavingAndMonitorMode_Configure() is used to configure the monitor mode, baseband
processor should leave enough time to send this command and receive acknowledgebefore enable Monitor Enable pin. Data structure
adi_adrv9001_SystemPowerSavingAndMonitorModeCfg defines the Monitor Mode configuration and is shown as following:
typedef struct adi_adrv9001_SystemPowerSavingAndMonitorModeCfg
adi_adrv9001_SystemPowerDownMode_e powerDownMode;
uint32_t initialBatterySaverDelay_us;
uint32_t detectionTime_us;
uint32_t sleepTime_us;
uint8_t detectionFirst;
adi_adrv9001_MonitorDetectionMode_e detectionMode;
bool detectionDataBufferEnable;
bool externalPllEnable;
} adi_adrv9001_SystemPowerSavingAndMonitorModeCfg_t;
Monitor modes support there type of system power down mode. The initial, sleep and detection durations are user configurable, and
users can decide detection first or sleep first when ADRV9001 is moved into monitor mode.
The enumerator adi_adrv9001_MonitorDetectionMode_e defines five detection modes which can be used in different radio standards.
Some modes are standard dependent, such as the modes with suffix “SYNC” are only available for the DMR standard, and the modes
with suffix “FFT” are only available for the standards that use FSK modulation scheme. But the “MODE_RSSI” can be used for any radio
standards.
Current monitor mode only supports “ADI_ADRV9001_MONITOR_DETECTION_MODE_RSSI” detection modo, other detection
mode will be added in software support in future.
typedef enum adi_adrv9001_MonitorDetectionMode
{
ADI_ADRV9001_MONITOR_DETECTION_MODE_RSSI, /*!< RSSI detection only */
ADI_ADRV9001_MONITOR_DETECTION_MODE_SYNC, /*!< DMR Sync detection only */
ADI_ADRV9001_MONITOR_DETECTION_MODE_FFT, /*!< detection only */
ADI_ADRV9001_MONITOR_DETECTION_MODE_RSSI_SYNC, /*!< RSSI and Sync detection */
ADI_ADRV9001_MONITOR_DETECTION_MODE_RSSI_FFT, /*!< RSSI and FFT detection */
} adi_adrv9001_MonitorDetectionMode_e;
ADRV9001 can always buffer the latest incoming data in Monitor Mode detection cycle, once a valid incoming signal is detected and the
baseband processor has been waked up by ADRV9001, ADRV9001 can send out the buffered Rx data to baseband processor. This
procedure can make sure the baseband processor won’t miss the valid incoming signal when it’s in the sleep state.
Monitor Mode utilizes same power down modes with System Power Saving, but additional detection function than System Power
Saving, and they can use the same DGPIO as the power saving trigger interface. Users can use either System Power Saving or Monitor
Preliminary Technical Data UG-1828
Rev. PrA | Page 161 of 253
Mode, and these two modes can also be dynamically switched for different time slots, a System Power Saving or Monitor Mode API
command should be sent during each time switching between System Power Saving.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 162 of 253
DIGITAL PREDISTORTION
BACKGROUND
It is well known that one of the main criteria of a power amplifier (PA) operation is its ability to maintain linearity, i.e. the gain is
constant regardless of the input amplitude. However, in practice, a power amplifier can only maintain linearity up to a certain input level
beyond which the gain starts to lower and the power amplifier enters into a nonlinear or compression region as shown in Figure 139. For
most low-power linear amplifiers, they operate in the linear region as shown in the red circle. Unfortunately, a power amplifier that
operates mostly in the linear region has lower efficiency. power amplifier efficiency is defined as the ratio of output RF power to the DC
supply power. Therefore, it is desirable to operate power amplifier at . high efficiency to save DC power and reduce heat dissipation.
To achieve higher power amplifier efficiency, the highest input signal peak is usually set at around 1dB (P1dB) compression region as
shown in the blue circle in Figure 139. However, compression of the peak signals produces harmonics and hence intermodulations. Some
of the intermodulations fall back right into or adjacent to the carrier spectrum, therefore not only distorting the transmit signal but also
widening the spectrum of the transmit signal, so called spectral regrowth. If left untreated, the error vector magnitude (EVM)
performance of the transmit signal would be degraded and the spectral regrowth would interfere adjacent channels, resulting in worse
than required adjacent channel power ratio (ACPR) performance. Digital Pre-Distortion (DPD) is designed to mitigate this problem.
PA OUTPUT
1bB
COMPRESSION
REGION
PA INP UT
LINEAR REGION
IDEAL PA OUTP UT
ACTUAL PA O UTPUT
1bB
24159-140
Figure 139. Ideal Power Amplifier Output vs. Actual Power Amplifier Output
ADRV9001 DPD FUNCTION
The ADRV9001 device provides a fully integrated DPD function that supports both narrow-band (NB) and wide-band (WB)
applications. It is a hardware/software combined solution which performs linearization of the power amplifier by pre-distorting the
digital transmit signal with the inverse of the power amplifier’s nonlinear characteristics. After amplifying by the power amplifier, the
pre-distortion compensates power amplifier’s nonlinearity so the amplified RF transmit signal becomes linear. Therefore, the integrated
DPD solution allows power amplifier to operate at very high efficiency while achieving a satisfactory EVM and ACPR performance.
Figure 140 depicts a high level block diagram of the DPD algorithm. As shown in this figure, before the power amplifier, a “Predistortor”
block is added in the transmit datapath which distorts the transmit signal d(t) with the inverse of the power amplifier’s nonlinear
characteristics, as shown by the first Input/Output figure curve. Spectral regrowth is introduced after the pre-distortion. However, after
the “pre-distorted” transmit signal x(t) being amplified by the power amplifier, the power amplifier nonlinear characteristics, as shown
by the second Input/Output figure curve cancels out the pre-distortion. Therefore, the output of the power amplifier y(t) becomes linear,
as shown by the third Input/Output figure curve. In addition, the spectral regrowth after pre-distortion is also corrected. The “DPD
Coefficients Computation” block is used to compute the pre-distortion parameters by utilizing “Predistortor” output signal x(t) as well as
the power amplifier output signal y(t) through a feedback path. It models the behavior of the power amplifier in the reverse direction, i.e.
from output to input, therefore, it characterizes the inverse of the power amplifier nonlinearity and then feeds the parameters to the
“Predistortor”.
Preliminary Technical Data UG-1828
Rev. PrA | Page 163 of 253
DATA, d(
t
)INPUT, x(
t
)OUTPUT, y(
t
)
FREQUENCY
MAGNITUDE
MAGNITUDE
FREQUENCY
MAGNITUDE
FREQUENCY
OUTPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
COMPRESSION
PREDISTORTOR PA
DPD
COEFFICIENTS
COMPUTAION
24159-141
Figure 140. High Level Block Diagram of DPD Algorithm
In the ADRV9001 device, DPD is considered as one of the transmit (Tx) tracking calibrations. It is a real-time signal processing with
iterative updates to account for hardware variations such as temperature and power level changes. Similar to some other Tx tracking
calibrations, it requires a loopback path from the Tx to the Observation Rx (ORx) to perform the calibration. In this case, an external
loop back path (ELB) type 2 is required (please refer to Rx/ORx Signal Chain section for more details about the loopback paths), in
which, the Tx output signal after power amplifier is looped back to the ORx as shown in Figure 141. The user must make sure this path is
established before enabling the integrated DPD. In FDD applications where only one Rx is used or in the TDD applications during Tx
time slots, unused Rx can be used to perform DPD calibration as well as some other Tx tracking calibrations. Please refer to ADRV9001
Example Use Cases section for more details.
DPD
ACTUATOR
DPD
LO
SYNTHESIZER
BALUN
POWER
AMPLIFIER
ELB TYPE 2
DIRECTIONAL
COUPLER DUPLEXER
ANTENNA
DAC
COEFFICIENTS
CALCULATION
ENGINE
DAC
Tx ANALOG F RO NT END
ADRV9001
Tx DATA +
LO
SYNTHESIZER
BALUN
ADC
ADC
ORx ANALOG FRONT E ND
24159-142
Figure 141. High level Block Diagram of ADRV9001 DPD Implementation
Similar as shown in Figure 55 ADRV9001 DPD includes 2 major components, a “DPD Actuator” and a “Coefficients Calculation
Engine”. The “Coefficients Calculation Engine” computes the DPD coefficients periodically and then updates the “DPD Actuator” for
real-time pre-distortion of the transmit signal. The pre-distortion coefficients are associated with polynomial terms defined by the power
amplifier model. In order to meet the real-time processing requirement, polynomial terms that are associated with a common time-delay
input data are pre-computed and stored into Look-up Tables (LUT) in the “DPD Actuator”. In the device, without frequency hopping, 2
LUTs are used for all waveforms, one is currently being active for performing pre-distortion while the other one is being updated at the
background to track the changes and replace the current LUT when ready, resulting in seamless transmit operation. “DPD Actuator” also
includes a functionality to perform the calculation of the amplitude of the input signal, which is used to search the LUT. The outputs of
the LUT are then multiplied with different time delayed input data according to the configured DPD model and combined to form the
final pre-distorted transmit data.
ADRV9001 DPD SUPPORTED WAVEFORMS
The integrated DPD supports NB waveforms such as TETRA. Note some NB standard waveforms such as Direct Modulation types with
constant envelope do not require DPD. The different modes of operation for TETRA are listed in Table 69. The integrated DPD supports
all TETRA 1 and 2 modes.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 164 of 253
Table 69. Supported NB Standards and Associated Operational Parameters
Standard Bandwidth (kHz) Modulation Number of Carriers PAR (dB) before CFR
TETRA1 25 DQPSK 1 3.1
TETRA2 25 4 QAM 8 9.6
TETRA2 25 16 QAM 8 9.5
TETRA2 25 64 QAM 8 10.3
TETRA2 50 4 QAM 16 10.2
TETRA2 50 16 QAM 16 10.3
TETRA2 50 64 QAM 16 10
TETRA2 100 64 QAM 32 11.2
TETRA2 150 64 QAM 48 10.8
Besides that, the integrated DPD also supports some WB LTE and LTE-like waveforms with their associated operational parameters.
Other WB waveforms can be supported if the power amplifier behavior fits the designed hardwired amplifier model, as well as the
sampling rates and transceiver bandwidth.
The WB LTE standards supported and their associated operation parameters are summarized in Table 70.
Table 70. Supported WB Standards and Associated Operational Parameters
LTE Bandwidth (MHz) Number of Carriers PAR (dB) Before CFR
1.4 Multicarrier ~11
3 Multicarrier ~11
5 Multicarrier ~11
10 Multicarrier ~11
15 Multicarrier ~11
20 Multicarrier ~11
As shown in Table 69 and Table 70, multicarrier TETRA2 has a Peak-to-Average Ratio (PAR) between 9.6 dB to 11.2 dB and multi-
carrier LTE signal typically has a PAR of about 11dB. To achieve higher power amplifier efficiency and DPD algorithm stability, a
waveform with a large PAR is expected to have crest factor reduction (CFR) performed in baseband processor before DPD operation. It
is important that CFR is applied to a multicarrier signal before transmission since it keeps the average power higher while maintaining
the same peak back off in the digital transmit data. Also, CFR suppresses large peaks to below a preset threshold therefore eliminating
occasional large peaks that could make DPD unstable if the peak is beyond the compression threshold limit of the power amplifier. For
example, an LTE signal has a PAR of about 11 dB and the PAR can be reduced by CFR to be about 7 dB by trading off EVM. Note it is
the responsibility of baseband processor to perform CFR with an appropriate tradeoff between PAR reduction and EVM degradation
before sending the transmit data to ADRV9001. It should be also noted that additional EVM degradation caused by the integrated DPD
is negligible compared to the degradation caused by CFR.
ADRV9001 DPD PERFORMANCE
The integrated DPD algorithm has been tested using MOS type of power amplifiers. Figure 142 and Figure 143 shows the AM-AM and
AM-PM performance of the raw transmit signal input versus the power amplifier output before and after DPD. The test waveform is
TETRA1. From Figure 143, it can be seen clearly that the power amplifier nonlinearity is successfully corrected by the integrated DPD.
18000
16000
14000
12000
10000
8000
6000
4000
2000
002000 4000 6000 8000 10000 12000 14000 16000 18000
OUTPUT AMPLITUDE (Linear)
INPUT AMP LITUDE ( Li near)
50
–50
–40
–30
–20
–10
10
0
20
30
40
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
REL ATIV E P HAS E ANGLE ( Degrees)
INPUT AMP LITUDE ( Li near) ×10
4
24159-143
Figure 142. Raw Transmit Signal Input vs. Nonlinearized Power Amplifier Output
Preliminary Technical Data UG-1828
Rev. PrA | Page 165 of 253
18000
16000
14000
12000
10000
8000
6000
4000
2000
002000 4000 6000 8000 10000 12000 14000 16000 18000
OUTPUT AMPLITUDE (Linear)
INP UT AMP LI TUDE ( Linear)
50
–50
–40
–30
–20
–10
10
0
20
30
40
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
REL ATI V E P HAS E ANGL E ( Degrees)
INP UT AMP LI TUDE ( Linear) ×10
4
24159-144
Figure 143. Raw Transmit Signal Input vs. Linearized Power Amplifier Output
Figure 144 shows an example ACPR performance before and after DPD. The blue curve represents the ACPR performance before DPD,
from which, spectral regrowth could be observed. The black curve represents the ACPR performance after DPD. It is obvious that the
ACPR performance is significantly improved.
24159-145
Figure 144. ACPR Performance Before and After DPD
Satisfactory DPD performance also depends on successful completion some operations inside the device such as ADC and DAC
calibrations. Most of those operations are guaranteed internally in the device but the following operations are user configurable. It is
important to perform all those optional operations to achieve the optimal DPD performance.
• Time alignment between transmit x(t) and loopback y(t) for data capture (as shown in Figure 55)
• Tx closed loop gain control (CLGC) tracking calibration (not available in the current release)
• Tx LOL calibration
• Tx and Rx QEC calibration
Note that DPD could only support slow frequency hopping mode.
DPD CONFIGURATION
To use the integrated DPD properly and ensure optimal performance, user needs to configure DPD parameters properly. This could be
done through ADRV9001 Transceiver Evaluation Software (TES) or Software Development Kit (SDK). The configuration consists of 2
sets of DPD parameters. The first set of DPD parameters is “pre initial calibration” parameters since they should be configured before
performing initial calibration when the device is at the “STANDBY” state. The second set of DPD parameters is “post initial calibration”
parameters since they should be configured after performing initial calibration when the device is at the “CALIBRATED” state. These
DPD parameters will be explained in details in the next two subsections.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 166 of 253
DPD Pre Initial Calibration Parameters Configuration
In order to properly set the pre initial calibration parameters of DPD, the user should have a general understanding of the DPD model
used in the device. The DPD model is described by the following equations:
1
0
()
T
t
xn
−
=
=∑
ψt(|d(n – lt)|)d(n – kt)
ψt(|d(n – lt)|) =
7
,, ,,
0
| ( )|
t
i
tlti tl i t
i
b a dn l
=
−
∑
where:
T is the total number of taps in the DPD model.
ψt(|d(n – lt)|) is the function implemented by the LUT for tap, t.
lt and kt are part of the hardware model, representing the amplitude and data delay, respectively. The user can optionally include/exclude
each individual power term in ψt(|d(n – lt)|) by controlling the corresponding
,,t lt i
b
(setting it to either 0 for excluding or 1 for including),
to better model their power amplifier.
,,
t
tl i
a
are coefficients that are estimated by the coefficients calculation engine and used to generate the LUTs by the DPD actuator. For
,,t lt i
b
and
,,
t
tl i
a
, the subscripted t represents the index for the tap, lt represents the amplitude delay, and i represents the order of the
power term. Only 0th to 7th order power term is supported in the function, function ψt(|d(n – lt)|).
As aforementioned, this set of DPD parameters must be configured before initial calibration. It is defined by the following API data
structure:
typedef struct adi_adrv9001_DpdInitCfg
{
bool enable;
adi_adrv9001_DpdAmplifier_e amplifierType;
adi_adrv9001_DpdLutSize_e lutSize;
adi_adrv9001_DpdModel_e model;
bool changeModelTapOrders;
uint32_t modelOrdersForEachTap[4];
uint8_t preLutScale;
} adi_adrv9001_DpdInitCfg_t;
Table 71 briefly summarizes all the DPD pre initial calibration parameters described in the above data structure.
Table 71. DPD Pre Initial Calibration Parameters
Parameter Type Description Default Note
enable bool Sets “TRUE” to place the “DPD Actuator” in the datapath on
the specified channel to prepare for DPD operation.
FALSE Set “TRUE” does not start
the DPD operation. DPD
starts when the
corresponding tracking
calibration bit is set.
amplifierType enum Selects the type of amplifier
ADI_ADRV9001_DPD_AMPLIFIER_NONE = 0,
ADI_ADRV9001_DPD_AMPLIFIER_DEFAULT =1,
ADI_ADRV9001_DPD_AMPLIFIER_GAN =2
1 “1” is the only allowed
power amplifier type
currently.
lutSize enum Determines the LUT size
ADI_ADRV9001_DPD_COMPANDER_SIZE_256 = 0,
ADI_ADRV9001_DPD_LUT_SIZE_512 = 1
1 Only 2 LUT sizes are
supported.
model enum Selects the DPD model.
ADI_ADRV9001_DPD_MODEL_0 = 0,
ADI_ADRV9001_DPD_MODEL_1 = 1,
ADI_ADRV9001_DPD_MODEL_3 = 3,
ADI_ADRV9001_DPD_MODEL_4 = 4,
Model 4 is the ADRV9001 Model.
4 “4” is the only allowed
DPD model currently. User
should always choose “4”.
Preliminary Technical Data UG-1828
Rev. PrA | Page 167 of 253
Parameter Type Description Default Note
changeModelTapOrders bool Sets “TRUE” to use the model tap orders defined by
“modelOrdersForEachTap”. Set “FALSE” to ignore
“modelOrdersForEachTap” and use the default order.
FALSE The default model tap
order for DPD Model 4 is:
[0] = 0x001F,
[1] = 0x007F,
[2] = 0x001F,
[3] = 0x001E
modelOrdersForEachTap array A bit map for each of the taps in a model to indicate which
power terms are included in the model. Tap 0 and 2 should
have the same order.
[0] =
0x001F,
[1] =
0x007F,
[2] =
0x001F,
[3] =
0x001E
The default bit map
represents the default tap
order for Model 4.
preLutScale uint8_t
(U2.1)
Describes the prescaling factor for the LUT. 2.0 Min=1.0, Max=3.5
Each of these parameters are described in more details as the following:
enable
The enable parameter is used to place the “DPD Actuator” on the datapath of the specified channel to prepare for DPD operation. This
could be done through TES under the “Initialization” tab as shown in Figure 145.
24159-146
Figure 145. TES Configuration for Placing the DPD Actuator in the Data Path
Note that setting it to be “TRUE” is necessary but not sufficient to start DPD operation. The DPD starts when the corresponding
tracking calibration bit is also set, as shown in Figure 146.
24159-147
Figure 146. TES Configuration for Enabling DPD Tracking Calibration
The profile must indicate that there exists an external loopback connection and an external power amplifier for this channel. This can be
done by setting “Board Configurations” in TES properly, as shown in Figure 147.
24159-148
Figure 147. TES Configuration for External Loopback with External Power Amplifier
UG-1828 Preliminary Technical Data
Rev. PrA | Page 168 of 253
amplifierType
Currently, the power amplifier type should always be set to ADI_ADRV9001_DPD_AMPLIFIER_DEFAULT if DPD is enabled. The
default power amplifier type is referring to “non GaN” type, such as MOS type. In the future, other power amplifier type might be
supported.
lutSize
Currently, the supported LUT sizes are 256 and 512. This size determines the number of entries in the DPD LUT. A larger number of
entries provides better LUT granularity.
model
Currently, the model should be set to ADI_ADRV9001_DPD_MODEL_4 only. The other models exist for backwards compatibility with
other transceivers and should not be used at this time. Model 4 consists of four taps (T=4) which can be described by the following
equation:
3
0
( ) (| ( )|) ( )
tt t
t
xn dn l dn k
ψ
=
= −−
∑
Delays for each tap are described in Table 72.
Table 72. Delays of DPD Model 4
Tap Delay of Data (k) Delay of Magnitude (l)
0 0 0
1 1 1
2 2 2
3 1 2
Based on Table 72, the equation could be rewritten as:
( ) (| ( ) |) ( ) (| ( 1) |) ( 1) (| ( 2) (| ( 2)|) ( 1)
0 1 23
xn dn dn dn dn dn dn dn
ψ ψ ψψ
= + − −+ − + − −
where ψ0(|d(n)|), ψ1(|d(n-1)|), ψ2(|d(n-2)|) and ψ3(|d(n-2)|) represent four taps, generated by the LUT.
DPD Model 4 tap configuration used to generate the final pre-distorted data x(t) is shown in Figure 148:
x
x
+ +
Z1TAP1
TAP3
TAP2
TAP0
Z1
Z1x
Z1
Z1Z1
Z1
LUT
0
1
3
2
d(
t
)
d
(t)
d
(t
–1
)
d
(t
– 2
)
x
(t)
|d(
t
)|
24159-149
Figure 148. ADRV9001 DPD Model 4 LUT Configuration
As shown in Figure 148, d(t) is the raw complex transmit (Tx) signal before predistortion. Its amplitude is the basis that the DPD
actuator uses to predistort the d(t) via its LUT. The LUT consists of four taps, which are calculated with precomputed DPD coefficients
(w), as the following:
TAP0 = a0,0,0 + a0,0,1|d(t)| + a0,0,2|d(t)|2 + a0,0,3|d(t)|3 + a0,0,4|d(t)|4
TAP1 = a1,1,0 + a1,1,1|d(t − 1)| + a1,1,2|d(t − 1)|2 + a1,1,3|d(t − 1)|3 + a1,1,4|d(t − 1)|4 + a1,1,5|d(t – 1)|5 + a1,1,6|d(t – 1)|6
TAP2 = a2,2,0 + a2,2,1|d(t − 2)| + a2,2,2|d(t − 2)|2 + a2,2,3|d(t − 2)|3 + a2,2,4|d(t − 2)|4
TAP3 = a3,2,1|d(t − 2)| + a3,2,2|d(t − 2)|2 + a3,2,3|d(t − 2)|3 + a3,2,4|d(t − 2)|4
Note the TAPx equations represent the default power term setting for each tap in Model 4, from which, can be easily derived as the
following depending if a power term is included or excluded:
Tap 0: b0,0,0 = 1, b0,0,1 = 1, b0,0,2 = 1, b0,0,3 = 1, b0,0,4 = 1, b0,0,5 = 0, b0,0,6 = 0, b0,0,7 = 0
Tap 1: b1,1,0 = 1, b1,1,1 = 1, b1,1,2 = 1, b1,1,3 = 1, b1,1,4 = 1, b1,1,5 = 1, b1,1,6 = 1, b1,1,7 = 0
Preliminary Technical Data UG-1828
Rev. PrA | Page 169 of 253
Tap 2: b2,2,0 = 1, b2,2,1 = 1, b2,2,2 = 1, b2,2,3 = 1, b2,2,4 = 1, b2,2,5 = 0, b2,2,6 = 0, b2,2,7 = 0
Tap 3: b3,2,0 = 0, b3,2,1 = 1, b3,2,2 = 1, b3,2,3 = 1, b3,2,4 = 1, b3,2,5 = 0, b3,2,6 = 0, b3,2,7 = 0
If using an array B for 4 taps and for each tap using a byte to represent the above setting (the least significant bit represents the 0th power
term), it is clear that the default setting is equivalent to B[0] = 0x1F, B[1] = 0x7F, B[2] = 0x1F and B[3] = 0x1E.
The connections from the 4 outputs are combined to produce the final output, x(t) as the following:
x(t) = TAP0[|d(t)|] × d(t) + {TAP1[|d(t − 1)|] + TAP3[|d(t − 2)|]} × d(t – 1) + TAP2[|d(t − 2)|] × d(t – 2)
changeModelTapOrders
This flag is used to provide user an option to select the default model tap orders or choose a customized model tap orders. If this flag is
set to be “TRUE”, the next field in the data structure “modelOrdersForEachTap”, should be used to set the model tap orders for the
specified channel. If it is “FALSE”, then “modelOrdersForEachTap” will be ignored and it will use the default tap orders as discussed
(B[0] = 0x1F, B[1] = 0x7F, B[2] = 0x1F and B[3] = 0x1E).
modelOrdersForEachTap
This is an array of bitmaps for each tap t (t=0 to 3), formulated in the same way as discussed above for the default
setting. It provides user an option to customize the order so that a power term could be included or excluded in the polynomial to better
model the power amplifier. Table 73 are recommendations for setting this field. The user could try those suggestions and find out the
best model through tests. The method of selecting the best model tap orders is discussed in the DPD Tuning and Testing section as a part
of DPD tuning recommendations.
Table 73. Suggested Model Orders for Narrow-Band Waveforms
Taps Model Orders for Each Tap
Tap 1 B[1] = 0x1F, 0x3F, 0x7F, 0xFF
Tap 0 and Tap 2 B[0] = B[2] = 0x03, 0x07, 0x0F, 0x1F, (Tap 0 and Tap 2 should be the same.)
Tap 3 B[3] = 0x0, 0x02, 0x06, 0x0E, 0x1E, 0x3E
The user could configure the changeModelTapOrders and modelOrdersForEachTap through TES, as shown in Figure 149 and Figure 150.
Figure 149 shows the default model tap configuration and Figure 150 shows a customized model tap configuration which is equivalent to
B[0] = 0x07, B[1] = 0x7F, B[2] = 0x07 and B[3] = 0x06. (Note Tap 0 and Tap 2 should always be the same. For simplicity GUI uses X to
represent )
24159-150
Figure 149. Configuring Default Model Tap Order Through TES
24159-151
Figure 150. Configuring Customized Model Tap Order Through TES
UG-1828 Preliminary Technical Data
Rev. PrA | Page 170 of 253
preLutScale
This value, given as a fixed point U2.1 number, sets the scaling factor before searching the LUT. The scaling factor can be set as 1, 1.5, 2,
2.5, 3 and 3.5. This allows the user to scale the input signal magnitude in order to cover close to the full range of the LUT for better DPD
performance. If the signal input to the compander is too small, then only part of the LUT is utilized. When the input signal is small, user
could try different scaling factors to increase the signal level which might improve the DPD performance. The scaling factor can be
determined according to the dBFS of the input data peak. As an example, if the signal peak power is less than -4dBFS, the scaling factor
3.5 could be applied. As shown in Figure 149 and Figure 150, the default value of “pre-LUT Scale” is 2, which could be further changed
by user.
DPD Post Initial Calibration Parameters Configuration
The second set of DPD parameters should be configured after initial calibration. It is defined by the following data structure:
typedef struct adi_adrv9001_DpdCfg
{
uint32_t numberOfSamples;
bool outlierRemovalEnable;
uint32_t outlierRemovalThreshold;
uint32_t additionalPowerScale;
uint32_t rxTxNormalizationLowerThreshold;
uint32_t rxTxNormalizationUpperThreshold;
bool immediateLutSwitching;
bool useSpecialFrame;
bool resetLuts;
} adi_adrv9001_DpdCfg_t;
Table 74 briefly summarizes all the DPD post initial calibration parameters described in the data structure.
Table 74. DPD Post Initial Calibration Parameters
Parameter Type Description Min Max Default Note
numberOfSamples uint32_t Specifies the number of
samples to use for each
iteration of DPD
computation.
1024 4096 4096 The maximum
value is preferred.
outlierRemovalEnable uint8_t
(bool)
Enables an algorithm for
removing captured data that
may render DPD
computation unstable.
FALSE Currently not
supported, so
user should set
“FALSE”.
outlierRemovalThreshold uint32_t
(U2.30)
If the above parameter is
enabled, defines a threshold
for removing captured data
that may render DPD
computation unstable.
0 Currently not
used since outlier
removal
algorithm is not
supported.
additionalPowerScale uint32_t Provides an estimate of the
standard deviation of the
modem input data
magnitude to scale the data
for internal DPD
computation.
0 232-1 4
rxTxNormalizationLowerThreshold uint32_t
(U2.30)
Signal power for the lower
threshold for the
normalization of the
magnitude and phase of the
RX and TX data
0 1.0 0.0031622776602
(−25 dBFS)
rxTxNormalizationUpperThreshold uint32_t
(U2.30)
Signal power for the upper
threshold for the
normalization of the
magnitude and phase of the
RX and TX data
0 1.0 0.031622776602 (-
15 dBFS)
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Rev. PrA | Page 171 of 253
Parameter Type Description Min Max Default Note
immediateLutSwitching bool Determines whether the LUT
switches immediately or at
the end of Tx data frame.
TRUE FALSE not
currently
supported.
useSpecialFrame bool DPD only runs on a user
indicated special frame.
FALSE Currently not
supported.
resetLuts bool Reset LUTs so that no pre-
distortion is applied.
FALSE User should reset
LUTs at the start
of DPD operation.
Each of these parameters are described in more details as the following:
numberOfSamples
It specifies the number of samples used per DPD data capture with a limit of 4096. In general, the DPD performance could be improved
if more samples are used. For TETRA1, currently, the Linearization Channel (LCH) is not supported so the numberOfSamples should be
set to 4096. When LCH is supported, the numberOfSamples could be changed to a different value. More information will be provided in
the future.
For LTE, the Number of Sample should be set to 4096 without frequency hopping.
outlierRemovalEnable
This feature removes anomalous captured data before DPD computation. Currently it is not implemented and should be disabled.
outlierRemovalThreshold
Since outlier removal is not implemented, this threshold is ignored.
additionalPowerScale
This parameter is used to scale the higher power terms during the calculation of the auto-correlation matrix using transmit data d(n). It
is used to keep the nominal magnitude of each of the power terms about the same to avoid ill condition of the correlation matrix. The
scaling factor could be defined as , where “std” stands for standard deviation. User could measure and then pass
the information through this parameter.
rxTxNormalizationLowerThreshold/rxTxNormalizationUpperThreshold
These are required parameters for the normalization of the magnitude and phase of the Rx and Tx data. These thresholds are used to
pick a linear region for normalizing the data. The region chosen should be below the compression point but above the noise. In the AM-
AM and AM-PM plots shown in Figure 142, a possible choice of the linear region is highlighted in red. In general,
rxTxNormalizationUpperThreshold should be set to 0.5 of the peak signal amplitude and rxTxNormalizationLowerThreshold should be
set to 0.3 of the peak signal amplitude. Once they are set, the threshold values should be fixed and not vary from capture to capture.
Therefore, by knowing the peak Tx signal in dBFS, rxTxNormalizationUpperThreshold should be set to “peak Tx dBFS – 6 dB” and
rxTxNormalizationLowerThreshold should be set to “peak Tx dBFS – 10.5 dB”. Peak Tx is usually set at P1dB by adjusting the Tx
attenuation setting.
The user could enter those thresholds in dBFS through TES. If using API, the linear numbers should be used which can be calculated as
10(threshold_dBFS/10).
immediateLutSwitching
When a new DPD solution is formed, the new solution is loaded into a spare LUT, which can then be switched with the active LUT.
There are two options regarding the LUT switching. When immediateLutSwitching is set to be “TRUE”, the new LUT swaps out the
active LUT immediately when ready. When immediateLutSwitching is set to be “FALSE”, after the updated LUT is available, LUT
swapping is triggered after the next data frame is completed. Note this only applies to TDD operations. FDD systems should always use
immediate LUT switching. Currently, it should always set to be “TRUE”.
useSpecialFrame
In order to achieve optimal performance, DPD needs to capture the peaks of the signal. Some standards allow for transmission of special
data that can be used for DPD estimation. In other cases, the baseband processor may know in advance that a frame will contain good
data for DPD estimation. In these cases, the user may choose to control which frames are used for DPD. The flag indicates that the user
will control the frames that DPD can capture. This is currently not supported so it should be disabled.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 172 of 253
resetLuts
To start DPD operation from a known state, user should reset LUTs. By setting resetLuts to be 1, it sets most polynomial terms to be 0 to
remove the pre-distortion at the beginning of DPD operation.
User could configure the DPD post initial calibration parameters through TES as shown in Figure 151.
24159-152
Figure 151. Configuring DPD Post Initial Calibration Parameters Through TES
BOARD CONFIGURATION
Besides configuring the DPD pre initial calibration and post initial calibration parameters, user should also configure 2 other parameters
related to the board configuration. These 2 parameters are externalLoopbackPeakPower and externalLoopbackPathDelay, which should
be provided to ADRV9001 before performing initial calibrations.
externalLoopbackPeakPower
It indicates the peak power of ORx input signal loop backed from the Tx output. For DPD to achieve an optimal performance, the ideal
externalLoopbackPeakPower should be set about -18dBm with a tolerance of ±5dBm. User could adjust the peak power by utilizing an
external step attenuator after power amplifier.
externalLoopbackPathDelay
DPD requires the alignment of the Tx signal capture x(t) with the external loopback capture y(t). The externalLoopbackPathDelay
parameter provides user the capability to compensate for additional delays on the external loopback path from the ADRV9001 Tx output
to ORx input. User should measure this delay and provide it to ADRV9001 before initial calibration. The measured delay is then used to
compensate the delay between x(t) and y(t). This parameter is critical especially for wideband applications due to high sample rate. In
narrowband application, it is less critical so user could simply set it to be zero unless there is a larger than usual delay in the external
loopback path.
User could set these 2 configurations through TES as shown in Figure 152.
24159-153
Figure 152. Configuring Board Configuration Related Parameters Through TES
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Rev. PrA | Page 173 of 253
DPD API PROGRAMMING
A set of API commands are provided to set and inspect the DPD parameters, which is summarized in Table 75. Board configuration
parameters should be set through ADRV9001 initialization structure. Please refer to the doxygen document for more details.
Table 75. DPD APIs
DPD Rx Function Name Description
adi_adrv9001_dpd_Initial_Configure Configures the pre initial calibration DPD parameters. Called by
adi_adrv9001_Utilities_InitRadio_Load() as part of device initialization.
adi_adrv9001_dpd_Initial_Inspect Inspects the pre initial calibration DPD parameters.
adi_adrv9001_dpd_Configure Configures the post initial calibration DPD parameters.
adi_adrv9001_dpd_Inspect Inspects the post initial calibration DPD parameters.
DPD TUNING AND TESTING
Figure 153 describes an example setup for testing the integrated DPD with the ADRV9001 evaluation board in narrowband applications.
(In narrowband applications such as TETRA, power amplifier input should be connected to the TX1 output and power amplifier output
should be connected to RX1B.) As shown in Figure 153, an LPF is required at the Tx1 output port to filter out the Tx harmonics before
feeding the signal to power amplifier driver (If the power amplifier driver has an internal LPF, then the external LPF is not needed). Since
the device uses square wave mixer, it produces strong odd-order harmonics. Without filtering those harmonics, the DPD performance
could be impacted. The step attenuators external to the ADRV9001 evaluation board are optional. Note it is important to set up the
external loopback path before operating the integrated DPD. To achieve optimal DPD performance for TETRA waveforms, it is
recommended to use an external LO source for TX due to possible better phase noise performance, while the RX LO remains internal
because the RF receive signal is downconverted to an IF instead of directly to baseband. For wideband applications, the setup is similar
but both TX and RX LOs could be set to be internal because a wideband signal is less sensitive to phase noise. A spectrum analyzer can be
set up to observe the ACPR performance during a DPD operation.
XILINX
ZYNQ
FP G A BOARD
SIGNAL
GENERATOR
PC
POWER
AMPLIFIER
AMPLIFIER
DRIVER
FOR CAPT URING S P E CTRUM ANALYZ E R S CRE E N S HOT
GPIB
POWER
DIVIDER/
DIRECTIONAL
COUPLER
Tx1 P O RT
Rx1 PORT
STEP
ATTENUATOR HIGH POWER
ATTENUATOR
USB T O
ETHERNET
ADAPTER
USB T O
GPIB
ADAPTER
SPECTRUM
ANALYZER
ETHERNET
USB
USB REFERENCE
CLOCK POWER
DIVIDER
Tx EXTERNAL LO1
EXTERNAL
REFERENCE
CLOCK
EXTERNAL
REFERENCE
CLOCK
LPF
ADRV9001
TES
ADRV9001
EVAL
BOARD
24159-154
Figure 153. An Example Setup for Testing the Integrated DPD in Narrowband Applications
Once the setup is ready, user should further configure the TES and available external components properly which includes the following
major steps:
• Select desired profile.
• Perform board configuration to indicate external loopback path with external power amplifier is available.
• Enter the peak power of the loopback signal (ideally, it should be adjusted to be -18dBm±5dB. This could be achieved by tuning the
external step attenuator).
• Measure the external loopback delay and provide it through TES.
• Configure other initialization parameters such as RF frequency, LO source, etc. as desired. Also, enabling DPD for TX and configure
the model tap polynomial terms. It is recommended to start with the default model tap. (The method of tuning the model tap order
will be discussed in the next section.)
UG-1828 Preliminary Technical Data
Rev. PrA | Page 174 of 253
• Turn on DPD tracking calibration and all the other available tracking calibrations and start with the default DPD post calibration
parameter settings provided in TES.
• After programming, load, and play the provided sample Tx input file.
• Properly tune the Tx attenuation and/or the step attenuator to make sure that the ACPR performance at the device Tx output is
satisfactory before passing to power amplifier. In addition, make sure that the Tx peak signal is around P1dB compression region for
optimal DPD performance.
The user could compare the ACPR performance through spectrum analyzer with and without using the integrated DPD. Significant
ACPR performance improvement with the integrated DPD should be observed even with internal LO sources. For TETRA waveforms,
the ACPR after the second iteration of DPD is between −70 dB and −60 dB at an amplifier compression of P1dB. For LTE waveforms, the
ACPR after the second iteration of DPD is between −55 dB and −50 dB at an amplifier compression of P1dB.
Tuning the Model Tap Order
DPD can be considered as an adaptive filter which is modelled according to the behavior of the power amplifier. As mentioned earlier,
the ADRV9001 default model (Model 4) consists of four taps. Each tap consists of a series of polynomial terms to fit the nonlinear
behavior due to compression at higher output power. The order of polynomial terms is determined by intermodulation falling closer to
the carrier spectrum. In DPD, the orders of intermodulations that need to be considered are usually third, fifth, and seventh orders, with
decreasing magnitude, respectively. An nth-order intermodulation expands the signal bandwidth by n times. By inspecting the
bandwidth expansion factor on a spectrum analyzer, the user can estimate how many orders of intermodulations that need to be
included in the polynomial terms, in order to suppress the spectral regrowth down to the required ACPR. It is important not to include
higher order power terms than needed, which might cause DPD unstable.
DPD Model 4 consists of four taps as shown in the example tap arrangement diagram in Figure 154. The four taps can be classified into
three categories:
The main tap – The main tap of the DPD adaptive filter that suppresses most of the spectral regrowth due to intermodulation; hence it
has the greatest number of polynomial terms. It is labelled as TAP1.
The side taps – There are two side taps on each side of the main taps. They are memory terms that compensate for frequency-dependent
distortion in the frequency domain, and time misalignment between the transmit and receive captured data. The side taps have the same
number of polynomial terms; and each side tap has about half of the number of polynomial terms of the main tap. They are labelled as
TAP0 and TAP2.
The cross-term tap – The cross term is designed for further suppressing the residual spectral regrowth left over by the other three taps.
The number of polynomial terms is usually equal to or less than that of each side tap. It is labelled as TAP3.
x(t–2)x|(t–2)|
k–1
k = 1:3
x(t)|x(t)|
k–1
k=1:3
x(t–1)|x(t–1)|
k–1
k=1:7
DECREASING t IN x(t)
DECREASING t IN |x(t)|
k
INCREASING t IN |x(t)|
k
INCREASING t IN x(t)
x(t–1)|x(t–2)|
k–1
NONE or k = 2:3
73 3
3
SIDE TERMS
MAIN TERMS
CROSS TERMS
TAP
1
TAP
3
TAP
2
TAP
0
24159-155
Figure 154. Example Polynomial Constellation Configuration for Model 4
Note that in Figure 154, k represents the order. To handle 7th harmonics, the main tap must include the power terms up to k = 7.
Preliminary Technical Data UG-1828
Rev. PrA | Page 175 of 253
To find the best model tap order for a specific power amplifier design model, the user can take the following recommended procedures:
1. Set the amplifier output power to have a compression ratio of 1 dB or slightly less, as shown in Figure 1, i.e. the maximum peak of
the output signal is 1 dB below ideal linearity.
2. Determine the initial highest polynomial order of the main tap, TAP1, by measuring the spectral regrowth bandwidth to carrier
bandwidth ratio. All lower order polynomial terms must be included. For example, if the bandwidth ratio is 5, set the initial highest
polynomial to k = 5,that is, x(t – 1)|x(t – 1)|4
3. Set the other taps to zeros, that is, turn off the other taps.
4. Use only TAP1 to execute DPD with order 5, then 6, and 7 (i.e. up to two orders above the initial estimate). Measure the ACPR for
each case. Select the one that yields a better ACPR. If the difference is small, select a lower order one, say 5.
5. While keeping the main tap determined above, set the side taps, TAP0 and TAP2, to about half the order of the main tap. In the
above example, the main tap has an order of 5, select the initial side tap order to be 2. Execute DPD with the main tap of order 5,
and the side tap order of 2, then 3, and 4. Select the side tap order that yields the lowest ACPR, say 3.
6. While keeping the main tap and side tap orders determined above, set the initial cross term tap order, TAP3, to be 2. Execute DPD
with the cross-term tap order of 2 and 3. Select none, 2 and 3, which yields the best ACPR. If the difference is small, select the lower
order one, including “none” taps. Some power amplifiers do not need a cross term.
7. Iterate the above procedure as necessary with different combinations until you are confident with the selections. Keep all tap order
selections to be minimal that satisfies your ACPR requirement with a 5 dB margin, which helps to keep DPD more stable. For
example, if your ACPR requirement is −60 dB, set your ACPR target to be −65 dB.
UG-1828 Preliminary Technical Data
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GENERAL-PURPOSE INPUT/OUTPUT AND INTERRUPT CONFIGURATION
ADRV9001 provides user with number of software configurable General-Purpose Input/Output (GPIO) pins. By utilizing API functions,
user can configure GPIO pins to operate with a variety of control or monitoring functions. ADRV9001 has two types of GPIO:
• 16 digital GPIO pins
• referenced to VIOCTRL_1P8 supply
• designated DGPIO_0 through DGPIO_15
• 12 analog GPIO pins
• referenced to VAGPIO_1P8 supply
• designated AGPIO_0 through AGPIO_11
The Digital and Analog GPIO pins can be utilized as real-time status signals that provide device status information from ADRV9001 to
the baseband processor when the GPIO pins are configured as outputs, with respect to ADRV9001. When set as inputs, the GPIO pins
can be utilized as real-time control signals that can alter the device state. The API functions related to GPIO configuration give the user
the ability to configure pins as inputs or outputs and assign functionality to specific pins.
Figure 155, Figure 156 illustrates the different functionalities that can be enabled in the device and then controlled using the Digital
GPIO pins and Analog GPIO pins, not all functionalities can be enabled at the same time.
DGPIO 15
DGPIO 14
DGPIO 13
DGPIO 12
DGPIO 11
DGPIO 10
DGPIO 9
DGPIO 8
DGPIO 7
DGPIO 6
DGPIO 5
DGPIO 4
DGPIO 3
DGPIO 2
DGPIO 1
DGPIO 0
MANUAL PIN TOGGLE
I/O
BUFFER
I/O
CROSS
Tx S SI REFERENCE CLO CK OUTP UT
MO NITOR W AKE UP I RQ
CONTROL OUTPUT
ORx ENABLE CONTROL
Rx GAI N CONT ROL
Tx ATTE NUATI ON CONTRO L
PA RAMP CO NTRO L
MONITOR MODE CONTROL
HOPPING MODE CONTROL
AGC O V E RLO AD INDICATO R
24159-156
Figure 155. Digital GPIO Features Overview
I/O
BUFFER
I/O
CROSS
AGPIO 11
AGPIO 10
AGPIO 9
AGPIO 8
AGPIO 7
AGPIO 6
AGPIO 5
AGPIO 4
AGPIO 3
AGPIO 2
AGPIO 1
AGPIO 0
Rx EXT E RNAL G AIN CONTRO L
RF FRONT END CO NTRO L
MANUAL PIN TOGGLE
AUXDAC
24159-157
Figure 156. Analog GPIO Feature Overview
In configuring the GPIO, the two major factors to consider are the GPIO output enable control and the GPIO source control.
The output enable determines the direction of the pin, if a pin is set as output, then the GPIO I/O buffer is configured as an output. The
GPIO CMOS output drive strength can be increased for capacitive loads bigger than 10 pF to increase the edge rate of output signal
during transitional period.
The GPIO source control determines the functionality of the pin. The Digital GPIO source control is assigned in groups of 2, this means
that DGPIO_0 to DGPIO_1 share a single source control, DGPIO_2 to DGPIO_3 share a single source control, etc. The Analog GPIO
source control is assigned in groups of 4, that means that AGPIO_0 to AGPIO_3 share a single source control, AGPIO_4 to DGPIO_7
share a single source control, etc.
Preliminary Technical Data UG-1828
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The following subsections explain the operation details of digital GPIO and analog GPIO.
DIGITAL GPIO OPERATION
Each Digital GPIO pin can be set to either input or output mode, the input mode allows the baseband processor to drive pins on the
ADRV9001 to execute specific tasks, the output mode allows the ADRV9001 to output various control or status signals to baseband
processor.
The API commands adi_adrv9001_gpio_ControlInit_Configure() and adi_adrv9001_gpio_Configure() are used to configure the digital
GPIO work mode.
Note that conflicts regrading GPIO usage may occur when using combinations of certain features, users should ensure that multiple
functions are not assigned to the same GPIO pins.
Digtial GPIO Input Features
The following table provides a list of digital GPIO input features available that interact with datapath control elements on ADRV9001,
for the Digital GPIO features with the Table 76, the API automatically sets the I/O direction of the GPIO pins assigned for the feature.
Table 76. Summary of Input Digital GPIO Features
Feature Description
GPIO Pins Available for
Feature
ORx Enable Configure specific Digital GPIO pins to enable/disable Rx observation channel.
DGPIO_0 through DGPIO_11:
ORx Enable control pin select.
Pin Based Tx attenuation
Increment and
Decrement
Configures specific Digital GPIO pins to increase or decrease attenuation on
any Tx channel after a rising edge on the assigned pin.
DGPIO_0 through DGPIO_15:
Tx attenuation increment pin
select.
DGPIO0 through DGPIO_15:
Tx attenuation decrement pin
select.
Pin Based Rx/ORx Gain
Index Increment and
Decrement
Configures specific Digital GPIO pins to increase or decrease gain index on
any Rx or ORx channel after a rising edge on the assigned pin.
DGPIO_0 through DGPIO_15:
Rx/ORx gain index increment
pin select.
DGPIO0 through DGPIO_11:
Rx/ORx gain index decrement
pin select.
Tx Power Amplifier Ramp
Control
Configure specific Digital GPIO pins to ramp up the power amplifier
controlling on any Tx channel after a rising edge on the assigned pin and
ramp down the power amplifier controlling on any Tx channel after a falling
edge on the assigned pin
DGPIO_0 through DGPIO_15:
power amplifier Ramp
controlling pin select.
Monitor Enable Configure specific Digital GPIO pins to enter or leave monitor mode or
wakeup adrv9001 when it’s in sleep mode.
DGPIO_0 through DGPIO_11:
Mon_enable pin select
Power Saving Control Configure Specific Digital GPIO to power up/down chip to save power DGPIO_0 through DGPIO_11:
Power Saving control pin
select
Hopping Mode control Configure specific Digital GPIO pins to control the Hopping mode, including
the hopping enable, update gain value, frequency index, etc.
DGPIO_0 through DGPIO_11:
Hopping Event pin select
DGPIO_0 through DGPIO_15:
Hopping gain value pin select
DGPIO_0 through DGPIO_15:
Hopping frequency index pin
select
ORx Enable Control
Please refer to the Microprocessor and System Control section for information related to Rx observation channel control.
Pin-Based Tx Attenuation Control
A complete description of Tx attenuation control is provided in the Transmitter Signal Chain section in this User Guide.
Pin-based Tx attenuation control provides an interface to make attenuation adjustments with precise timing control. The pin-based
control offers lower latency than SPI based attenuation change operations. In pin-based attenuation control, certain digital GPIO pins
UG-1828 Preliminary Technical Data
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are assigned “increment attenuation” or “decrement attenuation” functionality. By applying a high pulse on the assigned GPIO pin, the
attenuation for a specific channel is either increased or decreased, depending on the assigned functionality. Increment and decrement
functionality can be assigned to any digital GPIO from DGPIO_0 to DGPIO_15. Pin-based Tx attenuation control allows multiple
increments or decrements of Tx attenuation.
Set Tx attenuation control mode to “GPIO_MODE” by the API function adi_adrv9001_Tx_Attenuation_Configure() or
adi_adrv9001_Tx_AttenuationMode_Set(), and select the properly GPIOs for each channel by the API function
adi_adrv9001_TxAttenPinCtrlCfgSet() (TBD), baseband processor can send the pulses to ADRV9001 via the specific digital GPIO pins
to increase or decrease the Tx attenuation.
Pin-Based Rx Gain Control
A complete description of Rx Gain control is provided in the Rx Gain Control section of this User Guide.
Pin-based Rx gain control is relevant for applications which require Manual Gain Control (MGC) and precise timing for gain change
events. The pin-based control offers lower latency than SPI based gain change operations. In pin-based gain control, certain digital GPIO
pins are assigned “increment gain index” or “decrement gain index” functionality for a particular receiver channel. By applying a high
pulse on the assigned GPIO pin, the gain index for a specific channel is either increased or decreased, depending on the assigned
functionality. The pulse width requirement is 2 AGC clock cycles (184.32 MHz) in the logic high state. Increment and decrement
functionality can be assigned to any digital GPIO from DGPIO_0 to DGPIO_15.
Note that if the user has programmed a gain table that operates in a subset of the full gain table range (i.e. using index 195 to 255), the
pin-based Rx gain control does not have knowledge of this status. if the gain decrement pulse is applied when the gain index is 195. The
gain index will be decreased off table. It is possible that off-table gain indices (i.e. gain indices below 195) correspond to maximum gain
condition. It is recommended to exercise care when applying pulses when the gain index is at the edge of useful section gain table, or
design gain table with this in mind.
Set Rx Gain control mode to “PIN” by the API function adi_adrv9001_Rx_GainControl_Configure() or
adi_adrv9001_Rx_GainControl_Mode_Set(), configures the properly digital GPIO pins for gain increase and decrease control and other
control parameters by API function adi_adrv9001_Rx_GainControl_PinMode_Configure(), then baseband processor can send the
pulses to ADRV9001 via the specific digital GPIO pins to increase or decrease the Rx Gain index.
Power Amplifier Ramp Control
A complete description of power amplifier ramp control is being provided in the user guide in the future.
When the power amplifier ramp control function is utilized in ADRV9001, certain digital GPIO pin can be assigned as the “power
amplifier ramp control enable” functionality driven by the baseband processor, the rising edge of power amplifier ramp control enable
with programable delay will be act as the ramp up trigger signal and the falling edge of power amplifier ramp enable with programable
delay acts as the ramp down trigger signal.
Monitor Enable
See the Power Saving and Monitor Mode section for a complete description of monitor mode.
When the monitor mode is initialized in ADRV9001, certain digital GPIO is assigned as “Mon_enable” functionality driven by the
baseband processor, after necessary parameters initialization for monitor mode, by de-asserting and asserting the monitor enable pin will
enable the transitions between the Normal and Monitor operation modes or wake up ADRV9001 from sleep state at the falling edge of
“Mon_enable”.
Hopping Mode Control
TBD.
Digtial GPIO Output Features
This section outlines digital GPIO output features available on the device. Output GPIO features on ADRV9001 use a concept called
source control. The source control describes what is the source of the signals routed to GPIO pins, whether they are from the monitor
feature or the ARM.
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Table 77 summarizes the available source control selections, source control is relevant for GPIO pins that are configured in the output
mode, GPIO pins operating in the input mode do not require a source control setup.
Table 77. Summary of Digital GPIO Output Features
Feature Description GPIO Pins Available for Feature
Control out Mux Allows a choice of Main/RX/TX control signals to output from ADRV9001 to
monitor the status of the device
Any Digital GPIO
Manual Pin Toggle
Manual control the GPIO output level, API functions sets output pin levels
and reads the input pin levels
Any Digital GPIO
Monitor WakeUp
Baseband
Processor/DSP
Interrupt signal to wake up baseband processor/DSP when baseband
processor/DSP is in sleep state
Any Digital GPIO
Rx AGC overload
indicator
Allows output the AGC overload signals Any Digital GPIO
TX DCLK OUT Allows output the SSI reference clock for baseband processor to generate the
TX SSI clock, data and strobe to ADRV9001
DGPIO_12 through DGPIO_13
TX Channel 1 SSI reference clock
out pin select,
DGPIO_14 through DGPIO_15
TX Channel 2 SSI reference clock
out pin select
Mirror Analog GPIO
Input
Allow the Analog GPIO input to output on Digital GPIO pins Any Digital GPIO
Control Out Mux
Control Out Mux (sometimes referred as “Monitor out”) allows status signals within the ADRV9001 to be output to digital GPIOs, there
are several types control out muxes as described below:
• Rx Control Out (Available for Rx1, Rx2)
• Tx Control Out (Available for Tx1, Tx2)
• Main Control Out
For each element in this list, there is a corresponding table that provides the available signals. Each row in the table has, at most, 8 signals
that can be routed to GPIO pins.
Rx Control Out Table
[TBD]
Tx Control Out Table
[TBD]
Main Control Out Table
[TBD]
Manual Pin Toggle
This feature allows control of the logic level of individual digital GPIO pins, after configuring the I/O direction and source control, the
adi_adrv9001_gpio_OutputPinLevel_Set() command is used to set the output level of GPIO pins.
adi_adrv9001_gpio_OutputPinLevel_Get() command is used to read the GPIO pins output levels.
Additionally, adi_adrv9001_gpio_InputPinLevel_Get() command can be used to read the input GPIO level if the relative GPIO is
configured as input.
Monitor Wake-Up Baseband Processor/DSP
Certain digital GPIO pin is assigned as “wake up baseband processor/DSP” to output the interrupt signal to wake up the baseband
processor/DSP when ADRV9001 works in monitor mode and specific detection conditions are met.
Rx AGC Overload Indicator
The status of peak detectors and power detector in the Rx channel can be retrieved to baseband processor through a set of DGPIO pins.
One DGPIO configuration is for using the peak detect mode, in which the overrange and under-range conditions of both APD and HB
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detectors are provided to user. The other DGPIO configuration is for using the peak/power detect mode, in which the overrange and
underrange conditions of APD and power detector are provided to user.
The DGPIO pins could be associated with either one of the receivers, Rx1 or Rx2. However, when the similar information is required for
both receivers, they could be selectively muxed and provided to user simultaneously.
Data structure of adi_adrv9001_GainControlCfg_t, and of its substructures, adi_adrv9001_PeakDetector_t,
adi_adrv9001_PowerDetector_t initialize the necessary Gain control parameters as well as the digital GPIO pins assignment for the
overload indicator, API command adi_adrv9001_Rx_GainControl_Configure() is provided to set the parameters. See the Rx Gain
Control section for the detail.
TX DCLK OUT
This mode allows to configure the GPIO pins to a pair of differential or a single-ended reference clock for baseband processor if the TX
SSI and RX SSI runs at different lane rate, the users could use this reference clock to generate the TX LSSI clock, data and strobe when
the RX SSI and TX SSI run at different clock rate. TX1_DCLK_OUT± functionality can be assigned DGPIO_15 and DGPIO_14 when it
is in LVDS mode, or either of DGPIO_15 or DGPIO_14 can be used as the Tx1 SSI DCLK out if it is in CMOS mode.
TX2_DCLK_OUT± functionality can be assigned DGPIO_13 and DGPIO_12 when it’s in LVDS mode, or either of DGPIO_13 or
DGPIO_12 can be used as the Tx1 SSI DCLK out if it is in CMOS mode.
Mirror Analog GPIO Input
The digital GPIO sources can be configured to select Analog GPIO as input, potentially mirroring up to all available 12 analog GPIOs'
input on the digital GPIOs as output.
ANALOG GPIO OPERATION
The main purpose of the Analog GPIO pins is to serve as control pins for the external control elements, such as a Digital Step Attenuator
(DSA), Low Noise Amplifier (LNA), external LO/VCO components, T/R switch of TDD system, etc. An alternative function of some
Analog GPIO pins are to provide the auxiliary DAC output.
A high level overview of the analog GPIO features are provided in Table 78. Other features may be exposed in future software releases.
Table 78. Summary of Analog GPIO Features
Feature Description GPIO Pins Available for Feature
RX Gain Table
External Control
Word
The RX gain table includes a column for 2-bit control of an
external gain element (LNA), each Rx channel has 2 fixed
Analog GPIO pins associated with it.
Rx1 external control word: [AGPIO_1, AGPIO_0],
[AGPIO_5, AGPIO_4], [AGPIO_9, AGPIO_8]
Rx2 external control word: [AGPIO_3, AGPIO_2],
[AGPIO_7, AGPIO_6], [AGPIO_11, AGPIO_10]
Manual Pin Toggle Manual control the GPIO output level, API functions sets
output pin levels and reads the input pin levels
Any Analog GPIO
Mirror Digital GPIO
Input
Allow the digital GPIO input to output on the analog GPIO pins Any Analog GPIO
RF Front-End Control Allow the RF front end control signal output on analog GPIO
pins
AGPIO_0 through AGPIO_11
Auxiliary DAC Output Allow the auxiliary DAC output on analog GPIO pins AGPIO_0: AuxDAC0 output pin select
AGPIO_1: AuxDAC1 output pin select
AGPIO_2: AuxDAC2 output pin select
AGPIO_3: AuxDAC3 output pin select
RX Gain Table External Control Word
A complete description of RX Gain Table external control is provided in Rx Gain Control section in this User Guide.
For proper use of this feature, a custom gain table must be created that uses the external control column. When a gain index with a non-
zero value in the external control column of the gain table is selected, the value of the external control column will be output on a pair of
analog GPIO pins. The configuration of the GPIO pins for the gain table external control word is performed with the
adi_adrv9001_RxGainTableExtCtrlPinsSet() API command.
Manual Pin Toggle
Similar with the manual pin toggle for digital GPIOs, this feature allows control of the logic level of individual analog GPIO pins, after
configuring the I/O direction and source control, the Adi_adrv9001_GpioAnalogOutPinLevelSet() command is used to set the output
level of GPIO pins. adi_adrv9001_GpioAnalogOutPinLevelGet() command is used to read the analog GPIO pins output levels.
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Additionally, adi_adrv9001_GpioAnalogInputPinLevelGet() command can be used to read the analog GPIO input level if the relative
analog GPIOs are configured as input.
Mirror Digital GPIO Input
The analog GPIO sources can be configured to select digital GPIO as input, potentially mirroring DGPIO_0 through DGPIO_11/input
on the analog GPIOs as output/[TBD]
RF Front-End Control
To save the baseband processor control pins, ADRV9001 provides the function to output control signals via analog GPIO pins to power
up/down the external RF front end components (i.e. LNA, TX Gain blocks, Ext PLL) or switch the T/R switch of a TDD system. For
example, a TX_On, RX_ON output signal through the analog GPIOs and associated with the ADRV9001 internal work timing and state
can be used to enable/disable the power amplifier and LNA respectively. Alike, EXT_PLL_ENABLE, VCO_ENABLE can be used to
enable/disable the relative components if they are necessary.
Auxiliary DAC Output
Auxiliary DAC can supply bias voltages, analog control voltages, or other system functionality, refer the Auxiliary Converters and
Temperature Sensor section for the detail. Analog GPIO 0 through 3 provide the alternative function for the Aux DAC 0 through 3
output respectively.
INTERRUPT
The ADRV9001 features the general purpose interrupt output pin (GP_INT), the GP_INT pin can alert the baseband processor that an
important event or error regarding the device operation has occurred. These events include of unlocking of PLLS, Stream Processors
errors or ARM exception, etc.
A description of the interrupt sources and their bit positions is provided in Table 79. An Interrupt source can be masked so that it won’t
be transmitted to the BBIC on GP_INT pin or in status registers. An interrupt is masked when the corresponding mask SPI bit is set to
‘1’. The GP_INT pin represents a logical OR of the enabled GP_INT mask sources. It is not necessary to enable all of the interrupt
sources.
Table 79. GP_INT Bitmask Description
Bit Position Description Component
0 ARM Error. ARM
1 Force set an interrupt ARM
2 ARM system error ARM
3 ARM calibration error ARM
4 Monitor interrupt ARM
5 Tx1 power amplifier Protection Error Transmitter
6 Tx2 power amplifier Protection Error Transmitter
7 Low Power Clock PLL Lock indicator Lower Power Clock PLL
8 RF PLL 1 Lock indicator RF PLL1
9 RF PLL 2 Lock indicator RF PLL2
10 Aux PLL Lock indicator Aux PLL
11 Clock PLL Lock indicator Clock PLL
12 Main clock 1105 MCS Clock Distribution
13 Main clock 1105 Second MCS Clock Distribution
14 RX1 LSSI MCS RX SSI
15 RX2 LSSI MCS RX SSI
16 Main Stream Processor Error Stream Processor
17 Stream Processor 0 Error Stream Processor
18 Stream Processor 1 Error Stream Processor
19 Stream Processor 2 Error Stream Processor
20 Stream Processor 3 Error Stream Processor
21 Not used
22 Not used
23 Not used
24 Not used
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The GP_INT pin is configured by adi_adrv9001_gpio_GpIntMask_Set() after device initialization. When a rising edge is detected on the
GP_INT pin, the baseband processor should call the API command adi_adrv9001_gpio_GpIntHandler() , the interrupt handler will
return information related to the interrupt source to the user. Calling this command may be sufficient to clearing the error. Either
handler function returns a recovery action which suggests further action if necessary, adi_adrv9001_gpio_GpIntStatus_Get() can also be
used to read in the current interrupt status register.
Two cases are provided for users to handle the interrupt.
Usecase 1: User Handles Status Register
In this scenario, full control (via public API functions) is given to the user to set/get mask, sticky mask and status registers (although the
status register is a read only). Hence the user can custom tailor solutions (recovery actions) to handle the different events/interrupts. This
requires that the user completely maintains the status register (i.e. clear interrupts that have been serviced bit by bit).
Usecase 2: User Calls ADI GPIntHandler (Recommended)
In this scenario, the user can monitor the GP_INT pins and call a central GPIntHandler function provided by ADI to handle decoding
and maintaining the status register. The user can then plug their custom actions into the corresponding sub block of the GPIntHandler
function (or implement their recovery action after GPIntHandler). The advantage of using this technique (and why it is recommended)
is that ADI can provide some built-in recovery action for specific events before potentially calling user functions. Figure 157 shows the
sequence of events between baseband processor and ADRV9001 API with respect to the GP interrupts.
BASEBAND
PROCESSOR
(USER)
EVENT
ADRV9001
API
MONITOR GP_INT
GP_INT GOES HIGH
adi _adrv9001_G pIntHand ler( )
READ ST ATUS RE GIS TER
LOOP THROUGH
ALL STATUS BITS
PROGRAMM E D TO
GP_INT E X E CUTING
RECOVERY CODE EVENT
CLE AR STAT US BITS
AS THEY ARE PROCESSED
RET URN STAT US RE GIS TER P RIOR
TO CLEARING PLUS GP_INT MASK
COM P LET E ANY FURTHE R
PROCESSING IF NECESSARY
AN INTERRUPT EVE NT
IN EV E NT G ROUP
OCCURS
adi _adrv9001_G pIntM askS et ( FO R GP_I NT T O FIRE ON INTERRUP T EVE NT GROUP)
24159-158
Figure 157. Sequence of Events Between Baseband Processor and ADRV9001 API with Respect to GP Interrupts
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AUXILIARY CONVERTERS AND TEMPERATURE SENSOR
The ADRV9001 device features auxiliary data converters including four 12-bit auxiliary Digital-to-Analog converters (AuxDAC) and
four 12-bit auxiliary analog-to-digital converter (AUXADC_x). An integrated diode-based temperature sensor is available to readback
the approximate die temperature of the device.
These features are included to simplify control tasks and reduce pin count requirements on the baseband processor by offloading these
tasks to the ADRV9001. Example usage of the auxiliary converters include static voltage measurements performed by the AuxADC and
flexible voltage control performed by the AuxDAC. This section outlines the operation of these features along with API command for
configuration and control.
AUXILIARY DAC (AUXDAC)
There are four, independent, 12-bit AuxDACs integrated in the ADRV9001. The auxiliary DACs have an output voltage of
approximately 0.05 V to VAGPIO_1P8 – 0.05V. The AuxDACs use the enumeration adi_adrv9001_AuxDac_e when referenced in the
API. The pins used for the AuxDAC features are listed in Table 80.
Table 80. AuxDAC Pin Mapping and adi_adrv9001_AuxDac_e Enum Description
Aux DAC Number Pin Name Pin Number Enum Name
AUXDAC[0] AGPIO_0 F12 ADI_ADRV9001_AUXDAC0
AUXDAC[1] AGPIO_1 F10 ADI_ADRV9001_AUXDAC1
AUXDAC[2] AGPIO_2 F3 ADI_ADRV9001_AUXDAC2
AUXDAC[3] AGPIO_3 F5 ADI_ADRV9001 _AUXDAC3
The capacitive load of the AuxDAC pins should not exceed more than 100 pF otherwise stability issues may occur.
The AuxDAC uses the AGPIO pins on the device. Conflicts between AGPIO and AuxDAC functionality may occur. In case of these
conflicts, the AuxDAC takes precedence over all other AGPIO functionality when AuxDAC is enabled for a specific pin. When the
AuxDAC is disabled, the configured AGPIO functionality is applied. The AuxDAC can be enabled one pin at a time to allow flexibility
between AuxDAC and AGPIO functionality.
The AuxDAC is typically used in applications requiring analog control signals. The data interface used to set the output level of the
AuxDAC is SPI (API) or internal LUT (power amplifier RAMP function enabled) based. There is no CMOS/LVDS data interface to
provide input data to the AuxDAC.
The (ideal) output voltage expressed on the AuxDAC is based on the following equation (in volts):
2048
0.9 1.7
4096
AUXDAC
AuxDacValue
V−
=+×
where AuxDacValue is the 12-bit digital code applied to the AuxDAC.
The AuxDAC is not a precision converter, it is best used in feedback systems. Above AuxDAC output equation is to be characterized,
AuxDAC output voltage versus input codes for a full range code sweep of the AuxDAC will be added in the future after necessary
characterization.
AuxDAC API Programming
A set of API commands are provided to set and inspect the AuxDAC, which is summarized in Table 81.
Table 81. AuxDAC API list
AuxDAC Function Name Description
adi_adrv9001_AuxDac_Configure Sets the configuration for AuxDACs, enable/disable the selected AuxDAC
adi_adrv9001_AuxDac_Inspect Gets the configuration of selected AuxDAC
adi_adrv9001_AuxDac_Code_Set Sets 12 bit DAC code of selected AuxDAC
adi_adrv9001_AuxDac_Code_Get Reads the DAC word of selected AuxDAC
AUXILIARY ADC (AUXADC)
ADRV9001 contains four dedicated AuxADCs denoted as: AUXADC_0, AUXADC_1, AUXADC_2, and AUXADC_3. The AuxADC is
a 12-bit output delta-sigma converter useful for measuring DC and near-DC signals (<8KHz). The input voltage range of the AuxADC is
150mV to 800mV. Readback of the AuxADC input voltage is performed using API commands.
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The AuxADCs use the enumeration adi_adrv9001_AuxAdc_e when referenced in the API. The pins used for the AuxADC features are
listed in Table 82.
Table 82. AuxADC Pin Mapping and adi_adrv9001_AuxAdc_e Enum Description
Aux DAC Number Pin Name Pin Number Enum Name
AUXADC[0] AUXADC_0 H11 ADI_ADRV9001_AUXADC0
AUXADC[1] AUXADC _1 B8 ADI_ADRV9001_AUXADC1
AUXADC[2] AUXADC _2 B7 ADI_ADRV9001_AUXADC2
AUXADC[3] AUXADC _3 H4 ADI_ADRV9001_AUXADC3
The AuxADC clock rate is set to 30.72MHz (or close when ADRV9001 ARM system clock is changed) to get the best ADC performance.
There are no on chip calibrations executed for the AuxADC, the ADC accuracy is limited to the accuracy of the supply reference. A
simplified procedure for measuring and accounting for the AuxADC gain and offset error is performed, those AuxADC gain and offset
errors are used to compensate the AuxADCs measure results.
AuxADC API Programming
AuxDAC relative API commands are summarized in Table 83, users can find the detail in API help file.
Table 83. AuxADC API list
AuxDAC Function Name Description
adi_adrv9001_AuxAdc_Configure Sets to enable/disable the selected AuxADC
adi_adrv9001_AuxAdc_Inspect Gets the configuration of selected AuxDAC
adi_adrv9001_AuxAdc_Voltage_Get Sets 12 bit DAC code of selected AuxDAC
adi_adrv9001_AuxDac_Code_Get Reads the ADC code of selected AuxADC and converts to mV
TEMPERATURE SENSOR
The device features a temperature sensor that measures the temperature on the die. The temperature sensor uses an ADC similar to the
AuxADC, however it is a separate instantiation and has no connections to a device pin.
The initiation of a temperature measurement is performed without user intervention by the ARM processor. The user can retrieve this
measurement results in centigrade through an API command adi_adrv9001_ TemperatureGet().
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RF PORT INTERFACE INFORMATION
The RF ports of the ADRV9001 consisting of the transmit (TX1±, TX2±) and the receive ports (RX1A±, RX1B±, RX2A±, and RX2B±)
support a operational frequency range from 30 MHz to 6 GHz. This wide frequency range fulfils the requirements of many application
space. However, for optimized performance within a narrowband with minimal amplitude roll off and optimized linearity and noise
performance, the RF ports will need to be impedance-matched.
This User Guide provides some example impedance matching networks for a selection of frequency bands. Locating a balun/transformer
to cover the entire frequency range of the ADRV9001 with minimal phase and amplitude imbalance proves to be a challenging task given
limited selection of commercially available baluns. For this reason, the example RF matching networks were chosen based on the
available baluns/transformers and RF trace implementations on evaluation PCB.
The matching networks are divided into two categories, wideband and narrowband. The wideband matching networks cover a range of
almost 3 GHz and possess more amplitude roll off as compared to the narrowband match. This roll off is often dominated by the
characteristic performance of the balun/transformer. For more optimized performance within a narrowband, the frequency specific
narrowband matches are recommended.
TRANSMIT PORTS: TX1± AND TX2±
The ADRV9001 uses a direct conversion transmitter architecture consisting of two identical and independently controlled TX channels.
The differential output impedance of transmitter outputs is matched to 50 Ω as shown in Figure 158. Additionally, the TX outputs must
be biased to a low noise 1.8 V supply.
RECEIVE PORTS: RX1A±, RX1B±, RX2A±, AND RX2B±
The ADRV9001 has two RF inputs for each receiver to accommodate different matching for each RF bands of interest. The mixer
architecture is very linear and inherently wideband which facilitates wideband impedance matching. The differential input impedance of
the RX inputs are 100Ω as shown inFigure 159 and Figure 160.
When selecting a balun/transformer for the receive paths a 2:1 impedance transformation is required to accommodate the 50 Ω single-
ended impedance to 100 Ω differential impedance as required by the ADRV9001 RX inputs.
The receiver input pins are self-biased internally to 650mV and therefore will require AC coupling/DC blocking capacitors at its inputs.
EXTERNAL LO PORTS: LO1± AND LO2±
Two external LO inputs (LO1 and LO2) can be applied to ADRV9001 and each external LO signal can be used for any of two receivers or
two transmitters instead of internally generated LO signal. AC-coupling interface is needed for both positive and negative sides of
external LO input pins which are internally biased. Similar to RX RF interface, a balun with 2:1 impedance transformation is necessary to
accommodate the 50 Ω single-ended impedance to 100 Ω differential impedance as required by the ADRV9001 Ext LO inputs.
DEVICE CLOCK PORT: DEV_CLK1±
There are two low-frequency (below 100MHz) clock interface modes and a LVDS type clock interface mode that can support clock signal
running as fast as 1GHz. For the high frequency clock interface, off-chip 100 ohm resistive termination will be required along with ac-
coupling caps. More information is available on the subsequent section named connection for external device clock.
RF RX/TX PORTS IMPEDANCE DATA
This section provides the port impedance data for all transmitters and receivers in the ADRV9001 integrated transceiver. Please note the
following:
• The reference plane for this data is the ADRV9001 ball pads.
• Single-ended mode port impedance data is not available. However, a rough assessment is possible by taking the differential mode
port impedance data and dividing both the real and imaginary components by 2.
Contact Analog Devices Applications Engineering for the impedance data in Touchstone format.
UG-1828 Preliminary Technical Data
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0
5.0
–5.0
2.0
1.0
–1.0
–2.0
0.5
–0.5
0.2
–0.2
m1
FREQUENCY = 30.00MHz
S(2,2) = 0.036/174.443
IM P EDANCE = 46.518 + j0.327
m2
FREQUENCY = 1.000GHz
S(2,2) = 0.064/–152.286
IM P EDANCE = 44.598 + j2.647
m3
FREQUENCY = 2.000GHz
S(2,2) = 0.392/109.862
IM P EDANCE = 40.221 – j 2.724
m6
FREQUENCY = 6.000GHz
S(1,1) = 0.306/109.200
IM P EDANCE = 35.022 + j22.294
m5
FREQUENCY = 4.500GHz
S(2,2) = 0.249/143.402
IM P EDANCE = 32.079 + j10.157
m4
FREQUENCY = 3.000GHz
S(2,2) = 0.166/–177.256
IM P EDANCE = 35.757 – j 0.0585
FREQUENCY ( 30.00Hz TO 6. 000GHz)
S(2,2)
M6
M5
M3 M2
M1
M4
24159-159
Figure 158. ADRV9001 TX port Series Equivalent Differential Impedance
0
5.0
–5.0
2.0
–1.0
–2.0
0.5
–0.5
0.2
–0.2
m1
FREQUENCY = 30.00MHz
S(3,3) = 0.034/25.570
IM P EDANCE = 106.227 + j3.095
m2
FREQUENCY = 1.000GHz
S(3,3) = 0.062/–119.363
IM P EDANCE = 93.526 – j 10.208
m3
FREQUENCY = 2.000GHz
S(3,3) = 0.109/–125.024
IM P EDANCE = 86.866 – j 15.742
m6
FREQUENCY = 6.000GHz
S(3,3) = 0.187/128.165
IM P EDANCE = 76.218 + j23.228
m5
FREQUENCY = 4.500GHz
S(3,3) = 0.172/–167.199
IM P EDANCE = 71.122 – j 5.579
m4
FREQUENCY = 3.000GHz
S(3,3) = 0.136/–156.169
IM P EDANCE = 77.425 – j 8.680
S(3,3)
M6
M4M3 M2
M1
FREQUENCY ( 30.000MHz TO 6.000G Hz )
M5
24159-160
Figure 159. ADRV9001 RX A Port Series Equivalent Differential Impedance
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0
5.0
–5.0
2.0
1.0
–1.0
–2.0
0.5
–0.5
0.2
–0.2
m1
FREQUENCY = 30.00MHz
S(2,2) = 0.033/26.630
IM P EDANCE = 106.055 + j3.153
m2
FREQUENCY = 1.000GHz
S(2,2) = 0.051/–113.978
IM P EDANCE = 95.566 – j 8.865
m3
FREQUENCY = 6.000GHz
S(2,2) = 0.083/–104.261
IM P EDANCE = 94.788 – j 15.342
m6
FREQUENCY = 6.000GHz
S(2,2) = 0.193/–170.932
IM P EDANCE = 67.838 – j 4.293
m5
FREQUENCY = 4.500GHz
S(2,2) = 0.152/–150.217
IM P EDANCE = 75.844 – j11.760
m4
FREQUENCY = 3.000GHz
S(2,2) = 0.108/–129.045
IM P EDANCE = 86.136 – j 14.596
FREQUENCY (30.00M Hz TO 6.000G Hz)
S(2,2)
M6
M5M4M3
M2M1
24159-161
Figure 160. ADRV9001 RX B Port Series Equivalent Differential Impedance
ADS Setup Using DAC and SEDZ File
ADI supplies the port impedance as an *.s1p Series Equivalent Differential Z(impedance) file. This format allows simple interface to ADS
by using the Data Access Component (DAC). In the below diagram Term1 is the single ended input or output and Term2 represents the
differential input or output RF port on ADRV9001. The Pi on the single ended side and the differential Pi configuration on the
differential side allows maximum flexibility in designing matching circuits, and is suggested for all design layouts as it can step the
impedance up or down as needed with appropriate component population.
24159-162
Figure 161. Simulation Setup in ADS with SEDZ S1P Files and DAC Component
Operation is as follows:
1. The DAC block reads the rf port*.s1p file. This is the device RF port reflection coefficient.
2. The two equations convert the RF port reflection coefficient to a complex impedance. The end result is the RX_SEDZ variable.
3. The RF port calculated complex impedance (RX_SEDZ) is utilized to define the Term2 impedance.
a. Term2 is used in differential mode and Term1 is used in single-ended mode.
Setting up the simulation this way allows one to measure the S11, S22, and S21 of the 3-port system without complex math operations
within the display page.
Note for highest accuracy, EM modelling result of the PCB artwork and S-parameters of the matching components and balun should be
used in the simulations.
The first differential shunt reactive component such as L103 in Figure 161 is inserted to tune out parallel parasitic reactance of input
impedance of the device. If ac-coupling cap is necessary, C118 and C119 can be used utilized for this purpose.
For a wide-band match application, because of well controlled input/output impedance characteristics of ADRV9001 for entire range of
its RX/TX operational frequency band, minimal matching network can be implemented to control undesirable impedance deviation
typically associated with the high side of frequency range a balun operates. Additionally, by selecting a balun with the same differential
UG-1828 Preliminary Technical Data
Rev. PrA | Page 188 of 253
side termination impedance as the impedance of RX inputs and of TX outputs, a broad-band match can be accomplished by avoiding
unnecessary impedance transformation network which is inherently band-limiting.
One can also consider adding additional differential series capacitive component on the balanced side of balun to facilitate ac-coupling
and Pi match on both sides of the balun as shown below.
+
S1P_EQN
S1P8
–+
–
D
C
BALUN 3P O RT
CMP1
BALUN
DIFFERENTIAL MATCH
+S1P_EQN
S1P9
–+S1P_EQN
S1P7
–
+
S1P_EQN
S1P5
–
+
S1P_EQN
S1P6
–
+
S1P_EQN
S1P5
–
+
S1P_EQN
S1P6
–
+S1P_EQN
S1P4
–+S1P_E
QN
S1P4
–
24159-163
Figure 162. RF Matching Network with Additional Series AC-Coupling Capacitors
For a narrowband impedance match application to filter out signals outside of frequency band of interest, one can use Pi match
technique for desired bandwidth of impedance match with a selected balun’s terminal impedance. Pi match can be considered as two L
match networks back to back and would allow independent control of Q and impedance ratio obtainable from a matching network.
Narrowband matching network tuned for frequency bands of RX and TX can further improve out of band rejection of a transceiver for
frequency duplexed systems.
GENERAL RECEIVER PORT INTERFACE
ADRV9001 has two independent receive input channels(Rx1 and Rx2). Both Rx channels can support up to 40MHz bandwidth and use
differential signalling interface. The differential input signals would be applied to an integrated mixer. The mixer input pins are
internally biased to 0.65 Volt and would need to be AC coupled depending on the common mode voltage level of the external circuit
Important considerations for the receiver RF port interface are as follows:
1. Device to be interfaced: filter, balun, T/R switch, external LNA, etc. Does this device represent a short to ground at DC?
2. Rx1 and Rx2 maximum safe input power is 18 dBm (peak).
3. Rx1 and Rx2 optimum DC bias voltage is 0.65 V bias to ground.
4. Board Design: reference planes, transmission lines, impedance matching, etc. Figure 162 shows possible differential receiver port
interface circuits. The options in Figure 163 and Figure 164 are valid for all receiver inputs operating in differential mode, though
only the Rx1 signal names are indicated. Impedance matching may be necessary to obtain datasheet performance levels.
Differential Receiver Input Interface Circuits
RECEIVER
INPUT
STAGE
(MIXER OR LNA)
Rx1_INN
Rx1_INP
24159-164
Figure 163. Differential Receiver Interface Using A Transformer
Rx1_INN
Rx1_INP
RECEIVER
INPUT
STAGE
(MIXER OR LNA)
C
C
C
C
24159-165
Figure 164. Differential Receiver Interface Using a Transmission Line Balun
Given wide RF bandwidth applications, SMD balun devices function well offering acceptable differential balance and insertion loss in a
relatively small (0603, 0805) package.
Preliminary Technical Data UG-1828
Rev. PrA | Page 189 of 253
Example of RX1 A Port Frequency Match Simulation
Reasonable approximation of return loss of a frequency matching network can be obtained with a simple S parameter simulation
available in ADS without PCB artwork. Figure 165 illustrates a wide-band frequency match simulation setup in ADS for ADRV9001
RX1(2) A input pins in ADS for evaluating a possible configuration for a desired match to 3 GHz.
24159-166
Figure 165. ADS Simulation Example Setup with Simple Physical Board Trace Models
AT THE FINAL S E RIES INDUC TOR WITH A SHORT TL
AT THE SINGL E-ENDED TERMINAL OF BALUN
AT THE F IRST SHUNT CAPACITOR WITH A SHORT TL
S (5,5) (H)
FREQUENCY ( 10M HZ TO 3GHZ)
dB (S(5,5)) (H)
FREQUENCY (G Hz)
H
00.5 1.0 1.5 2.0 2.5 3.0
24159-167
Figure 166. ADS Simulation Results of Return Loss Curve
S parameters for a selected balun and ac-coupling SMD type caps and ADRV9001 RX input impedance can be used to represent balun’s
balanced side interface to the device. Shunt and series matching component can be added with short TLs to represent possible PCB traces
associated with these matching components on the single side of balun. Peaking of return loss at 2.5 GHz looking into the single-ended
interface of balun has been reduced by a clockwise rotation of high frequency portion of S11 curve on the Smith chart by adding a shunt
capacitor followed by series inductor after short transmission lines away from the balun’s single-ended terminal.
GENERAL TRANSMITTER BIAS AND PORT INTERFACE
This section considers the dc biasing of the ADRV9001 transmitter (Tx) outputs and how to interface to each Tx port. ADRV9001
transmitters operate over a range of frequencies. At full output power, each differential output side draws approximately 100mA of DC
bias current. The Tx outputs are DC biased to a 1.8V supply voltage using either RF chokes (wire-wound inductors) or a transformer
center tap connection.
Careful design of the DC bias network is required to ensure optimal RF performance levels. When designing the DC bias network, select
components with low DC resistance (RDCR) to minimize the voltage drop across the series parasitic resistance element with either of the
UG-1828 Preliminary Technical Data
Rev. PrA | Page 190 of 253
suggested dc bias schemes suggested in Figure 167. The RDCR resistors indicate the parasitic elements. As the impedance of the parasitics
increase, the voltage drop (ΔV) across the parasitic element increases causing the transmitter RF performance (that is, PO 1dB PO MAX,
and so forth) to degrade. The choke inductance (LC) should be selected high enough relative to the load impedance such that it does not
degrade the output power.
The recommended dc bias network is shown inFigure 168. This network has fewer parasitic and fewer total components.
VDC = 1.8V
CB
RDCR ΔV
VBIAS = 1.8V – ΔV
VBIAS = 1.8V – ΔV
ΔV RDCR
LC
+
–
+
–
LC
OUTPUT
STAGE
IBIAS = ~ 100mA
TX1_OUT–/
TX2_OUT–
TX1_OUT+/
TX2_OUT+
24159-168
IBIAS = ~ 100mA
Figure 167. ADRV9001 RF DC Bias Configurations Depicting Parasitic Losses Due to Wire Wound Chokes
ΔV
VBIAS = 1.8V – ΔV
VBIAS = 1.8V – ΔV
+–
ΔV +–
CB
Tx1 OR Tx2
OUTPUT
STAGE
IBIAS = ~ 100mA
1.8V
RDCR
RDCR
IBIAS = ~ 100mA
TX1_OUT–/
TX2_OUT–
TX1_OUT+/
TX2_OUT+
24159-169
Figure 168. ADRV9001 RF DC Bias Configurations Depicting Parasitic Losses Due to Center Tapped Transformers
Figure 169 to Figure 172 identify four basic differential transmitter output configurations. Impedance matching networks (balun single-
ended port) are most likely to be required to achieve optimum device performance from ADRV9001. Also, the transmitter outputs must
be ac-coupled in most applications due to the dc bias voltage applied to the differential output lines of the transmitter.
The recommended RF transmitter interface is shown in Figure 169 featuring a center tapped balun. This configuration offers the lowest
component count of the options presented.
Brief descriptions of the transmitter port interface schemes are provided as follows.
• Center tapped transformer passes the bias voltage directly to the transmitter outputs
• RF chokes are used to bias the differential transmitter output lines. Additional coupling capacitors (CC) are added in the creation of
a transmission line balun
• RF chokes are used to bias the differential transmitter output lines and connect into a transformer
• RF chokes are used to bias the differential output lines that are ac-coupled into the input of a driver amplifier.
Transmitter Interface Configurations
Tx1 O R Tx2
OUTPUT STAGE Tx1_OUT–/
Tx2_OUT–
Tx1_OUT+/
Tx2_OUT+
1.8V
C
B
24159-170
Figure 169. ADRV9001 RF Transmitter Interface Configuration A
Preliminary Technical Data UG-1828
Rev. PrA | Page 191 of 253
Tx1 O R Tx2
OUTPUT STAGE
C
B
Tx1_OUT–/
Tx2_OUT–
Tx1_OUT+/
Tx2_OUT+
L
C
L
C
1.8V
1.8V
1.8V
C
C
C
C
24159-171
Figure 170. ADRV9001 RF Transmitter Interface Configuration B
Tx1 OR Tx2
OUTPUT STAGE Tx1_OUT–/
Tx2_OUT–
Tx1_OUT+/
Tx2_OUT+
L
C
L
C
1.8V
1.8V
1.8V
C
B
24159-172
Figure 171. ADRV9001 RF Transmitter Interface Configuration C
Tx1 O R Tx2
OUTPUT STAGE
C
B
Tx1_OUT–/
Tx2_OUT–
Tx1_OUT+/
Tx2_OUT+
L
C
L
C
1.8V
1.8V
1.8V C
C
C
C
DRIVER
AMPLIFIER
24159-173
Figure 172. ADRV9001 RF Transmitter Interface Configuration D
If a Tx balun is selected that requires a set of external dc bias chokes, careful planning is required. It is necessary to find the optimum
compromise between the choke physical size, choke dc resistance (RDCR) and the balun low frequency insertion loss. In commercially
available dc bias chokes, resistance decreases as size increases. However, as choke inductance increases, resistance increases. Therefore, it
is undesirable to use physically small chokes with high inductance as they exhibit the greatest resistance. For example, the voltage drop of
a 500 nH, 0603 choke at 100 mA is roughly 50 mV.
Table 84. Sample Wire-Wound DC Bias Choke Resistance vs. Size vs. Inductance
Inductance (nH) Resistance (Size: 0603) Resistance (Size: 1206)
100 0.10 0.08
200 0.15 0.10
300 0.16 0.12
400 0.28 0.14
500 0.45 0.15
600 0.52 0.20
When selecting a dc bias choke inductor, shunting impedance of the choke inductor would need to be high for TX frequency band in
order to minimize its loading to outputs . Therefore, the self resonant frequency of the selected choke inductor must be higher than
intended TX frequency.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 192 of 253
Additionally, ADRV9001 provides built-in TX power ramp-up pattern generator to bring transmit power level in a pre-determined way
to protect internal devices from sudden voltage spikes which may happen due to in-rush current passing through an external DC bias
choke inductor. The supply side of choke inductors should also be tied to a capacitor with its self-resonant frequency higher that TX
frequency. When both TX channel are active, each TX outputs should be tied to its own supply plane via a bias chock inductor or ferrite
bead to reduce coupling between two TXs through the same supply feedline.
IMPEDANCE MATCHING NETWORK EXAMPLES
Impedance matching networks are required to achieve performance levels noted on the datasheet. This section provides example
topologies and components used on the evaluation Board. The impedance matching networks provided in this section have not been
evaluated in terms of Mean Time to Failure (MTTF) in high volume production. Please consult with component vendors for long-term
reliability concerns. Additionally, please consult with balun vendors to determine appropriate conditions for DC biasing.
The schematics in Figure 173, Figure 174, and Figure 175 show two or three circuit elements in parallel marked DNI (Do Not Include).
This was done on the evaluation board schematic to accommodate different component configurations for different frequency ranges.
Only one set of SMD component pads are placed on the board to provide a physical location that can be used for the selected parallel
circuit element. For example, R216, L216, and C216 components only have one set of SMD pads for one SMD component. The
schematic shows that in a generic port impedance matching network, the series elements may be either a resistor, inductor or a capacitor
whereas the shunt elements may be either an inductor or a capacitor. Only one component of each parallel combination is placed in a
practical application. Note that in some matching circuits, some shunt elements may not be required. All components for a given
physical location remain DNI in those particular applications.
RECEIVER RF PORT IMPEDANCE MATCHING NETWORK
RX1A± and RX2A± Impedance Matching Network
The ADRV9001 evaluation board utilizes both the top and bottom layers of the PCB evaluation platform to accommodate two balun
footprints. The 0805 footprint accommodates the high frequency narrowband baluns while the backside accommodates the larger
DB1627 case style transformer.
The PCB traces of the evaluation board were included in the simulation when designing the impedance match. Table 83 provides
impedance matching networks specific to the ADRV9001 evaluation board. The component values apply to RX1A± and RX2A±.
RX1B± and RX2B± Impedance Matching Network
Both the RXA and RXB paths share the same input S-parameters. However, given the ball locations of the RXB paths being in an inner
row and column and the layout of both paths are slightly different, the RXB path will have its own distinct impedance matching network
that will be different from the RXA path. On the RXB path the low frequency DB1627 case style transformer is located on the top side of
evaluation platform and the high frequency 0805 footprint transformer is located on the bottom of the board. This configuration is
opposite of the RXA path. This was done to minimize coupling of the receive paths.
The PCB traces of the evaluation board were included in the simulation when designing the impedance match. Table 83 provides
impedance matching networks specific to the ADRV9001 evaluation board. The component values applies to RX1B± and RX2B±.
Preliminary Technical Data UG-1828
Rev. PrA | Page 193 of 253
L247
DNI
C247
DNI
R247
DNI
L248
DNI
C248
DNI
R248
DNI
L245
DNI
C245
DNI
R245
DNI
L238
DNI C238
DNI R238
DNI
L246
DNI
C246
DNI
R246
DNI
L219
DNI
C219
DNI
L218
DNI C218
DNI
R232
0Ω
DNI
265
2
5
6
3
4
C232
0.1µF
L217
DNI C217
DNI
L215
DNI C215
DNI
L221
DNI C221
DNI
R219
DNI
L236
DNI
AGND
AGND
AGND
AGND
J203 C236
DNI
R236
DNI
L216
DNI
0805 FO OTP RINT
UNBAL_IN
NC_6 GND GND_DC_FEED_RFGND
T205
DNI
BAL_OUT1
BAL_OUT2
3
4
C216
DNI
R216
DNI
L220
DNI
C220
DNI
R220
DNI
RX2A
RX2A_DC
RX2A_UNBAL1
TCM2-33X+T207
RX2A_IN+
RX2A_IN–
BALUN L OCATED
ON BO TTOM
OF THE BO ARD
BALUN L OCATED
ON TOP
OF THE BO ARD
NOTES
1. MATCHI NG COM P ONENT S APPLY TO RX 1A± AND RX2A±
24159-174
OVERLAP PADS
Figure 173. RX1A and RX2A Impedance Matching Network
Table 85. RX1A± and RX2A± Impedance Matching Network
Frequency Balun
L/C/R
215
L/C/R
216
L/C
217
L/C/R
238
L/C/R
236
L/C/R 245
L/C/R 246
L/C/R 247
L/C/R 248 L/C 218
L/C/R 219
L/C/R 220 L/C 221
C232
R232
30 MHz to
3 GHz
MiniCircuits
TCM2-33WX+
L215:
DNI
L216:
1.5 nH
L217:
DNI
L238:
DNI
L236:
DNI
L245/246:
DNI
L247/248:
DNI
L218:
DNI
L219/220:
DNI
L221:
DNI
C232:
DNI
C215:
DNI
CoilCraft
(02DS
series)
C217:
0.2pF
Murata
(GJM03
Series)
C238:
DNI
C236:
DNI
C245/246:
DNI
C247/248:
DNI
C218:
DNI
C219/220:
470 pF
Murata
(GRM03
Series)
C221:
DNI
R232:
DNI
C216:
DNI
R238:
0 Ω
R236:
DNI
R245/246:
0 Ω
R247/248:
DNI
R219/220:
DNI
R216:
DNI
3 GHz to
6 GHz
Johanson
4400
L215:
DNI
L216:
1.2 nH
CoilCraft
(02DS
series)
L217:
DNI
L238:
DNI
L236:
DNI
L245/246:
DNI
L247/248:
0.6 nH
CoilCraft
(02DS series)
L218:
14nH
CoilCraft
(02DS
series)
L219/220:
DNI
L221:DNI C232:
6 pF
Murata(
GJM03
Series)
C215:
DNI
C216:
DNI
C217:
0.2pF
Murata
(GJM03
Series)
C238:
DNI
C236:
DNI
C245/246:
DNI
C247/248:
DNI
C218:
DNI
C219/220:
DNI
C221:
DNI
R232:
DNI
R216:
DNI
R238:
DNI
R236:
0 Ω
R245/246:
DNI
R247/248:
DNI
R219/220:
0 Ω
30 MHz to
1 GHz
MiniCircuits
TCM2-33WX+
L215:
DNI
L216:
3.6 nH
CoilCraft
(02DS
series)
L217:
DNI
L238:
DNI
L236:
DNI
L245/246:
DNI
L247/248:
DNI
L218:
DNI
L219/220:
DNI
L221:
DNI
C232:
DNI
C215:
DNI
C216:
DNI
C217:
1.7pF
Murata
(GJM03
Series)
C238:
DNI
C236:
DNI
C245/246:
DNI
C247/248:
DNI
C218:
DNI
C219/220:
1000 pF
Murata
(GRM03
Series)
C221:
DNI
R232:
DNI
R216:
DNI
R238:
0 Ω
R236:
DNI
R245/246:
0 Ω
R247/248:
DNI
R219/220:
DNI
UG-1828 Preliminary Technical Data
Rev. PrA | Page 194 of 253
Frequency Balun
L/C/R
215
L/C/R
216
L/C
217
L/C/R
238
L/C/R
236
L/C/R 245
L/C/R 246
L/C/R 247
L/C/R 248 L/C 218
L/C/R 219
L/C/R 220 L/C 221
C232
R232
625 MHz to
2.8 GHz
Johanson
1720BL15A0100
L215:
DNI
L216:
0.6 nH
CoilCraft
(02DS
series)
L217:
DNI
L238:
DNI
L236:
DNI
L245/246:
DNI
L247/248:
DNI
L218:
DNI
L219/220:
DNI
L221:
DNI
C232:
DNI
C215:
DNI
C216:
DNI
C217:
DNI
C238:
DNI
C236:
DNI
C245/246:
DNI
C247/248:
DNI
C218:
DNI
C219/220:
470 pF
Murata
(GRM03
Series)
C221:
DNI
R232:
DNI
R216:
DNI
R238:
DNI
R236:
0 Ω
R245/246:
DNI
R247/248: 0
Ω
R219/220:
DNI
2.8 GHz – 5
GHz
Anaren
BD3150L50100A
AF
L217:
DNI
L216:
DNI
L217:
DNI
L238:
DNI
L236:
DNI
L245/246:
DNI
L247/248:
1.2 nH
CoilCraft
(02DS series)
L218:
DNI
L219/220:
DNI
L221:
DNI
C232:
DNI
C217:
DNI
C216:
DNI
C217:
DNI
C238:
DNI
C236:
DNI
C245/246:
DNI
C247/248:
DNI
C218:
DNI
C219/220:
2.5 pF
Murata(G
JM03
Series)
C221:
DNI
R232:
DNI
R216:
0 Ω
R238:
DNI
R236:
0 Ω
R245/246:
DNI
R247/248:
DNI
R219/220:
0 Ω
4.5 GHz to
6 GHz
Johanson
5400BL15B100
L217:
DNI
L216:
0.5 nH
CoilCraft
(02DS
series)
L217:
DNI
L238:
DNI
L236:
DNI
L245/246:
DNI
L247/248:
1.2 nH
CoilCraft
(02DS series)
L218:
DNI
L219/220:
DNI
L221:
6.7 nH
CoilCraft
(02DS
series)
C232:
DNI
C217:
DNI
C216:
DNI
C217:
DNI
C238:
DNI
C236:
DNI
C245/246:
DNI
C247/248:
DNI
C218:
DNI
C219/220:
0.6 pF
Murata
(GJM03
Series)
C221:
DNI
R232:
DNI
R216:
DNI
R238:
DNI
R236:
0 Ω
R245/246:
DNI
R247/248:
DNI
R219/220:
0 Ω
L251
DNI
C255
DNI
R225
DNI
L252
DNI
C256
DNI
R229
DNI
L249
DNI
C253
DNI
R222
DNI
L226
DNI C226
DNI R226
DNI
L250
DNI
C254
DNI
R224
DNI
L227
DNI
C227
DNI
L218
DNI C225
DNI
R233
0Ω
DNI
2
2
5
6
3
4
C233
0.1µF
OVERLAP PADS
L224
DNI C224
DNI
L222
DNI C222
DNI
L229
DNI C229
DNI
R227
DNI
L237
DNI
AGND AGND
AGND
AGND
AGND
J203 C237
DNI
R237
DNI
L223
DNI
0805 FO OTP RINT
UNBAL_IN
NC_6 GND GND_DC_FEED_RFGND
T206
DNI
BAL_OUT1
TCM2-33X+
TCM2-33X+T208
BAL_OUT2
3
4
C223
DNI
R223
DNI
L228
DNI
C228
DNI
R228
DNI
RX2B
RX2B_DC
RX2B_UNBAL1
RX2B_IN+
RX2B_IN–
BALUN L OCATED
ON BO TTOM
OF THE BO ARD
BALUN L OCATED
ON TOP
OF THE BO ARD
NOTES
1. MATCHI NG COM P ONENT S APPLY TO RX1B± AND RX2B±
24159-175
Figure 174. RX1B and RX2B Impedance Matching Networks
Preliminary Technical Data UG-1828
Rev. PrA | Page 195 of 253
Table 86. RX1B± and RX2B± Impedance Matching Network
L/C/R
249 L/C/R 251
L/C/R
227 C233
Frequency Balun L/C 222
L/C/R
223 L/C 224
L/C/R
226
L/C/R
237
L/C/R
250 L/C/R 252 L/C 225
L/C/R
228 L/C 229 R233
30 MHz to
3 GHz
MiniCircuits
TCM2-33WX+
L222:
DNI
L223:
2.3 nH
CoilCraft
(02DS
series)
L224:
DNI
L226:
DNI
L237:
DNI
L249/250:
DNI
L251/252:
DNI
L225:
DNI
L227/228:
DNI
L229:
DNI
C233:
DNI
C222:
0.5pF
Murata
(GJM03
Series)
C223:
DNI
C224:
DNI
C226
: DNI
C237:
DNI
C253/25
4: DNI
C251/252:
DNI
C225:
DNI
C227/22
8: 470 pF
Murata
(GRM03
Series)
C229:
DNI
R233:
DNI
R223:
DNI
R226:
0 Ω
R237:
DNI
R222/224:
0 Ω
R225/229:
DNI
R227/228:
DNI
3 GHz to
6 GHz
Johanson
4400
L222:
DNI
L223:
0.6 nH
CoilCraft
(02DS
series)
L224:
DNI
L226:
DNI
L237:
DNI
L249/250:
DNI
L251/252:
DNI
L225:
14 nH
CoilCraft
(02DS
series)
L227/228:
0.6 nH
CoilCraft
(02DS
series)
L229:
75 nH
CoilCraft
(026011
c series)
C233:
4.8 pF
Murata(
GJM03
Series)
C222:
DNI
C223:
DNI
C224:
DNI
C226:
DNI
C237:
DNI
C249/250:
DNI
C251/252:
DNI
C225:
DNI
C227/228:
DNI
C229:
DNI
R233:
DNI
C257:
0.2pF
Murata
(GJM03
Series)
R223:
DNI
R226:
DNI
R237:
0 Ω
R222/224:
DNI
R251/252:
0 Ω
R227/228:
DNI
30 MHz to
1 GHz
MiniCircuits
TCM2-33WX+
L222:
DNI
L223:
DNI
L224:
DNI
L226:
DNI
L237:
DNI
L249/250:
DNI
L251/252:
DNI
L225:
DNI
L227/228:
DNI
L229:
DNI
C233:
DNI
C222:
DNI
C223:
DNI
C224:
DNI
C226:
DNI
C237:
DNI
C249/250:
DNI
C251/252:
DNI
C225:
DNI
C227/228:
1000 pF
Murata
(GRM03
Series)
C229:
DNI
R233:
DNI
R223:
0 Ω
R226:
0 Ω
R237:
DNI
R222/224:
DNI
R225/229:
0 Ω
R227/228:
DNI
625 MHz to
2.8 GHz
Johanson
1720BL15A0100
L222:
DNI
L223:
0.5 nH
CoilCraft
(02DS
series)
L224:
DNI
L226:
DNI
L237:
DNI
L249/250
: DNI
L251/252:
DNI
L225:
DNI
L227/228:
DNI
L229:
DNI
C233:
DNI
C222:
DNI
C223:
DNI
C224:
DNI
C226:
DNI
C237:
DNI
C249/25
0: DNI
C251/252:
DNI
C225:
DNI
C227/228:
470 pF
Murata
(GRM03
Series)
C229:
DNI
R233:
DNI
R223:
DNI
R226:
DNI
R237:
0 Ω
R222/224:
DNI
R225/229:
0 Ω
R227/228:
0 Ω
2.8 GHz to
5 GHz
Anaren
BD3150L50100
AAF
L217:
DNI
L223:
0.6 nH
CoilCraft
(02DS
series)
L224:
DNI
L229:
DNI
L237:
DNI
L249/250:
DNI
L251/252:
1.2 nH
CoilCraft
(02DS series)
L225:
DNI
L227/228:
DNI
L229:
DNI
C233:
DNI
C217:
DNI
C223:
DNI
C224:
0.2 pF
Murata
(GJM03
Series)
C229:
DNI
C237:
DNI
C251/252:
DNI
C251/252:
DNI
C225:
DNI
C227/228:
5 pF
Murata
(GJM03
Series)
C229:
DNI
R233:
DNI
R223:
0 Ω
R229:
DNI
R237:
0 Ω
C249/250:
DNI
R251/252:
DNI
R227/228:
DNI
R222/224:
DNI
UG-1828 Preliminary Technical Data
Rev. PrA | Page 196 of 253
L/C/R
249 L/C/R 251
L/C/R
227 C233
Frequency Balun L/C 222
L/C/R
223 L/C 224
L/C/R
226
L/C/R
237
L/C/R
250 L/C/R 252 L/C 225
L/C/R
228 L/C 229 R233
4.5 GHz– 6
GHz
Johanson
5400BL15B100
L217:
3.5 nH
CoilCraft
(02DS
series)
L223:
DNI
L224:
1.3 nH
CoilCraft
(02DS
series)
L226:
DNI
L237:
DNI
L249/250:
DNI
L251/252:
DNI
L225:
8.2 nH
CoilCraft
(02DS
series)
L227/228:
1.3 nH
CoilCraft
(02DS
series)
L229:
3.3 nH
CoilCraft
(02DS
series)
C233:
DNI
C223:
0.5 pF
Murata
(GJM03
series)
C224:
DNI
C226:
DNI
C237:
2.2 pF
Murata
(GJM03
series)
C249/250:
DNI
C251/252:
DNI
C225:
DNI
C227/228:
DNI
C229:
DNI
R233:
DNI
C217:
DNI
R223:
DNI
R226:
DNI
R237:
DNI
R222/224:
DNI
R251/252:
0 Ω
R227/228:
DNI
RECEIVER RF PORT IMPEDANCE MATCH MEASUREMENT DATA
Receiver RF Port Impedance Match Measurement Data for 30 MHz to 3 GHz Band Match
Return loss was measured on RX1(2)A and RX1(2)B RF ports of eval boards and plotted below; blue and pink curves represent four
different return loss measurements and black dotted line represents simulated return loss curve on Figure 175 and Figure 176. Simulated
insertion loss curve including balun loss is plotted on Figure 177.
FREQUENCY (GHz)
00.5 1.0 1.5 2.0 2.5 3.0 3.5
24159-176
Figure 175. Return Loss of RX1(2)A Port
FREQUENCY (G Hz)
00.5 1.0 1.5 2.0 2.5 3.0 3.5
24159-177
Figure 176. Return Loss of RX1(2)B Port
Preliminary Technical Data UG-1828
Rev. PrA | Page 197 of 253
FREQUENCY (G Hz)
00.5 1.0 1.5 2.0 2.5 3.0 3.5
24159-178
Figure 177. Insertion Loss – Simulated RX1(2)A Port – Red Curve RX1(2)B Port – Blue Curve
TRANSMITTER RF PORT IMPEDANCE MATCHING NETWORK
TX1± and TX2± Impedance Matching Network
For the TX path, the ADRV9001 evaluation board utilizes both the top and bottom layers of the PCB evaluation platform to
accommodate two balun footprints. The 0805 footprint accommodates the high frequency narrowband baluns while the backside
accommodates the larger AT224-1A case style transformer.
The ADRV9001 evaluation board provides two options in providing the DC common mode bias for the TX outputs. For transformers
that provide a DC feed pin, this can be used to bias the TX output. For transformers that do not provide a DC feed pin, the TX outputs
are biased to 1.8V through pull up inductors. Only one bias option should be chosen, and provisions should be made to disable the
unused path.
The PCB traces of the evaluation board were included in the simulation when designing the impedance match. Figure 178 and Table 87
provides impedance matching networks specific to the ADRV9001 evaluation board. The component values apply to TX1± and TX2±.
Placement of C335 should be as close to dc feed pin of balun T302 as its purpose is to eliminate TX spectrum spurs and dampen the
transients. Ground terminal of C335 should be tied to a ground plane and the cap should be oriented in the same direction of ground
plane surrounding TX input trace so that the return current forms as small a loop as possible with the ground plane.
AGND
VANA2_1P8
TX2_OUT–
TX2_OUT+
VANA2_1P8
VANA2_1P8
AGND
RF OUTPUT 2
J302
T312
TCM1-13M+
652
C335
0.1µF
C334
0.1µF
C333
10µF
0805 FO OTPRINT
BAL_OUT1
BAL_OUT2
NC_6GNDGND_DC_FEED_RFGND
T302
DNI UNBAL_IN RFO_2
1
3
4
RX2B_DC
BALUN L OCATED
ON TOP
OF THE BOARD
BALUN L OCATED
ON BO TTOM
OF THE BOARD
L312
DNI
C351
DNI
C309
DNI
R312
DNI
L313
DNI
C313
DNI
R313
DNI
NOTES
1. MATCHING COMP ONENT S APPLY TO RX1B± AND RX2B±
R367
DNI
R368
DNI R368
0Ω
DNI
AGND
C310
DNI
L339
DNI
L311
DNI C339
DNI
C311
DNI
L309
DNI
L309
DNI
L348
DNI C348
DNI
R348
DNI
L314
DNI C314
DNI L316
DNI C316
DNI
L341
DNI
R341
DNI
C341
DNI
L315
DNI
R315
DNI
C315
DNI
6
4
1
TX2_BAL–
TX2_BAL+
3
2
SEC PRI
NC
C346
DNI
C347
DNI
IMP E DANCE CHARACTERIS TICS:
Tx OUTPUTS = 50Ω DIFFERENTIAL,
BALUN = 500Ω SET TO 500Ω DIFF
24159-179
Figure 178. TX1 and TX2 Impedance Matching Network
UG-1828 Preliminary Technical Data
Rev. PrA | Page 198 of 253
Table 87. TX1± and TX2± Impedance Matching Network
Frequency Balun L/C 311
L309
L310
C309
C310
L/C/R
312
L/C/R
313
L339
C339
C346/347
R367/368 R361
C333
C334
C335
L/C/R
341
L/C/R
348 L/C 314
L/C/R
315
L/C
316
30 MHz to
3 GHz
MiniCircuits
TC-1-13M+
L311: DNI
L309/310:
220 nH
(CoilCraft
LQW
18AN)
C309/
C310:
10 nF
(Murata
GRM03)
L312/313:
1.3 nH
(CoilCraft
0201 DS)
L339:
DNI
C346/347:
330 pF
(Murata
GRM03)
R361:
DNI
C333:
DNI
L341:
DNI
L348:
2.2 nH
(Coil-
Craft
0201 DS
L314:
DNI
L315:
2.2 nH
(Coil-
Craft
0201 DS
L316:
DNI
C311:
0.3 pF
(Murata
GJM03)
C312/313:
DNI
C339:
0.8 pF
(
Murata
GJM03)
R367, R368:
DNI
C334:
DNI
C341:
DNI
C348:
DNI
C314:
1 pF
(Murata
GJM03)
C315:
DNI
C316:
DNI
R312/313:
DNI
R339:
DNI
C335:
DNI
R341:
DNI
R348:
DNI
R315:
DNI
3 GHz to
6 GHz
Johanson
4400
L311:
DNI
L309/310:
DNI
C309/
C310: DNI
L312/313:
0.6 nH
(CoilCraft
0201 DS)
L339:
DNI
C346/347:
DNI
R361:
27 nH
(Murata
LQW18)
C333:
DNI
L341:
0.5 nH
(Coil-
Craft
0201DS)
L348:
DNI
L314:
DNI
L315:
0.5 nH
(Coil-
Craft
0201DS)
L316:
11 nH
(Coil-
Craft
0201DS)
C311:
0.2 pF
(Murata
GJM03)
C312/313:
DNI
C339:
0.3 pF
(Murata
GJM03)
R367/368:
0 Ω
C334:
DNI
C341:
DNI
C348:
DNI
C314:
0.2 pF
(Murata
GJM03)
C315:
DNI
C316:
DNI
R312/313:
DNI
R339:
DNI
C335:
2.7 pF
(Murata
GJM03)
R341:
DNI
R348:
DNI
R315:
DNI
30 MHz to
625 MHz
TDK
ATB2012_50
011
L311:
DNI
L309/310:
390 nH
(CoilCraft
0603 CS)
C309/C31
0: 10 nF
(Murata
GRM03)
L312/313:
DNI
L339:
DNI
C346, C347:
DNI
R361:
DNI
C333:
DNI
L341:
DNI
L348:
DNI
L314:
DNI
L315:
DNI
L316:
DNI
C311:
2 pF
(Murata
GJM03)
C312/
C313:
1 nF
Murata
GRM03)
C339:
DNI
R367/368:
0 Ω
C334:
DNI
C341:
DNI
C348:
DNI
C314:
DNI
C315:
DNI
C316:
DNI
R312/313:
DNI
R339:
DNI
C335:
DNI
R341:
0 Ω
R348:
DNI
R315: 0
Ω
30 MHz to 1
GHz
MiniCircuits
TC-1-13M+
L311: DNI L309/310:
220 nH
(CoilCraft
LQW18
AN)
C309/
C310:
10 nF
(Murata
GRM03)
L312/313:
DNI
L339:
DNI
C346/347:
0 Ω
R361:
DNI
C333:
DNI
L341:
DNI
L348:
DNI
L314:
DNI
L315:
7 nH
(Coil-
Craft
0201 DS
L316:
DNI
C311:
1 pF
(Murata
GJM03)
C312/
C313:
1 nF
Murata
GRM03)
C339:
DNI
R367/368:
DNI
C334:
DNI
C341:
DNI
C348:
270 pF
(Murata
GRM03)
C314:
2 pF
(Murata
GJM03)
C315:
DNI
C316:
DNI
R312/313:
DNI
R339:
DNI
C335:
DNI
R341:
DNI
R348:
DNI
R315:
DNI
625 MHz to
2.8 GHz
Johanson
1720BL15A0
100
L311: DNI L309/310:
DNI
C309/
C310: DNI
L312/313:
0.5 nH
(CoilCraft
0201 DS)
L339:
DNI
C346/347:
DNI
R361: 0
Ω
C333:
10 μF
L341:
DNI
L348:
DNI
L314:
DNI
L315:
DNI
L316:
27 nH
(Murata
LQP03
HQ)
C311:
0.3 pF
(Murata
GJM03)
C312/313
: DNI
C339:
DNI
R367, R368:
0 Ω
C334:
0.1 μF
C341:
10 pF
(Murata
GJM03)
C348:
DNI
C314:
DNI
C315:
DNI
C316:
DNI
R312/313:
DNI
R339:
DNI
C335:
0.1 μF
R341:
DNI
R348:
DNI
R315:
0 Ω
Preliminary Technical Data UG-1828
Rev. PrA | Page 199 of 253
Frequency Balun L/C 311
L309
L310
C309
C310
L/C/R
312
L/C/R
313
L339
C339
C346/347
R367/368 R361
C333
C334
C335
L/C/R
341
L/C/R
348 L/C 314
L/C/R
315
L/C
316
2.8 GHz to
5 GHz
Anaren
BD3150L501
00AAF
L311: DNI L309/310:
DNI
C309/
C310: DNI
L312/313:
1.2 nH
(CoilCraft
0201 DS)
L339:
DNI
C346/347:
DNI
R361:
0 Ω
C333:
10 μF
L341:
DNI
L348:
DNI
L314:
3.9 nH
(Coil-
Craft
0201
DS)
L315:
DNI
L316:
DNI
C311:
0.2 pF
(Murata
GJM03)
C312/
C313: DNI
C339:
DNI
R367, R368:
0 Ω
C334:
0.1 μF
C341:
2 pF
(Murata
GJM03)
C348:
DNI
C314:
DNI
C315:
DNI
C316:
DNI
R312/313:
DNI
R339:
DNI
C335:
0.1 μF
R341:
DNI
R348:
DNI
R315:
0 Ω
4.5 GHz to
6 GHz
Johanson
5400BL15B1
00
L311: DNI L309/310:
DNI
C309/
C310: DNI
L312/313:
1.3 nH
(Murata
LPQ03
HQ)
L339:
DNI
C346/347:
DNI
R361:
0 Ω
C333:
10 μF
L341:
DNI
L348:
DNI
L314:
DNI
L315:
DNI
L316:
2.5 nH
(Coil-
Craft
0201
DS)
C311:
DNI
C312/
C313: DNI
C339:
DNI
R367, R368:
0 Ω
C334:
0.1 μF
C341:
1 pF
(Murata
GJM03)
C348:
DNI
C314:
DNI
C315:
DNI
C316:
DNI
R312/313:
DNI
R339:
DNI
C335:
0.1 μF
R341:
DNI
R348:
DNI
R315: 0
Ω
TRANSMITTER RF PORT IMPEDANCE MATCH MEASUREMENT DATA
Data for Transmitter RF Ports for 30 MHz to 3 GHz Band Match
Return loss was measured on TX RF ports of eval boards and plotted on Figure 179; blue and pink curves represent four different return
loss measurements and black dotted line represents simulated return loss curve. Simulated Insertion loss including balun loss is plotted
on Figure 180.
FREQUENCY (G Hz)
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
24159-180
Figure 179. Tx1/Tx2 Return Loss
UG-1828 Preliminary Technical Data
Rev. PrA | Page 200 of 253
FREQUENCY (GHz)
00.5 1.0 1.5 2.0 2.5 3.0 3.0
24159-181
Figure 180. Tx1/Tx2 Insertion Loss, Simulated
EXTERNAL LO PORT IMPEDANCE MATCHING NETWORK
External LO1 and LO2 PORT can be used for injecting LO signal with very high spectral purity for internal receivers and transmitters.
RF matching network for these ports would be implemented on single-ended and differential sides of balun to reduce insertion loss due
to reflections at the desired LO frequency. Method of obtaining matching network is similar to RX and TX port matching. Depending on
the selected divide ratio of ADRV9001 external LO input frequency divider SPI register setting, a band of frequency in which external LO
matching network need to operate should be correctly derived by the division ratio chosen.
EXT LO Inputs
Unlike the internal synthesizers that always operate from 6 – 12 GHz regardless of the RF tune frequency, when an external LO pins are
used the frequency applied must be a multiple of 2 times(i.e. 2x,4x,8x, and so on) of the desired RF signal channel frequency. The LO
input signal is internally divided by a series of dividers to generate the required LO quadrature relationship at desired RF frequency of
upconvertion or downconversion for internal transmitters and receivers. Table 88 describes specification for EXT LO input pins when
input pins are driven by a differential signal by use of balun.
Alternatively single-ended external LO signal source can be used for positive side of EXT LO pin with negative side of input pin
terminated with a capacitor to provide ac ground. The frequency of external LO source should be set to 4x of desired RX or TX frequency
with EXT LO divider configured to division of 4 for the best in-phase and quadrature generation of LO necessary for internal receivers
and transmitters. Table 89 describes specification for single-ended EXT LO input source.
In general, higher power level of external LO signal applied gives better phase noise to some extent. The minimum input power level that
satisfy RX/TX phase noise requirements with some margin should be used. Refer to Table 89 for power level recommendation.
Table 88. Specifications for ADRV9001 RF EXT LO Differential Input Pins
Parameter Note Min Typical Max Unit
External LO frequency FEXTLO 60 12000 MHz
RF Channel frequency FCHANNEL 30 6000 MHz
External LO power 100 Ω matching
Signal amplitude depends on FEXTLO frequency.
Typical = 0dBm for FEXTLO <= 2GHz.
From 2 GHz, add 0.5dB/GHz.
For example,
Typical = +3dBm for FEXTLO = 8GHz.
−6 −3 ~
+3
+6 dBm
Input Impedance nominal, small signal input. Note below. 100 Ω
Differential Phase Error
Combined Differential Phase Error, Differential Amplitude Error, Duty Cycle
Error, and Even Order Harmonic Content
±5 degrees
Differential Amplitude
Error
1 dB
Duty Cycle Error 2 %
Even Order Harmonic
Content
−50 dBc
EXT LO Source
Modulus
Must match internal modulus on ADRV9001 8386560
Preliminary Technical Data UG-1828
Rev. PrA | Page 201 of 253
Table 89. Specifications for ADRV9001 RF EXT LO Single-ended Input Pin
Parameter Note Min Typical Max Unit
External LO frequency FEXTLO 60 2000 MHz
RF Channel frequency FCHANNEL 30 1000 MHz
External LO power 50 Ω matching 0 +3 +6 dBm
Input Impedance nominal, small signal input. Note below. 50 Ω
EXT LO Source Modulus Must match internal modulus on ADRV9001 8386560
0
5.0
–5.0
2.0
1.0
–1.0
–2.0
0.5
–0.5
0.2
–0.2
m1
FREQUENCY = 60.00M Hz
S(10,10) = 0.039/–81.146
IM P EDANCE = 100.912 – j 7.872
m2
FREQUENCY = 1.000G Hz
S(10,10) = 0.254/–135.783
IM P EDANCE = 65.484 – j 24.798
m3
FREQUENCY = 2.000G Hz
S(10,10) = 0.415/–173.750
IM P EDANCE = 41.462 – j 4.523
m8
FREQUENCY = 12.000G Hz
S(10,10) = 0.668/–157.623
IM P EDANCE = 20.688 – j 18.963
m7
FREQUENCY = 9.000G Hz
S(10,10) = 0.593/–64.388
IM P EDANCE = 77.231 – j 127.520
m6
FREQUENCY = 7.000G Hz
S(10,10) = 0.546/9.880
IM P EDANCE = 315.757 – j 84.329 m4
FREQUENCY = 3.000G Hz
S(10,10) = 0.496/151.568
IM P EDANCE = 35.627 + j22.290
m5
FREQUENCY = 4.500G Hz
S(10,10) = 0.535/101.068
IM P EDANCE = 47.846 – j 70.402
FREQUENCY ( 60.00MHz TO 12.00G Hz)
S(10, 10)
M6
M7
M8
M5
M3
M2
M1
M4
24159-182
Figure 181. External LO Series Equivalent Differential Input Impedance
Care should be taken when selecting an on-board balun for this application. Combination of amplitude and phase balance performance
of the balun can affect quadrature error performance. Additionally, duty cycle and differential second order harmonic distortion impacts
the ability of to correct quadrature error. The recommended minimum requirement for Ext LO input pins is a combination of no more
than 5 degree differential phase error, 1dB differential amplitude error, 2% duty cycle error, and less than -50dBc even order
harmonics(primarily 2nd order).
The ADRV9001 provides special mode of operation for external LO in range from 500MHz to 1000MHz. In that region it is possible to
inject external LO that will produce RF Channel frequency with x1 multiplier. For example:
For FEXTLO = 500 MHz the FCHANNEL = 500 MHz
For FEXTLO = 1000 MHz, the FCHANNEL = 1000 MHz
UG-1828 Preliminary Technical Data
Rev. PrA | Page 202 of 253
AGND
5
T303
NCR2-123+
T304
HHM1595A1
T305
TCM1-83X+
3
6
4
1
L329
DNI
C351
DNI
L327
DNI
C350
DNI
L324
DNI C317
DNI R308
DNI
AGND
AGND
AGND
L326
DNI C319
DNI R309
DNI R319
0Ω
DNI
R320
0Ω
DNI
AGND
AGND
AGND
J303 L325
DNI
C349
DNI
R318
DNI
R322
0Ω
DNI
R323
0Ω
DNI
LO1 IN/OUT
C350
100pF
DNI
R357
0Ω
DNI
R321
0Ω
DNI R324
0Ω
DNI
R329
0Ω
DNI
R328
0Ω
DNI
R325
0Ω
DNI
R327
0Ω
DNI
R326
0Ω
DNI
R356
0Ω
DNI
EXT_LO1+
2
5
5
4
3
2
6 1
NC
2 6
UNBAL
GND GND NC
BAL
BAL
L330
DNI
R310
DNI
L331
DNI C352
DNI
R330
100Ω
DNI
L334
DNI C353
DNI
EXT_LO1–
EXT_LO1+
R331
100Ω
DNI
L333
DNI
C322
100pF
DNI
R350
0Ω
DNI
C320
0.001µF
DNI
L332
DNI
R354
0Ω
DNI
C321
0.001µF
DNI
L335
DNI
R355
0Ω
DNI
C323
100pF
DNI
R311
DNI
24159-183
Figure 182. External LO Impedance Matching Network
Table 90. EXTLO1± and EXTLO2± Impedance Matching Network
Frequency Balun
L324
C317
R308
C349
L325
R318
L326
C319
R309
R356
R321
R320
R319 C357
L327/329
C350/351
R322/323
R326/327
R324/325
R328/329
L330/332
C320/321
R310/354
L331
C352
R330
L333/335
C322/323
R311/355
L334
C353
R331 R350
60 MHz to
2 GHz
MiniCircuits
TCM1-83X+
L324:
DNI
L325:
0.6 nH
(Coil-
Craft
0201DS)
L326:
DNI
R319:
0 Ω
C357:
DNI
L327/
L329:
DNI
R326/
R327:
DNI
L330/
L332:
DNI
L331:
DNI
L333/335:
0.6 nH
(Coil-
Craft
0201DS)
L334:
DNI
R350:
DNI
C317:
DNI
C349:
DNI
C319:
DNI
R356:
DNI
C350/
C351:
DNI
R324/325:
DNI
C320/
C321:
DNI
C352:
1.2 pF
(Murata
GJM03)
R330
C322/
C323:
DNI
C353:
DNI
R308:
DNI
R318:
DNI
R309:
DNI
R321:
DNI
R322/
R323: DNI
R328/
R329:
470 pF
(Murata
GRM03)
R310/
R354:
0 Ω
R311/
R355:
DNI
R331:
DNI
R320:
DNI
60 MHz to
6 GHz
MiniCircuits
TCM1-83X+
L324:
DNI
L325:
DNI
L326:
DNI
R319:
0.5 nH
(Coil-
Craft
0201DS)
C357:
DNI
L327/
L329:
DNI
R326/
R327:
DNI
L330/
L332:
1.3 nH
(Coil-
Craft
0201DS)
L331:
DNI
L333/
L335:
1.5 nH
(Coil-
Craft
0201DS)
L334:
DNI
R350:
DNI
C317:
DNI
C349:
DNI
C319:
DNI
R356:
DNI
C350/
C351:
DNI
R324/
R325:
DNI
C320/
C321:
DNI
C352:
0.2 pF
(Murata
GJM03)
C322/
C323:
DNI
C353:
0.1 pF
(Murata
GJM03)
R308:
DNI
R318:
0 Ω
R309:
DNI
R321:
DNI
R322/
R323:
DNI
R328/
R329:
470 pF
(Murata
GRM03)
R310/
R354:
DNI
R330:
DNI
R311/355:
DNI
R331:
DNI
R320:
DNI
Preliminary Technical Data UG-1828
Rev. PrA | Page 203 of 253
Frequency
Balun
L324
C317
R308
C349
L325
R318
L326
C319
R309
R356
R321
R320
R319
C357
L327/329
C350/351
R322/323
R326/327
R324/325
R328/329
L330/332
C320/321
R310/354
L331
C352
R330
L333/335
C322/323
R311/355
L334
C353
R331
R350
3 GHz to 6
GHz
TDK
HHM1595A1
L324:
DNI
L325:
DNI
L326:
DNI
R319:
DNI
C357:
DNI
L327/
L329:
DNI
R326/
R327:
0 Ω
L330/
L332:
DNI
L331:
DNI
L333/
L335:
DNI
L334:
DNI
R350:
DNI
C317:
DNI
C349:
DNI
C319:
DNI
R356:
DNI
C350/
C351:
DNI
R324/
R325:
470 pF
(Murata
GRM03)
C320/
C321:
DNI
C352:
DNI
C322/
C323:
DNI
C353:
DNI
R308:
DNI
R318:
0 Ω
R309:
DNI
R321:
DNI
R322/
R323:
DNI
R328/
R329:
DNI
R310/
R354:
0 Ω
R330:
DNI
R311/355:
0 Ω
R331:
DNI
R320:
0 Ω
4 GHz to 12
GHz
MiniCircuits
NCR2-123+
L324:
DNI
L325:
DNI
L326:
DNI
R319:
DNI
C357:
DNI
L327/
L329:
DNI
R326/
R327:
470 pF
(Murata
GRM03)
L330/
L332:
DNI
L331:
DNI
L333/
L335:
DNI
L334:
DNI
R350:
DNI
C317:
DNI
C349:
DNI
C319:
DNI
R356:
DNI
C350/
C351:
DNI
R324/
R325: DNI
C320/
C321:
DNI
C352:
DNI
C322/
C323:
DNI
C353:
DNI
R308:
DNI
R318: 0
Ω
R309:
DNI
R321:
0 Ω
R322/
R323:
0 Ω
R328/
R329:
DNI
R310/
R354:
0 Ω
R330:
DNI
R311/
R355:
0 Ω
R331:
DNI
R320: DNI
A single-ended external LO signal can be applied by bypassing balun interface and installing appropriate impedance matching network
comprised of L324/C317, C349/L325/R318, and L326/C319 and AC-coupling cap of C357. Additionally, R350 should be replaced with a
large capacitor to provide an ac-ground for the negative side of input pin of internal buffer circuitry.
EXTERNAL LO IMPEDANCE MATCH MEASUREMENT DATA
External RF Port Impedance Match Measurement Data for 60 MHz to 6 GHz Band Match
Return loss was measured on EXT LO RF ports of eval boards and plotted on Figure 183; blue and pink curves represent four different
return loss measurements and black dotted line represents simulated return loss curve. Simulated Insertion loss including balun loss is
plotted on Figure 184.
FREQUENCY (G Hz)
0.06 1.06 2.06 3.06 4.06 5.06 6.00
24159-184
Figure 183. External LO1/ External LO2 Return Loss of Ext LO Port
UG-1828 Preliminary Technical Data
Rev. PrA | Page 204 of 253
FREQUENCY (GHz)
0123456
24159-185
Figure 184. External LO1/ External LO2 Insertion Loss, Simulated
CONNECTION FOR EXTERNAL DEVICE CLOCK (DEV_CLK_IN)
ADRV9001 can accommodate 3 different types of external clock signals applied at device clock input pins. A differential low voltage
differential signalling (LVDS) clock signal or a single-ended clipped sinewave clock signal from a TCXO can be applied to the device
input pins. Furthermore, a crystal can be connected to device clock input pins to configure it as a crystal oscillator/driver by applying DC
voltage into MODEA pin as shown below;
Table 91. Device Clock Input Interface Modes Description
Voltage Applied at
MODEA Pin
Device Clock Input
Electrical Interface
DEV_CLK_OUT Divider Value Applied
to DEV_CLK_IN Signal Note
0 V (grounded) LVDS /16 Up to 1GHz clock
0.45 V CMOS or XTAL /2 CM0S(10MHz to 80MHz)
/XTAL(20 MHz to 80 MHz) with
Nominal Gm multiplier = x8
0.9 V CMOS or XTAL /2 CM0S(10MHz to 80MHz)
/XTAL(20 MHz to 80 MHz) with
Nominal Gm multiplier = x6
1.35 V CMOS or XTAL /2 CM0S(10MHz to 80MHz)
/XTAL(20 MHz to 80 MHz) with
Nominal Gm multiplier = x2
1.8 V CMOS or XTAL /2 CM0S(10MHz to 80MHz)
/XTAL(20 MHz to 80 MHz) with
Nominal Gm multiplier = x4
By applying 1.8V to MODEA pin A for CMOS interface mode, a clipped sinewave clock signal from a TCXO can be applied to pin
named DEV_CLK_IN+(E7) via a AC coupling capacitor and pin DEV_CLK_IN-(E8) should be left unconnected.
A Xtal should be connected to both DEV_CLK_IN+ and DEV_CLK_IN- pins with a DC voltage between 0.45 and 1.8V applied to
MODEA pin.
When LVDS mode input clock interface is selected with MODEA pin grounded, an external clock is used as the reference clock for the
RFPLL and the Clocking PLL on the device and thus needs to be a very clean clock source. Connect the external clock inputs to the
DEV_CLK_IN+ (E7) and DEV_CLK_IN- (E8) balls via AC coupling capacitors and should be terminated with 100 Ω as shown in
Figure 185, Figure 186, and Figure 187. The inputs are biased on the device to a 618 mV voltage level. The input impedance plot over
operating frequency is shown on Figure 188. The operational frequency range of the DEV_CLK signal is between 10 MHz and 1000
MHz. Ensure that the external clock peak-to-peak amplitude does not exceed 2V (Note that either positive and negative side of
differential input pins should not exceed 1 Vpeak.). For best synthesizer performance, a high slew rate signal is best with fast rise and fall
times.
Preliminary Technical Data UG-1828
Rev. PrA | Page 205 of 253
Device Clock Interface Modes
DEV_CLK_IN+
LVDS
CLOCK 100nF
100Ω
E8
E7
100nF DEV_CLK_IN–
24159-186
Figure 185. LVDS Interface Mode
DEV_CLK_IN+
CMOS
CLOCK 100nF
E8
E7
UNCONNECTED DEV_CLK_IN–
24159-187
Figure 186. CMOS Interface Mode
DEV_CLK_IN+
E8
E7
DEV_CLK_IN–
24159-188
Figure 187. Crystal (XTAL) Interface Mode
0
5.0
–5.0
2.0
1.0
–1.0
–2.0
0.5
–0.5
0.2
–0.2
m1
FREQUENCY = 10.00MHz
S(5,5) = 0.997/–402
IM P EDANCE = 9.694E3 + j2.467E 4
m2
FREQUENCY = 100. 0MHz
S(5,5) = 0.997/–4.067
IM P EDANCE = 137.890 – j 2.809E3
m3
FREQUENCY = 300. 0MHz
S(5,5) = 0.990/–12.133
IM P EDANCE = 46.714 – j 938.620
m4
FREQUENCY = 600.0MHz
S(5,5) = 0.969/–23.831
IM P EDANCE = 36.427 – j 471.206
m5
FREQUENCY = 1. 000GHz
S(5,5) = 0.932/–38.422
IM P EDANCE = 32.096 – j 283.752
FREQUENCY ( 100.0kHz TO 1.000GHz )
S(5,5)
M5
M3
M2
M1
M4
24159-189
Figure 188. Device Clock Input Series Equivalent Differential Impedance
Device clock input board traces connected to device clock inputs balls should be implemented with stripline transmission lines using
inner copper layers in PCB stackup. The frequency of device clock input signal can go as high as 1GHz and stripline transmission line
approach will provide better signal integrity of clock signal especially at higher frequency as well as superior shielding of RF emission of
device clock signal.
The DEV_CLK_IN signal is available on the DEV_CLK_OUT pin. Table 91 describes default division applied to DEV_CLK_IN signal
after power up. Use can change this divider later on using API command. It should be noted that DEV_CLK_OUT pin is a CMOS type
pin. It is intended to be used to provide clock to BBIC or on-board microcontroller or audio CODEC type devices. It is not intended to
be used by another RF sensitive IC.
DEV_CLK_IN PHASE NOISE REQUIREMENTS
To prevent performance degradation, the DEV_CLK reference must be a very clean signal. Best performance from the synthesizer would
result if the applied reference were ideal, however that is unrealistic. Table 92 lists the required phase noise of the DEV_CLK signal for a
UG-1828 Preliminary Technical Data
Rev. PrA | Page 206 of 253
1dB system PN degradation compared to an ideal DEVICE CLOCK. For different DEV_CLK frequencies, the table can be scaled
appropriately. Clock source with phase noise performance outlined in Table 92 (or better) allows ADRV9001 to deliver datasheet
performance. It should be noted that Table 92 provide reference information for ADRV9001 operating with LTE type standards. Each
standard will determine its own DEV_CLK phase noise requirements. As an example, Table 93 provides recommendation for DEV_CLK
when ADRV9001 is intended to operate with LMR type standards. Ideally DEV_CLK phase noise requirement should be derived from
customer specific application and its requirements set for adjacent channel rejection.
In general, using a higher phase noise source can degrade performance delivered by ADRV9001 transceiver.
Table 92. DEV_CLK_IN Phase Noise Requirements for 1dB system PN degradation compared to an ideal DEVICE CLOCK
Frequency Offset
From Carrier
Narrow PLL Loop Bandwidth (Approximately
50 kHz) (Default, Typically <3 GHz)
Wide PLL Loop Bandwidth (Approximately 300 kHz)
(User Configured, Typically >3 GHz )
122.88 MHz
(dBc/Hz)
153.6 MHz
(dBc/Hz)
245.76 MHz
(dBc/Hz)
122.88 MHz
(dBc/Hz)
153.6 MHz
(dBc/Hz)
245.76 MHz
(dBc/Hz)
100 Hz −113.02 −111.08 −107.00 −114.02 −112.08 −108.00
1000 Hz −125.02 −123.08 −119.00 −127.02 −125.08 −121.00
10 KHz −133.02 −131.08 −127.00 −138.02 −136.08 −132.00
100 KHz −137.02 −135.08 −131.00 −146.02 −144.08 −140.00
1 MHz −133.02 −131.08 −127.00 −147.02 −145.08 −141.00
10 MHz −104.02 −102.08 −98.00 −118.02 −116.08 −112.00
Table 93. DEV_CLK_IN Phase Noise Requirements for LMR Type Applications
Frequency Offset From Carrier PLL Loop Bandwidth Optimized for LMR Type Applications, 38.4 MHz (dBc/Hz)
100 Hz
−106
1000 Hz −151
10 kHz −151
100 kHz −151
10 MHz −151
CONNECTION FOR MULTICHIP SYNCHRONIZATION (MCS) INPUT
A LVDS type MCS signal applied between MCS+(D7) and MCS-(D8) pins is used to provide time alignment synchronization for the
both RF and datalink systems. Similar to device clock input signal, a clock source with fast rise and fall times should be used as MCS
input signal. PCB traces for routing MCS signals should be implemented following guidelines that are similar to LVDS mode device
clock input trace.
Preliminary Technical Data UG-1828
Rev. PrA | Page 207 of 253
PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS
The ADRV9001 is a highly integrated RF agile transceiver with significant signal conditioning integrated onto one chip. Due to the
integration complexity of the ADRV9001 and its high pin count, careful printed circuit board (PCB) layout is important to optimize
performance. This section provides a checklist of issues to look for and guidelines on how to optimize the PCB to mitigate performance
issues. The goal of this document is to help achieve the best possible performance from the ADRV9001 while reducing board layout
effort. It is assumed that the reader is an experienced analog/RF engineer who understands RF PCB layout and has an understanding of
RF transmission lines as well as low-noise analog design techniques. The ADRV9001 evaluation card is used as the reference for this
information, but all guidelines are best practices that can be applied to other reference designs. This document provides guidelines for
system designers and discusses the following issues relative to layout and power management.
• PCB material and stack up selection
• Fan-out and layout guidelines relative to trace widths and spacing
• Component placement and routing guidelines
• RF and Data Port transmission line layout
• Isolation techniques used on the ADRV9001 customer evaluation board
PCB MATERIAL AND STACK UP SELECTION
Figure 189 shows the PCB stackup used for the ADRV9001 customer evaluation boards. These boards employ 12 layers to achieve proper
routing and isolation to best demonstrate all device functionality. The dielectric material used is I-SPEED with a thickness of 7 mil on
outer layers. The board design uses the I-SPEED laminate for its low loss tangent at high frequencies. The ground planes under the I-
SPEED laminate (layers 2 and 11) are the reference planes for the transmission lines routed on the outer surfaces. These layers are solid
copper planes under the RF traces with no discontinuities. Layers 2 and 11 are crucial to maintaining the RF signal integrity.
RF traces on the outer layers need to be a controlled impedance to get the best performance. These outer layers use 0.5 ounce copper. 0.5
and 1-ounce copper thickness are used for all the inner layers in this board. All ground planes on this board are full copper floods with
no splits except for vias, through-hole components and isolation structures (more on this in later sections).
Layers 3, 5, 7, 9 are mainly used to route power supply domains. The Date Port interface lines are routed on layers 1, 7 and 12. Those
layers have impedance control set to 100Ω differential for the differential LVDS pairs. The remaining digital signals are routed on inner
layers 3, 5, 9 and 10. Table 94 describes details of the trace impedance controls used on different layers.
There are no buried in or blind vias used in this PCB design. All vias used in the PCB design are thru hole type. For vias carrying high
frequency or RF sensitive signals, back drilling technique is applied.
Figure 189. ADRV9001 Customer Evaluation Card Stackup
UG-1828 Preliminary Technical Data
Rev. PrA | Page 208 of 253
Table 94. Impedance Table
Layer
Structure
Type
Coated
Microstrip1
Target
Impedance
(Ω)
Impedance
Tolerance
(Ω)
Target
Linewidth
(mils)
Edge
Coupled
Pitch
(mils)
Reference
Layers
Modelled
Linewidth
(mils)
Modelled
Impedance
(Ω)
Coplaner
Space
(mils)
1 Single
ended
N/A 50.00 ±5 12.00 0.00 (2) 13.00 50.87 9.50
1 Single
ended
Yes 50.00 ±5 13.50 0.00 (2) 12.00 50.42 10.75
1 Edge
Coupled
Differential
Yes 100.00 ±10 8.25 15.25 (2) 8.00 100.43 9.15
1 Edge
Coupled
Differential
N/A 100.00 ±10 7.50 14.50 (2) 9.00 100.55 9.25
3 Single
ended
N/A 50.00 ±5 4.00 0.00 (2, 4) 4.25 49.53 17.88
3 Edge
Coupled
Differential
N/A 100.00 ±10 3.75 10.75 (2, 4) 3.75 100.86 12.02
7 Edge
Coupled
Differential
N/A 100.00 ±10 6.00 14.25 (6, 8) 6.00 99.75 12.02
9 Edge
Coupled
Differential
N/A 100.00 ±10 6.25 15.00 (8, 11) 6.00 100.68 12.14
10 Edge
Coupled
Differential
N/A 100.00 ±10 4.25 9.50 (11, 8) 4.50 100.23 11.89
12 Edge
Coupled
Differential
Yes 100.00 ±10 8.00 15.25 (11) 8.00 100.80 10.00
12 Single
ended
Yes 50.00 ±5 12.00 0.00 (11) 12.00 50.31 10.00
12 Edge
Coupled
Differential
N/A 100.00 ±10 7.50 14.50 (11) 9.00 100.55 9.25
12 Edge
Coupled
Differential
N/A 100.00 ±10 8.25 15.50 (11) 8.25 99.64 10.02
1 N/A means not applicable.
FAN-OUT AND TRACE SPACE GUIDELINES
The ADRV9001 device family uses a 196-pin BGA 12 × 12 mm package. The pitch between the pins is 0.8 mm. This small pitch makes it
impractical to route all signals on a single layer. RF pins have been placed on the outer edges of the ADRV9001 package. This helps in
routing the critical signals without a fan-out via. Each digital signal is routed from the BGA pad using a 4.5 mil trace. The trace is
connected to the BGA using via-in-the-pad structure. The signals are buried in the inner layers of the board for routing to other parts of
the system.
Extra care needs to be taken to ensure that DEV_CLK signal is shielded from any potential source of noise. Recommended approach is to
use differential signalling for DEV_CLK clock. The data port interface signals when used in LVDS-SSI mode needs to be routed as 100 Ω
differential pairs. Figure 190 shows the fan out scheme of the ADRV9001 evaluation card. There are no traces being routed between BGA
pads on the top layer. As mentioned before ADRV9001 evaluation card uses via-in-the-pad technique. This routing approach can be
used for ADRV9001 if there are no issues with manufacturing capabilities.
Preliminary Technical Data UG-1828
Rev. PrA | Page 209 of 253
4.5mil
TRACE
VIA-IN-THE-PAD
VIA S IZ E = 14mil
PAD SI ZE = 15mil
AIR G AP = 17.5mi l
24159-290
Figure 190. Trace Fan-Out Scheme on ADRV9001 Evaluation Card (PCB layer TOP and Layer 8 Enabled)
COMPONENT PLACEMENT AND ROUTING PRIORITIES
The ADRV9001 transceiver requires few external components to function, but those that are needed require careful placement and
routing to optimize performance. This section provides a priority order and checklist for properly placing and routing critical signals and
components as well as those whose location and isolation are not as critical.
Board layout design involves compromise. The recommendations within this User Guide are intended for wide RF bandwidth
applications. For narrow RF bandwidth applications, the board line impedance parameters within this document may not be optimal.
The following list provides general suggestions for board design:
• Match the customer board design as close as possible to the ADRV9001 board design.
• Be attentive to power distribution and power ground return methodology.
• Do not run high speed digital lines in close proximity to dc power distribution routes or RF line routes.
Signals with Highest Routing Priority
RF lines and DEV_CLK clock are the signals that are most critical and should be routed with highest priority. Figure 191 shows the
general directions in which each of the signals should be routed so that they can be properly isolated from noisy signals.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 210 of 253
24159-191
Figure 191. RF I/O, DEV_CLK, and Data Port Signal Routing Guidelines
• RF baluns are typically used to interface single-ended signals to the differential receiver and transmitter ports. These baluns and
their associated matching circuits affect overall RF performance. Every effort should be made to optimize the component selection
and placement to avoid performance degradation. The RF Port Interface Information section describes proper matching circuit
placement and routing in more detail. Please refer to that paragraph for more information.
• Use microstrip or coplanar waveguides (CPWG) for transmission lines. These structures do not require via structures that cause
additional impedance discontinuities that vary across frequency. For Rx1B and Rx2B, receiver ports, which do not have balls on the
perimeter of the BGA, a via structure such as stripline may be necessary.
• Design the RF line systems between the device ball pad reference plane and the balun/filter reference plane for a differential
impedance (ZDIFF) of 100 Ω for the receivers and 50 Ω for the transmitters. This is a compromise impedance with respect to
frequency and a good starting point for design. The ZDIFF can be optimized to fit a narrower frequency range. It is desirable to
design the lines for reasonable coupling (−10 dB to −15 dB) to promote adequate EMI suppression performance.
• In most cases, the required board artwork stack-up is going to be different than the ADRV9001 evaluation board stack-up.
Optimization of RF transmission lines specific to the desired board environment is essential to the design and layout process.
• The ADRV9001 evaluation board uses microstrip lines for Rx and Tx RF traces. Some data port signal are routed using a
combination of microstrip lines on the bottom of the PCB and stripline traces on internal layers due to board complexity. In general,
RF traces should not use vias unless a direct line route is not possible.
Preliminary Technical Data UG-1828
Rev. PrA | Page 211 of 253
• Differential lines from the balun to the Rx and Tx pins need to be as short as possible. The length of the single ended transmission
line should also be short to minimize the effects of parasitic coupling.
• The system designer can optimize the RF performance with the proper selection of balun, matching components, and ac coupling
capacitors. The external LO traces and the DEV_CLK_IN traces may require matching components as well to ensure optimal
performance. Matching network design is explained in greater detail in the RF Port Interface Information section of this document.
• RF signal path isolation is critical to achieving the level of isolation specified in the ADRV9001 datasheet. More details on proper
isolation are provided in the Isolation Techniques Used on the ADRV9001 Evaluation Card section.
• For each RF Tx output, install a 10µF capacitor near the balun power supply pin connected to the VANA1_1P8, VANA2_1P8
supplies. If baluns with no dc supply connection are used, power will need to be supplied to the Tx outputs using RF chokes.
Connect chokes between the VANA1_1P8 and Tx1 output and VANA2_1P8 and Tx2 output respectively. In both cases, the 10µF
capacitor acts as a reservoir for Tx supply current. The TX Balun DC Supply Options section describes the Tx output power supply
configuration in more detail.
• Connect the external clock inputs to the DEV_CLK_IN+ (E7) and DEV_CLK_IN− (E8) pins using ac coupling capacitors. Use a
100 Ω termination at the input to the device. Figure 192 illustrates the recommended placement for termination resistor near the
DEV_CLK_IN pins. Traces should be shielded by surrounding ground with vias staggered along the edge of the differential trace
pair. This arrangement creates a shielded channel that prevents the reference clock from any interference from other signals. Refer
to the ADRV9001 evaluation card layout for exact details.
BGA BAL LS
100Ω TERMINATION
RESISTOR
DEV_CLK_IN
TRACE S (INNE R LAYER)
24159-192
Figure 192. DEV_CLK_IN Signal Routing Recommendations
• The EXT_LO1+ (A12), EXT_LO1- (A11), EXT_LO2+ (A3), EXT_LO2- (A4) pins are internally dc biased. If an external LO is used,
connect it via ac coupling capacitors.
• The data port interface should be routed at the beginning of the PCB design and with the same priority as RF signals. This is
especially important if data port runs in LVDS configuration. Attention should be paid to provide appropriate isolation between
data port differential pairs.
Signals with Secondary Routing Priority
Power supply quality has direct impact on overall system performance. To achieve optimal performance, users should follow
recommendations regarding power supply routing. The following recommendations outline how different power domains should be
routed and which supplies can be tied to the same supply but separated by a ferrite bead.
A general recommendation for power supply routing is to follow the star methodology in which each power domain is deliver by a
separate trace from the source supply. Care should be taken to make sure that each power trace is surrounded by ground. Figure 193
shows an example of such traces routed on the evaluation card on layer 3. Each trace is separated from any other signal by ground plane
fill and vias. This approach is essential to providing necessary isolation between power domains.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 212 of 253
Figure 193. Layout Example of Power Supply Connections Routed with Ground Shielding (Layer 3)
Figure 194 shows an example of how the ferrite beads, reservoir capacitors and decoupling capacitors should be placed.
Recommendation is to connect a ferrite bead between a power plane and ADRV9001 at a distance away from ADRV9001. The ferrite
bead should supply a trace with a reservoir capacitor connected to it. That trace should then be shielded with ground and provide power
to ADRV9001 Power pin. A 1 µF capacitor should be placed near the power supply pin with the ground side of the bypass capacitor
placed so that ground currents flow away from other power pins and their bypass capacitors.
SEPARAT E TRACE
SURROUNDE D BY GROUND
FERRITE
BEAD 100µF
RESERVOIR
CAPACITOR
1µF BY PASS
CAPACITOR
AGND
C1043
1µF
VRX2LO_1P3
C1042
100µF
R1011
0Ω
VDDA_1P3
VDDA_1P0
R1012
DNI
2 1 1
E1024
120Ω
TP1024
RED
VIA TO
POWER
DOMAIN
BALL
Figure 194. Placement Example of Ferrite Beads, Reservoir and Bypass Capacitors on ADRV9001 Customer Card
(Layers: TOP, 3-Power and BOTTOM)
There are two possible power supply architectures for ADRV9001 transceivers, as follows:
• High performance, low risk, four power domains
• 1.8 V digital
• 1.8 V analog
• 1.3 V analog
• 1.0 V digital
Preliminary Technical Data UG-1828
Rev. PrA | Page 213 of 253
This approach utilizes the ADRV9001 internal LDOs to generate 1.0 V for all internal blocks. Figure 195 outline power supply routing
recommendations for this architecture.
TRACE TO 1.8V DIG
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1.3V
CONNECT 2 PINS TOGETHER
WITH 4.7µF CAPACITOR CONNECT 2 P INS TOGETHER
WITH 4.7µF CAPACITOR
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1. 8V Tx2
TRACE WITH F B TO 1. 8V ANLG
4.7µ F CAPACITOR
4.7µ F CAPACITOR
4.7µ F CAPACITOR
TRACE WITH F B TO 1.8V Tx1
TRACE TO 1.0V DIG.
HIGH CURRENT
TRACE WITH F B TO 1.3V
TRACE WITH F B TO 1.3V
TRACE WITH F B TO 1.3V
TRACE WITH F B TO 1.3V
TRACE WITH F B TO 1.3V
TRACE WITH F B TO 1.3V
TRACE WITH F B TO 1.3V
TRACE WITH F B TO 1.3V
TRACE WITH F B TO 1.8V ANLG
4.7µ F CAPACI
TOR
4.7µ F CAPACITOR
4.7µ F CAPACITOR
24159-195
Figure 195. ADRV9001 Power Supply Domains with Connection Guidelines, All Internal LDOs in Use
• Power supply optimization, higher risk (utilize noise sensitive 1.0V analog), 5 power domains:
• 1.8 V digital,
• 1.8 V analog,
• 1.3 V analog,
• 1.0 V digital,
• 1.0 V analog,
This approach that utilizes some of ADRV9001 internal LDOs to generate 1.0 V for internal blocks. For remining blocks it expect the
1.0 V to be delivered from external power source. Figure 196 outline power supply routing recommendations for this architecture.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 214 of 253
TRACE TO 1.8V DIG
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1.3V
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1. 0V ANLG
TRACE WITH F B TO 1. 0V ANLG
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1. 8V Tx2
TRACE WITH F B TO 1. 8V ANLG
4.7µ F CAPACITOR
4.7µ F CAPACITOR
TRACE WITH F B TO 1. 8V Tx1
TRACE TO 1.0V DIG.
HIGH CURRENT
TRACE WITH F B TO 1.3V
4.7µ F CAPACITOR
4.7µ F CAPACITOR
TRACE WITH F B TO 1.0V ANLG + 1 µF CAP TRACE WITH F B TO 1.0V ANLG + 1 µF CAP
TRACE WITH F B TO 1.3V
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1. 0V ANLG
TRACE WITH F B TO 1. 0V ANLG
TRACE WITH F B TO 1. 3V
TRACE WITH F B TO 1. 0V ANLG
TRACE WITH F B TO 1. 8V ANLG
4.7µ F CAPACITOR
4.7µ F CAPACITOR
24159-196
Figure 196. ADRV9001 Power Supply Domains with Connection Guidelines, Some Internal LDOs bypassed, 1.0 V Analog Domain Required
Ceramic 4.7 µF bypass capacitors must be placed at the VRFVCO2_1P0, VRFVCO1_1P0, VRX2LO_1P0, VRX1LO_1P0,
VCLKVCO_1P0, VAUXVCO_1P0, VCONV_1P0 and VDIG_0P9 pins. Place these capacitors as close as possible to the device with the
ground side of the bypass capacitor placed so that ground currents flow away from other power pins and their bypass capacitors if at all
possible.
In scenario, when power supply follows recommendation outlined in Figure 196 (some internal LDOs bypassed, external 1.0V analog
domain in use), 4.7 μF capacitors at VRX2LO_1P0, VRX1LO_1P0 pins are not necessary. 1.0 V domains connected to VRFLO1_1P0 and
VRFLO2_1P0 require 1 μF capacitors.
Signals with Lowest Routing Priority
The following guidelines govern those signals that are the lowest signal routing priority. These can be routed after all critical signal routes
have been completed so they don’t interfere with the critical component placement and routing. The signals shown in Figure 197 can be
routed with the lowest priority.
• Connect a 4.99 kΩ resistor to RBIAS pin (C14). This resistor must have a 1% tolerance or better.
• The device has support for JTAG boundary scan, and the MODE pin is used to access the function. Connect the MODE pin (L13) to
ground for normal operation. Refer to the datasheet for JTAG boundary scan information.
• Connect the RESETB pin (K13) to VIOCTRL_1P8 with a 10 kΩ resistor for normal operation. The device can be reset by driving
this pin low.
• When routing digital signals from rows K and below, it is important to route them away from the analog section (rows A through H).
Digital signal routing should not pass above the red dotted line highlighted in Figure 197.
• The AGPIO_N signals can be routed using inner PCB layers. Those signals are intended to control analog blocks such as power
amplifiers or low noise amplifiers. The AGPIO_0 thru AGPIO_3 can also be used as general purpose analog outputs when muxed to
Preliminary Technical Data UG-1828
Rev. PrA | Page 215 of 253
the internal AUXDAC outputs. To prevent noise coupling into those signals, the user should route them away from digital region
(above the red dotted line highlighted in Figure 197.
• The AuxADC_N signals can be routed using inner PCB layers. Those signals are intended to sense analog voltage levels such as
temperature sensors. To prevent noise coupling into those signals the user should route them away from digital region (above red
dotted line highlighted in Figure 197).
• MODEA signal is intended to setup operation of DEV_CLK_IN± pins (LVDS differential, CMOS single-ended, XTAL with
different bias voltage). User should follow recommendation outlined in RF Port Interface Information section when controlling this
pin.
• MCS± signals should be treated as differential. If multi-chip synchronization feature is intended to be used in end application, those
signals should be routed with traces matching length of DEV_CLK_IN± traces.
BIAS TO GND OR 1.8V ANALOG
ROUTE AS DIF FE RENTIALPAIR
ALL DIGITAL GPIO
SIGNALS ROUTED
BELO W T HE RED L INE
4.99kΩ RESISTOR
24159-197
Figure 197. ADRV9001 AuxADC, SPI, Analog GPIO/AuxDAC, MCS±, and Digital GPIO Signal Routing Guidelines
RF AND DATA PORT TRANSMISSION LINE LAYOUT
RF Line Design Summary
The RF line design is a compromise between many variables. Line impedance, line to line coupling, and physical size represent the
parameters subject to compromise. Smallest physical size is in direct opposition to the ZCM of the line, which is directly opposed to the
line EMI performance. In addition, the interface between the RF line width and the device ball pad diameter on the PCB represents a
potential discontinuity. As the RF line width approaches the ball pad diameter, the risk associated with potential interface discontinuity
reduces.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 216 of 253
Balanced lines for differential mode signalling used between the device and the RF balun should be as short as possible. The length of the
single ended transmissions lines for RF signals should also be as short as possible. Keeping signal paths as short as possible reduce
susceptibility to undesired signal coupling and reduce the effects of parasitic capacitance, inductance, and loss on the transfer function of
the transmission line and impedance matching network system. The routing of these signal paths is the most critical factor in optimizing
performance and, therefore, should be routed prior to any other signals and maintain the highest priority in the PCB layout process.
BOTTOM SIDE
ALTERNATIVE,
LOWER-BANDS
BALUN FOOT P RINT
HIGHER-BANDS BALUN
FOOTPRINT
SINGLE-ENDED PI
NETWORK
RESISTOR/OPTIONALAC
COUPLI NG CAPACITOR
SWITCHING NETWORK
DIFFERENTIAL
PI NETWORK
TOP SIDE
24159-198
Figure 198. Receiver Matching Network on ADRV9001 Evaluation Board
The circuit in Figure 198 shows the layout topology for the chosen receiver matching network. Note the location and orientation of each
component – placement is critical to achieve expected performance. Similarly, the circuit in Figure 199 shows the layout topology used
for the transmitter matching network. (see the RF Port Interface Information section for circuit details). More details concerning the dc
supply to the transmitter section are provided in the next section.
All the RF signals must have a solid ground reference under each path to maintain the desired impedance. None of the critical traces
should run over a discontinuity in the ground reference.
Preliminary Technical Data UG-1828
Rev. PrA | Page 217 of 253
BOTTOM SIDE
ALTERNATIVE,
LOWER-BANDS
BALUN F OOTPRINT
HIG HE R- BANDS BALUN
FOOTPRINT
SINGLE-ENDED
PI NETWORK
RESISTOR/OPTIONALAC
COUPLING CAPACITOR
SWITCHING NETWORK
DIFFERENTIAL
PI NETWORK
TOP SIDE
24159-199
Figure 199. Transmitter Matching Network on ADRV9001 Evaluation Board
Transmitter Bias and Port Interface
This section considers the dc biasing of the ADRV9001 transmitter (Tx) outputs and how to interface to each Tx port. At full output
power, each differential output side draws approximately 100mA of DC bias current. The Tx outputs are dc biased to a 1.8V supply
voltage using either RF chokes (wire-wound inductors) or a transformer (balun) center tap connection.
Careful design of the DC bias network is required to ensure optimal RF performance levels. When designing the dc bias network, select
components with low dc resistance (RDCR) to minimize the voltage drop across the series parasitic resistance element with either of the
dc bias schemes suggested in Figure 200 and Figure 201 The red resistors (R_DCR) indicate the parasitic elements. As the impedance of
the parasitic increase, the voltage drop (ΔV) across the parasitic element increases which causes the transmitter RF performance (i.e
PO,1dB, PO,MAX, etc…) to degrade. The choke inductance (L_c) should be selected high enough relative to the load impedance such
that it does not degrade the output power. If chokes are used they should be very well matched (including PCB traces). Uneven matching
of chokes design can cause unwanted emission of spikes at the Tx output. This emission can affect components connected to the Tx
output.
The recommended dc bias network is the one using the center tap balun is shown in Figure 201. This network has fewer parasitic and
fewer total components.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 218 of 253
VDC = 1.8V
CB
RDCR ΔV
VBIAS = 1.8V – ΔV
VBIAS = 1.8V – ΔV
ΔV RDCR
LC
+
–
+
–
LC
OUTPUT
STAGE
IBIAS = ~ 100mA
TX1_OUT–/
TX2_OUT–
TX1_OUT+/
TX2_OUT+
IBIAS = ~ 100mA
24159-294
Figure 200. ADRV9001 DC Bias Configuration for the Transmitter Output Using Wire-Wound Chokes
ΔV
VBIAS = 1.8V – ΔV
VBIAS = 1.8V – ΔV
+–
ΔV +–
CB
Tx1 O R Tx2
OUTPUT
STAGE
IBIAS = ~ 100mA
1.8V
RDCR
RDCR
IBIAS = ~ 100mA
TX1_OUT–/
TX2_OUT–
TX1_OUT+/
TX2_OUT+
24159-295
Figure 201. ADRV9001 DC Bias Configuration for the Transmitter Output Using a Center-Tapped Transformer
The ADRV9001 evaluation board provides flexibility to configure each Tx output to work with either a center tapped transformer
(balun) or a set of two closely matched wire wounded chokes. The center tapped transformer passes the bias voltage directly to the
transmitter outputs through each differential input. This configuration offers the lowest component count.
In some cases, the desired balun does not provide a dc connection to the transmitter output lines. To support this situation, the
ADRV9001 evaluation board provides the placeholders for RF chokes tied to the VANA1_1P8 (for Tx1 output) and VANA2_1P8 (for
Tx2 output) supply. It also provides the placeholders for ac coupling capacitors to prevent creating a dc short through the balun to
ground.
Impedance matching networks on the balun single-ended port are usually required to achieve optimum performance. In addition, ac
coupling is often required on the single-ended side if the balun contains a dc path from one of the transmitter’s differential outputs to the
single-ended port.
Careful planning is required for the Tx balun selection. If a Tx balun is selected that requires a set of external DC bias chokes, it is
necessary to find the optimum compromise between the choke physical size, choke dc resistance (RDCR) and the balun passband
insertion loss. Users should refer to the RF Port Interface Information section of this document for more information on Tx output
balun and RF choke selection as well as matching circuit recommendations.
TX Balun DC Supply Options
Each transmitter requires approximately 200mA supplied through an external connection. The PCB layout of the ADRV9001 board
allows use of external chokes to provide 1.8V power domain to the ADRV9001 outputs to allow users to try different baluns that may not
have a dc center tap pin to supply the bias voltage to the transmitter outputs.
To reduce switching transients when attenuation settings change, the balun dc feed should be powered directly by the 1.8V plane. The
geometry of the 1.8V plane should be designed so that each balun or each pair of chokes is associated with its Tx output. The
VANA1_1P8 should be used to power Tx1 output and VANA2_1P8 should be used to power Tx2 output.
If careful layout and isolation of the dc supply is not followed, it can adversely affect Tx-Tx isolation. Figure 202 shows the power supply
layout configuration used on the ADRV9001 board to achieve the desired Tx-Tx isolation performance. This image illustrates star
connection from common 1.8 V analog power plane.
Preliminary Technical Data UG-1828
Rev. PrA | Page 219 of 253
1.8V CO MMO N
POWER PLAIN FEED 1.8V CO MMO N
POWER PLAIN FEED
TX2 SUPPLY DO M AIN
(VANA2_1P8) T X2 SUPPLY DOMAIN
(VANA1_1P8)
LOOP BET WEEN CE NTRE TAP BALUN /
EXTERNAL CHOKES AND TX POW E R
DOM AINS NEE DS TO BE KEPT SHORT.
24159-200
Figure 202. 1.8 V Transmitter Power Supply Routing on the ADRV9001 Evaluation Board
An example of the balun feed supply designed to achieve the isolation managed in the evaluation board is shown in Figure 203 and
Figure 204.
DC Balun
When a Tx balun that is able to conduct dc is used then the system shown in Figure 203 should be used. The decoupling cap near the Tx
balun should be placed as close as possible to the balun’s DC feed pin. Its orientation should be perpendicular to the ADRV9001 device
so the return current avoids a ground loop with the ground pins surrounding the Rx input. The customer card provides an option to
install an RF isolation inductor which can provide extra isolation between the Tx1 and Tx2 balun supply feeds. A 10µF capacitor and a
0.1 µF capacitor are helpful on the dc feed pin to eliminate Tx spectrum spurs and dampen the transients. Note that when this supply
approach is used the series matching components must be dc shorts. It is recommended to use 0 Ω if an inductor is not needed to match
the balun impedance to the Tx output impedance.
DC FEE D FRO M
VANA1/ 2_1P 8 P LANE
RESERVOIR
CAPACITORS
OPTIONAL RF
ISOLATI ON INDUCTOR BALUN RF BAL UN S E LECT IO N COMPONENTS.
DC CONT INUI TY ON DIFFERENTIAL SI DE
DECOUPLING
CAPACITOR
(ORIENTATION IS
IMPORTANT)
24159-202
Figure 203. Transmitter Power Supply for a Balun with a Center Tap
Chokes
The ADRV9001 evaluation board provides flexibility to be configured to use a Tx balun that is not capable of conducting dc current. In
such a scenario, the user should install dc chokes as well as their decoupling capacitors as highlighted in Figure 204. Care should be taken
to match both chokes to avoid potential current spikes. Difference in parameters between both chokes can cause unwanted emission at
Tx outputs. Note that if the differential input to the balun can create a dc short to ground (through the balun), the series matching
components must be capacitors. If a short can form on the single-ended side, the single-end series blocking element must be a capacitor.
UG-1828 Preliminary Technical Data
Rev. PrA | Page 220 of 253
SERIES MATCHING
COMPONENTS
DECOUPLING
CAPACITORS
Tx DC POW E R
FEE D CHOKES
BALUN RF BALUN S E LECT IO N AND
DIFFERENTIAL/SINGLE-ENDED SERIES
DC BLO CKING COMPONENTS
DC FEE D FRO M
VANA1/ 2_1P 8 P LANE
24159-201
Figure 204. Transmitter Power Supply Using RF Chokes
SSI Data Port Trace Routing Recommendations
The Data Port interface transfer I/Q data between BBIC/FPGA and ADRV9001 Tx and Rx datapaths. There are two possible mode of
operation for SSI data port:
• CMOS-SSI mode – single ended - with clock rate for data transfer up to 80 MHz
• LVDS-SSI mode – differential - with clock rate for data transfer up to 500 MHz DDR (1000 MHz data rate)
Correct layout practice should be followed while routing SSI interface signals.
If CMOS-SSI mode is selected, single-ended signal lines between ADRV9001 and BBIC/FPGA should be as short as possible. Trace
capacitance should also be minimized to minimize the current needed by ADRV9001 to drive the line. Refer to the ADRV9001 datasheet
document for details regarding pin drive capabilities.
If LVDS-SSI mode is selected, the user should route all LVDS signals as 100 Ω differential pairs.
• When routing the PCB layout for LVDS-SSI data lines, the designer must decide to route the signals using stripline or microstrip
traces. There are positives and negatives for each that should be carefully considered.
• Stripline has less loss and emits less EMI than microstrip lines, but stripline traces require the use of vias that can add complexity to
the task of controlling the impedance by adding line inductance.
Microstrip is easier to implement if the component placement and density allow for routing on the top layer, simplifying the task of
controlling the impedance.
If using the top layer of the PCB is problematic or the advantages of stripline are desirable, then follow these recommendations:
• Minimize the number of vias.
• Use blind vias wherever possible to eliminate via stub effects, and use micro-vias to minimize via inductance.
• If using standard vias, use maximum via length to minimize the stub size. For example, on an 8-layer board, use layer 7 for the
stripline pair.
• For each via pair, a pair of ground vias should be placed in close proximity to them to minimize the impedance discontinuity.
In LVDS-SSI mode
• for Tx data port inputs, termination of 100Ω is implemented inside ADRV9001
• for Rx data port outputs, it is expected that 100 Ω termination is implemented at the receiver end.
Preliminary Technical Data UG-1828
Rev. PrA | Page 221 of 253
Evaluation Board FMC Connector Signals Mapping
The ADRV9001 evaluation board utilize FMC standard connector as an interface to carrier boards. Table 95 outlines signal mapping
utilized on FMC connector implemented on ADRV9001 evaluation board. Second column refers to FMC standard pinout names. For
more information refer to ADRV9001 EVB schematic.
Table 95. FMC Pinout Mapping Utilized by ADRV9001 Evaluation Board
Schematic Net Name FMC Connector Mappings
FPGA_REF_CLK+ G02-FMC_CLK1_M2C_P
FPGA_REF_CLK- G03-FMC_CLK1_M2C_N
DEV_CLK_OUT H04-FMC_CLK0_M2C_P
SM_FAN_TACH H05-FMC_CLK0_M2C_N
RX1_DCLK_OUT+ G06-FMC_LA00_CC_P
RX1_DCLK_OUT- G07-FMC_LA00_CC_N
RX1_STROBE_OUT+ H07-FMC_LA02_P
RX1_STROBE_OUT- H08-FMC_LA02_N
RX1_IDATA_OUT+ G09-FMC_LA03_P
RX1_IDATA_OUT- G10-FMC_LA03_N
RX1_QDATA_OUT+ H10-FMC_LA04_P
RX1_QDATA_OUT- H11-FMC_LA04_N
DGPIO_13_TX1_DCLK_OUT+ D08-FMC_LA01_CC_P
DGPIO_12_TX1_DCLK_OUT- D09-FMC_LA01_CC_N
TX1_DCLK_IN+ H13-FMC_LA07_P
TX1_DCLK_IN- H14-FMC_LA07_N
TX1_STROBE_IN+ C10-FMC_LA06_P
TX1_STROBE_IN- C11-FMC_LA06_N
TX1_IDATA_IN+ G12-FMC_LA08_P
TX1_IDATA_IN- G13-FMC_LA08_N
TX1_QDATA_IN+ D11-FMC_LA05_P
TX1_QDATA_IN- D12-FMC_LA05_N
RX2_DCLK_OUT+ D20-FMC_LA17_CC_P
RX2_DCLK_OUT- D21-FMC_LA17_CC_N
RX2_STROBE_OUT+ H25-FMC_LA21_P
RX2_STROBE_OUT- H26-FMC_LA21_N
RX2_IDATA_OUT+ G21-FMC_LA20_P
RX2_IDATA_OUT- G22-FMC_LA20_N
RX2_QDATA_OUT+ H22-FMC_LA19_P
RX2_QDATA_OUT- H23-FMC_LA19_N
DGPIO_15_TX2_DCLK_OUT+ C22-FMC_LA18_CC_P
DGPIO_14_TX2_DCLK_OUT- C23-FMC_LA18_CC_N
TX2_DCLK_IN+ G24-FMC_LA22_P
TX2_DCLK_IN- G25-FMC_LA22_N
TX2_STROBE_IN+ H28-FMC_LA24_P
TX2_STROBE_IN- H29-FMC_LA24_N
TX2_IDATA_IN+ D23-FMC_LA23_P
TX2_IDATA_IN- D24-FMC_LA23_N
TX2_QDATA_IN+ G27-FMC_LA25_P
TX2_QDATA_IN- G28-FMC_LA25_N
RX1_ENABLE C14-FMC_LA10_P
RX2_ENABLE D27-FMC_LA26_N
TX1_ENABLE D14-FMC_LA09_P
TX2_ENABLE G30-FMC_LA29_P
SPI_EN H19-FMC_LA15_P
SPI_CLK G15-FMC_LA12_P
SPI_DIO G31-FMC_LA29_N
UG-1828 Preliminary Technical Data
Rev. PrA | Page 222 of 253
Schematic Net Name FMC Connector Mappings
SPI_DO G16-FMC_LA12_N
MODE D17-FMC_LA13_P
RESET_TRX D18-FMC_LA13_N
DEV_MCS_FPGA_IN+ C18-FMC_LA14_P
DEV_MCS_FPGA_IN- C19-FMC_LA14_N
DGPIO_0 G18-FMC_LA16_P
DGPIO_1 G19-FMC_LA16_N
DGPIO_2 H20-FMC_LA15_N
DGPIO_3 H17-FMC_LA11_N
DGPIO_4 D15-FMC_LA09_N
DGPIO_5 C15-FMC_LA10_N
DGPIO_6 C26-FMC_LA27_P
DGPIO_7 D26-FMC_LA26_P
DGPIO_8 H31-FMC_LA28_P
DGPIO_9 H32-FMC_LA28_N
DGPIO_10 H16-FMC_LA11_P
DGPIO_11 C27-FMC_LA27_N
GP_INT H34-FMC_LA30_P
VADJ_TEST_1 (VADJ_ERR) G33-FMC_LA31_P
VADJ_TEST_2 (PLATFORM_STATUS) G34-FMC_LA31_N
FPGA_MCS_IN+ H37-FMC_LA32_P
FPGA_MCS_IN- H38-FMC_LA32_N
ISOLATION TECHNIQUES USED ON THE ADRV9001 EVALUATION CARD
Given the density of sensitive and critical signals, significant isolation challenges are faced when designing a PCB for the ADRV9001.
Isolation requirements listed below were followed to accurately evaluate the ADRV9001 device performance. Analytically determining
aggressor-to-victim isolation in a system is very complex and involves considering vector combinations of aggressor signals and coupling
mechanisms.
Isolation Goals
Table 96 lists the isolation targets for each RF channel-to-channel combination type. To meet these goals with significant margin,
isolation structures were designed into the ADRV9001 evaluation board.
Table 96. Port to Port Isolation Goals
30 MHz to 1 GHz 1 GHz to 6 GHz
Tx1 to Tx2 75 dB 70 dB
Tx1 to Rx1A/Rx1B 75 dB 70 dB
Tx1 to Rx2A/Rx2B 75 dB 70 dB
Rx1A/Rx1B to Rx2A/Rx2B 70 dB 65 dB
Rx1A to Rx1B 70 dB 65 dB
Isolation Between RF IO Ports
These are the primary coupling mechanisms between RF IO paths on the evaluation board:
• Magnetic field coupling
• Surface propagation
• Cross domain coupling via ground
To reduce the impact of these coupling mechanisms on the ADRV9001 customer evaluation board, several strategies were used. Large
slots are opened in the ground plane between RF IO paths. These discontinuities prevent surface propagation. These structures consist of
a combination of slots and square apertures. Both structures are present on every copper layer of the PCB stack. The advantage of using
square apertures is that signals can be routed between the openings without disturbing the isolation benefits that the array of apertures
provides. A careful designer will notice various bends in the routing of differential paths. These routes were developed and tuned
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through iterative electromagnetic simulation to minimize magnetic field coupling between differential paths. These techniques are
illustrated in Figure 205.
ISOLATION S TRUCTURE S
SQUARE APERTURES
ISOLATION S TRUCTURE S
SLOTS
DIFFERENTIALPATH
ROUTING
Tx2 Tx1
Rx2A
Rx1A
Rx1B
Rx2B
Ext_LO2
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Figure 205. RF I/O Isolation Structures
When utilizing the proposed isolating structures, it is important to place ground vias around the slots and apertures. Figure 206
illustrates the methodology used on the ADRV9001 evaluation card. When slots are used, ground vias should be placed at each end of the
slots and along each side. When square apertures are used, at least one single ground via should be placed adjacent to each square. These
vias should be through-hole vias connecting the top to the bottom layer and all layers in between. The function of these vias is to steer
return current to the ground planes near the apertures.
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Figure 206. Current Steering Vias Placed Near Isolation Slots and Square Apertures
For accurate slot spacing and square apertures layout, simulation software should be used when designing a PCB for an ADRV9001
based transceiver. As a general rule, spacing between square apertures should be no more than 1/10 of the shortest wavelength
supported. The wavelength can be calculated using Equation 1
300
[] []r
Wave length m Frequency MHz
ε
=×
(1)
where:
εr is the dielectric constant of the isolator material. For ISOLA I-speed material, εr = 3.56 and for FR4-408 HR material, εr = 3.77.
Example: given a maximum RF signal frequency of 6 GHz, for ISOLA I-speed material, using microstrip structures, and εr = 3.56, the
minimum wavelength is approximately 26.4 mm To fulfil the 1/10 of a wavelength rule, square aperture spacing should be at a distance
of 2.64 mm or closer.
Additional shielding is provided by using connecting VSSA balls under the device to form a shield around RF IO ball pairs. This ground
provides a termination for stray electric fields. Figure 207 shows how this is done for Tx1. The same is done for each set of sensitive RF
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I/O ports. Ground vias are used along single ended RF IO traces. Optimal via spacing is 1/10 of a wavelength, but that spacing can vary
somewhat due to practical layout considerations.
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Figure 207. Shielding of Rx Launches
RF IO baluns are spaced and aligned to reduce magnetic coupling from the structures in the balun package. Care must also be taken to
reduce cross talk over shared grounds between baluns. Another precaution taken involved placing and orienting SMA connectors to
minimize connector to connector coupling between ports.
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POWER SUPPLY RECOMMENDATIONS
TBD.
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ADRV9001 EVALUATION SYSTEM
The ADRV9001 family demonstration system enables customers to evaluate the device without having to develop custom software or
hardware. The system is comprised of a radio daughtercard, an Xilinx ZYNQ ZC706 motherboard, an SD card with operating system, a
12 V power supply for the ZYNQ ZC706 that connects to a wall outlet, and a C#-based evaluation software application. The evaluation
system uses an Ethernet interface to communicate with the PC.
INITIAL SETUP
The ADRV9001 transceiver evaluation software (TES) is the graphical user interface (GUI) to communicate with the evaluation
platform. It can run with or without evaluation hardware connected. When TES runs without the hardware connected, it can be fully
configured for a particular operating mode. If the evaluation hardware is connected, set up the desired operating parameters with TES
and then the software can program the evaluation hardware. After the device is configured, the evaluation software can be used to
transmit waveforms using custom waveform files as well as observe signals received on one of the receiver input ports. An initialization
sequence in form of an IronPython script can be generated and executed using TES.
HARDWARE KIT
The ADRV9001 demonstration system kit contains:
• The customer evaluation (CE) board in form of a daughter card with FMC connector
• One (1) SD card containing image of Linux operating system with required evaluation software
• SD card type is 16 GB size, type 10
Requirements
The hardware and software require the following:
• The ADRV9001 demonstration system kit
• The Xilinx ZC706 ZYNQ evaluation platform: EK-Z7-ZC706 (not included in the ADRV9001 demonstration kit)
• One (1) 12 V power supply for powering the ZC706 ZYNQ.
• The operating system on the controlling PC must be Windows® 7 (×86 and ×64) or Windows 10 (×86 and ×64)
• The PC must have a free Ethernet port with the following constraints:
• If the Ethernet port is occupied by another LAN connection, use a USB-to-Ethernet adapter
• The PC should be able to access over this dedicated Ethernet connection the following ports:
• 22—SSH protocol
• 55557—access to the evaluation software on the ZYNQ ZC706 platform
• TES—contact your ADI representative to obtain access to this software
• The user must have administrative privileges
Hardware Setup
Xilinx ZC706 ZYNQ platform setup requires the following steps:
1. All jumpers are in the positions shown in Figure 208.
2. SW11 is in position as shown in Figure 208 (1, 2, 5 = A position)
3. The SD card included with the evaluation kit is placed in the J30 slot of the ZYNQ platform
The evaluation hardware setup is shown in Figure 209.
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Figure 208. Xilinx ZC706 ZYNQ Evaluation Board with Jumper Settings and Switch Position Configured to Work with ADRV9001 Evaluation Platform
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ETHERNET
CONNECTION
PC RUNNING T RANS CE IVER
EVALUATION SOFTWARE 50Ω
TERMINATION
SD CARD F RO M
ADRV9001 E VALUATION KIT
SWITCHING
POWER SUPPLY
(12V DC)
POWER
SWITCH
J501
Tx1
Tx2 Rx2A
Rx1A
EXTERNAL
LO 1
SIGNAL GENERATOR
Rx2B
Rx1B
SIGNAL GENERATOR
SIGNALANALYZER
EXTERNAL
LO 2
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Figure 209. ADRV9001 Evaluation Card and ZYNQ ZC706 Evaluation Platform with Connections Required for Testing
The ADRV9001 evaluation system utilizes a Linux operating system. Linux requires time to boot up as well as soft shut down before
hardware power off. The user is expected to use the software power off feature or press the SW9 button on the ZYNQ ZC706 evaluation
platform before physically switching power off using SW1. If this advice is not followed, the file system on the SD card can get corrupted
and the ADRV9001 evaluation system might stop operating.
To set up the evaluation board for testing, follow steps listed below:
1. Connect the ADRV9001 evaluation card and the ZYNQ ZC706 evaluation platform together as shown in Figure 210. Use the LPC
FMC connector (J5). Take care to be sure the connectors are properly aligned.
2. Make sure that all jumpers on the ZYNQ ZC706 evaluation platform as well as the SW11 position (1, 2, 5 = “A” position) match
settings shown in Figure 209.
3. Insert the SD card that came with the ADRV9001 evaluation kit into ZYNQ ZC706 evaluation platform SD card slot (J30).
4. On the ADRV9001 evaluation card, provide a device clock (frequency must match the setting selected in the TES), at a +13dBm
power level to J501 connector. (This signal drives the reference clock into the ADCLK944 clock distribution chip on the board – the
Q1/Q1_N pins of ADCLK944 generates the DEV_CLK for the ADRV9002 and REF_CLK for the Xilinx FPGA on the ZYNQ
platform).
a. It should be noted that quality of clock source used to generate DEV_CLK will directly impact overall system performance.
User needs to ensure that high quality, stable and low phase noise clock source is used here.
5. Connect a 12V, 5A power supply to the ZYNQ evaluation platform at the J22 header.
6. Connect the ZYNQ evaluation platform to the PC with an Ethernet cable (connect to P3). There is no driver installation required.
a. In the case when the Ethernet port is already occupied by another connection, use an USB-to-Ethernet adapter.
b. On an Ethernet connection dedicated to the ZYNQ platform, the user must manually set the following:
i. IPv4 Address to: 192.168.1.2
ii. IPv4 Subnet Mask to: 255.255.255.0
Refer to Figure 211 for more details. The user should make sure that ports listed below are not blocked by firewall software on their PC:
• 22—SSH protocol
• 55557—access to the evaluation software on ZYNQ platform
Note that the ZYNQ ZC706 evaluation platform IP address is set by default to: 192.168.1.10.
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Figure 210. IP Settings for Ethernet Port Dedicated for ZYNQ ZC706 Evaluation Platform
HARDWARE OPERATION
Start Up
1. Turn on the evaluation system by switching the ZYNQ ZC706 evaluation platform power switch (SW1) to the on position. If
hardware is connected correctly, two green LEDs (D801 and DS901) on the ADRV9001 evaluation card should be on.
The ZYNQ ZC706 evaluation platform uses a Linux operating system. It takes approximately 30 seconds before the system is ready
for operation and can accept commands from PC software. Boot status can be observed on ZYNQ ZC706 evaluation platform GPIO
LEDs (L, C, R, O). The correct sequence should follow the description below:
2. After SW1 is turned on, all 4 LEDs are ON for approximately 15 seconds. During this time the image is copied from the SD card
into FPGA memory.
3. Next, LEDs should start flashing (moving single ON light) which indicates that the Linux operating system is booting up. That
should take another 15 seconds.
4. When LEDs stop flashing, the system is ready for normal operation and awaits connection with the PC over Ethernet (which should
be established using TES).
Shutdown
When shutdown is executed using the TES, the Linux operating system starts the power-down procedure. It takes a few seconds to finish.
All four LEDs blinking together indicates that the user can safely power off the system using SW1 on the ZYNQ ZC706 evaluation
platform. Power off must be executed using TES software or the user must power down ZYNQ ZC706 evaluation platform using SW9
push button (Figure 208) before the user powers off the evaluation system by switching SW1 to off position.
Correct shutdown should be performed by executing one of these options:
• In the TES, select File and then select Shutdown Zynq Platform.
• On the ZYNQ platform, press the SW9 push button.
After a few seconds, when all four GPIO LEDs on the ZYNQ platform blink together, the user can safely power off the system using SW1
on the ZYNQ platform.
Other Considerations
• The reference clock signal (in range from 10 MHz to 1000MHz, CW tone, +13 dBm maximum) should be connected to J501.
• It should be noted that quality of clock source used to generate DEV_CLK directly impacts overall system performance. User needs
to ensure that high quality, stable and low phase noise clock source is used here.
• For receiver testing on the ADRV9001 evaluation card, use a clean signal generator with low phase noise to provide an input signal
to the selected receiver RF input. Use a shielded RG-58, 50 Ω coaxial cable (1 m or shorter) to connect the signal generator.
• To set the input level near the Rx receiver’s full scale, the generator level (for a single tone signal) should be set to approximately -
15 dBm. This level depends on the input frequency and the gain settings through the path.
• Note that there should be no input signal applied to the receiver input when performing an init calibration.
• For transmitter testing, connect a spectrum analyzer to either Tx output on the ADRV9001 evaluation card. Use a shielded RG-58,
50 Ω coaxial cable (1m or shorter) to connect the spectrum analyzer.
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• Both transmitter outputs should be terminated, either into spectrum analyzers or into 50 Ω if unused because the initial calibrations
run on both channels and can take a long time to complete if a Tx channel is not correctly terminated.
TRANSCEIVER EVALUATION SOFTWARE (TES)
Installation and Configuration
Customers should contact an ADI representative to obtain access to TES. After the initial software download, copy the software to the
target system and unzip the files (if not already unzipped). The downloaded zip container should have an executable file that installs the
SDK and then the evaluation software.
Administrator privileges are not demanded by TES installer by default. However, if user intends to install TES to a folder that requires
administrative privileges, then installation process needs to run with administrator privileges.
After running an executable file, a standard installation process follows. Figure 211 shows the recommended configuration. Microsoft
.NET Framework 4.5 or newer is necessary for TES to operate. During installation process TES will look for Microsoft .NET Framework
and if not available on PC it will try to download it from Microsoft server. When Microsoft .NET Framework installation is selected,
installer will check and inform the operator if newer version is already installed. If so, it will skip .NET Framework installation.
24159-303
Figure 211. Software Installation Components
During installation process TES will ask user for Destination Folder where files should be installed, Figure 211. It is recommended to stay
with the default location C:\Program Files (x86)\Analog Devices\ADRV9002 Transceiver Evaluation Software If this is not possible,
TES can be installed into any other location that user have write access to it. The last step of the installation process is to select shortcut
configuration.
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Figure 212. Software Installation Directory
Starting the Transceiver Evaluation Software
User can start the TES by clicking on Start -> ADRV9001 Transceiver Evaluation Software. Figure 213 shows the opening page of the
TES after it is activated.
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Figure 213. Main Interface of Transceiver Evaluation Software Bridge
When evaluation hardware is connected to a PC and the user wants to start using the complete evaluation system, TES will establish a
connection with the Xilinx ZYNQ system via Ethernet connection after clicking the Connect button. When proper connection is
established, the user can configure an evaluation hardware. After selecting Connection tab, top part of that window shows the TCP IP
address (default 192.168.1.10) and Port Number (default 55557), where bottom part of the window displays information about
connected hardware and revisions of different software setup blocks. Please contact the ADI Applications Engineering team if the
ADRV9001 Evaluation System needs to operate over a remote connection and a different IP address for the Xilinx ZYNQ platform is
desired.
Figure 214 shows an example of correct connection between a PC and a Xilinx ZYNQ system with an ADRV9001 daughter card
connected to it. In this window user can check used hardware version as well as all software components versions used by the system in
current TES revision.
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Figure 214. Setup Revision Information
Configuring the Device
Contained within the Device Configuration tab are setup options for the device. In this page the user can select the following:
• Product:
• Currently only ADRV9002 is supported
• System
• TDD, FDD, TDM_FDD are supported
• Under TDD
• DMR setup is supported
• Analog FM setup is supported
• LTE setup is supported
• Configuration 1 and Configuration 3 setup is supported
• Under FDD
• Analog FM setup is supported
• LTE setup is supported
• Configuration 2 setup is supported
• Under TDM_FDD
• Tetra is supported
• Signal type, this depends on the selected system and setup
• RX supports I/Q and frequency deviation types
• TX supports I/Q, I/Q FM/FSK, Direct FM/FSK types
• Frequency Deviation
• This option is available only for TX FM type setups.
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Figure 215. Device Configuration Tab
In the Board Configuration tab, there are settings for transmitter External Loopback. This is typically used for DPD type applications.
The user can either enable and disable the external loopback after power amplifier. If it is enabled, the user should enter the expected
loopback peak power in the Peak Power entry. Default peak power is −18 dBm. These are associated with RX1/2B ports.
The external loopback path delay can be measured using API, sending a low level wideband signal in the datapath for delay
measurement. This action disrupts transmit signal in the air. User should do this in a test environment and before the power amplifier is
transmitting real data. The user can use the ExternalPathDelay_Calibrate() and ExternalPathDelay_Get() to retrieve the external
loopback path delay in ns.
POWER
AMPLIFIER
–18dBm ±5dB
Tx1 ORx1
COUPLER
ATTENUATOR
–X dB
Rx1A
24159-308
Figure 216. Receiver/Observation Receiver Loopback Diagram
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Figure 217. Board Configuration Tab
Initialization
The Initialization tab (see Figure 218 and Figure 219) provides access to the settings that determine device startup configuration. This
page allows the user to:
• Set the device clock.
• Set the device clock frequency.
• Set the divisor value applied to the frequency at DEV_CLK_OUT.
• Enable/disable the DEV_CLK_OUT signal (presently, only enable is available).
• Select the clock PLL type to be either high performance or low power (Note that LP PLL supports only certain sampling rates).
• Select the ARM clock divisor value from 1, 2, and 4. Lower ARM clock rate saves power.
• Configure the LO
• Set PLL Retuning to allow or disallow PLL retuning when switching between Tx and Rx
• When Tx and Rx are using the same LO, but different frequency, when switching between Tx and Rx, PLL needs to be
retuned to lock. If Tx and Rx are using different LOs, there is no need to do PLL retuning.
• Set carrier frequency
• Intermediate frequency is supported for RX. Recommended range from 490KHz to 20MHz.
• Set Rx1/Rx2/Tx1/Tx2 carrier source (internal or external, options vary depending of selected setup).
• If external LO is utilized then
• Set the divisor value
• TES informs the user about the external LO frequency that must be provided to the ADRV9002 transceiver at the External
LO input.
• If Internal LO is used, user has the option to select Best Phase Noise and Best Power Saving for their application. Note only
Sub-1 G frequencies are supported for Best Phase Noise option.
• Select channel control mode (hardware enable signals or API command).
• Select HIGH, MED, or LOW receiver ADC rate.
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• Select active Rx ADC from high performance or low power types
• Select Rx frequency offset correction
• Select DAC, 3 dB boost mode
• Select Tx frequency offset correction
• Enable or disable DPD
• Select DPD tap polynomial terms
• A default configuration is provided
• The user has the freedom to configure individual tabs
• Enable/disable Rx and Tx initialization calibrations
24159-310
Figure 218. Device Initialization Tab-1
24159-311
Figure 219. Initialization Tab-2
Receiver Gain Control
The receiver Gain Control tab (Figure 220) allows user to configure per channel, receiver gain control mode. Configuration selected in
that tab is then applied to the ADRV9001 during initialization. During runtime user can change interface gain as well as if manual mode
is enabled Rx gain.
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Interface Gain provides ability to select MSBs or LSBs 16 bits from the data bus. This operation can be interpreted as a signal gain. In
TDD operation, the user has the option to update the interface gain Now or in the Next Frame. For more details, see the Digital Gain
Control and Interface Gain (Slicer) section.
By selecting the Manual radio button in Gain Control Mode, the user can select initial gain value. Receiver gain can be changed
dynamically during receiver capture operation.
By selecting the Automatic radio button in Gain Control Mode, the user can configure basic ADRV9001 internal AGC parameters. The
AGC becomes operational and automatically adjusts the receiver gain level when the ADRV9001 starts to receive data in the Receive tab.
See the Receiver Gain Control sectin for more information about AGC operation.
The user also has the ability to select Correction or Compensation for Gain Compensation operation.
• Compensation: the process of compensating for the analog attenuation in the device (prior to the ADC) with a corresponding
amount of digital gain before the digital signal is sent to the user. Gain compensation uses the digital gain to effectively undo analog
gain so from receiver data recipient signal stays constant. The digital gain is effectively compensating for the analog attenuation.
• Correction: the process of correction uses digital gain to make the gain steps more accurate. This is to ensure receiver gain steps are
accurate.
Filters
ADRV9001 evaluation software allows users to specify their own custom programmable filter for the receiver. This filter is up to 128 taps. The
custom filter has to be in the format of csv or txt file and coefficients need to be 24-bit signed integers.
GPIO Configuration
Receiver Gain Control
DGPIOs on the evaluation board from DGPIO_0 to DGPIO_11 can be used for feedback signals as well as setting gain index for receiver
gain control (see Figure 221).
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Figure 220. Rx Gain Control Tab
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Figure 221. GPIO Configuration
For more detailed information refer to Rx Gain Control section of this document.
Tx Attenuation Control
User can utilize DGPIO pins for TX attenuation control. User can assign DGPIO pins to attenuation increment and decrement. The step
size can be specified in the “Attenuation Control” tab. Default step size is set to 0.05 dB.
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Figure 222. Attenuation Control (Tx)
Once the pins have been assigned, user can go to Transmit tab and start normal playback. User can then adjust Tx attenuation level using
the up-down arrows and this will adjust the Tx attenuation value by the step size specified before.
Rx and Tx Overview
The “Rx Overview” (Figure 223) and “Tx Overview” (Figure 224) tabs aim to provide more detail on ADRV9001 selected mode of
operation using “Device Configuration” tab (Figure 215). The Rx and Tx datapath overview diagrams are provided in each tab. These
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tabs provide user with read back of ADC/DAC sampling frequencies, analog filtering configuration, datapath sampling rate, data port
format, mode of operation and sampling rate.
In “Rx Overview” tab (Figure 223) user can also read back IF frequency and observe pFIR channel filtering characteristics and their
passband flatness. Quick zooming capability allows zooming of the passband response using the mouse cursor as well as restoring to the
full-scale plot. The TES also provides capability to export the data plotted on the graphs to an external file. This is done by right-clicking
on the graph area and selecting option “Export Data to File”. Data can then be saved to file for later analyses.
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Figure 223. Rx Overview Tab
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Figure 224. Tx Overview Tab
Other Functionalities
Under File menu there are:
• Save Session and Load Session options which allow save and restore TES configuration parameters,
• Generate Profile File provides option to create JSON type profile configuration file.
• Force Update Platform provides option to forcibly clean up the resources in the SD card in case of error
• Shut Down Platform which allows to safely power down Xilinx ZYNQ system,
• Exit which exits TES software.
In case of some erroneous operation, TES is capable to capture its state. This functionality is provided by means of Log File functionality
that allows to capture steps that lead to error operation. File created using Log File function can be sent back to the ADI support team for
further debug.
Programming the Evaluation System
After all tabs are configured, the user must press the Program button. This starts programming and initialization of an evaluation
hardware. The TES sends a series of API commands that are executed by a dedicated Linux application that runs on the Xilinx ZYNQ
platform.
The user will see a progress bar at the bottom of the window. When programming has completed the system is ready to operate.
TRANSMITTER OPERATION
Selecting the Transmit tab opens a page as shown in Figure 225. The upper plot displays the FFT of the digital data and the lower plot
shows its time domain waveform. When multiple Tx outputs are enabled, the user can select desired data to be displayed in the Spectrum
plot using the checkboxes below the plot.
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Once the Transmit tab is open, the user can:
• Check the RF Tx Carrier frequency in MHz,
• Change Tx attenuation level in 0.05dB steps
• Transmit content of selected file. Some example files are supplied with TES. Assuming default TES installation process, example files
are located in C:\Program Files (x86)\Analog Devices\ADRV9002 Transceiver Evaluation Software\Example directory.
• Transmit a single tone, two tones and zeros. User has the ability to adjust the digital power of the single/dual tone signal as well as
their frequency offsets
• Have a frequency offset correction option. This allows user to change frequency on the air without re-programming the chip.
Pressing the play symbol moves the ADRV9001 to the transmit state and starts a process where selected Data Files for the “Tx1” and
“Tx2” are sent to the ADRV9001. The data is then stored on the Xilinx ZYNQ motherboard RAM and the RAM pointer loops through
the data continuously until the stop button is pressed.
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Figure 225. Transmit Data Tab
Transmit Data File Format
Transmit data should be saved in file with extension of txt or csv. The data samples should be either complex (real and imaginary) or real
only. Data samples should be Q1.15 fixed point integers (Note in TX Direct Modulation mode, the data sample should be Q4.12 fixed
point integers). Data samples should follow the following format:
If the data is only real, imaginary column should be removed, with only one column of real samples.
For example in the case of DMR FM/FSK Direct Modulation, only real data samples are used, in which case data will have only one
column.
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The length of TX transmit data should be multiple of 64. data file will be played continuously, therefore the data should be phase
continuous.
Real | Imaginary
----------|-----------
I1 | Q1
I2 | Q2
I3 | Q3
I4 | Q4
. | .
. | .
. | .
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RECEIVER OPERATION
The Receive tab opens a window as shown in Figure 226. The upper plot displays the FFT of the received input data and the lower plot
shows its time domain waveform. When multiple Rx inputs are enabled, the user can select the desired data to be displayed in the
Spectrum plot using the checkboxes below the plot.
In TDD operation, Rx data is displayed only when Rx enabled is high. It will not display data gap between TDD time slots.
Once the Receive tab is open, the user can:
• Check the RF Rx Carrier frequency in MHz,
• Change capture length in number of samples,
• Change Rx gain level (gain table index),
• Change Rx interface gain (in 4 steps),
• Enable/disable Baseband DC Rejection tracking calibration
• Change frequency offset in Hz
• Read back main parameters measured in received signal such as fundamental frequency, its amplitude and DC offset,
• Plot and save received data by clicking on floppy disk icon in bottom left corner.
• Save Rx captured data (specified in Capture Length window) in form of *.csv file.
Pressing the play symbols enables the selected receivers and displays received data continuously until the “stop” button is pressed.
Frequency Deviation
If RX frequency deviation is enabled in the configuration step, RX input signal will be demodulated. For example if a continuous wave of
900.003 MHz is sent to the RX port with LO of 900 MHz, which means in baseband there is a tone of 3 kHz offset from LO, on the RX
tab it is expected to see a constant of 3000 in the time domain plot.
Captured Data Format
RX captured data can be saved using the save button next to the play button. The data is saved in csv format. Each column corresponds
to one channel. Data samples follow 1Q15 fixed point format, and they are interleaved. Shown as follows:
Channel 1 | Channel 2
----------|-----------
I1 | I1
Q1 | Q1
I2 | I2
Q2 | Q2
. | .
. | .
. | .
In the case of RX frequency deviation, only I samples are shown, all Q samples are 0.
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Figure 226. Receive Data Tab
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IronPython Scripting
The IronPython editor is under view and allows the user to use IronPython to write a unique sequence of events and then execute them
using the ADRV9001 evaluation system.
For the IronPython scripting tab to operate, the user must download the Iron Python 2.7 environment. The latest version can be
downloaded from the Iron Python website. After Iron Python is installed, the user needs to tell TES its installation library path using
IronPython, then select File and select Set IronPython path. For the default Iron Python installation, this path is set to C:\Program
Files (x86)\IronPython 2.7\Lib.
Figure 227 shows the IronPython tab after executing the File > New function in the IronPython Script tab. The top portion of the
window contains IronPython script commands whereas the bottom portion of the window displays the script output.
To use this tab, take the following steps:
1. Scroll to the bottom of the file where there is text that states #### YOUR CODE GOES HERE ####
2. On a new line below this, type exactly Adrv9001 followed by the dot character (“.”).
3. The editor suggests a number of options. For example, type tx followed by the dot character.
4. The editor suggests a number of options. Type TxAtten and view the available Tx Attenuation related methods.
5. After selecting TxAttenSet, modify the TxAttenSet parameters accordingly.
6. Go to IronPython, select Build and then select Run. This function executes Iron Python script open in currently active script tab
using ADRV9001 evaluation hardware. Script output is displayed in bottom side of the Iron Python script tab.
For this example, the Tx attenuation for the selected channel changes.
Figure 227. IronPython Scripting Window
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TIME DIVISION DUPLEXING (TDD)
ADRV9001 supports automatic TDD operation. User can send and receive TDD framed data by configuring this tab. This of course
depends on how system and setup is selected described in the previous sections. ADRV9001 comes with predefined timing
configurations by default. However user can configure the timing as needed.
In the TDD tab, user can configure the following:
• Frame and Sequences
• User can specify the duration of a frame
• User can select from sequencing of frames
• User can specify the number of frames in a sequence.
• Channel Enable Mode
• Automated TDD state machine, this mode allows GUI to transmit and receive TDD framed data
• Automated TDD state machine should be used for TDD evaluation.
• Manual SPI/PIN mode, these modes transmit and receive data continuously.
• RX/TX enables
• User can enable/disable receiver/transmitter channel
• Tollgate Timing Control
• By default, Autopopulate Tollgate is selected
• Tollgate is a term used to indicate in the FPGA when transmitting (Tx) and capturing (Rx) start and end in time
• User can use custom tollgate timing by selecting Customize Tollgate, however as of v7.0, the user is recommended to choose
the autopopulate option
• Frame timing
• A predefined timing is generated by the GUI based on the profile selected
• User can modify the timing by entering Primary Assert/Deassert, Secondary Assert/Deassert
• Assert/Deassert entries are frame locations, they are not durations, for example if RX1 primary assert is 0 and primary deassert
is 10000 μs, this means within the specified frame the RX1 enable is on from 0 to 10000 μs and off for the rest of the frame.
• In Figure 228, it shows visually what primary/secondary assert/deassert mean. Blue and red indicates TX and RX subframe
data.
PRIMARY DEASSERT TIME
PRIMARY ASSERT TIME
PRIMARY DEASSERT TIME
PRIMARY ASSERT TIME
SECONDARY DEASSERT TIME
SECONDARY DEASSERT TIME
SECONDARY DEASSERT TIME
SECONDARY ASSERT TIME
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Figure 228. TDD Frame Timing Illustration
Note: as of v0.7.0, user should use predefined values for TDD configurations, ue of custom values may cause exception.
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Figure 229. TDD Configuration Tab
TRACKING CALIBRATIONS
Tracking calibration algorithms can be enabled/disabled in the tracking cal tab. Certain algorithms can only be enabled in certain
profiles. For example RX harmonic distortion can only be enabled if it is configured in DMR, Analog FM, and Tetra profiles. It grays out
and is disabled in LTE and custom profiles.
The user can enable and disable an individual tracking algorithm to observe its effect while transmitting and receiving a signal.
For more detailed information , see the Transmitter/Receiver/Observation Receiver Signal Chain Calibrations section.
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Figure 230. Tracking Calibration Tab
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DIGITAL PRE-DISTORTION
For more detailed information on DPD, see the Digital Predistortion section for more details.
TDD ENABLEMENT DELAYS
For more detailed information on TDD enablement delays, see the Timing Parameters Control section for more details.
AUXILIARY DAC/ADC
ADRV9001 evaluation software allows user for setting Auxiliary ADC/DAC for different control or monitoring purposes. User can go to
Auxiliary tab and enable Aux DAC/ADC here. For Aux DACs, user needs to specify a DAC code, valued from 0 ~ 4095. This effectively
sets the voltage level for that Aux DAC pin. For Aux ADCs, user can press Capture Again to observe the one time voltage value on the
Aux DAC pin.
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Figure 231. Auxiliary DACs and ADCs
RADIO STATE
Once board is connected, user can view/set radio state. This is under View->Radio State. Certain operations in the GUI can set radio to
certain states. User should be aware in what state the radio is operating on and control the GUI accordingly. User can also set the radio to
certain state from this window.
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Figure 232. Radio State Window
POWER MONITORING
The ADRV9001 evaluation software allows user to monitor power usage of the system. On top there is a button Power Monitoring,
which shows detailed voltage, current and power status of each power domain. Below is a screenshot of the power monitor window.
Note the VDDA_1P0 power domain is currently not supported by ADRV9002 and its readback should be ignored.
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Figure 233. Power Monitoring Window
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POWER SAVINGS AND MONITOR MODE
User can specify certain power saving mode in this tab. We divide power saving modes to two categories. System Power Savings and
Channel Power Savings. System Power Savings include CLKPLL, LDO and ARM power down. These can be controlled via DGPIO pins.
Channel Power Savings include RF PLL and LDO power down. These can be controlled via DGPIO pins, as well as using Tx/Rx enables.
Monitor mode can be enabled if Monitor Mode Wakeup Pin is set. Monitor mode window can be brought up from View->Monitor
Mode. If Monitor Mode Wakeup Pin is unassigned, then monitor mode is not enabled.
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Figure 234. Monitor Mode Window
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Figure 235. Power Savings and Monitor Mode
LOG FILE
On top of the GUI, there is a button Log File, which shows logging information of the system. If the PC is connected to the evaluation
platform, log file will show the version numbers for different component of the system, including firmware, FPGA, API etc. If errors
occur, for example programming the chip fails, log file will provide certain debugging information on what is failing.
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Figure 236. Log File Window
USING OF MATLAB AND PYTHON
User can use Matlab and Python to initialize the system. First connect PC to the part by clicking on Connect button. Then configure the
system to the desired state. Then program. After program is successful, in the GUI click Sample Code-> Matlab / Python/C99 to
generate Matlab, Python, and C initialization code. User can then execute the generate Matlab Python or C code to bring the part to the
same desired state as GUI did. Note before executing the generated code user should Disconnect the board.
EVALUATION SYSTEM TROUBLESHOOTING
The following is a quick help guide describing what to do if the system is not operational. This guide assumes that the user followed
instructions and assembled his setup according to hardware configuration described in this document.
No LED Activity
1. Check if the board is properly powered. There should be 12V present at the J22 input, and after powering the ZYNQ platform on
(SW1 turned on) the following should be true:
a. Fan on the ZYNQ platform is activated. Ensure that fan cable is reconnected to ADRV9001 evaluation platform fan header
P702.
b. A number of green LEDs on the ZYNQ platform near SW1 are ON with no red LEDs active on the ZYNQ platform
c. ZYNQ GPIO LEDs follow the sequence described in the Hardware Operation section.
d. Two green LEDs (D801 and D901) on the ADRV9001 evaluation card should be ON.
2. If the LED sequence does not follow the described one, check jumper settings and SW11 positions on the ZYNQ platform. If
these are correct, check if the SD card is correct and properly inserted in the J30 socket. The user should use the SD card
supplied with the evaluation kit.
3. If there is still a problem and the user is certain that the ZYNQ platform is operational, contact an ADI representative for help.
LED Active but TES Reports That Hardware is Not Connected
1. Check if the Ethernet cable is properly connected between the PC used to run TES and the ZYNQ platform. LEDs on the ZYNQ
platform next to the Ethernet socket should flash when connection is active.
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2. If the cable is properly connected, then check if Windows OS is able to communicate over the Ethernet port with the ZYNQ
platform. Check if the IP number and open ports for the Ethernet connection used to communicate with the ZYNQ platform follow
advice described in the Hardware Operation section.
a. Run cmd.exe and then type: ping 192.168.1.10. The user should be able to see a reply from the ZYNQ platform. If no reply is
received, connection with the ZYNQ platform needs to be re-examined.
b. If connection with the ZYNQ platform is established but TTES still reports that hardware is not available, ensure that ports
number 22 (SSH) and 55557 (Evaluation Software) are not blocked by firewall software on the Ethernet connection used to
communicate with the ZYNQ platform. Both ports are required to be open for normal operation.
3. Check for physical damage to the EVB.
a. Look for ferrite bead E803 located on the TOP side of PCB, next to mounting hole. There is a possibility that during transit or
when in use nut used to keep PCB stand in place damaged E803. Ensure that E803 is in place with good connection. If E803 got
broken, replace it with BLM41PG600SN1L from Murata or similar.
Orange LED Blinks Constantly
1. The ZYNQ ZC706 generated power domain for IOs that control ADRV9001 over FMC interface. That power domain is called
VADJ. For proper operation voltage on that power domain should not exceed 1.89V. The SD card provided together with an
evaluation card ensures that VADJ is properly set.
On an Evaluation Card, there is an orange LED installed close to the FMC connector. Role of this LED is to indicate if VADJ voltage
exceeded 2.0V level. If that was the case this LED will be ON
a. If LED is ON when EVB system is powered up, this indicates that VADJ exceeded 2.0V and there is a possibility that pins that
connects ADRV9002 to the FPGA IOs over FMC connector were exposed to voltage higher than 2.0V. This is an abnormal
operation that might decrease life time of ADRV9002 or in worst case scenario damage the IC.
2. Chip might still operate correctly but user should understand that VADJ exceeded recommended level. The only way to remove
uncertainty here is to change ADRV9002 on an evaluation board to the new one.
Init Calibration Fail
User may experience program failure due to init calibration. This is usually caused by Rx input is connected to the signal generator and
RF output is ON. This causes ADRV9002 to interfere with its own internal Rx calibration. User should turn off RF signal during
programming.
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HAL INTEGRATION
TBD
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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UG24159-7/20(PrA)
