Intel®Wireless Flash Memory
(W30 SCSP)
128WQ Family
Datasheet
This versatile and compact Stacked Chip Scale Package (SCSP) solution from Intel is created by
combining the Intel®Wireless Flash Memory (W30) device with low-power PSRAM. Ideal for
high-performance, low-power, board-constrained memory applications, the Intel®Wireless
Flash Memory (W30 SCSP) family retains all the features of the Intel®Wireless Flash Memory
(W30) discrete device, such as a flexible multi-partition architecture that provides dual-
operation Read-While-Write/Read-While-Erase (RWW/RWE) capability and high performance
asynchronous/synchronous burst reads. Device upgrades and migrations are easy with a
common package footprint and signal ballout for all SCSP combinations. Manufactured on
Intel®0.13 micron ETOX™ VIII process technology, this device provides the highest levels of
quality and reliability.
■Flash Architecture
— Flexible, Multiple-Partition, Dual-Operation:
Read-While-Write / Read-While-Erase
— 32 Partitions, 4 Mbits each
—31 Main Partitions, 8 Main Blocks each
—1 Parameter Partition, 8 Parameter + 7
Main Blocks
—32-Kword Main Blocks, 4-Kword
Parameter Blocks
— Top or Bottom Parameter - single Flash die
— Dual Parameter - dual Flash die
■Flash Performance
— 65 ns Initial Access Speed
— 25 ns Async 4-Word Page-Mode Reads
— 20 ns Sync Burst-Read Speed
— 4-, 8-, 16-, Continuous-Word Burst Lengths
— Burst-/ Page-Mode Reads in all Blocks and
across all partition boundaries
— Burst Suspend
— Programmable WAIT Configuration
— Enhanced Factory Programming Mode:
3.1µs/Word
— Flash Protection Register
—64 Unique Device Identifier Bits
—64 User-Programmable OTP Bits
■Flash Automation Suspend Operations
— Erase Suspend to Program or Read
— Program Suspend to Read
— 5/9 µs (typ) Program/Erase Suspend Latency
■Flash Data Protection
— Absolute Protection with VPP and WP#
— Individual Dynamic zero-Latency Block
Locking
— Individual Block Lock-Down
— Erase/Program Lockout during Power
Transitions
■Flash Software
—Intel
®Flash Data Integrator (FDI) Optimized
— Common Flash Interface (CFI)
■SCSP Architecture
—Flash
— Flash + Flash
—Flash+PSRAM
— Flash + Flash + PSRAM
— Reduces Board Space Requirement
— Simplifies PCB Design Complexity
— Easy Migration to Future SCSP Devices
■SCSP Voltage
—1.7Vto1.95VV
CC
—2.2Vto3.3VV
CCQ (Flash only)
—2.7Vto3.1VV
CCQ (Flash + PSRAM)
■SCSP Packaging
— 0.8 mm Ball-Pitch Intel®SCSP
— Area: 8x10 mm, Height: 1.2mm and 1.4mm
— 88-Ball (8 x 10 Matrix): 80 Active Balls with
2 Support Balls at Each Corner
■PSRAM Architecture and Performance
—2.7Vto3.1VP-V
CC
— 65 ns Access Speed
— 8-Word Page Read
— 18 ns for 32 M/64 M Page Read Speed
— Low Power Mode
■Flash Quality and Reliability
— Extended Temperature: –25 °C to +85 °C
— Minimum 100K Block Erase Cycles
— 0.13 µm ETOX™ VIII Process
Order Number: 252063-005
May 2004
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
2Datasheet
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not
finalize a design with this information.
The Intel® Wireless Flash Memory (W30 SCSP) family may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2004.
*Other names and brands may be claimed as the property of others.
Datasheet 3
Contents
1.0 Introduction....................................................................................................................................7
1.1 Nomenclature .......................................................................................................................7
1.2 Conventions..........................................................................................................................7
2.0 Functional Overview .....................................................................................................................9
2.1 Block Diagram ......................................................................................................................9
2.2 Flash Memory Map and Partitioning ...................................................................................10
3.0 Package Information ...................................................................................................................12
3.1 80-Active Ball Single or Double-Die SCSP .........................................................................12
3.2 80-Active Ball Triple-Die SCSP ..........................................................................................13
4.0 Ballout and Signal Descriptions ................................................................................................14
4.1 Signal Ballout......................................................................................................................14
4.2 Signal Descriptions .............................................................................................................15
5.0 Maximum Ratings and Operating Conditions...........................................................................17
5.1 Absolute Maximum Ratings ................................................................................................17
5.2 Operating Conditions ..........................................................................................................18
5.3 Capacitance........................................................................................................................18
6.0 Electrical Specifications .............................................................................................................19
6.1 DC Characteristics..............................................................................................................19
7.0 AC Characteristics ......................................................................................................................20
7.1 Flash AC Characteristics ....................................................................................................20
7.2 PSRAM AC Characteristics ................................................................................................21
7.3 PSRAM Operations ............................................................................................................25
7.4 Power-up Sequence and Initialization ................................................................................25
7.5 Mode Register ....................................................................................................................25
7.5.1 Mode Register Setting ........................................................................... 26
7.5.2 Cautions for setting Mode Register ....................................................... 27
7.6 Low Power mode ................................................................................................................28
8.0 Device Operation .........................................................................................................................29
8.1 Bus Operations ...................................................................................................................29
8.2 Flash Command Definitions................................................................................................31
4Datasheet
9.0 Flash Read Operations ............................................................................................................... 31
10.0 Flash Program Operations ......................................................................................................... 31
11.0 Flash Erase Operations .............................................................................................................. 32
12.0 Flash Security Modes.................................................................................................................. 32
13.0 Flash Read Configuration Register ........................................................................................... 32
14.0 Flash Power Consumption ......................................................................................................... 32
Appendix A Write State Machine ........................................................................................................33
Appendix B Common Flash Interface................................................................................................. 33
Appendix C Flash Flowcharts .............................................................................................................33
Appendix D Additional Information ....................................................................................................34
Appendix E Ordering Information.......................................................................................................35
Datasheet 5
Revision History
Date of
Revision Version Description
10/02 -001 Initial draft
4/4/03 -002 General language and format edit; also edited out some line items.
5/6/03 -003 Update the 64M-bit PS, ICC, ISB, and IDP current.
10/03 -004 Updated to resolve some format issues.
5/04 -005 Restructured the datasheet according to the new layout.
6Datasheet
Datasheet 7
1.0 Introduction
This document contains information pertaining to the Stacked Chip Scale Package (SCSP)
products included in the Intel®Wireless Flash Memory (W30 SCSP) family. The intent of this
document is to provide information where the SCSP family differs from the Intel®Wireless Flash
Memory (W30) discrete device.
Refer to the latest revision 1.8 Volt Intel®Wireless Flash Memory with 3-Volt I/O datasheet (order
number 290702) for flash product details not included in this document.
1.1 Nomenclature
0x Hexadecimal prefix
0b Binary prefix
Byte 8 bits
CUI Command User Interface
DU Do Not Use
ETOX EPROM Tunnel Oxide
k (noun) 1 thousand
Kb 1024 bits
KB 1024 bytes
Kword 1024 words
M (noun) 1 million
Mb 1,048,576 bits
MB 1,048,576 bytes
OTP One Time Programmable
PLR Protection Lock Register
PR Protection Register
PRD Protection Register Data
RCR Read Configuration Register
RFU Reserved for Future Use
SCSP Stacked Chip Scale Package
SR Status Register
SRD Status Register Data
Word 16 bits
1.2 Conventions
Group Membership Brackets: Square brackets will be used to designate group membership or to
define a group of signals with a similar function, such as A[21:1] and SR[4,1], for
example.
VCC vs. VCC:When referring to a signal or package-connection name, the notation used is VCC,
etc. When referring to a timing or electrical level, the notation used is subscripted such as
VCC,etc.
Device: This term is used interchangeably throughout this document to denote either a particular
die, or the combination of the four die.
8Datasheet
CE#[2:1], OE#[2:1]: This is the method used to refer to more than one chip-enable or output
enable at the same time. When each is referred to individually, the reference will be CE#1
and OE#1 (for die #1), and CE#2 and OE#2 (for die #2).
VCC, P-VCC, S-VCC: When referencing flash memory signals or timings, the notation used is
VCC or VCC, respectively. When the reference is to PSRAM signals or timings, the
notation is prefixed with “P-” (e.g., P-VCC, P-VCC). When referencing SRAM signals or
timings, the notation is prefixed with “S-” (e.g., S-VCC or S-VCC).
R-OE#, R-LB#, R-UB#, R-WE#: Used to identify OE#, LB#, UB#, WE# RAM signals, and are
usually shared between 2 or more RAM die.
Datasheet 9
2.0 Functional Overview
This section provides an overview of the features and capabilities of the Intel®Wireless Flash
Memory (W30 SCSP) family.
The Intel®Wireless Flash Memory (W30 SCSP) family encompasses multiple flash memory +
PSRAM die combinations. Products range from a flash-only, single-die device to a triple-die, dual-
flash + PSRAM device. The user can choose PSRAM combined with one or two flash memory
dies, all offered in the same package footprint and signal ballout.
Table 1 summarizes the Intel®WirelessFlashMemory(W30SCSP)familyofferings
2.1 Block Diagram
Figure 1 is a block diagram showing all internal package connections for the SCSP family with
multiple dies. Refer to Table 1, “SCSP Family Matrix” on page 9 for valid combinations of flash
and PSRAM die. Unused connections on combinations with less than triple die are reserved and
should not be used.
Table 1. SCSP Family Matrix
Flash Die #1 Flash Die #2 RAM Die Package Size (mm) Notes
28F128W30B 28F128W30T 64M PSRAM 8 x 10 x 1.4 1,2,3
NOTES:
1. W30 = Intel®Wireless Flash Memory (W30), with 3-Volt I/O.
2. T/B = Top or bottom boot; B = Bottom boot (Flash Die#1); T = Top boot (Flash Die#2)
3. Super Sample Item: Super Samples are SCSP products with the highest density SCSP
combination and serves as a functional sample for all lower density SCSP products.
10 Datasheet
.
2.2 Flash Memory Map and Partitioning
Consult the latest 1.8 Volt Intel® Wireless Flash Memory with 3-Volt I/O datasheet (order number
290702) for individual flash die memory map and partitioning information.
Refer to Table 1, “SCSP Family Matrix” on page 9 for valid configurations per SCSP combination.
Table 2 and Table 3 shows the Memory Map and Partitioning information for two flash memory
die. Flash Die#1(with CE#1 as its Chip Select) is configured to bottom boot while Flash
Die#2(with CE#2 as its Chip Select) is configured to top boot.
Figure 1. Block Diagram
Flash Die #2
PSRAM Die
Flash Die #1
VCC2
P-VCC
CE#2
OE#2
R-WE#
R-UB#
R-LB#
P-MODE
VSS
VCC1
CE#1
OE#1
A[MAX:0]
P-CS#
R-OE#
A[MAX:0] D[15:0]
CLK
WP#
ADV#
RST#
WE#
VCCQ
VPP
WAIT
Datasheet 11
Table 2. 128W30B+128W30T Dual-Flash Die SCSP Memory Map and Partitioning
Flash
Die# Partitioning Block Size
(KW) Blk# Address Range
Flash die #2(Top Boot)
128M-bit
Parameter Partition One Partition 4 255-262 7F8000-7FFFFF
32 248-254 7C0000-7F7FFF
Main Partitions
One Partition 32 240-247 780000-7BFFFF
One Partition 32 232-239 740000-77FFFF
One Partition 32 224-231 700000-73FFFF
Four Partitions 32 192-223 600000-6FFFFF
Eight Partitions 32 128-191 400000-5FFFFF
Sixteen Partitions 32 0-127 000000-3FFFFF
Flash die #1(Bottom Boot)
128 Mbit
Main Partitions
Sixteen Partitions 32 135-262 400000-7FFFFF
Eight Partition 32 71-134 200000-3FFFFF
Four Partitions 32 39-70 100000-1FFFFF
One Partition 32 31-38 0C0000-0FFFFF
One Partition 32 23-30 080000-0BFFFF
One Partition 32 15-22 040000-07FFFF
Parameter Partition One Partition 32 8-14 008000-03FFFF
4 0-7 000000-007FFF
Table 3. 128W30B+64W30T Dual-Flash Die SCSP Memory Map and Partitioning
Flash
Die# Partitioning Block Size
(KW) Blk # Address Range
Flash die #2(Top Boot)
64 Mbit
Parameter Partition One Partition 4 127-134 3F8000-3FFFFF
32 120-126 3C0000-3F7FFF
Main Partitions
One Partition 32 112-119 380000-3BFFFF
One Partition 32 104-111 340000-37FFFF
One Partition 32 96-103 300000-33FFFF
Four Partitions 32 64-95 200000-2FFFFF
Eight Partition 32 0-63 000000-1FFFFF
Flash die #1(Bottom Boot)
128 Mbit
Main Partitions
Sixteen Partitions 32 135-262 400000-7FFFFF
Eight Partition 32 71-134 200000-3FFFFF
Four Partitions 32 39-70 100000-1FFFFF
One Partition 32 31-38 0C0000-0FFFFF
One Partition 32 23-30 080000-0BFFFF
One Partition 32 15-22 040000-07FFFF
Parameter Partition One Partition 32 8-14 008000-03FFFF
4 0-7 000000-007FFF
12 Datasheet
3.0 Package Information
3.1 80-Active Ball Single or Double-Die SCSP
Figure 2. 80-Active Ball Single or Double-Die SCSP Mechanical Specifications
Millimeters Inches
Dimens ions Symbol Min Nom Max Notes Min Nom Max
Package Height A 1.200 0.0472
Ball Height A1 0.200 0.0079
Package Body Thicknes s A2 0.860 0.0339
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Package Body Length D 9.900 10.000 10.100 0.3898 0.3937 0.3976
Package Body W idth E 7.900 8.000 8.100 0.3110 0.3150 0.3189
Pitch e 0.800 0.0315
Ball (Lead) Count N 88 88
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
Corner to Ball A1 Distance Along D S2 0.500 0.600 0.700 0.0197 0.0236 0.0276
Top View - Ball Down Bottom View - Ball Up
A
A2
D
E
Y
A1
Drawing not to scale.
S2
S1
A
C
B
E
D
G
F
J
H
K
L
M
e
1
2345678
b
A
C
B
E
D
G
F
J
H
K
L
M
A1 Index
Mark
123 456 78
Datasheet 13
3.2 80-Active Ball Triple-Die SCSP
Figure 3. 80-Active Ball Triple-Die SCSP Mechanical Specifications
Millimeters Inches
Dimensions Symbol Min Nom Max Notes Min Nom Max
Package Height A 1.400 0.0551
Ball Height A1 0.200 0.0079
Package Body Thickness A2 1.070 0.0421
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Package Body Length D 9.900 10.000 10.100 0.3898 0.3937 0.3976
Package Body Width E 7.900 8.000 8.100 0.3110 0.3150 0.3189
Pitch e 0.800 0.0315
Ball (Lead) Count N 88 88
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
Corner to Ball A1 Distance Along D S2 0.500 0.600 0.700 0.0197 0.0236 0.0276
Top View - Ball Down Bottom View - Ball Up
A
A2
D
E
Y
A1
Drawing not to scale.
S2
S1
A
C
B
E
D
G
F
J
H
K
L
M
e
12345678
b
A
C
B
E
D
G
F
J
H
K
L
M
A1
Ind e x
Mark 1 234 567 8
14 Datasheet
4.0 Ballout and Signal Descriptions
4.1 Signal Ballout
The Intel®Wireless Flash Memory (W30 SCSP) family is available in an 88-ball (80-active ball)
Stacked Chip Scale Package (SCSP) with a ball pitch of 0.8 mm, as shown in Figure 4.
Figure 4. 88-Ball (80-Active Ball) SCSP Package Ballout
NOTE: Solid balls are shown as ballout differences between various stacked combinations
across the Stacked-CSP Family. See Signal Descriptions for details on the electrical
connections per stacked combination.
Top View - Ball Side Down
87654321
A
B
C
D
E
F
G
H
J
K
L
M
DU
A4
DU DU DU
DUDUDU DU
A5
A3
A2 A7
A1 A6
A0
A18 A19 VSS
VSSA23
A24
A25
A17
VCC2
CLK
A21
A22 A12
A11
A13A9P-CS#
VPP,
VPEN
A20 A10 A15
WE # A8
D8 D2 D10 D5 D13 WAIT
A14 A16
CE#1 P-Mode
VSS VSS VSS
RFU
VCC1
VCC2 VCCQRFU
D0 D1
D9
D3
D4 D6
D7
D15D11
D12 D14
OE#1
OE # 2
P-VCC
S-CS2
R-WE#
R-UB#
R-LB#
R-OE#
S-VCC
S-CS1#
VCC1
WP # ADV #
RST#
CE#2
VCCQ
VSS VSSVCCQ VSS
Bottom View - Ball Side Up
87654321
A
B
C
D
E
F
G
H
J
K
L
M
DU
A4
DUDUDU
DU DU DUDU
A5
A3
A2A7
A1A6
A0
A18A19VSS
VSS A23
A24
A25
A17
VCC2
CLK
A21
A22A12
A11
A13 A9 P-CS# VPP,
VPEN
A20A10A15
WE #A8
D8D2D10D5D13WAIT
A14A16
CE#1P-Mode
VSSVSSVSS
RFU
VCC1
VCC2VCCQ RFU
D0D1
D9
D3
D4D6
D7
D15 D11
D12D14
OE#1
OE # 2
P-VCC
S-CS2
R-WE#
R-UB#
R-LB#
R-OE#
S-VCC
S-CS1#
VCC1
WP #ADV#
RST#
CE#2
VCCQ
VSSVSS VCCQVSS
Datasheet 15
4.2 Signal Descriptions
Table 4 describes the active signals used on the Intel®Wireless Flash Memory (W30 SCSP) family.
Table 4. Signal Descriptions (Sheet 1 of 2)
Symbol Type Descriptions
A[Max:0] Input
ADDRESS INPUTS for memory addresses of a SCSP device with:
•4Mbitdensity:A[Max]=A17
•8Mbitdensity:A[Max]=A18
•32 Mbit density: A[Max]=A20
•64 Mbit density: A[Max]=A21
•128 Mbit density: A[Max]=A22
D[15:0] Input/
Output
DATA INPUTS/OUTPUTS: Inputs data and commands during writing cycles, outputs data
during memory, status register, protection register and configuration code reads. These
signals float when the die or outputs are deselected. Data is internally latched during
writes.
CE#1
CE#2 Input
FLASH CHIP ENABLE: CE#-low selects the flash component. When asserted, the flash
internal control logic, input buffers, decoders, and sense amplifiers are activated. When
deasserted, the flash die is deselected, power reduces to standby levels, and data and
WAIT outputs are placed in high-Z state.
CE#1 connects to Flash Die#1 Chip Enable while CE#2 connects to Flash Die#2 Chip
Enable. CE#2 is only connected for SCSP combinations with 2 flash dies.
RST# Input
FLASH RESET: RST#-low resets flash internal circuitry and inhibits write operations. This
function may be employed to provide data protection during power transitions. After
exiting the reset state (RST# returned to logic-high), the selected flash die resumes
operation in asynchronous read-array mode.
OE#1
OE#2 Input
FLASH OUTPUT ENABLE: OE#-low activates device output through the flash data
buffers during a flash read cycle. When deasserted, the flash outputs tri-state to high-Z.
OE#1 connects to Flash Die#1 Output Enable while OE#2 connects to Flash Die#2
Output Enable. OE#2 is only connected for SCSP combinations with 2 flash dies.
WE# Input
FLASH WRITE ENABLE: WE# controls writes to the selected flash die. WE#-low allows
input to the flash CUI, array, PR/PLR, RCR, or block lock bits. Addresses and data are
latched on this signal’s rising edge.
ADV# Input
FLASH ADDRESS VALID: ADV# indicates valid address presence on address inputs of
the selected flash die. During synchronous read operations, all addresses are latched on
ADV#’s rising edge or CLK’s rising (or falling) edge, whichever occurs first.
CLK Input
FLASH CLOCK: CLK synchronizes the selected flash die to the system bus frequency in
synchronous-read configuration and increments an internal burst address generator.
During synchronous read operations, addresses are latched on ADV#’s rising edge or
CLK’s rising (or falling) edge, whichever occurs first.
CLK is only used for synchronous mode. Refer to flash product discrete datasheet for
information how to use this signal in asynchronous mode.
WAIT Output
FLASH WAIT: Wait is driven when CE# is asserted. Flash RCR[10][WP] determines the
WAIT asserted logic level.
•In synchronous array read modes, WAIT indicates invalid data when asserted and
validdatawhende-asserted.
•In synchronous non-array read modes, asynchronous page mode, and all write
modes, WAIT is asserted.
Refer to flash product discrete datasheet for more information.
16 Datasheet
WP# Input
FLASH WRITE PROTECT: Enables/disables the lock-down mechanism of the selected
flash die.
When WP# is logic low, the lock-down mechanism is enabled and blocks marked lock-
down can not be unlocked through software.
VPP Power
FLASH PROGRAM / ERASE SUPPLY: Valid Vpp voltage on this ball allow block erase
and program functions. Flash memory array contents cannot be altered when VPP<VPPLK.
Block Erase and program at invalid VPP Voltage should not be attempted.
VCC1
VCC2 Power
FLASH POWER SUPPLY: Supplies power to the flash core. VCC1 connects to Flash
Die#1 power supply while VCC2 connects to Flash Die#2 power supply.
VCC2 is only connected for SCSP combinations with 2 flash dies.
VCCQ Power OUTPUT BUFFER POWER SUPPLY: Supplies power for the input and output buffers.
VSS Power GROUND: Do not float any VSS connection.
S-CS1#
S-CS2 Input
SRAM CHIP SELECTS: Activates the SRAM internal control logic, input buffers,
decoders, and sense amplifiers. When either are deasserted (S-CS1# = VIH or S-CS2 =
VIL), the SRAM is deselected and its power reduces to standby levels.
S-CS1# and S-CS2 are only connected for SCSP combinations with SRAM die.
R-OE# Input
RAM OUTPUT ENABLE: R-OE#-low activates device output through the selected RAM
data buffers during a RAM read cycle. When deasserted, the selected RAM outputs tri-
state to high-Z.
R-OE# is only connected for SCSP combinations with 1 or more RAM die.
R-WE# Input RAM WRITE ENABLE: R-WE#-low allows writes to the selected RAM array.
R-WE# is only connected for SCSP combinations with 1 or more RAM die.
R-UB#
R-LB# Input
RAM UPPER / LOWER BYTE ENABLES: R-UB#-low enables the selected RAM high-
order bytes (D[15:8]). R-LB#-low enables the selected RAM low-order bytes (D[7:0]).
R-UB# and R-LB# are only connected for SCSP combinations with 1 or more RAM die.
S-VCC Power SRAM POWER SUPPLY: Supplies power for SRAM operations.
S-VCC is only connected for SCSP combinations with SRAM die.
P-CS# Input
PSRAM CHIP SELECT: Activates the PSRAM internal control logic, input buffers,
decoders, and sense amplifiers. When deasserted, the PSRAM is deselected and its
power reduces to standby levels.
P-CS# is only connected for SCSP combinations with PSRAM die.
P-Mode Input
PSRAM REFRESH: When deasserted, it enables PSRAM Lower Power Mode with partial
array refresh or zero array refresh according to the Mode register setting.
P-Mode is only connected for SCSP combinations with PSRAM die.
P-VCC Power PSRAM POWER SUPPLY: Supplies power for PSRAM operations.
P-VCC is only connected for SCSP combinations with PSRAM die.
RFU — RESERVED for FUTURE USE: Do not drive RFU balls and leave them disconnected.
Contact Intel regarding their future use.
DU — DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.
Table 4. Signal Descriptions (Sheet 2 of 2)
Symbol Type Descriptions
Datasheet 17
5.0 Maximum Ratings and Operating Conditions
5.1 Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
NOTICE: This document contains information available at the time of its release. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet
before finalizing a design.
Table 5. Absolute Maximum Ratings
Parameter Min Max Unit Notes
Temperature under Bias Expanded –25 +85 °C
Storage Temperature –55 +125 °C
Voltage On Any Signal (except VCC1,V
CC2, VCCQ, VPP,
and P-VCC) –0.2 +3.6 V 1
VCC1 and VCC2 Voltage –0.2 +2.45 V 1
VCCQ,andP-V
CC Voltage –0.2 +3.6 V 1
VPP Voltage –0.2 +14.0 V 1,2,3
Ish Output Short Circuit Current – 100 mA 4
NOTES:
1. All Specified voltages are relative to VSS. Minimum DC voltage is –0.2 V on input/output signals, –0.2 V
on VCCX and VPP signals. During transitions, this level may overshoot to –2.0 V for periods < 20 ns,
during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns.
2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns.
3. VPP program voltage is normally VPP1. The maximum DC voltage on VPP may overshoot to +14 V for
periods < 20 ns. VPP canbeV
PP2 for 1000 erase cycles on main blocks, 2500 cycles on parameter
blocks.
4. Output shorted for no more than one second. No more than one output shorted at a time.
18 Datasheet
5.2 Operating Conditions
5.3 Capacitance
Table 6. Extended Temperature Operation
Symbol Parameter
Flash/
Flash+Flash
Flash+PSRAM/
Flash+Flash+PSRAM
Unit
Min Max Min Max
TAOperating Temperature –40 +85 –25 +85 °C
VCC Flash Supply Voltage 1.7 1.95 1.7 1.95 V
VCCQ
P-VCC
Flash I/O Voltage
PSRAM Supply Voltage 2.2 3.3 2.7 3.1 V
VPP1 Flash Program Logic Level 0.9 1.95 0.9 1.95 V
VPP2 Flash Factory Program
Voltage 11.4 12.6 11.4 12.6 V
NOTE: VPP is normally VPP1. VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks for
extended temperatures and 2500 cycles on parameter blocks at extended temperature.
NOTICE: Refer to the 1.8-Volt Intel®Wireless Flash Memory with 3-Volt I/O datasheet (order
number 290702) for flash capacitance details. For SCSP products with two flash die, flash
capacitances for each of the flash die need to be considered accordingly.
Table 7. PSRAM Capacitance
Symbol Parameter Max Unit Condition
CIN Input Capacitance 8 pF TA=25°C,f=1MHz,
VIN=0V
COUT Output Capacitance 10 pF
Datasheet 19
6.0 Electrical Specifications
6.1 DC Characteristics
PSRAM DC characteristics are shown in Table 8. Refer to the 1.8-Volt Intel® Wireless Flash
Memory with 3-Volt I/O Datasheet (order number 290702) for Flash DC Characteristics.
NOTICE: DC Characteristics of all die in a SCSP device need to be considered accordingly,
depending on the SCSP device operation.
Table 8. PSRAM DC Characteristics
Parameter Description Test Conditions Min Typ Max Unit
P-VCC Voltage Range 2.7 – 3.1 V
ICC Operating
Current at min
cycle time
Iout=0mA
32M – – 45
mA
64M – – 50
ISB1 Standby Current P-CS#>=P-VCC-0.2V, P-
Mode>=P-VCC-0.2V
32M – 90 100 µA
64M – 110 150
ISB2
Partial Array
Refresh Current
(Standby Mode 2)
P-CS#>=P-VCC-0.2V, P-
Mode<=0.2V
32M
16Mbits – 60 70
µA
8Mbits – 50 60
4Mbits – 40 50
0Mbits – 20 30
64M
16Mbits – 90 110
8Mbits – 80 100
4Mbits – 70 90
0Mbits – 60 80
Isbd Deep Power
Down
P-CS#>=P-VCC-0.2V, P-
Mode<=0.2V
32M – 20 30 µA
64M – 60 80
VOH Output High
Voltage IOH = -0.5mA 32M 0.8P-Vcc – – V
64M 0.8P-Vcc – –
VOL Output Low
Voltage IOL =1mA 32M – – 0.2P-Vcc V
64M – – 0.2P-Vcc
VIH Input High
Voltage 0.8P-Vcc – P-VCC +0.3 V
VIL Input Low
Voltage -0.3 – 0.2P-VCC V
*IIL Input Leakage
Current VIN=0V to P-Vcc –1.0 – +1.0
µA
*IOL Input/Output
Leakage Current
VI/O=0V to P-Vcc, P-CS#=VIH or R-WE#=VIH or
R-OE#=VIH –1.0 – +1.0
*V
IN: Input voltage, VI/O: Input/Output voltage
20 Datasheet
7.0 AC Characteristics
7.1 Flash AC Characteristics
Refer to the 1.8-Volt Intel® Wireless Flash Memory with 3-Volt I/O Datasheet (order number
290702) for Flash AC Characteristics details not included in Table 9 below.
Table 9. Flash AC Read Characteristics
Sym Parameter
128W30 64W30
Unit
Min Max Min Max
Asynchronous Specifications
tAVAV Read Cycle Time 65 65 ns
tAVQV Address to Output Delay 65 65 ns
tELQV CE# Low to Output Delay 65 65 ns
tVLQV ADV# Low to Output Delay 65 65 ns
Latching Specifications
tAPA Page Address Access Time 25 25 ns
Clock Specifications
tCHQV CLK to Output Delay 20 20 ns
Datasheet 21
7.2 PSRAM AC Characteristics
Table 10. PSRAM AC Characteristics—Read-Only Operations
# Symbol Parameter
32M 64M
Unit Note
Min Max Min Max
Read Cycle
R1 tRC Read Cycle Time 65 – 65 – ns
R2 tAA Address access time – 65 – 65 ns
R3 tCO P-CS# Low to Output Valid – 65 – 65 ns
R4 tOE R-OE# Low to Output Valid – 45 – 45 ns
R5 tBA R-UB#, R-LB# Low to Output Valid – 65 – 65 ns
R6 tLZ P-CS# Low to Output in Low-Z 10 – 10 – ns
R7 tOLZ R-OE# Low to Output in Low-Z 5 – 5 – ns
R8 tHZ P-CS# High to Output in High-Z – 25 – 25 ns
R9 tOHZ R-OE# High to Output in High-Z – 25 – 25 ns
R10 tOH Output Hold from Address change 5 – 5 – ns
R11 tBLZ R-UB#, R-LB# Low to Output in Low-Z 5 – 5 – ns
R12 tBHZ R-UB#,R-LB#HightoOutputinHigh-Z – 25 – 25 ns
R13 tASO Address set to R-OE# low level 0 – 0 – ns 1
R14 tOHAH R-OE# high level to address hold -5 – -5 – ns
R15 tCHAH P-CS# high level to address hold 0 – 0 – 1
R16 tBHAH R-LB#, R-UB# high level to address hold 0 – 0 – 1,2
R17 tCLOL P-CS# low level to R-OE# low level 0 10,000 0 10,000 3
R18 tOLCH R-OE# low level to P-CS# high level 45 – 45 –
R19 tCP P-CS#highlevelpulsewidth 10 – 10 –
R20 tBP R-UB#, R-LB# high level pulse width 10 – 10 –
R21 tOP R-OE# high level pulse width – 10,000 – 10,000 3
Page Mode
PR1 tPC Page Cycle Time 18 – 18 – ns 4
PR2 tPA Page Mode Address Access Time – 18 – 18 ns
NOTE:
1. When.R13>=|R15|, |R16|. The minimum of R15 and R16 are -15ns. (See Figure 5, “Conditions for Calculating R15
and R16 Minimum Values” on page 22.)
2. R16 is specified from when both R-LB# and R-UB# become high level.
3. R17and R21(MAX) are applied while P-CS# is being hold at low level.
4. See Figure 7, “AC Waveform of PSRAM Read Operations” on page 23.
22 Datasheet
Figure 5. Conditions for Calculating R15 and R16 Minimum Values
Table 11. PSRAM AC Characteristics—Write Operations
# Symbol Parameter
32M 64M
Unit Note
Min Max Min Max
W1 tWC WriteCycleTime 65 – 65 – ns
W2 tAS Address Setup Time 0 – 0 – ns
W3 tWP Write Pulse Width 50 – 50 – ns
W4 tDW DatavalidtoWriteEnd 30 – 30 – ns
W5 tAW Address valid to end of write 55 – 55 – ns
W6 tCW P-CS#toendofwrite 55 – 55 – ns
W7 tDH Data Hold time 0 – 0 – ns
W8 tWR Write Recovery 0 – 0 – ns
W9 tBW R-UB#, R-LB# Setup to end of Write 55 – 55 – ns
W10 tCP P-CS# High level pulse width 10 – 10 – ns
W11 tBP R-UB#, R-LB# High level pulse width 10 – 10 – ns
W12 tWHP R-WE#Highlevelpulsewidth 10 – 10 – ns
W13 tOHAH R-OE# High level to address hold -5 – -5 – ns
W14 tCHAH P-CS# High level to address hold 0 – 0 – ns 1
W15 tBHAH R-UB#, R-LB# High level to address hold 0 – 0 – ns 1,2
W16 tOES R-OE# High level to R-WE# set 0 10,000 0 10,000 ns 3
W17 tOEH R-WE# High level to R-OE# set 0 10,000 0 10,000 ns
NOTES:
1. When W2>=|W14|, |W15| and W10>=18ns, W14 and W15 (MIN) are -15ns. (See Figure 6, “Conditions for
Calculating R14 and R15 Minimum Values” on page 23.)
2. W15 is specified from when both R-LB# and R-UB# become high level.
3. W16 and W17(MAX) are applied while P-CS# is being hold at low level.
4. See Figure 9, “AC Waveform PSRAM Write Operation”
Address
R-UB#,R-LB#,
P-CS#
R15, R16
R13R-OE#
Datasheet 23
NOTE: In read cycle, P-Mode and R-WE# should be fixed to high level
Figure 6. Conditions for Calculating R14 and R15 Minimum Values
Figure 7. AC Waveform of PSRAM Read Operations
Address
R-UB#,R-LB#,
P-CS#
W14, W15
W2R-WE#
W10
R1
Vih
Vil
R2
Vih R 3
Vil
R8
Vih R 5
Vil
R12
Vih R 4
Vil
R9
R7
R11
R6 R10
Voh
High-Z High-Z
Vol
Data
out
Valid
Output
Address
P-CS#
R-UB#,
R-LB#
R-OE#
24 Datasheet
NOTE: In page read cycle, P-Mode and R-WE# should be fixed to high level, and R-UB#, R-LB# are low level.
NOTES:
1. During address transition, at least one of pins P-CS#, R-WE#, or both of R-UB# and R-LB# pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, P-Mode and R-OE# should be fixed to high level.
4. Write operation is done during the overlap time of a low level P-CS#, R-WE#, R-LB# and/or R-UB#.
Figure 8. AC Waveform of PSRAM 8-Word Page Read Operation
Vih
A3-A
MAX
Valid
Vil Address
Vih
A0,A1,A2
Vil 000
R2 PR1
P-CS# R3
PR2R-OE#,
R-UB#,
R-LB#
R4
R9
Voh
High-Z Qn
Vol
Data out Qn+
7
Qn+
6
001 111
R1
Figure 9. AC Waveform PSRAM Write Operation
W1
Vih
Vil
W2 W8
Vih W6
Vil
W5
Vih W9
Vil
Vih W3
Vil
Voh W4 W7
High-Z High-Z
Vol
Address
P-CS#
R-UB#,
R-LB#
R-WE#
Data I/O Valid Data In
Low-Z
Datasheet 25
7.3 PSRAM Operations
7.4 Power-up Sequence and Initialization
The PSRAM functionality and reliability are independent of the power-up slew rate of the core P-
VCC. Any power-up slew rate is possible under use conditions.
The following power up sequence and operation should be used before starting normal operation.
The PSRAM power-up sequence is represented in Figure 10. Following power application, make
P-Mode high level after fixing P-Mode to low level for the period of tVHMH. Make P-CS# high
level before making P-Mode high level. Then, P-CS# and P-Mode are fixed to high level for the
period of tMHCL.
Normal Operation is possible once the power up sequence is complete.
NOTES:
1. Make P-Mode low level when starting the power supply.
2. tVHMH is specified from when the power supply voltage reaches the prescribed minimum value (P-Vcc
(MIN))
7.5 Mode Register
The PSRAM die has an internal register that helps control the Low Power mode of the PSRAM.
This register is called the Mode register, or Mode register. The densities that can be selected for
performing refresh are 16 Mbits, 8 Mbits, 4 Mbits and 0 Mbit. The density for performing refresh
can be set with the Mode register. Once the refresh density has been set in the Mode register, these
settings are retained until they are set again, while applying the power supply. However, the Mode
register setting will become undefined if the power is turned off, so set the Mode register again
after power application.
Figure 10. Timing Waveform for Power up sequence
tVHMH
tMHCL
tCHMH
Initialization
Vcc (MIN)
Normal Operation
P-CS#
P-Mode
P-Vcc
Table 12. Initialization timing
Parameter Symbol MIN MAX Unit
Power application to P-Mode low level hold tVHMH 50 us
P-CS# high level to P-Mode high level tCHMH 0ns
Following power application, P-Mode high level
hold to P-CS# low level tMHCL 200 us
26 Datasheet
7.5.1 Mode Register Setting
Since the initial value of the Mode register at power application is undefined, be sure to set the
Mode register after initialization at power application. When setting the density of partial refresh,
data before entering the Low Power Mode is not guaranteed.(This is the same for resetup)
However, since Low Power Mode is not entered unless P-Mode=L, when partial refresh is not
used, it is not necessary to set the Mode register. Moreover, when using page read without using
partial refresh, it is not necessary to set the Mode register.
The Mode register setting mode can be entered by successively writing two specific data after two
continuous reads of the highest address. The Mode register setting is a continuous four-cycle
operation -two read cycles and two writes cycles. See Table 13 for setting Mode register command
sequence.
For the timing chart and flow chart, refer to Figure 11 and Figure 12.
AMAX-A 5, aregister programming.
Table 13. Setting Mode Register Command Sequence
Command
Sequence
1st Bus Cycle
(Read Cycle)
2nd Bus Cycle
(Read Cycle)
3rd Bus Cycle
(Write Cycle)
4th Bus Cycle
(Write Cycle)
Partial refresh
density Address Data Address Data Address Data Address Data
16 Mbits Highest
Address _Highest
Address _Highest
Address 00H Highest
Address 04H
8Mbits Highest
Address _Highest
Address _Highest
Address 00H Highest
Address 05H
4Mbits Highest
Address _Highest
Address _Highest
Address 00H Highest
Address 06H
0Mbit Highest
Address _Highest
Address _Highest
Address 00H Highest
Address 07H
Figure 11. Mode Register Update--Timing Waveform
Highest Addr ess H ighest Address Highest Address Highest Addr ess
0000H 000XH
W7
W4W7W4
W8
W3
W8
W3
Mode Register Setting
W1W1W1W1R1R1R1R1
Address
P-CS#
R-OE#
R-WE#
Data I/O
R-UB#, R-LB#
Datasheet 27
NOTE: xxH=04H, 05H, 06H or 07H
7.5.2 Cautions for setting Mode Register
Since, for the Mode register setting, the internal counter status is judged by toggling P-CS# and R-
OE#, toggle P-CS# at every cycle during entry (read cycle twice, write cycle twice), and toggle R-
OE# like P-CS# at the first and second read cycles. If incorrect addresses or data are written, or if
addressed or data are written in the incorrect order, the setting of the Mode register is not
performed correctly.
When the highest address is read consecutively three or more times, the Mode register setting
entries are not performed correctly. (Immediately after the highest address is read, the setting of the
Mode register is not performed correctly.) Perform the setting of the Mode register after power
application or after accessing other than the highest address.
Once the refresh density has been set in the Mode register, these settings are retained until they are
set again, while applying the power supply. However, the Mode register setting will become
undefined if the power is turned off, so set the Mode register again after power application.
Figure 12. Mode Register Setting Flow Chart
Data=00H
Write to Highest Address
Data=xxH
Begin Normal
Operation
Read Highest Address
by Toggling both P-CS#
and R-OE#
START
Write to Highest Address
Read Highest Address
by Toggling both P-CS#
and R-OE#
Fail
Mode Register
setting exit
No
No
No
No
No
No
28 Datasheet
7.6 Low Power mode
In addition to the regular Standby mode with a full density data hold, Low Power mode performs
partial density data refresh or zero density data refresh.
The Low Power mode allows customers to turn off sections of the PSRAM die to save refresh
current. The PSRAM die is divided into four sections allowing certain sections to be refreshed with
P-Mode tied Low.
In regular Standby mode, both P-CS# and P-Mode are high level. But in Low Power mode, P-
Mode is low level. In Low Power mode, if 0M bit is set as the density, it is necessary to perform
initialization the same way as after applying power, in order to return to normal operation from
Low Power mode. Refer to Figure 10, “Timing Waveform for Power up sequence” on page 25 for
timing charts. When the density has been to set to 16 Mbits, 8 Mbits, or 4 Mbits in Low Power
mode, it is not necessary to perform initialization to return to normal operation from Low Power
mode. For timing charts, refer to Figure 13, “Low Power mode -Entry/Exit (16/ 8/ 4/ 0 Mbits)” .
Figure 13. Low Power mode -Entry/Exit (16/ 8/ 4/ 0 Mbits)
Table 14. Low Power mode-Entry/Exit
Parameter Description Min Max Unit
tCHML Low Power mode entry, P-CS# high level to P-Mode# Low level 0 ns
tMHCL1 Low Power mode(16/8/4 Mbits hold) exit to normal operation, P-Mode High
level to P-CS# Low level 30 ns
tMHCL2 Low Power Mode(0 Mbit data hold) exit to normal operation, P-Mode High
level to P-CS# Low level 200 us
NOTES:
1. tMHCL1 is the time it takes to return to normal operation from Low Power Mode (data hold: 16 /8 /4 Mbits).
2. tMHCL2 is the time it takes to return to normal operation from Low Power Mode (0 Mbits data hold).
tMHCL1/tMHCL2
tCHML
Low Power Mode
(Partial Array Refresh/Zero Refresh)
P-Mode
P-CS#
Datasheet 29
8.0 Device Operation
8.1 Bus Operations
Bus operations for the Intel®Wireless Flash Memory (W30 SCSP) family involve the following
chip enable and output enable signals, respectively.
•CE#1 for Flash Die#1 and CE#2 for Flash Die#2
•OE#1 for Flash Die#1 and OE#2 for Flash Die#2
All other control signals are shared between the two flash die. Table 15 to Table 16 explains the bus
operations of products across this SCSP family. Refer to the W30 datasheets (order numbers
290702) for single flash die SCSP bus operations.
Table 15. Flash Die#1 + Flash Die#2 Bus Operations
Device
Mode
RST#
CE#1
OE#1
WE#
ADV
VPP
WAIT
CE#2
OE#2
D[15:0]
Notes
Flash Die#1 Enabled
Sync Array Read H L L H L X Active H X Flash
DOUT 2,3,4
All Async /
Sync Non-Array
Read
HLLHX XAsserted H X Flash
DOUT 1,3,4,5
Write H L H L X VPP1
or
VPP2
Asserted H X Flash
DIN 3,4,6
Output Disable H L H H X X Active X X Flash
High-Z 4
Standby H H X X X X High-Z X X Flash
High-Z 4
Reset L X X X X X High-Z X X Flash
High-Z 4
30 Datasheet
Flash Die#2 Enabled
Sync Array Read H H X H L X Active L L Flash
DOUT 2,3,4
All Async /
Sync Non-Array
Read
H H X H X X Asserted L L Flash
DOUT 1,3,4,5
Write H H X L X
VPP1
or
VPP2
Asserted L H Flash
DIN 3,4,6
Output Disable H X X H X X Active L H Flash
High-Z 4
Standby H X X X X X High-Z H X Flash
High-Z 4
Reset LXXXX XHigh-Z X X Flash
High-Z 4
NOTES:
1. For asynchronous read operation, both die may be simultaneously selected, but may not simultaneously drive the
memory bus. See Section 8.2, “Flash Command Definitions” on page 31 for details regarding Flash selection overlap.
2. WAIT is only active during synchronous Flash reads. WAIT is driven if CE# is asserted. Refer to the 1.8-Volt Intel®
Wireless Flash Memory with 3-Volt I/O datasheet (order number 290702) for further information regarding WAIT Signal.
3. For either Flash die, OE#1/OE#2 and WE# should never be asserted simultaneously. If done so on a particular Flash die,
OE#1/OE#2 will override WE#.
4. L means VIL while H means VIH.XcanbeV
IL or VIH for inputs, VPP1,V
PP2 or VPPLK for VPP
.
5. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].
6. Refer to W30 datasheet for valid DIN during Flash writes.
Table 16. Flash (Single Die/Dual Die) + PSRAM Bus Operations
Device
Mode
RST#
CE#X
OE#X
WE#
ADV#
VPP
WAIT
P-CS#
P-Mode
R-OE#
R-WE#
R-UB#,
R-LB#
D[15:0]
Notes
Flash Die(#1 or #2) Enabled
Sync Array
Read HLLHL X Active
PSRAM must be in High-Z
Flash
DOUT
1,2,3,
4,6
All Async/
Sync Non-
array
Read
H L L H X X Asserted Flash
DOUT
1,2,3,
4,6,7
Write H L H L L
VPP1
or
VPP2
Asserted Flash
DIN
3,4,6,
8
Output
Disable HLHHX X Active
Any PSRAM mode allowed
Flash
High-Z 6
Standby H H X X X X High-Z Flash
High-Z 6
Reset LXXXX XHigh-Z Flash
High-Z 6
Device
Mode
RST#
CE#1
OE#1
WE#
ADV
VPP
WAIT
CE#2
OE#2
D[15:0]
Notes
Datasheet 31
8.2 Flash Command Definitions
Refer to the 1.8 Volt Intel®Wireless Flash Memory Datasheet (order number 290701) for
information regarding Flash Command Definitions.
9.0 Flash Read Operations
Refer to the 1.8 Volt Intel®Wireless Flash Memory Datasheet (order number 290701) for
information regarding flash read modes and operations.
10.0 Flash Program Operations
Refer to the 1.8 Volt Intel®Wireless Flash Memory Datasheet (order number 290701) for
information regarding flash program operations.
PSRAM Enabled
Read
FlashmustbeinHigh-Z
Note 2
LHLHL
PSRAM
DOUT 1,5
Write L H H L L PSRAM
DIN 5
Output
Disable
Any flash mode allowed
LHHHX
PSRAM
High-Z 6
Standby H H X X X PSRAM
High-Z 6
Low
Power
Mode XLXXX
PSRAM
High-Z 6
NOTES:
1. For asynchronous read operation, all dies may be simultaneously selected, but may not simultaneously drive the
memory bus. For synchronous burst-mode reads, only two die (one flash and the PSRAM) may be simultaneously
selected.
2. WAIT is only valid during synchronous flash reads. Refer to the discrete datasheet for detailed Wait functionality.
3. CE#X is CE#1 for Flash Die#1, CE#2 for Flash Die#2. OE#X is OE#1 for Flash Die#1, OE#2 for Flash Die#2.
4. For either flash die, OE#X and WE# should never be asserted simultaneously. If done so on a particular flash die,
OE#X will override WE#.
5. For PSRAM, R-OE# and R-WE# should never be asserted simultaneously.
6. X can be VIL or VIH for inputs, VPP1,V
PP2 or VPPLK for VPP
.
7. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].
8. Refer to W30 datasheet for valid DIN during flash writes.
Table 16. Flash (Single Die/Dual Die) + PSRAM Bus Operations
Device
Mode
RST#
CE#X
OE#X
WE#
ADV#
VPP
WAIT
P-CS#
P-Mode
R-OE#
R-WE#
R-UB#,
R-LB#
D[15:0]
Notes
32 Datasheet
11.0 Flash Erase Operations
Refer to the 1.8 Volt Intel®Wireless Flash Memory Datasheet (order number 290701) for
information regarding flash erase operations.
12.0 Flash Security Modes
Refer to the 1.8 Volt Intel®Wireless Flash Memory Datasheet (order number 290701) for
information regarding flash security modes and operations.
13.0 Flash Read Configuration Register
Refer to the 1.8 Volt Intel®Wireless Flash Memory Datasheet (order number 290701) for
information regarding flash Read Configuration Register (RCR) functions and programming.
14.0 Flash Power Consumption
Refer to the 1.8 Volt Intel®Wireless Flash Memory Datasheet (order number 290701) for
information regarding flash power considerations and consumption.
Datasheet 33
Appendix A Write State Machine
Refer to the 1.8 Volt Intel®Wireless Flash Memory Datasheet (order number 290701) for the Write
State Machine details.
Appendix B Common Flash Interface
Refer to the 1.8 Volt Intel®Wireless Flash Memory Datasheet (order number 290701) for the
Common Flash Interface details.
Appendix C Flash Flowcharts
Refer to the 1.8 Volt Intel®Wireless Flash Memory Datasheet (order number 290701) for the flash
flowchart details.
34 Datasheet
Appendix D Additional Information
:
S
Order Number Document
290701 1.8 Volt Intel®Wireless Flash Memory (W30) Datasheet
251407 Intel®Wireless Flash Memory (W30 SCSP) Datasheet
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office.
2. For the most current information on Intel®Flash memory products, software and tools, visit our website at
http://developer.intel.com/design/flash.
Datasheet 35
Appendix E Ordering Information
E.1 Device Name Decoder
Figure 14 shows the decoder for products in this SCSP family with both flash and RAM. Figure 15
shows the decoder for products in this SCSP family with flash die only (no RAM).
Figure 14. Decoder for Flash + RAM SCSP Device Name
F 2 0 W 0 Z B Q8D 3R
Package
Pinout Indicator
Product Line Designator
Flash Density
Voltage
Product Family
RD = Stacked-CSP
38F = Stacked-CSP Intel®
Flash Memory, Flash & RAM
0=Nodie
2=64Mbit
W = Intel® Wireless Flash Memory
0=NoDie Z = 3 Volt I/O, 1.8 Volt Core
Q= Quad ballout
3 0
RAM Density
0=NoDie
1=4Mbit
2=8Mbit
4=32Mbit
0
Parameter Location
B = Bottom Parameter
T = Top Parameter
Device Details
0 = Original version of
the products:
W30 Speed = 20 ns Sync/
25ns Page/65 ns Async
Flash Process = 0.13 µm
Flash #1
Flash #2
Flash #1
Flash #2
RAM #2
RAM #1
3=128Mbit
5=64Mbit
RAM = SRAM/PSRAM
pr
od
uc
t:
36 Datasheet
Figure 15. Decoder for Flash-Only SCSP Device Name
F 2 2 W 0 Z D Q8D 4R
Package
Pinout Indicator
Product Line Designator
Flash Density
VoltageProduct Family
RD = Stacked-CSP
48F = Intel® Flash Memory, Multiple
Flash-only Die
2=64Mbit
0=NoDie
W = Intel® Wireless memory
0 = No Die
Z=1.8Vcore,3VI/O
Q = Quad Ballout
0 0 0
Parameter Location
D = Bottom Parameter
for Flash Bank#1 (CE#1),
Top Parameter for Flash
Bank#2 (CE#2)
Device Details
0 = Original version of this
product:
Flash Process = 0.13 µm
Size=8x10x1.2mm
Flash #1
Flash #2
Flash Family
Flash #4
Flash #3
Flash Family
3=128Mbit
W30 Speed = 20 ns Sync/
25ns Page/65 ns Async
pro
duc
t:
Datasheet 37
E.2 Device Name List
Table 17 shows the complete list of device names for products with double flash dies. Flash Die#1
is configured bottom parameter while Flash Die#2 is configured top parameter. See Section 2.2,
“Flash Memory Map and Partitioning” on page 10 for the flash memory map and partitioning
details of devices with double flash dies.
Table 17. Double Flash Die SCSP Device Name List
Product Device Name
128W30B+128W30T+64PSRAM RD38F3350WWZDQ1
38 Datasheet
