2003 Microchip Technology Inc. Preliminary DS40300C
PIC16F62X
Data Sheet
FLASH-Based
8-Bit CMOS Microcontroller
DS40300C - page ii Preliminary 2003 Microchip Technology Inc.
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Trademarks
The Microchip name and logo, the Microchip logo, KEELOQ,
MPLAB, PIC, PICmicro, PICSTART and PRO MATE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,
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Mode and Total Endurance are trademarks of Microchip
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Serialized Quick Turn Programming (SQTP) is a service mark
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All other trademarks mentioned herein are property of their
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© 2003, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
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and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
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Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
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There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
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Microchip is willing to work with the customer who is concerned about the integrity of their code.
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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2003 Microchip Technology Inc. Preliminary DS40300C-page 1
PIC16F62X
Devices Included in this Data Sheet:
PIC16F627
PIC16F628
Referred to collectively as PIC16F62X
High Performance RISC CPU:
Only 35 instructions to learn
All single cycle instructions (200 ns), except for
program branches which are two-cycle
Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
Interrupt capability
16 special function hardware registers
8-level deep hardware stack
Direct, Indirect and Relative addressing modes
Peripheral Features:
16 I/O pins with individual direction control
High current sink/source for direct LED drive
Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs are externally accessible
Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
Timer1: 16-bit timer/counter with external crystal/
clock capability
Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
Capture, Compare, PWM (CCP) module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
Universal Synchronous/Asynchronous Receiver/
Transmitter USART/SCI
16 Bytes of common RAM
Special Microcontroller Features:
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Brown-out Detect (BOD)
Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Multiplexed MCLR-pin
Programmable weak pull-ups on PORTB
Programmable code protection
Low voltage programming
Power saving SLEEP mode
Selectable oscillator options
- FLASH configuration bits for oscillator
options
- ER (External Resistor) oscillator
Reduced part count
- Dual speed INTRC
Lower current consumption
- EC External Clock input
- XT Oscillator mode
- HS Oscillator mode
- LP Oscillator mode
In-circuit Serial Programming™ (via two pins)
Four user programmable ID locations
CMOS Technology:
Low power, high speed CMOS FLASH technology
Fully static design
Wide operating voltage range
- PIC16F627 - 3.0V to 5.5V
- PIC16F628 - 3.0V to 5.5V
- PIC16LF627 - 2.0V to 5.5V
- PIC16LF628 - 2.0V to 5.5V
Commercial, industrial and extended temperature
range
Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
-15µA typical @ 3.0V, 32 kHz
-< 1.0µA typical standby current @ 3.0V
Device
Memory
FLASH
Program
RAM
Data
EEPROM
Data
PIC16F627 1024 x 14 224 x 8 128 x 8
PIC16F628 2048 x 14 224 x 8 128 x 8
FLASH-Based 8-Bit CMOS Microcontrollers
PIC16F62X
DS40300C-page 2 Preliminary 2003 Microchip Technology Inc.
Pin Diagrams
Device Differences
Device Voltage
Range Oscillator
Process
Technology
(Microns)
PIC16F627 3.0 - 5.5 (Note 1) 0.7
PIC16F628 3.0 - 5.5 (Note 1) 0.7
PIC16LF627 2.0 - 5.5 (Note 1) 0.7
PIC16LF628 2.0 - 5.5 (Note 1) 0.7
Note 1: If you change from this device to another device, please verify oscillator characteristics in your
application.
2
3
4
5
6
7
8
9
•1
PDIP, SOIC
PIC16F62X
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VSS
VSS
VDD
VDD
RA1/AN1
RA0/AN0
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
RB1/RX/DT
RB2/TX/CK
RB3/CCP1 RB4/PGM
RB5
RA3/AN3/CMP1
RA4/TOCKI/CMP2
RA5/MCLR/VPP
RB0/INT
RA2/AN2/VREF
VSS
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RA3/AN3/CMP1
RA4/TOCKI/CMP2
RA5/MCLR/VPP
RB0/INT
RA2/AN2/VREF
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VDD
RA1/AN1
RA0/AN0
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
RB4/PGM
RB5
10
11
12
13
14
15
17
16
18
2
3
4
5
6
7
8
9
•1
PIC16F62X
12
13
14
15
16
17
19
18
20
10 11
SSOP
2003 Microchip Technology Inc. Preliminary DS40300C-page 3
PIC16F62X
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16F62X Device Varieties........................................................................................................................................................ 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization ................................................................................................................................................................. 15
5.0 I/O Ports ..................................................................................................................................................................................... 29
6.0 Timer0 Module ........................................................................................................................................................................... 43
7.0 Timer1 Module ........................................................................................................................................................................... 46
8.0 Timer2 Module ........................................................................................................................................................................... 50
9.0 Comparator Module.................................................................................................................................................................... 53
10.0 Voltage Reference Module......................................................................................................................................................... 59
11.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 61
12.0 Universal Synchronous/ Asynchronous Receiver/ Transmitter (USART) Module...................................................................... 67
13.0 Data EEPROM Memory ............................................................................................................................................................. 87
14.0 Special Features of the CPU...................................................................................................................................................... 91
15.0 Instruction Set Summary .......................................................................................................................................................... 107
16.0 Development Support............................................................................................................................................................... 121
17.0 Electrical Specifications............................................................................................................................................................ 127
18.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 143
19.0 Packaging Information.............................................................................................................................................................. 157
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PIC16F62X
DS40300C-page 4 Preliminary 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. Preliminary DS40300C-page 5
PIC16F62X
1.0 PIC16F62X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16F62X Product
Identification System section (Page 167) at the end of
this data sheet. When placing orders, please use this
page of the data sheet to specify the correct part
number.
1.1 FLASH Devices
FLASH devices can be erased and reprogrammed
electrically. This allows the same device to be used for
prototype development, pilot programs and production.
A further advantage of the electrically-erasable FLASH
is that it can be erased and reprogrammed in-circuit, or
by device programmers, such as Microchip's
PICSTART® Plus, or PRO MATE® II programmers.
1.2 Quick-Turnaround Production
(QTP) Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a
medium-to-high quantity of units and whose code
patterns have stabilized. The devices are standard
FLASH devices but with all program locations and con-
figuration options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.
1.3 Serialized Quick-Turnaround
Production (SQTPsm) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
PIC16F62X
DS40300C-page 6 Preliminary 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. Preliminary DS40300C-page 7
PIC16F62X
2.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16F62X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16F62X uses a Harvard architecture, in
which, program and data are accessed from separate
memories using separate buses. This improves
bandwidth over traditional Von Neumann architecture
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit
wide data word. Instruction opcodes are 14-bits wide
making it possible to have all single-word instructions.
A 14-bit wide program memory access bus fetches a
14-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (35) execute in a single
cycle (200 ns @ 20 MHz) except for program
branches.
The Table below lists program memory (FLASH, Data
and EEPROM).
TABLE 2-1: DEVICE DESCRIPTION
The PIC16F62X can directly or indirectly address its
register files or data memory. All Special Function
registers, including the program counter, are mapped in
the data memory. The PIC16F62X have an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation, on any register, using any
Addressing mode. This symmetrical nature, and lack of
‘special optimal situations’ make programming with the
PIC16F62X simple yet efficient. In addition, the learning
curve is reduced significantly.
The PIC16F62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
A simplified block diagram is shown in Figure 2-1, and
a description of the device pins in Table 2-1.
Two types of data memory are provided on the
PIC16F62X devices. Non-volatile EEPROM data
memory is provided for long term storage of data such
as calibration values, lookup table data, and any other
data which may require periodic updating in the field.
This data is not lost when power is removed. The other
data memory provided is regular RAM data memory.
Regular RAM data memory is provided for temporary
storage of data during normal operation. It is lost when
power is removed.
Device
Memory
FLASH
Program
RAM
Data
EEPROM
Data
PIC16F627 1024 x 14 224 x 8 128 x 8
PIC16F628 2048 x 14 224 x 8 128 x 8
PIC16LF627 1024 x 14 224 x 8 128 x 8
PIC16LF628 2048 x 14 224 x 8 128 x 8
PIC16F62X
DS40300C-page 8 Preliminary 2003 Microchip Technology Inc.
FIGURE 2-1: BLOCK DIAGRAM
Note 1: Higher order bits are from the STATUS register.
FLASH
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8-Level Stack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
RA4/T0CK1/CMP2
RA5/MCLR/VPP
RB0/INT
8
8
Brown-out
Detect
USART
CCP1
Timer0 Timer1 Timer2
RA3/AN3/CMP1
RA2/AN2/VREF
RA1/AN1
RA0/AN0
8
3
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB5
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
Low-voltage
Programming
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VREF
Comparator
Data EEPROM
2003 Microchip Technology Inc. Preliminary DS40300C-page 9
PIC16F62X
TABLE 2-1: PIC16F62X PINOUT DESCRIPTION
Name Function Input Type Output Type Description
RA0/AN0 RA0 ST CMOS Bi-directional I/O port
AN0 AN Analog comparator input
RA1/AN1 RA1 ST CMOS Bi-directional I/O port
AN1 AN Analog comparator input
RA2/AN2/VREF RA2 ST CMOS Bi-directional I/O port
AN2 AN Analog comparator input
VREF —ANVREF output
RA3/AN3/CMP1 RA3 ST CMOS Bi-directional I/O port
AN3 AN Analog comparator input
CMP1 CMOS Comparator 1 output
RA4/T0CKI/CMP2 RA4 ST OD Bi-directional I/O port
T0CKI ST Timer0 clock input
CMP2 OD Comparator 2 output
RA5/MCLR/VPP RA5 ST Input port
MCLR ST Master clear
VPP Programming voltage input. When configured
as MCLR, this pin is an active low RESET to
the device. Voltage on MCLR/VPP must not
exceed VDD during normal device operation.
RA6/OSC2/CLKOUT RA6 ST CMOS Bi-directional I/O port
OSC2 XTAL Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
CLKOUT CMOS In ER/INTRC mode, OSC2 pin can output
CLKOUT, which has 1/4 the frequency of
OSC1
RA7/OSC1/CLKIN RA7 ST CMOS Bi-directional I/O port
OSC1 XTAL Oscillator crystal input
CLKIN ST External clock source input. ER biasing pin.
RB0/INT RB0 TTL CMOS Bi-directional I/O port. Can be software
programmed for internal weak pull-up.
INT ST External interrupt.
RB1/RX/DT RB1 TTL CMOS Bi-directional I/O port. Can be software
programmed for internal weak pull-up.
RX ST USART receive pin
DT ST CMOS Synchronous data I/O.
RB2/TX/CK RB2 TTL CMOS Bi-directional I/O port.
TX CMOS USART transmit pin
CK ST CMOS Synchronous clock I/O. Can be software
programmed for internal weak pull-up.
RB3/CCP1 RB3 TTL CMOS Bi-directional I/O port. Can be software
programmed for internal weak pull-up.
CCP1 ST CMOS Capture/Compare/PWM I/O
Legend: O = Output CMOS = CMOS Output P = Power
= Not used I = Input ST = Schmitt Trigger Input
TTL = TTL Input OD = Open Drain Output AN = Analog
PIC16F62X
DS40300C-page 10 Preliminary 2003 Microchip Technology Inc.
RB4/PGM RB4 TTL CMOS Bi-directional I/O port. Can be software
programmed for internal weak pull-up.
PGM ST Low voltage programming input pin. Interrupt-
on-pin change. When low voltage program-
ming is enabled, the interrupt-on-pin change
and weak pull-up resistor are disabled.
RB5 RB5 TTL CMOS Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
RB6/T1OSO/T1CKI/PGC RB6 TTL CMOS Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
T1OSO XTAL Timer1 oscillator output.
T1CKI ST Timer1 clock input.
PGC ST ICSP™ Programming Clock.
RB7/T1OSI/PGD RB7 TTL CMOS Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
T1OSI XTAL Timer1 oscillator input. Wake-up from SLEEP
on pin change. Can be software programmed
for internal weak pull-up.
PGD ST CMOS ICSP Data I/O
VSS VSS Power Ground reference for logic and I/O pins
VDD VDD Power Positive supply for logic and I/O pins
TABLE 2-1: PIC16F62X PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
Legend: O = Output CMOS = CMOS Output P = Power
= Not used I = Input ST = Schmitt Trigger Input
TTL = TTL Input OD = Open Drain Output AN = Analog
2003 Microchip Technology Inc. Preliminary DS40300C-page 11
PIC16F62X
2.1 Clocking Scheme/Instruction
Cycle
The clock input (OSC1/CLKIN/RA7 pin) is internally
divided by four to generate four non-overlapping
quadrature clocks namely Q1, Q2, Q3 and Q4.
Internally, the program counter (PC) is incremented
every Q1, the instruction is fetched from the program
memory and latched into the instruction register in Q4.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 2-2.
2.2 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change, (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 2-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 2-2: CLOCK/INSTRUCTION CYCLE
EXAMPLE 2-1: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
CLKOUT
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, 3 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
PIC16F62X
DS40300C-page 12 Preliminary 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. Preliminary DS40300C-page 13
PIC16F62X
3.0 MEMORY ORGANIZATION
3.1 Program Memory Organization
The PIC16F62X has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. Only
the first 1K x 14 (0000h - 03FFh) for the PIC16F627
and 2K x 14 (0000h - 07FFh) for the PIC16F628 are
physically implemented. Accessing a location above
these boundaries will cause a wrap-around within the
first 1K x 14 space (PIC16F627) or 2K x 14 space
(PIC16F628). The RESET vector is at 0000h and the
interrupt vector is at 0004h (Figure 3-1).
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK
3.2 Data Memory Organization
The data memory (Figure 3-2) is partitioned into four
banks, which contain the general purpose registers and
the Special Function Registers (SFR). The SFR’s are
located in the first 32 locations of each Bank. Register
locations 20-7Fh, A0h-FFh, 120h-14Fh, 170h-17Fh
and 1F0h-1FFh are general purpose registers
implemented as static RAM.
The Table below lists how to access the four banks of
registers:
Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
implemented as common RAM and mapped back to
addresses 70h-7Fh.
3.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 224 x 8 in the
PIC16F62X. Each is accessed either directly or
indirectly through the File Select Register FSR (See
Section 3.4).
PC<12:0>
13
000h
0004
0005
03FFh
1FFFh
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
07FFh
PIC16F627 and
PIC16F628
PIC16F628 only
On-chip Program
Memory
RP1 RP0
Bank0 00
Bank1 01
Bank2 10
Bank3 11
PIC16F62X
DS40300C-page 14 Preliminary 2003 Microchip Technology Inc.
FIGURE 3-2: DATA MEMORY MAP OF THE PIC16F627 AND PIC16F628
Indirect addr.(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
PR2
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
File
Address
Indirect addr.(1) Indirect addr.(1)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
17Fh 1FFh
Bank 2 Bank 3
Indirect addr.(1)
TMR0 OPTION
RCSTA
TXREG
RCREG
CMCON
TXSTA
SPBRG
VRCON
General
Purpose
Register
1EFh
1F0h
accesses
70h - 7Fh
EFh
F0h
accesses
70h-7Fh
16Fh
170h
accesses
70h-7Fh
80 Bytes
EEDATA
EEADR
EECON1
EECON2(1)
General
Purpose
Register
80 Bytes
General
Purpose
Register
48 Bytes
11Fh
120h
14Fh
150h
6Fh
70h
16 Bytes
PORTB TRISB
1Ch
1Dh
1Eh
2003 Microchip Technology Inc. Preliminary DS40300C-page 15
PIC16F62X
3.2.2 SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 3-1). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 3-1: SPECIAL REGISTERS SUMMARY BANK 0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Reset(1)
Details
on Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25
01h TMR0 Timer0 Module’s Register xxxx xxxx 43
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 13
03h STATUS IRP RP1 RP0 TO PD ZDCC
0001 1xxx 19
04h FSR Indirect data memory address pointer xxxx xxxx 25
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 29
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 34
07h Unimplemented
08h Unimplemented
09h Unimplemented
0Ah PCLATH Write buffer for upper 5 bits of program counter ---0 0000 25
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 21
0Ch PIR1 EEIF CMIF RCIF TXIF CCP1IF TMR2IF TMR1IF 0000 -000 23
0Dh Unimplemented
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 46
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 46
10h T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 46
11h TMR2 TMR2 module’s register 0000 0000 50
12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50
13h Unimplemented
14h Unimplemented
15h CCPR1L Capture/Compare/PWM register (LSB) xxxx xxxx 61
16h CCPR1H Capture/Compare/PWM register (MSB) xxxx xxxx 61
17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 61
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 -00x 67
19h TXREG USART Transmit data register 0000 0000 74
1Ah RCREG USART Receive data register 0000 0000 77
1Bh Unimplemented
1Ch Unimplemented
1Dh Unimplemented
1Eh Unimplemented
1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 53
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.
PIC16F62X
DS40300C-page 16 Preliminary 2003 Microchip Technology Inc.
TABLE 3-2: SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Reset(1)
Details on
Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx 25
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 20
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 25
83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 19
84h FSR Indirect data memory address pointer xxxx xxxx 25
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 29
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 34
87h Unimplemented
88h Unimplemented
89h Unimplemented
8Ah PCLATH —— Write buffer for upper 5 bits of program counter ---0 0000 25
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 21
8Ch PIE1 EEIE CMIE RCIE TXIE CCP1IE TMR2IE TMR1IE 0000 -000 22
8Dh Unimplemented
8Eh PCON OSCF —PORBOD ---- 1-0x 24
8Fh Unimplemented
90h Unimplemented
91h Unimplemented
92h PR2 Timer2 Period Register 1111 1111 50
93h Unimplemented
94h Unimplemented
95h Unimplemented
96h Unimplemented
97h Unimplemented
98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 69
99h SPBRG Baud Rate Generator Register 0000 0000 69
9Ah EEDATA EEPROM data register xxxx xxxx 87
9Bh EEADR EEPROM address register xxxx xxxx 87
9Ch EECON1 ——— WRERR WREN WR RD ---- x000 87
9Dh EECON2 EEPROM control register 2 (not a physical register) -------- 87
9Eh Unimplemented
9Fh VRCON VREN VROE VRR VR3 VR2 VR1 VR0 000- 0000 59
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unim-
plemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.
2003 Microchip Technology Inc. Preliminary DS40300C-page 17
PIC16F62X
TABLE 3-3: SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Reset(1)
Details on
Page
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical reg-
ister)
xxxx xxxx 25
101h TMR0 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 43
102h PCL Program Counter's (PC) Least Significant Byte 0000 0000 25
103h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 19
104h FSR Indirect data memory address pointer xxxx xxxx 2 5
105h Unimplemented
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 34
107h Unimplemented
108h Unimplemented
109h Unimplemented
10Ah PCLATH —— Write buffer for upper 5 bits of program counter ---0 0000 25
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 21
10Ch Unimplemented
10Dh Unimplemented
10Eh Unimplemented
10Fh Unimplemented
110h Unimplemented
111h Unimplemented
112h Unimplemented
113h Unimplemented
114h Unimplemented
115h Unimplemented
116h Unimplemented
117h Unimplemented
118h Unimplemented
119h Unimplemented
11Ah Unimplemented
11Bh Unimplemented
11Ch Unimplemented
11Dh Unimplemented
11Eh Unimplemented
11Fh Unimplemented
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unim-
plemented.
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.
PIC16F62X
DS40300C-page 18 Preliminary 2003 Microchip Technology Inc.
TABLE 3-4: SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Reset(1)
Details on
Page
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical reg-
ister)
xxxx xxxx 25
181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 20
182h PCL Program Counter's (PC) Least Significant Byte 0000 0000 25
183h STATUS IRP RP1 RP0 TO PD ZDCC 0001 1xxx 19
184h FSR Indirect data memory address pointer xxxx xxxx 25
185h Unimplemented
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 34
187h Unimplemented
188h Unimplemented
189h Unimplemented
18Ah PCLATH —— Write buffer for upper 5 bits of program counter ---0 0000 25
18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 21
18Ch Unimplemented
18Dh Unimplemented
18Eh Unimplemented
18Fh Unimplemented
190h Unimplemented
191h Unimplemented
192h Unimplemented
193h Unimplemented
194h Unimplemented
195h Unimplemented
196h Unimplemented
197h Unimplemented
198h Unimplemented
199h Unimplemented
19Ah Unimplemented
19Bh Unimplemented
19Ch Unimplemented
19Dh Unimplemented
19Eh Unimplemented
19Fh Unimplemented
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unim-
plemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.
2003 Microchip Technology Inc. Preliminary DS40300C-page 19
PIC16F62X
3.2.2.1 STATUS Register
The STATUS register, shown in Register 3-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory (SRAM).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any STATUS bit. For other instructions, not
affecting any STATUS bits, see the “Instruction Set
Summary”.
REGISTER 3-1: STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
bit 4 TO: Timeout bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT timeout occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F62X
DS40300C-page 20 Preliminary 2003 Microchip Technology Inc.
3.2.2.2 OPTION Register
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0, and the weak pull-ups on PORTB.
REGISTER 3-2: OPTION REGISTER (ADDRESS: 81h, 181h)
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1). See Section 6.3.1
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate