STWBC-MC Digital controller for wireless battery chargers transmitters for Qi multicoil applications Datasheet - production data Memory - Flash and EEPROM with read-while-write (RWW) and Error Correction Code (ECC) - Program memory: 32 Kbytes Flash; data retention: 20 years at 55 C after 1000 cycles at 55 C - Data memory: 1 Kbyte true data EEPROM; data retention: 20 years at 55 C after 1000 cycles at 85 C - RAM: 6 Kbytes Features Digital controller for wireless battery charger transmitter Multi-coil inductive transmitters optimized for: - Cell phones and smartphones - Tablets and phablets - Charging accessories Support for Wireless Power Consortium (WPC) 1.2 EPP applications - Backward compatible with WPC BPP and 1.1 5W applications Transmitter reference design: - Multi-coil EPP topology - 2-layer PCBs - Active object detection - Graphical user interface for application monitoring Operating temperature: -40 C up to 105 C Package: VFQFPN32 5 x 5 mm Table 1. Ordering information Type Package STWBC-MC VFQFPN32, tube STWBC-MCTR VFQFPN32 tape and reel Support for half-bridge topology with DC/DC VIN range: 3 V to 5.5 V - Supports USB VIN Active presence detector Foreign object detection Q-factor measurement Parametric customization via GUI Turnkey firmware solution Peripherals - 10-bit ADC - UART interface - I2C master fast/slow speed rate - GPIOs August 2018 This is information on a product in full production. DocID031237 Rev 2 1/32 www.st.com Contents STWBC-MC Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 STWBC-MC system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 STWBC-MC pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Pins functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 2/32 4.1 Power supplies: VDD, VDDA, VSS, VSSA, VOUT . . . . . . . . . . . . . . . . . . 10 4.2 DC/DC converter: DCDC_DRV, DCDC_DAC, CMP_OUT_V, CS_CMP, DCDC_DAC_REF, DEMAGNET, VTARGET 10 4.3 Half-bridge driver: UPBL, DNBL, PWM_QFOD, WAVE_SNS . . . . . . . . . 10 4.4 Wireless power functions: TANK_VOLTAGE, ISENSE, COIL_TEMP, SYMBOL_DETECT, CURRENT_DEMOD, QFOD_ADC 11 4.5 Input power supply management: VMAIN, QC_IO . . . . . . . . . . . . . . . . . . .11 4.6 External digital interface: UART_TX, UART_RX . . . . . . . . . . . . . . . . . . . 12 4.7 End user signaling: LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.8 Coil selection: I2C_SDA, I2C_SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.9 Debug: SWIM, NRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.6 Loading capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.7 Pin output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.8 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.9 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.9.1 VOUT external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.9.2 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.9.3 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DocID031237 Rev 2 STWBC-MC Contents 5.9.4 Typical output level curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9.5 Fast pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.9.6 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.9.7 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.9.8 10-bit SAR ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 8 VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DocID031237 Rev 2 3/32 32 List of tables STWBC-MC List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. 4/32 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Flash program memory/data E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Voltage DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Current DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ADC accuracy characteristic at VDD/VDDA = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DocID031237 Rev 2 STWBC-MC List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Wireless charging system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STWBC-MC device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STWBC-MC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 External capacitor CVOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VOH standard pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VOL standard pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VOH standard pad at 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VOL standard pad at 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VOH fast pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VOL fast pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VOH fast pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VOL fast pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ADC equivalent input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ADC accuracy parameter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 VFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DocID031237 Rev 2 5/32 32 Description 1 STWBC-MC Description The STWBC-MC is the digital controller for the wireless battery charger (WBC) transmitters (TX) from STMicroelectronics optimized for the extended power profile (EPP) Wireless Power Consortium (WPC) multi-coil applications up to 15 W. It offers the most flexible and efficient solution for controlling the power transfer to a receiver (RX) in WBC-enabled applications such as smartphones, tablets and other battery-powered devices that use the electromagnetic induction for recharging. The TX is responsible for controlling the transmitting coil and generating the correct amount of power requested by the RX. The RX continuously provides the transmitter with the correct power level requested, by modulating the transmitter carrier through the controlled resistive or capacitive load. Generating the correct amount of power ensures the highest level of endto-end efficiency due to reduced energy losses. It also helps maintaining a lower operational temperature. The TX can adapt to the amount of energy transferred by the coil by modulating the frequency, duty cycle or amplitude of the PWM voltage on the transmitting coil. The STWBC-MC is capable of bidirectional communication with the RX as specified by the WPC 1.2 protocol. Figure 1. Wireless charging system description The STWBC-MC firmware is specifically designed to take advantage of the hardware to monitor and control the correct wireless charging operations. 6/32 DocID031237 Rev 2 STWBC-MC 2 STWBC-MC system architecture STWBC-MC system architecture The STWBC-MC is a flexible controller that supports a half-bridge coil driver together with a DC/DC controller, which regulates the input voltage of the bridge in order to control the amount of power transmitter to the receiver. It also controls the selection of the active coil for multi-coil topologies. The digital controller also regulates the half-bridge operating frequency and duty cycle to further adjusting the amount of power increasing the overall efficiency at the light-load. It implements the WPC 1.2 protocol, including foreign object detection (FOD) extensions. An accurate Q-factor measurement provides enhanced FOD. The STWBC-MC is able to manage both the WPC baseline power profile (up to 5 W) and extended power profile (EPP). Figure 2 illustrates the overall system blocks implemented in the STWBC-MC architecture. Figure 2. STWBC-MC device architecture 7JONPOJUPS 7PS 7 JOQVU Y-&% %JHJUBM DPOUSPMMFS %JHJUBMCPPTUBOE CSJEHFDPOUSPMMFS 5PQPMPHZ TQFDJGJD GJSNXBSF JODMVEJOH2J DFSUJGJDBUJPO 5FNQFSBUVSF QSPUFDUJPO "%$ 0WFSDVSSFOU QSPUFDUJPO 4JHOBMQSPUPDPM EFNPEVMBUPS (1*0T 2J'0% 2GBDUPS 6"35 *$ 1MVH1MBZ 458#$.$ "DUJWFPCKFDU EFUFDUPS ". Firmware The STWBC-MC firmware is available in a turnkey software package distributed as a binary file. The STWBC-MC provides the UART communication interface, for external programming of parameters and STWBC-MC control. DocID031237 Rev 2 7/32 32 STWBC-MC pinout and pin description 3 STWBC-MC STWBC-MC pinout and pin description This section shows the pinout used by the STWBC-MC. 61#- %/# -@'# 48*. /345 7%% 744 7065 6"35@59 Figure 3. STWBC-MC configuration 6"35@39 %$%$@%"$ 18.@2'0% 4:.#0-@%&5&$5 *$@4%" %&."(/&5 *$@4$- %$%$@%3*7& 7."*/ *4&/4& 45 8#$ &1 458#$.$ $0* -@5&.1 $.1@065@7 2'0%@"%$ 75"3(&5 5"/,@70-5" (& 2$@*0 744" 7%%" $633&/5@%&.0% -&% 8"7&@4/4 %$%$@%"$@3&' $4@$.1 %/#- ". Table 2. Pinout description 8/32 Pin number Pin name Pin type Description 1 UART_RX DI UART RX link on USB debug connector 2 PWM_QFOD DO PWM dedicated to QFOD circuit 3 I2C_SDA DO I2C_SDA used for coil selection 4 I2C_SCL DO I2C_SCL used for coil selection 5 DNBL DO Output signal for HB low side driver 6 LED DO Digital output for green and red LEDs indicators 7 QC_IO DO Quick charge circuit signal 8 CMP_OUT_V AI Boost output voltage sensing DocID031237 Rev 2 STWBC-MC STWBC-MC pinout and pin description Table 2. Pinout description (continued) Note: Pin number Pin name Pin type Description 9 CS_CMP AI Boost current sensing 10 DCDC_DAC_REF AI DAC reference value for boost output voltage 11 WAVE_SNS AI Symbol detector based on delta frequency 12 CURRENT_DEMOD AI Current demodulation 13 VDDA PS Analog power supply 14 VSSA PS Analog ground 15 TANK_VOLTAGE AI Analog input to measure the LC voltage (power calculation) 16 VTARGET AI Boost voltage measurement 17 QFOD_ADC AI High sensitivity peak voltage detector used for quality factor measurement 18 COIL_TEMP AI Analog input for temperature measurement. The input is connected to external NTC biased to the VDD_STWBC 19 ISENSE AI Analog input to measure the current flowing into the power bridge 20 VMAIN AI Analog input to measure the main power supply 21 DCDC_DRV DO DCDC boost PWM drive 22 DEMAGNET DI Transformer demagnetization sensing 23 SYMBOL_DETECT DI Voltage demodulation 24 DCDC_DAC DO Boost PWM output DAC (setting the CPP3 comparator voltage reference) 25 UPBL DO Output signal for HB high side driver 26 DNBL_FB DI Hardware PWM feedback 27 SWIM DIO 28 NRST DI Reset input monitoring 29 VDD PS Digital and I/O power supply 30 VSS PS Digital and I/O ground 31 VOUT Supply 32 UART_TX DO Digital I/O for debug interface Internal LDO output UART TX link on USB debug connector The operative voltage of analog inputs (AI) ranges from 0 V to 1.2 V. DocID031237 Rev 2 9/32 32 Pins functional description 4 STWBC-MC Pins functional description This section describes the functions related to the pins of the device. 4.1 Power supplies: VDD, VDDA, VSS, VSSA, VOUT The digital portion of the STWBC-MC is powered using VDD and VSS (typically 4.5 V). The analog portion of the STWBC-MC is powered using VDDA and VSSA (typically 4.5 V). VDD and VDDA should be correctly filtered to allow the correct operation of the device. The STWBC-MC generates its own internal power supply which needs a filter capacitor of 1 F on the VOUT pin. 4.2 DC/DC converter: DCDC_DRV, DCDC_DAC, CMP_OUT_V, CS_CMP, DCDC_DAC_REF, DEMAGNET, VTARGET The STWBC-MC is designed to drive a DC/DC boost converter placed in front of the halfbridge coil driver. The DC/DC power switch (external NMOS) is driven by the DCDC_DRV pin through an output buffer. The DC/DC inductor charging current is monitored using a sense resistor. The sense resistor has to be connected to the CS_CMP pin so that the STWBC-MC can detect current flowing into the inductor. The DC/DC converter loop compares a reference target voltage applied on the DCDC_DAC_REF pin with the feedback voltage connected to the CMP_OUT_V pin. The CMP_OUT_V signal is a partition of the DC/DC output voltage. The DCDC_DAC_REF reference voltage is variable in order to adjust the DC/DC output voltage depending on wireless power solution requirements. The DCDC_DAC_REF is generated by filtering the PWM signal present on the DCDC_DAC pin. A second order passive filter is required. The DC/DC output voltage is monitored by the STWBC-MC using the VTARGET pin. The VTARGET should be generated as a partition of the DCDC output voltage. In order to enhance the efficiency at the medium and low load, the DC/DC converter can operate in the quasi-resonant mode. To do so, the STWBC-MC monitors the demagnetization of the inductor using the DEMAGNET pin. 4.3 Half-bridge driver: UPBL, DNBL, PWM_QFOD, WAVE_SNS The power half-bridge is driven using UPBL and DNBL pins. The UPBL pin has to be connected to a high-side gate driver, while the DNBL pin has to be connected to a low-side gate driver for the power switches. UPBL and DNBL pins are active high: when 1, the corresponding power switch has to be ON. 10/32 DocID031237 Rev 2 STWBC-MC Pins functional description The STWBC-MC integrates a programmable deadtime between the active states of UPBL and DNBL avoiding simultaneous conduction of power switches. The external gate driver doesn't need to manage deadtime. The STWBC-MC requires the following capability to be supported by the gate driver: UPBL = 0, DNBL = 0: in such case, the power half-bridge must be in the high impedance state. UPBL = 1, DNBL = 0: high side power switch must be ON. UPBL = 0, DNBL = 1: low side power switch must be ON. UPBL = 1, DNBL = 1: optional mode where both high and low side power switches must be ON (simultaneous conduction). While the power half-bridge is driven with the UPBL and DNBL signals, a low energy drive is needed to run the coil quality factor estimation. For this function, the bridge is driven by using the PWM_QFOD pin instead of UPBL (UPBL is 0 during this operation). PWM_QFOD has to be connected to the low energy high side switch while DNBL is still used for the low side low impedance switch drive. In many situation the STWBC-MC requires a 1/4 wave synchronization with the LC tank connected to the half-bridge. A simple passive detector must be connected to the LC tank and the WAVE_SNS pin. The WAVE_SNS pin should be limited to a 0.6 V swing. 4.4 Wireless power functions: TANK_VOLTAGE, ISENSE, COIL_TEMP, SYMBOL_DETECT, CURRENT_DEMOD, QFOD_ADC The STWBC-MC requires monitoring the peak voltage on the LC tank as well as the rectified current circulating in the tank. To do so, a peak voltage detector of the LC tank must be connected to the TANK_VOLTAGE pin and a filtered current sensor must be connected to the ISENSE pin . For quality factor measurement, a high sensitivity peak voltage detector of the LC tank must be connected to the QFOD_ADC pin. The STWBC-MC requires external signal conditioning blocks to pre-demodulate the WPC Qi messages. One of this block detects the effect of modulation on the LC tank voltage and it must be connected to the SYMBOL_DETECT pin. Another block is required to detect the effect of modulation on the LC tank current and it must be connected to the CURRENT_DEMOD pin. For safety reason the STWBC-MC is capable to monitor the temperature of the transmitting coil. In order to do so, a NTC thermistor must be connected to the COIL_TEMP pin. 4.5 Input power supply management: VMAIN, QC_IO The STWBC-MC monitors the input power supply voltage using the VMAIN pin. This voltage is used for optimum programming of the DCDC converter but also for the wireless power mode of the operation. The STWBC-MC is capable of requesting 12 V output voltage available from some USB wall adaptors. While the USB wall adaptor provides 5 V by default, using a specific signaling on the D+ and D- signals of the USB interface, 12 V can be obtained if supported. When 12 V is DocID031237 Rev 2 11/32 32 Pins functional description STWBC-MC available, the STWBC-MC can provide up to 15 W to a receiver load. The QC_IO pin has to be connected to a simple interfacing circuit with the USB connector. When QC_IO is 0, 5 V is requested to the USB wall adaptor. When QC_IO is 1, 12 V is requested to the USB wall adaptor. 4.6 External digital interface: UART_TX, UART_RX The STWBC-MC can be programmed and/or controlled using a 57600 bps, 8 bits, 1 start, 1 stop no-parity UART interface. The STWBC-MC UART TX output is present on the UART_TX pin and the UART RX input is present on the UART_RX pin. 4.7 End user signaling: LED The STWBC-MC manages 2 LEDs (red and green typically) using a single LED pin. The pin is output 0 to drive the first LED, output 1 to drive the second LED and high impedance to not drive any LED. A simple circuit can be used to interface the LEDs with this LED pin. 4.8 Coil selection: I2C_SDA, I2C_SCL The STWBC-MC embeds an IC master interface on I2C_SDA and I2C_SCL pins. This interface is used to select the active coil in a multi-coil TX system, with the aid of a GPIO expander. 4.9 Debug: SWIM, NRST The SWIM pin may be used to interface with the STLINK/V2 debugger. The STWBC-MC can be reset using the active low NRST pin. 12/32 DocID031237 Rev 2 STWBC-MC Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. VDDA and VDD must be connected to the same voltage value. VSS and VSSA must be connected together with a shortest wire loop. 5.2 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TA max. (given by the selected temperature range). 5.3 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD and VDDA = 5 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range. 5.4 Typical curves Unless otherwise specified, all typical curves are given as design guidelines only and are not tested. 5.5 Typical current consumption For typical current consumption measurements, VDD and VDDA are connected together as shown in Figure 4. DocID031237 Rev 2 13/32 32 Electrical characteristics STWBC-MC Figure 4. Supply current measurement conditions 5.6 Loading capacitors The loading conditions used for the pin parameter measurement are shown in Figure 5. Figure 5. Pin loading conditions 14/32 DocID031237 Rev 2 STWBC-MC 5.7 Electrical characteristics Pin output voltage The input voltage measurement on a pin is described in Figure 6. Figure 6. Pin input voltage 5.8 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device reliability. Table 3. Voltage characteristics Symbol Ratings VDDX - VSSX Supply voltage(1) VIN Input voltage on any other pin(2) Min. Max. -0.3 6.5 VSS -0.3 VDD +0.3 Unit V VDD - VDDA Variation between different power pins - 50 mV VSS - VSSA Variation between all the different ground pins(3) - 50 mV 1. All power VDDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external power supply. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. VSS and VSSA signals must be interconnected together with a short wire loop. DocID031237 Rev 2 15/32 32 Electrical characteristics STWBC-MC Table 4. Current characteristics(1) Symbol IVDDX IVSSX Ratings Max. Total current into VDDX power lines(2) (2) Total current out of VSSX power lines Output current sunk by any I/Os and control pin IIO Output current source by any I/Os and control pin IINJ(PIN)(3), (4) Injected current on any pin IINJ(TOT)(3), (4), (5) Sum of injected currents Unit 100 100 Ref. to Table 10 on page 21 mA 4 20 1. Data based on characterization results, not tested in production. 2. All power VDDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external power supply. 3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 4. Negative injection disturbs the analog performance of the device. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with the IINJ(PIN) maximum current injection on four I/O port pins of the device. Table 5. Thermal characteristics Symbol TSTG TJ 16/32 Ratings Storage temperature range Max. Unit -65 to 150 C Maximum junction temperature DocID031237 Rev 2 150 STWBC-MC 5.9 Electrical characteristics Operating conditions The device must be used in operating conditions that comply with the parameters in Table 6. In addition, a full account must be taken for all physical capacitor characteristics and tolerances. Table 6. General operating conditions Symbol fCPU Parameter Conditions Internal CPU clock frequency VDD1, VDDA1 Operating voltages VDD, VDDA VOUT JA TA - - - (1) 3 Typ. Max. Unit 16 5 MHz (1) 5.5 5(1) - 1.8(2) - at 1 MHz 470 - 3300 nF ESR of external capacitor(2) - 0.05 - 0.2 capacitor(2) - - - 15 nH FR4 multilayer PCB VFQFPN32 - 26 - C/W Ambient temperature Pd = 100 mW -40 - 105 C - 3.3 Core digital power supply - CVOUT: capacitance of external capacitor(3) (1) - 5 Nominal operating voltages ESL of external (4) Min. V 1. The external power supply can range from 3 V to 5.5 V although IC performances are optimized for the power supply equal to 5 V. 2. Internal core power supply voltage. 3. Care should be taken when the capacitor is selected due to its tolerance, its dependency on temperature, DC bias and frequency. 4. To calculate PDmax (TA), use the formula PDmax = (TJmax - TA)/JA. Table 7. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ. Max. 2.98(1) VIT+ Power-on reset threshold - 2.65 2.8 VIT- Brownout reset threshold - 2.58 2.73 2.88(1) VHYS(BOR) Brownout reset hysteresis - - 70 - Unit V mV 1. VDD rise must be monotone. The slew rate should be between 1 V/s and 0.5 V/s. DocID031237 Rev 2 17/32 32 Electrical characteristics 5.9.1 STWBC-MC VOUT external capacitor The stabilization of the main regulator is achieved by connecting an external capacitor CVOUT(a) to the VOUT pin. The CVOUT is specified in Section 5.9: Operating conditions. Care should be taken to limit the series inductance to less than 15 nH. Figure 7. External capacitor CVOUT a. ESR is the equivalent series resistance and ESL is the equivalent inductance. 18/32 DocID031237 Rev 2 STWBC-MC 5.9.2 Electrical characteristics Memory characteristics Flash program and memory/data E2PROM. General conditions: TA = -40 C to 105 C. Table 8. Flash program memory/data E2PROM Symbol tPROG tERASE Parameter Conditions Standard programming time (Including erase) for byte/word/block (1 byte/4 bytes/128 bytes) - Fast programming time for 1 block (128 bytes) - - 3 3.3 Erase time for 1 block (128 bytes) - - 3 3.3 TA = 25 C 10 K - - TA = 85 C 100 K - - TA= 105 C 35 K - - Data retention (program memory) after 10 K erase/write cycles at TA= 25 C TRET = 85 C 15 - - Data retention (program memory) after 10 K erase/write cycles at TA= 25 C TRET = 105 C 11 - - Data retention (data memory) after 100 K erase/write cycles at TA= 85 C TRET = 85 C 15 - - Data retention (data memory) after 35 K erase/write cycles at TA= 105 C TRET = 105 C 6 - - Supply current during program and erase cycles -40 C TA 105 C - 2 - Erase/write cycles(2)program memory) NWE tRET IDDPRG Min.(1) Typ.(1) Max.(1) Erase/write cycles(2) (data memory) - 6 Unit 6.6 ms ms Cycles Years mA 1. Data based on characterization results, not tested in production. 2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. DocID031237 Rev 2 19/32 32 Electrical characteristics 5.9.3 STWBC-MC I/O port pin characteristics The I/O port pin parameters are specified under general operating conditions for VDD and TA unless otherwise specified. Unused input pins should not be left floating. Table 9. Voltage DC characteristics Symbol Description VIL Input low voltage VIH Input high voltage(2) Output low voltage at 3.3 V VOL2 Output low voltage at 5 V(3) VOL3 Output low voltage high sink at 3.3 V / 5 VOH1 Output high voltage at 3.3 V(3) VOH3 Output high voltage at 5 Hysteresis input RPU Pull-up resistor Max.(1) -0.3 - 0.3 * VDD 0.7 * VDD - VDD - - 0.4(4) - - 0.5 - 0.6(4) - VDD -0.4(4) - - VDD -0.5 - - - - - 0.1 * VDD - 30 45 60 V(2), (5) V(3) Output high voltage high sink at 3.3 V / 5 HVS Typ. (3) VOL1 VOH2 Min.(1) V(2), (5) voltage(6) VDD -0.6(4) 1. Data based on characterization result, not tested in production. 2. Input signals cannot exceed VDDX (VDDX = VDD, VDDA). 3. Parameter applicable to signals: PWM_QFOD, DNBL, LED, QC_IO, DCDC_DRV, DCDC_DAC, UPBL, UART_TX. 4. Electrical threshold voltage not characterized at -40 C. 5. Parameter applicable to the signals: SWIM, DEMAGNET. 6. Applicable to any digital inputs. 20/32 DocID031237 Rev 2 Unit V k STWBC-MC Electrical characteristics Table 10. Current DC characteristics Symbol IOL1 IOL2 Description Standard output low level current at 3.3 V and VOL1(2) Standard output low level current at 5 V and VOL2 (2) (3) IOLhs1 High sink output low level current at 3.3 V and VOL3 IOLhs2 (3) High sink output low level current at 5 V and VOL3 Min. Typ. Max.(1) - - 1.5 - - 3 - - 5 - - 7.75 mA IOH1 Standard output high level current at 3.3 V and VOH1(2) - - 1.5 IOH2 Standard output high level current at 5 V and VOLH2(2) - - 3 - - 5 - - 7.75 - - 1 - - 4 - - 20 IOHhs1 IOHhs2 ILKg I_Inj I_Inj High sink output high level current at 3.3 V and High sink output high level current at 5 V and VOH3(3) VOH3(3) Input leakage current digital - analog VSS VIN VDD(4) Injection current(5), (6) Total injection current (sum of all I/O and control pins) (5) Unit A mA 1. Data based on characterization result, not tested in production. 2. Parameter applicable to signals: PWM_QFOD, DNBL, LED, QC_IO, DCDC_DRV, DCDC_DAC, UPBL, UART_TX. 3. Parameter applicable to the signals: SWIM, DEMAGNET. 4. Applicable to any digital inputs. 5. The maximum value must never be exceeded. 6. The negative injection current on TANK_VOLTAGE, VTARGET, QFOD_ADC, COIL_TEMP, ISENSE, VMAIN pins have to be avoided since it affects ADC conversion accuracy. DocID031237 Rev 2 21/32 32 Electrical characteristics 5.9.4 STWBC-MC Typical output level curves This section shows the typical output level curves measured on a single output pin for the three pad family present in the STWBC-MC device. Standard pad This pad class is associated to the following pins: I2C_SDA, I2C_SCL, LED, QC_IO, SYMBOL_DETECT, SWIM, UART_TX. . Figure 8. VOH standard pad at 3.3 V Figure 9. VOL standard pad at 3.3 V 7PI <7> 7EE7 5 $ 7EE7 5$ 7PM <N7> 7EE7 5 $ *PI <N"> 7EE7 5 $ 7EE7 5$ 7EE7 5 $ *PM <N"> ". ". Figure 11. VOL standard pad at 5 V 7EE7 5 $ 7EE7 5$ 7EE7 5$ 7PM <N7> 7PI <7> Figure 10. VOH standard pad at 5 V 7EE7 5 $ 7EE7 5$ 7EE7 5$ *PI <N"> *PM <N"> ". 22/32 DocID031237 Rev 2 ". STWBC-MC 5.9.5 Electrical characteristics Fast pad This pad class is associated to the PWM_QFOD, DNBL, DCDC_DRV, DCDC_DAC, UPBL pins. Figure 12. VOH fast pad at 3.3 V Figure 13. VOL fast pad at 3.3 V 7PI <7> 7EE7 5 $ 7EE7 5$ 7EE7 5 $ 7EE7 5 $ 7PM <N7> *PI <N"> 7EE7 5$ 7EE7 5 $ ". *PM <N"> ". Figure 14. VOH fast pad at 3.3 V Figure 15. VOL fast pad at 3.3 V 7EE7 5 $ 7EE7 5$ 7EE7 5$ 7PM <N7> 7PI <7> 7EE7 5$ 7EE7 5$ 7EE7 5$ *PI <N"> ". DocID031237 Rev 2 *PM<N"> ". 23/32 32 Electrical characteristics 5.9.6 STWBC-MC Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 11. NRST pin characteristics Symbol VIL(NRST) Parameter NRST input low level voltage Conditions Min.(1) Typ. Max.(1) - -0.3 - 0.3 x VDD - 0.7 x VDD - VDD + 0.3 IOL = 2 mA - - 0.5 - 30 40 60 - - - 75 - 500 - - - 15 - - (1) VIH(NRST) NRST input high level voltage(1) VOL(NRST) NRST output low level voltage (1) (2) RPU(NRST) NRST pull-up resistor tIFP(NRST) NRST input filtered pulse(3) tINFP(NRST) NRST not input filtered pulse(3) tOP(NRST) NRST output filtered pulse(3) Unit V k ns s 1. Data based on characterization results, not tested in production. 2. The RPU pull-up equivalent resistor is based on a resistive transistor. 3. Data guaranteed by design, not tested in production. 5.9.7 I2C interface characteristics Table 12. I2C interface characteristics Standard mode Symbol Parameter Min.(1) Fast mode Max.(1) Min.(1) Max.(1) tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0(2) - 0(2) 900(2) tr(SDA) tr(SCL) SDA and SCL rise time (VDD = 3.3 to 5 V)(3) - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time (VDD = 3.3 to 5 V)(3) - 300 - 300 s ns th(STA) START condition hold time 4.0 - 0.6 - tsu(STA) Repeated START condition setup time 4.7 - 0.6 - tsu(STO) STOP condition setup time 4.0 - 0.6 - s STOP to START condition time (bus free) 4.7 - 1.3 - s - 50 - 50 pF tw(STO:STA) Cb s Capacitive load for each bus line(4) 1. Data based on standard I2C protocol requirement, not tested in production. 2. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time. 3. I2C multifunction signals require the high sink pad configuration and the interconnection of 1 k pull-up resistances. 4. 50 pF is the maximum load capacitance value to meet the I2C std. timing specifications. 24/32 Unit DocID031237 Rev 2 STWBC-MC 5.9.8 Electrical characteristics 10-bit SAR ADC characteristics The 10-bit SAR ADC parameters are specified under general operating conditions for VDDA and TA unless otherwise specified. Table 13. ADC characteristics Symbol N RADCIN Parameter Min. Typ. Max. Unit Resolution - 10 - bit ADC input impedance(1) 1 - - M (1) (2) VIN Input conversion voltage range 0 - Vref (3) - 1.250 ADC main reference voltage 1.25 , V - 1. Maximum input analog voltage cannot exceed VDD/VDDA. 2. Exceeding the maximum voltage on TANK_VOLTAGE, VTARGET, COIL_TEMP, ISENSE, QFOD_ADC signals has to be avoided since it may impact the ADC conversion accuracy defined in Table 14. 3. ADC reference voltage at TA = 25 C. ADC accuracy characteristics See Figure 17 for more details about ADC accuracy parameter definition. Table 14. ADC accuracy characteristic at VDD/VDDA = 5 V Symbol |EO| Parameter Offset error(3), (4) error(3), (4), (5) Min.(2) Typ.(1) Max.(2) - 0.5 - - 0.4 - |EG| Gain EOG Offset + gain error (3), (4), (5), (6) -8.3 - 8.9 EOG Offset + gain error(3), (4), (5), (7) -10.9 - 10.9 Offset + gain error(3), (4), (5), (8) -13.8 - 10.9 - 0.8 - - 2.0 - EOG (1), (2), (3) |ED| Differential linearity error |EL| Integral linearity error(3), (4) Unit LSB 1. Operating temperature: TA = 25 C . 2. Data based on characterization results, not tested in production. 3. ADC accuracy vs. negative injection current. The injecting negative current on any of the analog input pins should be avoided as this reduces the accuracy of the conversion being performed on another analog input. It is recommended that a Schottky diode (pin to ground) should be added to standard analog pins which may potentially inject a negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy. The ADC accuracy parameters may be also impacted exceeding the ADC maximum input voltage VIN. 4. Results in manufacturing test mode. 5. Gain error evaluated with the two-point method. 6. Temperature operating range: 0 C TA 85 C. 7. Temperature operating range: -25 C TA 105 C. 8. Temperature operating range: -40 C TA 105 C. DocID031237 Rev 2 25/32 32 Electrical characteristics STWBC-MC ADC equivalent input circuit Figure 16 shows the ADC equivalent input circuit. Figure 16. ADC equivalent input circuit Figure 17. ADC accuracy parameter definitions 26/32 DocID031237 Rev 2 STWBC-MC Electrical characteristics ET = total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = offset error: deviation between the first actual transition and the first ideal one. EOG = offset + gain error (1-point gain): deviation between the last ideal transition and the last actual one. EG = gain error (2-point gain): defined so that EOG = EO + EG (parameter correlated to the deviation of the characteristic slope). ED = differential linearity error: maximum deviation between actual steps and the ideal one. EL = integral linearity error: maximum deviation between any actual transition and the end point correlation line. DocID031237 Rev 2 27/32 32 Thermal characteristics 6 STWBC-MC Thermal characteristics The STWBC-MC functionality cannot be guaranteed when the device is operating under the maximum chip junction temperature (TJmax). TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x JA) where: TAmax is the maximum ambient temperature in C JA is the package junction to ambient thermal resistance in C/W PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/Omax represents the maximum power dissipation on output pins where: PI/Omax = (VOL * IOL) + [(VDD - VOH) * IOH], taking into account the actual VOL/IOL and VOH/IOH of the I/Os at the low and high level. Table 15. Thermal characteristics Symbol JA Parameter Thermal resistance junction to ambient(1) Value Unit 26 C/W 1. Thermal resistance are based on JEDEC JESD51-2 with a 4-layer PCB in a natural convection environment. 28/32 DocID031237 Rev 2 STWBC-MC 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 VFQFPN32 package information Figure 18. VFQFPN32 package outline DocID031237 Rev 2 29/32 32 Package information STWBC-MC Table 16. VFQFPN32 package mechanical data Databook dimension (mm) Symbol Note: Min. Typ. Max. A 0.80 0.90 1.00 A1 0 0.02 0.05 A3 - 0.20 - b 0.18 0.25 0.30 D 4.85 5.00 5.15 D2 3.40 3.45 3.50 E 4.85 5.00 5.15 E2 3.40 3.45 3.50 e - 0.50 0.55 L 0.30 0.40 0.50 ddd - - 0.08 VFQFPN stands for "Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead". Very thin profile: 0.80 < A 00 mm. Details of the terminal 1 are optional, but must be located on the top surface of the package by using either a mold or marked features. Package outline exclusive of any mold flashes dimensions and metal burrs. 30/32 DocID031237 Rev 2 STWBC-MC 8 Revision history Revision history Table 17. Document revision history Date Revision Changes 03-Jan-2018 1 Initial release. 07-Aug-2018 2 Document has been changed from internal to public. DocID031237 Rev 2 31/32 32 STWBC-MC IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2018 STMicroelectronics - All rights reserved 32/32 DocID031237 Rev 2