LP2951CMX3.3NOPB - NATIONAL SEMICONDUCTOR

LM49100

LM49100 Mono Class AB Audio Sub-System with a True-Ground Headphone

Amplifier

Literature Number: SNAS392E

September 2007

LM49100

Mono Class AB Audio Sub-System with a True-Ground

Headphone Amplifier

General Description

The LM49100 is a fully integrated audio subsystem capable

of delivering 1.275W of continuous average power into a

mono 8Ω bridged-tied load (BTL) with 1% THD+N and with a

5V power supply. The LM49100 also has a stereo true-ground

headphone amplifier capable of 50mW per channel of con-

tinuous average power into a 32Ω single-ended (SE) loads

with 1% THD+N.

The LM49100 has three input channels. One pair of SE inputs

can be used with a stereo signal. The other input channel is

fully differential and may be used with a mono input signal.

The LM49100 features a 32-step digital volume control and

ten distinct output modes. The mixer, volume control, and de-

vice mode select are controlled through an I2C compatible

interface.

Thermal overload protection prevent the device from being

damaged during fault conditions. Superior click and pop sup-

pression eliminates audible transients on power-up/down and

during shutdown.

Key Specifications

■ Power Output at VDD = 5V:

Loudspeaker (LS):

RL = 8Ω, THD+N ≤ 1% 1.275W

Headphone (VDDHP = 2.8V):

RL = 32Ω, THD+N ≤ 1% 50mW

■ Shutdown current 0.01µA

Features

■Mono and stereo inputs

■Thermal Overload Protection

■True-ground Headphone Drivers

■I2C Control Interface

■Input mute attenuation

■2nd Stage headphone attenuator

■32-step digital volume control

■10 Operating Modes

■Minimum external components

■Click and Pop suppression

■Micro-power shutdown

■Available in space-saving 3mm x 3mm 25 bump GR

package

■RF Suppression

Applications

■Mobile Phones

■PDAs

■Laptops

■Portable Electronics

Boomer® is a registered trademark of National Semiconductor Corporation.

LM49100 Mono Class AB Audio Sub-System with a True-Ground Headphone Amplifier

Typical Application

300015o4

FIGURE 1. Typical Audio Amplifier Application Circuit

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LM49100

Connection Diagrams

GR Package

3mm × 3mm × 1mm

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Top View

Order Number LM49100GR

See NS Package Number GRA25A

GR Package Marking

300015f6

Top View

XY — 2 Digit datecode

TT — Lot traceability

G — Boomer Family

C9 — LM49100GR

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LM49100

Bump Descriptions

Bump Name Description

A1 VDDCP Positive Charge Pump Power Supply

A2 GNDCP Charge Pump Ground

A3 MIN+ Positive Mono Input

A4 BYPASS Half-Supply Bypass

A5 RIN Right Input

B1 C1N Negative Terminal – Charge Pump Flying Capacitor

B2 C1P Positive Terminal – Charge Pump Flying Capacitor

B3 MIN- Negative Mono Input

B4 LIN Left Input

B5 LS− Negative Loudspeaker Output

C1 VSSCP Negative Charge Pump Power Supply

C2 VSSHP Negative Headphone Power Supply

C3 GND Ground

C4 ADDR I2C Address Identification

C5 VDDLS Loudspeaker Power Supply

D1 HPL Left Headphone Output

D2 VDDHP Positive Headphone Power Supply

D3 VDDI2C I2C Power Supply

D4 SDA I2C Data

D5 LS+ Loudspeaker Output Positive

E1 HPR Right Headphone Output

E2 VDDLS Loudspeaker Power Supply

E3 AGND Headphone Signal Ground (See Application Information section).

E4 GND Ground

E5 SCL I2C Clock

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LM49100

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (Loudspeaker) 6V

Supply Voltage (Headphone) 3V

Storage Temperature −65°C to +150°C

Input Voltage −0.3V to VDD + 0.3V

Power Dissipation (Note 3) Internally Limited

ESD Susceptibility (Note 4) 2000V

ESD Susceptibility (Note 5) 200V

Junction Temperature 150°C

Thermal Resistance

θJA (GR) 50.2°C/W

Operating Ratings

Temperature Range

TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ +85°C

Supply Voltage VDDLS 2.7V ≤ VDDLS ≤ 5.5V

Supply Voltage VDDHP 2.4 V ≤ VDDHP ≤ 2.9V

I2C Voltage (VDDI2C ) 1.7V ≤ VDDI2C ≤ 5.5V

VDDHP ≤ VDDLS

VDDI2C ≤ VDDLS

Electrical Characteristics VDDLS = 3.6V, VDDHP = 2.8V (Notes 1, 2)

The following specifications apply for all programmable gain set to 0 dB, CB = 4.7μF, RL (SP) = 8Ω, RL(HP) = 32Ω, f = 1 kHz unless

otherwise specified. Limits apply for TA = 25°C.

Symbol Parameter Conditions

LM49100 Units

(Limits)

Typical

(Note 6)

Limit

(Note 7)

IDD Supply Current

VDDLS = 3.0V

VDDHP = 2.8V

Modes 1, 3, 5

VIN = 0V, No Load 2.9 mA

Modes 2, 4, 6

VIN = 0V, No Load 3.4 mA

Modes 7, 10, 14

VIN = 0V, No Load 4.8 mA

VDDLS = 3.6V

VDDHP = 2.8V

Modes 1, 3, 5

VIN = 0V, No Load 2.9 4.3 mA (max)

Modes 2, 4, 6

VIN = 0V, No Load 3.5 5.4 mA (max)

Modes 7, 10, 14

VIN = 0V, No Load 4.8 7.4 mA (max)

VDDLS = 5.0V

VDDHP = 2.8V

Modes 1, 3, 5

VIN = 0V, No Load 3.1 mA

Modes 2, 4, 6

VIN = 0V, No Load 3.6 mA

Modes 7, 10, 14

VIN = 0V, No Load 5.0 mA

ISD Shutdown Supply Current Mode 0 0.01 1 µA (max)

VOS Output Offset Voltage

VIN = 0V, Mode 7, Mono 6.0 25 mV (max)

VIN = 0V, Mode 7, Headphone Gain = –24dB 2.2 5.5 mV

VIN = 0V, Mode 7, Headphone Gain = –18dB 2.4 mV (max)

VIN = 0V, Mode 7, Headphone Gain = –12dB 3.2 mV

VIN = 0V, Mode 7, Headphone Gain = 0dB 7 15 mV (max)

POUT Output Power VDDLS = 3.0V

f = 1kHz

RL = 8Ω

10%

425

525

f = 1kHz

RL = 16Ω

10%

RL = 32Ω

10%

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LM49100

Symbol Parameter Conditions

LM49100 Units

(Limits)

Typical

(Note 6)

Limit

(Note 7)

POUT Output Power VDDLS = 3.6V

f = 1kHz

RL = 8Ω

10%

640

790

600 mW (min)

f = 1kHz

RL = 16Ω

10%

RL = 32Ω

10%

46 mW (min)

POUT Output Power VDDLS = 5.0V

f = 1kHz

RL = 8Ω

10%

1275

1575

f = 1kHz

RL = 16Ω

10%

RL = 32Ω

10%

THD+N Total Harmonic Distortion +

Noise VDDLS = 3.0V f = 1kHz

Loudspeaker;

Mode 1, RL =

8Ω, POUT =

215mW

0.05 %

Headphone;

Mode 4, RL =

32Ω, POUT =

25mW

0.02 %

THD+N Total Harmonic Distortion +

Noise VDDLS = 3.6V f = 1kHz

Loudspeaker;

Mode 1, RL =

8Ω, POUT =

320mW

0.05 %

Headphone;

Mode 4, RL =

32Ω, POUT =

25mW

0.02 %

THD+N Total Harmonic Distortion +

Noise VDDLS = 5.0V f = 1kHz

Loudspeaker;

Mode 1, RL =

8Ω, POUT =

630mW

0.035 %

Headphone;

Mode 4, RL =

32Ω, POUT =

25mW

0.02 %

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LM49100

Symbol Parameter Conditions

LM49100 Units

(Limits)

Typical

(Note 6)

Limit

(Note 7)

eNNoise

A-weighted, 0 dB, inputs

terminated to GND, output

referred

Headphone

Mode 2,10 12 µV

Mode 4, 7 13 µV

Mode 6, 14 16 µV

Loudspeaker

Mode 1 14 µV

Mode 3, 7, 10,

14 23 µV

Mode 5 27 µV

TON Turn-on Time 26 ms

TOFF Turn-off Time 1 ms

ZIN Input Impedance

Maximum gain setting 12.5 10

kΩ (min)

kΩ (max)

Maximum attenuation setting 110 90

130

kΩ (min)

kΩ (max)

AVVolume Control

Stereo (Left

and Right

Channels)

Input referred maximum

attenuation −54 –52

–56

dB (min)

dB (max)

Input referred maximum gain 18 17.5

18.5

dB (min)

dB (max)

Mono

Input referred maximum

attenuation −60 –58

–62

dB (min)

dB (max)

Input referred maximum gain 12 11.5

12.5

dB (min)

dB (max)

CMRR Common Mode Rejection Ratio

Headphone Mode 2, f = 217 Hz,

VCM = 1 VPP,RL = 32Ω 64 dB

Loudspeaker Mode 1, f = 217 Hz, VCM = 1 VPP,

RL = 8Ω 58 dB

PSRR Power Supply Rejection Ratio

VRIPPLE = 200mVpp on VDD LS, output referred, inputs terminated to GND, f = 217Hz

LS, Mode 1 90 dB

LS, Mode 3, 7, 10, 14 78 dB

LS, Mode 5 77 dB

PSRR Power Supply Rejection Ratio VRIPPLE = 200mVpp on VDD HP, output referred, inputs terminated to GND, f = 217Hz

LS, Mode 7, 10, 14 83 dB

PSRR Power Supply Rejection Ratio

VRIPPLE = 200mVpp on VDD LS, output referred, inputs terminated to GND, f = 217Hz

HP, Mode 2, 10 90 dB

HP, Mode 4, 7 88 dB

HP, Mode 6, 14 87 dB

PSRR Power Supply Rejection Ratio

VRIPPLE = 200mVpp on VDD HP, output referred, inputs terminated to GND, f = 217Hz

HP, Mode 2, 10 83 dB

HP, Mode 4, 7 83 dB

HP, Mode 6, 14 80 dB

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LM49100

I2C (Notes 2, 7)

The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ VDDI2C ≤ 5.5V, unless otherwise specified.

Symbol Parameter Conditions (Note 8) LM49100 Units

(Limits)

Typical

(Note 6)

Limits

(Note 7)

t1I2C Clock Period 2.5 µs (min)

t2I2C Data Setup Time 100 ns (min)

t3I2C Data Stable Time 0 ns (min)

t4Start Condition Time 100 ns (min)

t5Stop Condition Time 100 ns (min)

t6I2C Data Hold Time 100 ns (min)

VIH I2C Input Voltage High 0.7xVDDI2CV (min)

VIL I2C Input Voltage Low 0.3xVDDI2CV (max)

I2C (Notes 2, 7)

The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ VDDI2C ≤ 2.2V, unless otherwise specified.

Symbol Parameter Conditions (Note 8) LM49100 Units

(Limits)

Typical

(Note 6)

Limits

(Note 7)

t1I2C Clock Period 2.5 µs (min)

t2I2C Data Setup Time 250 ns (min)

t3I2C Data Stable Time 0 ns (min)

t4Start Condition Time 250 ns (min)

t5Stop Condition Time 250 ns (min)

t6I2C Data Hold Time 250 ns (min)

VIH I2C Input Voltage High 0.7xVDDI2CV (min)

VIL I2C Input Voltage Low 0.3xVDDI2CV (max)

Note 1: All voltages are measured with respect to the GND pin unless other wise specified.

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions

which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters

where no limit is given, however, the typical value is a good indication of device performance.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum

allowable power dissipation is PDMAX = (TJMAX – TA)/ θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM49100, see power

derating currents for more information.

Note 4: Human body model, 100 pF discharged through a 1.5kΩ resistor.

Note 5: Machine Model, 220pF - 240pF discharged through all pins.

Note 6: Typicals are measured at 25°C and represent the parametric norm.

Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 8: Please refer to Figure 3 (I2C Timing Diagram).

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LM49100

Typical Performance Characteristics

THD+N vs Frequency

VDD = 3.6V, RL = 8Ω, PO = 320mW

BW = 22kHz, LS, Mode 1

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THD+N vs Frequency

VDD = 3.6V, RL = 32Ω, PO = 25mW

HP, BW = 22kHz, Mode 4,7

300015o6

THD+N vs Frequency

VDD = 3V, RL = 8Ω, PO = 215mW

BW = 22kHz, LS, Mode 1

300015o8

THD+N vs Frequency

VDD = 3V, RL = 32Ω, PO = 25mW

BW = 22kHz, HP, Mode 4, 7

300015q2

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LM49100

THD+N vs Frequency

VDD = 5V, RL = 8Ω, PO = 630mW

BW = 22kHz, Loudspeaker, Mode 1

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THD+N vs Frequency

VDD = 5V, RL = 32Ω, PO = 25mW

BW = 22kHz, Headphone, Mode 4,7

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THD+N vs Output Power

RL = 32Ω, f = 1kHz

BW = 22kHz, HP, Mode 4

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THD+N vs Output Power

RL = 8Ω, f = 1kHz

BW = 22kHz, LS, Mode 1

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Output Power vs Supply Voltage

VDDHP = 2.8V, RL = 8Ω,

f = 1kHz, LS

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Output Power vs Supply Voltage

VDDHP = 2.8V, RL = 32Ω,

f = 1kHz, HP

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LM49100

Power Dissipation vs Output Power

VDD = 3.6V, RL = 8Ω,

f = 1kHz, Mode 1

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Power Dissipation vs Output Power

VDD = 3V, RL = 8Ω,

f = 1kHz, Mode 1

300015p6

Power Dissipation vs Output Power

VDD = 5V, RL = 8Ω,

f = 1kHz, Mode 1

300015p7

Supply Current vs VDDLS

VDDHP = 2.8V, Mode 1, 3, 5, No Load

30001564

Supply Current vs VDDLS

VDDHP = 2.8V, Mode 2, 4, 6, No Load

30001565

Supply Current vs VDDLS

VDDHP = 2.8V, Mode 7,10, 14, No Load

30001570

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LM49100

PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDHP

VDDHP = 2.8V, CB = 4.7μF, Mode 2, 10, HP

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PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDHP

VDDHP = 2.8V, CB = 4.7μF, Mode 4, 7, HP

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PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDHP

VDDHP = 2.8V, CB = 4.7μF, Mode 6, HP

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PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 2, 10, HP

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PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 4, 7, HP

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PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 6, 14, HP

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LM49100

PSRR vs Frequency

RL = 8Ω, VRIPPLE = 200mVPP on VDDHP

VDDHP = 2.8V, CB = 4.7μF, Mode 7, 10, 14, LS+HP

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PSRR vs Frequency

RL = 8Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 1, LS

300015l6

PSRR vs Frequency

RL = 8Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 7, 10, 14, LS+HP

300015m0

PSRR vs Frequency

RL = 8Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 3, LS

300015l7

PSRR vs Frequency

RL = 8Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 5, LS

300015l8

Crosstalk vs Frequency

PO = 12mW, f = 1kHz, Mode 4, HP

30001525

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LM49100

LM49100 Control Tables

TABLE 1. I2C Control Register Table

The LM49100 is controlled through an I2C compatible interface. The I2C chip address is 0xF8 (ADR pin = 0) or 0xFAh (ADDR pin

= 1).

D7 D6 D5 D4 D3 D2 D1 D0

Modes Control 0 0 1 1 MC3 MC2 MC1 MC0

HP Volume (Gain)

Control 0 1 INPUT_MU

TE 0 0 HPR_SD HPVC1 HPVC0

Mono Volume

Control 1 0 0 MV4 MV3 MV2 MV1 MV0

Left Volume (Gain)

Control 1 1 0 LV4 LV3 LV2 LV1 LV0

Right Volume (Gain)

Control 1 1 1 RV4 RV3 RV2 RV1 RV0

TABLE 2. Headphone Attenuation Control

The following bits have added for extra headphone output attenuation:

Gain Select HPVC1 HPVC0 Gain, dB

0 0 0 0

1 0 1 −12

2 1 0 −18

3 1 1 −24

TABLE 3. Output Mode Selection

Output

Mode

Number

MC3 MC2 MC1 MC0 Handsfree Mono Output Right HP Output Left HP Output

0 0 0 0 0 SD SD SD

1 0 0 0 1 2 × GM × M SD SD

2 0 0 1 0 SD GHP × (GM × M) GHP × (GM × M)

3 0 0 1 1 2 × (GL × L + GR × R) SD SD

4 0 1 0 0 SD GHP × (GR × R) GHP × (GL × L)

5 0 1 0 1 2 × (GL × L + GR × R

+ GM × M) SD SD

6 0 1 1 0 SD GHP × (GR × R + GM × M) GHP × (GL × L + GM × M)

7 0 1 1 1 2 × (GL × L + GR × R) GHP × (GR × R) GHP × (GL × L)

10 1 0 1 0 2 × (GL × L + GR × R) GHP × (GM × M) GHP × (GM × M)

14 1 1 1 0 2 × (GL × L + GR × R) GHP × (GR × R + GM × M) GHP × (GL × L + GM × M)

GL— Left channel gain

GR — Right channel gain

GM — Mono channel gain

GHP — Headphone Amplifier gain

R — Right input signal

L — Left input signal

SD — Shutdown

M — Mono input signal

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LM49100

TABLE 4. Mono/Stereo Left/Stereo Right Input Gain Control

Volume Step MV4/LV4/RV4 MV3/LV3/RV3 MV2/LV2/RV2 MV1/LV1/RV1 MV0/LV0/RV0 R/L Gain, dB MonoGain,

1 0 0 0 0 0 −54 −60

2 0 0 0 0 1 −47 −53

3 0 0 0 1 0 −40.5 −46.5

4 0 0 0 1 1 −34.5 −40.5

5 0 0 1 0 0 −30.0 −36

6 0 0 1 0 1 −27 −33

7 0 0 1 1 0 −24 −30

8 0 0 1 1 1 −21 −27

9 0 1 0 0 0 −18 −24

10 0 1 0 0 1 −15 −21

11 0 1 0 1 0 −13.5 −19.5

12 0 1 0 1 1 −12 −18

13 0 1 1 0 0 −10.5 −16.5

14 0 1 1 0 1 −9 −15

15 0 1 1 1 0 −7.5 −13.5

16 0 1 1 1 1 −6 −12

17 1 0 0 0 0 −4.5 −10.5

18 1 0 0 0 1 −3 −9

19 1 0 0 1 0 −1.5 −7.5

20 1 0 0 1 1 0 −6

21 1 0 1 0 0 1.5 −4.5

22 1 0 1 0 1 3 −3

23 1 0 1 1 0 4.5 −1.5

24 1 0 1 1 1 6 0

25 1 1 0 0 0 7.5 1.5

26 1 1 0 0 1 9 3

27 1 1 0 1 0 10.5 4.5

28 1 1 0 1 1 12 6

29 1 1 1 0 0 13.5 7.5

30 1 1 1 0 1 15 9

31 1 1 1 1 0 16.5 10.5

32 1 1 1 1 1 18 12

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LM49100

Application Information

MINIMIZING CLICK AND POP

To minimize the audible click and pop heard through a head-

phone, maximize the input signal through the corresponding

volume (gain) control registers and adjust the output amplifier

gain accordingly to achieve the user’s desired signal gain. For

example, setting the output of the headphone amplifier to

-24dB and setting the input volume control gain to 24dB will

reduce the output offset from 7mV (typical) to 2.2mV (typical).

This will reduce the audible click and pop noise significantly

while maintaining a 0dB signal gain.

SIGNAL GROUND NOISE

The LM49100 has proprietary suppression circuitry, which

provides an additional -50dB (typical) attenuation of the head-

phone ground noise and its incursion into the headphone. For

optimum utilization of this feature the headphone jack ground

should connect to the AGND (E3) bump.

300015m9

I2C PIN DESCRIPTION

SDA: This is the serial data input pin.

SCL: This is the clock input pin.

ADDR: This is the address select input pin.

I2C COMPATIBLE INTERFACE

The LM49100 uses a serial bus which conforms to the I2C

protocol to control the chip's functions with two wires: clock

(SCL) and data (SDA). The clock line is uni-directional. The

data line is bi-directional (open-collector). The LM49100's

I2C compatible interface supports standard (100kHz) and fast

(400kHz) I2C modes. In this discussion, the master is the

controlling microcontroller and the slave is the LM49100.

The I2C address for the LM49100 is determined using the

ADDR pin. The LM49100's two possible I2C chip addresses

are of the form 111110X10 (binary), where X1 = 0, if ADDR pin

is logic LOW; and X1 = 1, if ADDR pin is logic HIGH. If the

I2C interface is used to address a number of chips in a system,

the LM49100's chip address can be changed to avoid any

possible address conflicts.

The bus format for the I2C interface is shown in Figure 2. The

bus format diagram is broken up into six major sections:

The "start" signal is generated by lowering the data signal

while the clock signal is HIGH. The start signal will alert all

devices attached to the I2C bus to check the incoming address

against their own address.

The 8-bit chip address is sent next, most significant bit first.

The data is latched in on the rising edge of the clock. Each

address bit must be stable while the clock level is HIGH.

After the last bit of the address bit is sent, the master releases

the data line HIGH (through a pull-up resistor). Then the mas-

ter sends an acknowledge clock pulse. If the LM49100 has

received the address correctly, then it holds the data line LOW

during the clock pulse. If the data line is not held LOW during

the acknowledge clock pulse, then the master should abort

the rest of the data transfer to the LM49100.

The 8 bits of data are sent next, most significant bit first. Each

data bit should be valid while the clock level is stable HIGH.

After the data byte is sent, the master must check for another

acknowledge to see if the LM49100 received the data.

If the master has more data bytes to send to the LM49100,

then the master can repeat the previous two steps until all

data bytes have been sent.

The "stop" signal ends the transfer. To signal "stop", the data

signal goes HIGH while the clock signal is HIGH. The data

line should be held HIGH when not in use.

I2C INTERFACE POWER SUPPLY PIN (VDDI2C)

The LM49100's I2C interface is powered up through theVDD

I2C pin. The LM49100's I2C interface operates at a voltage

level set by the VDD I2C pin which can be set independent to

that of the main power supply pin VDD. This is ideal whenever

logic levels for the I2C interface are dictated by a microcon-

troller or microprocessor that is operating at a lower supply

voltage than the main battery of a portable system.

300015d5

FIGURE 2. I2C Bus Format

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LM49100

300015d6

FIGURE 3. I2C Timing Diagram

PCB LAYOUT AND SUPPLY REGULATION

CONSIDERATIONS FOR DRIVING 8Ω LOAD

Power dissipated by a load is a function of the voltage swing

across the load and the load's impedance. As load impedance

decreases, load dissipation becomes increasingly dependent

on the interconnect (PCB trace and wire) resistance between

the amplifier output pins and the load's connections. Residual

trace resistance causes a voltage drop, which results in power

dissipated in the trace and not in the load as desired. For ex-

ample, 0.1Ω trace resistance reduces the output power dis-

sipated by an 8Ω load from 158.3mW to 156.4mW. The

problem of decreased load dissipation is exacerbated as load

impedance decreases. Therefore, to maintain the highest

load dissipation and widest output voltage swing, PCB traces

that connect the output pins to a load must be as wide as

possible.

Poor power supply regulation adversely affects maximum

output power. A poorly regulated supply's output voltage de-

creases with increasing load current. Reduced supply voltage

causes decreased headroom, output signal clipping, and re-

duced output power. Even with tightly regulated supplies,

trace resistance creates the same effects as poor supply reg-

ulation. Therefore, making the power supply traces as wide

as possible helps maintain full output voltage swing.

BRIDGE CONFIGURATION EXPLANATION

The LM49100 drives a load, such as a loudspeaker, connect-

ed between outputs, LS+ and LS-.

This results in both amplifiers producing signals identical in

magnitude, but 180° out of phase. Taking advantage of this

phase difference, a load is placed between LS- and LS+ and

driven differentially (commonly referred to as ”bridge mode”).

Bridge mode amplifiers are different from single-ended am-

plifiers that drive loads connected between a single amplifier's

output and ground. For a given supply voltage, bridge mode

has a distinct advantage over the single-ended configuration:

its differential output doubles the voltage swing across the

load. Theoretically, this produces four times the output power

when compared to a single-ended amplifier under the same

conditions. This increase in attainable output power assumes

that the amplifier is not current limited and that the output sig-

nal is not clipped.

Another advantage of the differential bridge output is no net

DC voltage across the load. This is accomplished by biasing

LS- and LS+ outputs at half-supply. This eliminates the cou-

pling capacitor that single supply, single-ended amplifiers

require. Eliminating an output coupling capacitor in a typical

single-ended configuration forces a single-supply amplifier's

half-supply bias voltage across the load. This increases in-

ternal IC power dissipation and may permanently damage

loads such as loudspeakers.

POWER DISSIPATION

Power dissipation is a major concern when designing a suc-

cessful single-ended or bridged amplifier.

A direct consequence of the increased power delivered to the

load by a bridge amplifier is higher internal power dissipation.

The LM49100 has a pair of bridged-tied amplifiers driving a

handsfree loudspeaker, LS. The maximum internal power

dissipation operating in the bridge mode is twice that of a sin-

gle-ended amplifier. From Equation (1), assuming a 5V power

supply and an 8Ω load, the maximum MONO power dissipa-

tion is 634mW.

PDMAX-LS = 4(VDD)2 / (2π2 RL): Bridge Mode (1)

The LM49100 also has a pair of single-ended amplifiers driv-

ing stereo headphones, HPR and HPL. The maximum inter-

nal power dissipation for HPR and HPL is given by equation

(2). Assuming a 2.8V power supply and a 32Ω load, the max-

imum power dissipation for LOUT and ROUT is 49mW, or 99mW

total.

PDMAX-HPL = 4(VDDHP)2 / (2π2 RL): Single-ended Mode (2)

The maximum internal power dissipation of the LM49100 oc-

curs when all three amplifiers pairs are simultaneously on;

and is given by Equation (3).

PDMAX-TOTAL =

PDMAX-LS + PDMAX-HPL + PDMAX-HPR (3)

The maximum power dissipation point given by Equation (3)

must not exceed the power dissipation given by Equation (4):

17 www.national.com

LM49100

PDMAX = (TJMAX - TA) / θJA (4)

The LM49100's TJMAX = 150°C. In the GR package, the

LM49100's θJA is 50.2°C/W. At any given ambient tempera-

ture TA, use Equation (4) to find the maximum internal power

dissipation supported by the IC packaging. Rearranging

Equation (4) and substituting PDMAX-TOTAL for PDMAX results in

Equation (5). This equation gives the maximum ambient tem-

perature that still allows maximum stereo power dissipation

without violating the LM49100's maximum junction tempera-

ture.

TA = TJMAX - PDMAX-TOTAL θJA (5)

For a typical application with a 5V power supply and an 8Ω

load, the maximum ambient temperature that allows maxi-

mum mono power dissipation without exceeding the maxi-

mum junction temperature is approximately 114°C for the GR

package.

TJMAX = PDMAX-TOTAL θJA + TA(6)

Equation (6) gives the maximum junction temperature

TJMAX. If the result violates the LM49100's 150°C, reduce the

maximum junction temperature by reducing the power supply

voltage or increasing the load resistance. Further allowance

should be made for increased ambient temperatures.

The above examples assume that a device is a surface mount

part operating around the maximum power dissipation point.

Since internal power dissipation is a function of output power,

higher ambient temperatures are allowed as output power or

duty cycle decreases. If the result of Equation (3) is greater

than that of Equation (4), then decrease the supply voltage,

increase the load impedance, or reduce the ambient temper-

ature. If these measures are insufficient, a heat sink can be

added to reduce θJA. The heat sink can be created using ad-

ditional copper area around the package, with connections to

the ground pin(s), supply pin and amplifier output pins.

POWER SUPPLY BYPASSING

As with any power amplifier, proper supply bypassing is crit-

ical for low noise performance and high power supply rejec-

tion. Applications that employ a 5V regulator typically use a

1µF in parallel with a 0.1µF filter capacitors to stabilize the

regulator's output, reduce noise on the supply line, and im-

prove the supply's transient response. However, their pres-

ence does not eliminate the need for a local 4.7µF tantalum

bypass capacitor and a parallel 0.1µF ceramic capacitor con-

nected between the LM49100's supply pin and ground. Keep

the length of leads and traces that connect capacitors be-

tween the LM49100's power supply pin and ground as short

as possible.

SELECTING EXTERNAL COMPONENTS

Input Capacitor Value Selection

Amplifying the lowest audio frequencies requires high value

input coupling capacitor (CIN in Figure 1). A high value ca-

pacitor can be expensive and may compromise space effi-

ciency in portable designs. In many cases, however, the

loudspeakers used in portable systems, whether internal or

external, have little ability to reproduce signals below 150Hz.

Applications using loudspeakers and headphones with this

limited frequency response reap little improvement by using

large input capacitor.

The internal input resistor (Ri), typical 12.5kΩ, and the input

capacitor (CIN) produce a high pass filter cutoff frequency that

is found using Equation (7).

fc = 1 / (2πRiCIN) (7)

Bypass Capacitor Value Selection

Besides minimizing the input capacitor size, careful consid-

eration should be paid to value of CB, the capacitor connected

to the BYPASS pin. Since CB determines how fast the

LM49100 settles to quiescent operation, its value is critical

when minimizing turn-on pops. Choosing CB equal to 2.2µF

along with a small value of Ci (in the range of 0.1µF to 0.33µF),

produces a click-less and pop-less shutdown function. As dis-

cussed above, choosing CIN no larger than necessary for the

desired bandwidth helps minimize clicks and pops. CB's value

should be in the range of 4 to 5 times the value of CIN . This

ensures that output transients are eliminated when power is

first applied or the LM49100 resumes operation after shut-

down.

www.national.com 18

LM49100

Demo Board Schematic

300015q3

Demo Board Schematic

19 www.national.com

LM49100

Demonstration Board Layout

300015f0

Signal 1 Layer

300015f1

Signal 2 Layer

www.national.com 20

LM49100

300015f2

Top Layer

300015f3

Top Overlay

21 www.national.com

LM49100

300015e8

Bottom Layer

300015e9

Bottom Overlay

www.national.com 22

LM49100

Revision History

Rev Date Description

1.0 06/21/07 Initial release.

1.1 06/28/07 Changed the mktg outline from TLA25XXX to GRA25A.

1.2 08/09/07 Replaced some curves.

1.3 08/13/07 Changed the f = 1kHz into f = 217Hz (PSRR) in the Electrical

Characteristics table.

1.4 08/14/07 Edited Table 1.

1.5 09/18/07 Edited the schematic diagram.

23 www.national.com

LM49100

Physical Dimensions inches (millimeters) unless otherwise noted

Dimensions: X1 = X2 = 3 mm, X3 = 1 mm

GR Package

Order Number LM49100GR

See NS Package Number GRA25A

www.national.com 24

LM49100

Notes

25 www.national.com

LM49100

Notes

LM49100 Mono Class AB Audio Sub-System with a True-Ground Headphone Amplifier

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