LTC1854/LTC1855/LTC1856
1
1854565af
Typical applicaTion
DescripTion
8-Channel, ±10V Input
12-/14-/16-Bit, 100ksps ADC
Converters with Shutdown
The LTC
®
1854/LTC1855/LTC1856 are 8-channel, low
power, 12-/14-/16-bit, 100ksps, analog-to-digital con-
verters (ADCs). These ADCs operate from a single 5V
supply and the 8-channel multiplexer can be programmed
for single-ended inputs, pairs of differential inputs, or
combinations of both. In addition, all channels are fault
protected to ±30V. A fault condition on any channel will not
affect the conversion result of the selected channel.
An onboard precision reference minimizes external com-
ponents. Power dissipation is 40mW at 100ksps and lower
in two power shutdown modes (27.5mW in Nap mode and
40µW in Sleep mode.) DC specifications include ±3LSB
INL for the LTC1856, ±1.5LSB INL for the LTC1855 and
±1LSB for the LTC1854.
The internal clock is trimmed for 5µs maximum conversion
time and the sampling rate is guaranteed at 100ksps. A
separate convert start input and data ready signal (BUSY)
ease connections to FIFOs, DSPs and microprocessors.
100kHz, 12-Bit/14-/16-Bit Sampling ADC
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
FeaTures
applicaTions
n Single 5V Supply
n
Sample Rate: 100ksps
n
8-Channel Multiplexer with ±30V Protection
n
±10V Bipolar Input Range
Single Ended or Differential
n
±3LSB INL for the LTC1856, ±1.5LSB INL for the
LTC1855, ±1LSB INL for the LTC1854
n
Power Dissipation: 40mW (Typ)
n SPI/MICROWIRE™ Compatible Serial I/O
n Power Shutdown: Nap and Sleep
n
SINAD: 87dB (LTC1856)
n
Operates with Internal or External Reference
n
Internal Synchronized Clock
n 28-Pin SSOP Package
n Industrial Process Control
n
Multiplexed Data Acquisition Systems
n
High Speed Data Acquisition for PCs
n Digital Signal Processing
LTC1856 Typical INL Curve
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
MUXOUT+
MUXOUT–
ADC+
ADC–
AGND1
CONVST
RD
SCK
SDI
DGND
SDO
BUSY
OVDD
DVDD
AVDD
AGND3
AGND2
REFCOMP
VREF
LTC1854/
LTC1855/
LTC1856
SOFTWARE-PROGRAMMABLE
SINGLE-ENDED OR
DIFFERENTIAL INPUTS
±10V BIPOLAR INPUT RANGE
10µF
0.1µF 10µF
10µF 0.1µF1µF
10µF
3V TO 5V
5V
5V
2.5V
0.1µF
µP
CONTROL
LINES
0.1µF
CODE
–32768
INL (LSB)
0
0.5
1.0
0
185456 G01
–0.5
–1.0
–2.0 –16384 16384 32767
–1.5
2.0
1.5
LTC1854/LTC1855/LTC1856
2
185456fa
package/orDer inFormaTionabsoluTe maximum raTings
Supply Voltage (OVDD = DVDD = AVDD = VDD) ............ 6V
Ground Voltage Difference
DGND, AGND1, AGND2, AGND3 ....................... ±0.3V
Analog Input Voltage
ADC+, ADC–
(Note 3) ...................(AGND1 – 0.3V) to (AVDD + 0.3V)
CH0-CH7, COM ................................................... ±30V
Digital Input Voltage (Note 4) ......(DGND – 0.3V) to 10V
Digital Output Voltage ....(DGND – 0.3V) to (DVDD + 0.3V)
Power Dissipation ................................................ 500mW
Operating Temperature Range
LTC1854C/LTC1855C/LTC1856C .............. 0°C to 70°C
LTC1854I/LTC1855I/LTC1856I ............. – 40°C to 85°C
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(Notes 1, 2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
MUXOUT+
MUXOUT–
ADC+
ADC–
AGND1
CONVST
RD
SCK
SDI
DGND
SDO
BUSY
OVDD
DVDD
AVDD
AGND3
AGND2
REFCOMP
VREF
TJMAX = 125°C, θJA = 160°C/W
EXPOSED PAD (PIN #) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER
LTC1854CG
LTC1854IG
LTC1855CG
LTC1855IG
LTC1856CG
LTC1856IG
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
PARAMETER CONDITIONS
LTC1854 LTC1855 LTC1856
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Resolution l12 14 15 Bits
No Missing Codes l12 14 15 Bits
Transition Noise 0.06 0.25 1 LSBRMS
Integral Linearity Error (Note 7) l±1 ±1.5 ±3 LSB
Differential Linearity Error l–1 1 –1 1.5 –2 4 LSB
Bipolar Zero Error (Note 8) l±5 ±8 ±23 LSB
Bipolar Zero Error Drift ±0.1 ±0.1 ±0.1 ppm/°C
Bipolar Zero Error Match 3 4 10 LSB
Bipolar Full-Scale Error External Reference (Note 11)
Internal Reference (Note 11)
l±0.34
±0.45
±0.14
±0.40
±0.1
±0.4
%
%
Bipolar Full-Scale Error Drift External Reference
Internal Reference
±2.5
±7
±2.5
±7
±2.5
±7
ppm/°C
ppm/°C
Bipolar Full-Scale Error Match 5 10 15 LSB
Input Common Mode Range l±10 ±+10 ±10 V
Input Common Mode Rejection Ratio 96 96 96 dB
converTer anD mulTiplexer characTerisTics
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
MUXOUT connected to ADC inputs. (Notes 5, 6)
LTC1854/LTC1855/LTC1856
3
1854565af
analog inpuT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Input Range CH0 to CH7, COM ±10 V
ADC+, ADC– (Note 3) ADC– ±2.048 V
Impedance CH0 to CH7, COM 31 kΩ
MUXOUT+, MUXOUT–5 kΩ
Capacitance CH0 to CH7, COM 5 pF
Sample Mode ADC+, ADC–12 pF
Hold Mode ADC+, ADC–4 pF
Input Leakage Current ADC+, ADC–, CONVST = Low l±1 µA
Dynamic accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. MUXOUT connected to ADC inputs. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC1854 LTC1855 LTC1856
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal 74 83 87 dB
THD Total Harmonic Distortion 1kHz Input Signal
First Five Harmonics
–102 –95 –101 dB
Peak Harmonic or Spurious Noise 1kHz Input Signal –99 –99 –103 dB
Channel-to-Channel Isolation 1kHz Input Signal –120 –120 –120 dB
–3dB Input Bandwidth 1 1 1 MHz
Aperture Delay –70 –70 –70 ns
Aperture Jitter 60 60 60 ps
Transient Response Full-Scale Step
(Note 9)
4 4 4 µs
Overvoltage Recovery (Note 12) 150 150 150 ns
LTC1854/LTC1855/LTC1856
4
185456fa
inTernal reFerence characTerisTics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Output Voltage IOUT = 0 l2.475 2.50 2.525 V
VREF Output Temperature Coefficient IOUT = 0 ±10 ppm/°C
VREF Output Impedance –0.1mA ≤ IOUT ≤ 0.1mA 8 kΩ
VREFCOMP Output Voltage IOUT = 0 4.096 V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 5.25V l2.4 V
VIL Low Level Input Voltage VDD = 4.75V l0.8 V
IIN Digital Input Current VIN = 0V to VDD l±10 µA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage VDD = 4.75V, IO = –10µA, OVDD = VDD
VDD = 4.75V, IO = –200µA, OVDD = VDD
l
4
4.74 V
V
VOL Low Level Output Voltage VDD = 4.75V, IO = 160µA, OVDD = VDD
VDD = 4.75V, IO = 1.6mA, OVDD = VDD
l
0.05
0.10
0.4
V
V
IOZ Hi-Z Output Leakage VOUT = 0V to VDD, RD = High l±10 µA
COZ Hi-Z Output Capacitance RD = High 15 pF
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = VDD 10 mA
DigiTal inpuTs anD DigiTal ouTpuTs
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
power requiremenTs
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Positive Supply Voltage (Notes 9 and 10) 4.75 5.00 5.25 V
Positive Supply Current
Nap Mode
Sleep Mode
CONVST = 0V or 5V
l8.0
5.5
8.0
12
7
13
mA
mA
µA
Power Dissipation
Nap Mode
Sleep Mode
CONVST = 0V or 5V
40.0
27.5
40.0
mW
mW
µW
LTC1854/LTC1855/LTC1856
5
1854565af
Timing characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND, AGND1,
AGND2 and AGND3 wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above AVDD =
DVDD = OVDD = VDD, they will be clamped by internal diodes. This product
can handle currents of greater than 100mA below ground or above VDD
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle currents of greater
than 100mA below ground without latchup. These pins are not clamped to
VDD.
Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended analog MUX input with respect to ground or ADC+ with respect to
ADC– tied to ground.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency Through CH0 to CH7 Inputs
Through ADC+, ADC– Only
l100
166
kHz
kHz
tCONV Conversion Time l4 5 µs
tACQ Acquisition Time Through CH0 to CH7 Inputs
Through ADC+, ADC– Only
l
1
4 µs
µs
fSCK SCK Frequency (Note 13) l0 20 MHz
trSDO Rise Time See Test Circuits 6 ns
tfSDO Fall Time See Test Circuits 6 ns
t1CONVST High Time l40 ns
t2CONVST to BUSY Delay CL = 25pF, See Test Circuits l15 30 ns
t3SCK Period l50 ns
t4SCK High l10 ns
t5SCK Low l10 ns
t6Delay Time, SCK↓ to SDO Valid CL = 25pF, See Test Circuits l25 45 ns
t7Time from Previous SDO Data Remains
Valid After SCK↓CL = 25pF, See Test Circuits l5 20 ns
t8SDO Valid After RD↓CL = 25pF, See Test Circuits l11 30 ns
t9RD↓ to SCK Setup Time l20 ns
t10 SDI Setup Time Before SCK↑l0 ns
t11 SDI Hold Time After SCK↑l7 ns
t12 SDO Valid Before BUSY↑RD = Low, CL = 25pF, See Test Circuits l5 20 ns
t13 Bus Relinquish Time See Test Circuits l10 30 ns
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111 for the LTC1856, between 00 0000 0000 0000 and 11
1111 1111 1111 for the LTC1855 and between 0000 0000 0000 and 1111
1111 1111 for the LTC1854.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: Full-scale bipolar error is the worst case of –FS or +FS
untrimmed deviation from ideal first and last code transitions, divided by
the full-scale range, and includes the effect of offset error.
Note 12: Recovers to specied performance after (2 • FS) input
overvoltage.
Note 13: t6 of 45ns maximum allows fSCK up to 10MHz for rising capture
with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns
setup time for the receiving logic).
LTC1854/LTC1855/LTC1856
6
185456fa
Typical perFormance characTerisTics
LTC1855 Typical INL Curve
LTC1855 Typical DNL Curve
LTC1855 Nonaveraged
4096-Point FFT Plot
LTC1854 Typical INL Curve
LTC1854 Typical DNL Curve
LTC1854 Nonaveraged
4096-Point FFT Plot
LTC1856 Typical INL Curve
LTC1856 Typical DNL Curve
LTC1856 Nonaveraged
4096-Point FFT Plot
CODE
–32768
INL (LSB)
0
0.5
1.0
32767
185456 G01
–0.5
–1.0
–2.0 –16384 016384
–1.5
2.0
1.5
CODE
–32768
DNL (LSB)
0
0.5
1.0
32767
185456 G02
–0.5
–1.0
–2.0 –16384 016384
–1.5
2.0
1.5
FREQUENCY (kHz)
0 15 25 50
185456 G03
5 10 20 30 40 45
35
MAGNITUDE (dB)
–60
–40
–20
0
–80
–100
–70
–50
–30
–10
–90
–110
–130
–120
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 87dB
THD = –101dB
CODE
–8192
INL (LSB)
0
0.4
0.2
0.6
8191
185455 G04
–0.2
–0.6
–0.4
–1
–4096 04096
–0.8
1
0.8
CODE
–8192
DNL (LSB)
0
0.4
0.2
0.6
8191
185456 G05
–0.2
–0.4
–1
–4096 04096
–0.6
–0.8
1
0.8
FREQUENCY (kHz)
0 15 25 50
185456 G06
5 10 20 30 40 45
35
MAGNITUDE (dB)
–60
–40
–20
0
–80
–100
–70
–50
–30
–10
–90
–110
–130
–120
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 83dB
THD = –95dB
CODE
–2048
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
–1024 0
185456 G07
–0.6
0.6
0.8
0.2
1024 2047
CODE
–2048
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
–1024 0
185456 G08
–0.6
0.6
0.8
0.2
1024 2047
FREQUENCY (kHz)
0
MAGNITUDE (dB)
–70
–30
0
40
185456 G09
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120
–130 10 20 30 50
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 73.6dB
THD = –102dB
LTC1854/LTC1855/LTC1856
7
1854565af
Typical perFormance characTerisTics
LTC1855 SINAD
vs Input Frequency
LTC1855 Total Harmonic
Distortion vs Input Frequency
LTC1855 Channel-to-Channel
Offset Error Matching vs
Temperature
LTC1854 SINAD
vs Input Frequency
LTC1854 Total Harmonic
Distortion vs Input Frequency
LTC1854 Channel-to-Channel
Offset Error Matching vs
Temperature
LTC1856 SINAD
vs Input Frequency
LTC1856 Total Harmonic
Distortion vs Input Frequency
LTC1856 Channel-to-Channel
Offset Error Matching vs
Temperature
INPUT FREQUENCY (kHz)
1
74
SINAD (dB)
78
82
90
10 100
185456 G10
86
76
80
88
84
INPUT FREQUENCY (kHz)
1
–110
TOTAL HARMONIC DISTORTION (dB)
–100
–90
–70
10 100
185456 G11
–80
TEMPERATURE (°C)
–50
–1.0
CHANNEL-TO-CHANNEL
OFFSET ERROR MATCHING (LSBs)
–0.5
0
0.5
1.0
–25 0 25 50
185456 G12
75 100
INPUT FREQUENCY (kHz)
1
60
SINAD (dB)
85
10 100
185456 G13
65
70
80
75
INPUT FREQUENCY (kHz)
1
–110
TOTAL HARMONIC DISTORTION (dB)
–100
–90
–60
10 100
185456 G14
–80
–70
TEMPERATURE (°C)
–50
–0.5
CHANNEL-TO-CHANNEL
OFFSET ERROR MATCHING (LSBs)
–0.25
0
0.25
0.5
–25 0 25 50
185456 G15
75 100
INPUT FREQUENCY (kHz)
1
60
SINAD (dB)
65
70
80
10 100
185456 G16
75
INPUT FREQUENCY (kHz)
TOTAL HARMONIC DISTORTION (dB)
–60
–70
–80
185456 G17
–110
–90
–100
100
1 10
TEMPERATURE (°C)
–50
–0.25
ERROR MATCHING (LSB)
–0.15
–0.05
0.05
–25 025 50
185456 G18
75
0.15
0.25
–0.20
–0.10
0
0.10
0.20
100
LTC1854/LTC1855/LTC1856
8
185456fa
Typical perFormance characTerisTics
Internal Reference Voltage
vs Temperature
Change in REFCOMP Voltage
vs Load Current
LTC1856 Power Supply
Feedthrough vs Ripple Frequency
Supply Current vs Supply Voltage Supply Current vs Temperature
LTC1856 Channel-to-Channel Gain
Error Matching vs Temperature
LTC1855 Channel-to-Channel Gain
Error Matching vs Temperature
LTC1854 Channel-to-Channel Gain
Error Matching vs Temperature
TEMPERATURE (°C)
–50
–1.0
CHANNEL-TO-CHANNEL
GAIN ERROR MATCHING (LSBs)
–0.5
0
0.5
1.0
–25 0 25 50
185456 G19
75 100
TEMPERATURE (°C)
–50
–0.5
CHANNEL-TO-CHANNEL
GAIN ERROR MATCHING (LSBs)
–0.25
0
0.25
0.5
–25 0 25 50
185456 G20
75 100
TEMPERATURE (°C)
–50
–0.25
CHANNEL-TO-CHANNEL GAIN
ERROR MATCHING (LSB)
–0.15
–0.05
0.05
–25 025 50
185456 G21
75
0.15
0.25
–0.20
–0.10
0
0.10
0.20
100
TEMPERATURE (°C)
–50
INTERNAL REFERENCE VOLTAGE (V)
25 75
185456 G22
–25 0 50
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480 100
LOAD CURRENT (mA)
–50
–0.04
CHANGE IN REFCOMP VOLTAGE (V)
–0.02
0
0.02
0.04
–40 –30 –20 –10
185456 G23
0 10
RIPPLE FREQUENCY (Hz)
–60
POWER SUPPLY FEEDTHROUGH (dB)
–40
–20
–10
100 10k 100k 1M
185456 G24
–80
1k
–30
–50
–70
fSAMPLE = 100kHz
VRIPPLE = 60mV
SUPPLY VOLTAGE (V)
4.5
SUPPLY CURRENT (mA)
8.0
8.5
5.5
185454 G25
7.5
7.0 4.75 55.25
9.0 fSAMPLE = 100kHz
TEMPERATURE (°C)
–50
7.0
POSITIVE SUPPLY CURRENT (mA)
7.5
8.0
8.5
9.0
–25 0 25 50
185456 G26
75 100
fSAMPLE = 100kHz
LTC1854/LTC1855/LTC1856
9
1854565af
pin FuncTions
COM (Pin 1): Common Input. This is the negative reference
point for all single-ended inputs. It must be free of noise
and is usually connected to the analog ground plane.
CH0 (Pin 2): Analog MUX Input.
CH1 (Pin 3): Analog MUX Input.
CH2 (Pin 4): Analog MUX Input.
CH3 (Pin 5): Analog MUX Input.
CH4 (Pin 6): Analog MUX Input.
CH5 (Pin 7): Analog MUX Input.
CH6 (Pin 8): Analog MUX Input.
CH7 (Pin 9): Analog MUX Input.
MUXOUT+ (Pin 10): Positive MUX Output. Output of the
analog multiplexer. Connect to ADC+ for normal opera-
tion.
MUXOUT– (Pin 11): Negative MUX Output. Output of the
analog multiplexer. Connect to ADC– for normal opera-
tion.
ADC+ (Pin 12): Positive Analog Input to the Analog-to-
Digital Converter.
ADC– (Pin 13): Negative Analog Input to the Analog-to-
Digital Converter.
AGND1 (Pin 14): Analog Ground.
VREF (Pin 15): 2.5V Reference Output. Bypass to analog
ground with a 1µF tantalum capacitor.
REFCOMP (Pin 16): Reference Buffer Output. Bypass to
analog ground with a 10µF tantalum and a 0.1µF ceramic
capacitor. Nominal output voltage is 4.096V.
AGND2 (Pin 17): Analog Ground.
AGND3 (Pin 18): Analog Ground. This is the substrate
connection.
AVDD (Pin 19): 5V Analog Supply. Bypass to analog ground
with a 0.1µF ceramic and a 10µF tantalum capacitor.
DVDD (Pin 20): 5V Digital Supply. Bypass to digital ground
with a 0.1µF ceramic and a 10µF tantalum capacitor.
OVDD (Pin 21): Positive Supply for the Digital Output
Buffers (3V to 5V). Bypass to digital ground with a 0.1µF
ceramic and a 10µF tantalum capacitor.
BUSY (Pin 22): Output shows converter status. It is low
when a conversion is in progress.
SDO (Pin 23): Serial Data Output.
LTC1854/LTC1855/LTC1856
10
185456fa
FuncTional block Diagram
pin FuncTions
DGND (Pin 24): Digital Ground.
SDI (Pin 25): Serial Data Input.
SCK (Pin 26): Serial Data Clock.
RD (Pin 27): Read Input. This active low signal enables
the digital output pin SDO and enables the serial interface,
SDI and SCK are ignored when RD is high.
CONVST (Pin 28): Conversion Start. The ADC starts a
conversion on CONVST’s rising edge.
2.5V
REFERENCE
INTERNAL
CLOCK
1.6384X
4.096V
8k
AGND1
CONTROL
LOGIC
SERIAL I/O
INPUT MUX
AGND3
AGND2REFCOMPVREF
ADC–
MUXOUT+
MUXOUT–ADC+
DGND
AVDD
DV
DD
MUX ADDRESS
DATA OUT
CONVST
19 20
28
25
2
3
9
1
22
26
27
21
23
24181716151312101114
SDI
BUSY
SCK
RD
OVDD
SDO
18545 BD
12-/14-/16-BIT
SAMPLING ADC
+
–
COM
CH7
CH1
•
•
•
CH0
LTC1854/LTC1855/LTC1856
11
1854565af
TesT circuiTs
Timing Diagrams
Load Circuits for Access Timing Load Circuits for Output Float Delay
1k
(A) Hi-Z TO VOH AND VOL TO VOH
25pF
1k
5V
DNDN
(B) Hi-Z TO VOL AND VOH TO VOL
25pF
18545 TC01
1k
(A) VOH TO Hi-Z
25pF
1k
5V
DNDN
(B) VOL TO Hi-Z
25pF
18545 TC02
t1 (For Short Pulse Mode)
t1
CONVST 50%
18545 TD01
50%
t
2
(CONVST to BUSY Delay)
t2
CONVST
BUSY
2.4V
0.4V
18545 TD02
t3, t4, t5 (SCK Timing)
SCK
18545 TD03
t4t5
t3
t
6
(Delay Time, SCK
↓
to SDO Valid)
t7 (Time from Previous Data Remains Valid After SCK↓)
t6
t7
SCK
SDO 2.4V
0.4V
0.4V
18545 TD04
t
8
(SDO Valid After RD
↓
)
t8
RD
SDO 2.4V
0.4V
0.4V
18545 TD05
Hi-Z
t9 (RD↓ to SCK Setup Time)
t9
0.4V
2.4V
18545 TD06
RD
SCK
LTC1854/LTC1855/LTC1856
12
185456fa
Timing Diagrams
t10 (SDI Setup Time Before SCK↑)
t10
SCK
SDI 2.4V
2.4V
0.4V
18545 TD07
t11 (SDI Hold Time After SCK↑)
t11
SCK
SDI 2.4V
2.4V
0.4V
18545 TD08
t
12
(SDO Valid Before BUSY
↑
, RD = 0)
t12
BUSY
SDO 2.4V B15
2.4V
18545 TD09
t13 (BUS Relinquish Time)
t13
RD
SDO
2.4V
18545 TD10
10%
90% Hi-Z
LTC1854/LTC1855/LTC1856
13
1854565af
applicaTions inFormaTion
OVERVIEW
The LTC1854/LTC1855/LTC1856 are innovative, multi-
channel ADCs. The on-chip resistors provide attenuation
and offset for each channel. The precisely trimmed attenua-
tors ensure an accurate input range. Because they precede
the multiplexer, errors due to multiplexer on-resistance
are eliminated.
The input word selects the single ended or differential
inputs for each channel or pair of channels. Overrange
protection is provided for unselected channels. An over-
range condition on an unused channel will not affect the
conversion result on the selected channel.
CONVERSION DETAILS
The LTC1854/LTC1855/LTC1856 use a successive ap-
proximation algorithm and an internal sample-and-hold
circuit to convert an analog signal to a 12-/14-/16-bit serial
output respectively. The ADCs are complete with a precision
reference and an internal clock. The control logic provides
easy interface to microprocessors and DSPs. (Please refer
to the Digital Interface section for the data format.)
The analog signals applied at the MUX input channels are
rescaled by the resistor divider network formed by R1, R2
and R3 as shown below. The rescaled signals appear on
the MUXOUT (Pins 10, 11) which are also connected to
the ADC inputs (Pins 12, 13) under normal operation.
Before starting a conversion, an 8-bit data word is clocked
into the SDI input on the first eight rising SCK edges to
select the MUX address and power down mode. The ADC
enters acquisition mode on the falling edge of the sixth
clock in the 8-bit data word and ends on the rising edge
of the CONVST signal which also starts a conversion (see
Figure 7). A minimum time of 4µs will provide enough time
for the sample-and-hold capacitors to acquire the analog
signal. Once a conversion cycle has begun, it cannot be
restarted.
During the conversion, the internal differential 12-/14-/16-
bit capacitive DAC output is sequenced by the SAR from
the most significant bit (MSB) to the least significant bit
(LSB). The input is successively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a high speed comparator. At
the end of a conversion, the DAC output balances the analog
input (ADC+ – ADC–). The SAR contents (a 12-/14-/16-bit
data word) which represents the difference of ADC+ and
ADC– are loaded into the 12-/14-/16-bit shift register.
DRIVING THE ANALOG INPUTS
The input range for the LTC1854/LTC1855/LTC1856 is
±10V and the MUX inputs are overvoltage protected to
±30V. The input impedance is typically 31kΩ; therefore, it
should be driven with a low impedance source. Wideband
noise coupling into the input can be minimized by placing
a 3000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If
an amplifier is to be used to drive the input, care should
be taken to select an amplifier with adequate accuracy,
linearity and noise for the application. The following list is
a summary of the op amps that are suitable for driving the
LTC1854/LTC1855/LTC1856. More detailed information is
available in the Linear Technology data books and online
at www.linear.com.
LT
®
1007: Low noise precision amplifier. 2.7mA supply
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
MUX
INPUT
R1
25k
REFCOMP
CH SEL
R3
10k
185456 AI01
R2
17k
MUXOUT
LTC1854/LTC1855/LTC1856
14
185456fa
applicaTions inFormaTion
LT1227: 140MHz video current feedback amplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1468/LT1469: Single and dual 90MHz, 16-bit accurate
op amp. Good AC/DC specs. ±5V to ±15V supplies.
LT1677: Single, low noise op amp. Rail-to-rail input and
output. Up to ±15V supplies.
LT1792: Single, low noise JFET input op amp, ±5V sup-
plies.
LT1793: Single, low noise JFET input op amp, 10pA bias
current, ±5V supplies.
LT1881/LT1882: Dual and quad, 200pA bias current, rail-
to-rail output op amps. Up to ±15V supplies.
LT1844/LT1885: Dual and quad, 400pA bias current,
rail-to-rail output op amps. Up to ±15V supplies. Faster
response and settling time.
INTERNAL VOLTAGE REFERENCE
The LTC1854/LTC1855/LTC1856 have an on-chip, tem-
perature compensated, curvature corrected, bandgap
reference, which is factory trimmed to 2.50V. The full-scale
range of the LTC1854/LTC1855/LTC1856 is equal to ±10V.
The output of the reference is connected to the input of a
gain of 1.6384x buffer through an 8k resistor (see Figure
3). The input to the buffer or the output of the reference
Figure 2. Analog Input Filtering
Figure 1. LTC1854/LTC1855/LTC1856 Simplified Equivalent Circuit
2.5V
REFERENCE
INTERNAL
CLOCK
1.6384X
4.096V
8k
AGND1
CONTROL
LOGIC
SERIAL I/O
INPUT MUX
AGND3
AGND2REFCOMPVREF
ADC–
MUXOUT+
MUXOUT–ADC+
DGND
AVDD DVDD
MUX ADDRESS
DATA OUT
CONVST
SDI
BUSY
SCK
RD
OVDD
SDO
18545 F01
12-/14-/16-BIT
SAMPLING ADC
+
–
COM
CH7
CH1
•
•
•
CH0
3000pF
18545 F02
AIN+
AIN–
CH0
CH1
MUXOUT+
MUXOUT–
ADC+
ADC–
•
•
•
•
LTC1854/LTC1855/LTC1856
15
1854565af
applicaTions inFormaTion
is available at VREF (Pin 15). The internal reference can be
overdriven with an external reference if more accuracy is
needed. The buffer output drives the internal DAC and is
available at REFCOMP (Pin 16). The REFCOMP pin can be
used to drive a steady DC load of less than 2mA. Driving
an AC load is not recommended because it can cause the
performance of the converter to degrade.
For minimum code transition noise the VREF pin and the
REFCOMP pin should each be decoupled with a capacitor to
filter wideband noise from the reference and the buffer.
FULL SCALE AND OFFSET
Figure 4 shows the ideal input/output characteristics for
the LTC1856. The code transitions occur midway be-
tween successive integer LSB values (i.e., –FS+0.5LSB,
–FS+1.5LSB, –FS+2.5LSB, … FS–1.5LSB, FS–0.5LSB).
The output is two’s complement binary with:
1 LSB =FS −(−FS)
65566
=20V
65536
=305.2µV
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero during a
calibration sequence. Offset error must be adjusted before
full-scale error. Zero offset is achieved by adjusting the
offset applied to the “–” input. For single-ended inputs, this
offset should be applied to the COM pin. For differential
inputs, the “–” input is dictated by the MUX address.
For zero offset error, apply –0.5LSB to the “+” input and
adjust the offset at the “–” input until the output code flick-
ers between 0000 0000 0000 0000 and 1111 1111 1111
1111 for the LTC1856, between 00 0000 0000 0000 and
11 1111 1111 1111 for the LTC1855 and between 0000
0000 0000 and 1111 1111 1111 for the LTC1854.
For full-scale adjustment, an input voltage of FS – 1.5LSBs
should be applied to the “+” input and the appropriate
reference adjusted until the output code flickers between
0111 1111 1111 1110 and 0111 1111 1111 1111 for the
LTC1856, between 01 1111 1111 1110 and 01 1111 1111
1111 for the LTC1855 and between 0111 1111 1110 and
0111 1111 1111 for the LTC1854.
These adjustments as well as the factory trims affect all
channels. The channel-to-channel offset and gain error
matching are guaranteed by design to meet the specifica-
tions in the Converter Characteristics table.
Figure 3. Internal or External Reference Source
Figure 4. Bipolar Transfer Characteristics
2.5V
REFERENCE
18545 F03
12-/14-/16-BIT
CAPACITIVE DAC
1.6384X BUFFER
8k
VREF
1µF
15
2.5V
16 REFCOMP
0.1µF
4.096V
10µF
185456 F04
011...111
011...110
000...001
000...000
111...111
111...110
100...001
100...000
FS – 1LSB
–(FS – 1LSB)
INPUT VOLTAGE (V)
OUTPUT CODE
LTC1854/LTC1855/LTC1856
16
185456fa
applicaTions inFormaTion
DC PERFORMANCE
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where
a DC signal is applied to the input of the MUX and the
resulting output codes are collected over a large number
of conversions. For example in Figure 5 the distribution
of output code is shown for a DC input that has been
digitized 4096 times. The distribution is Gaussian and the
RMS code transition is about 1LSB for the LTC1856.
DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 4µs. No external adjustments
are required and, with the maximum acquisition time of
4µs, throughput performance of 100ksps is assured.
3V Input/Output Compatible
The LTC1854/LTC1855/LTC1856 operate on a 5V supply,
which makes the devices easy to interface to 5V digital
systems. These devices can also interface to 3V digital
systems: the digital input pins (SCK, SDI, CONVST and
RD) of the LTC1854/LTC1855/LTC1856 recognize 3V or 5V
inputs. The LTC1854/LTC1855/LTC1856 have a dedicated
output supply pin (OVDD) that controls the output swings
of the digital output pins (SDO, BUSY) and allows the part
to interface to either 3V or 5V digital systems. The SDO
output is two’s complement.
Timing and Control
Conversion start and data read are controlled by two digital
inputs: CONVST and RD. To start a conversion and put the
sample-and-hold into the hold mode bring CONVST high
for at least 40ns. Once initiated it cannot be restarted until
the conversion is complete. Converter status is indicated
by the BUSY output, which goes low while the conversion
is in progress.
Figures 6a and 6b show two different modes of opera-
tion for the LTC1856. For the 12-bit LTC1854 and 14-bit
LTC1855, the last four and two bits of the SDO will output
zeros, respectively. In mode 1 (Figure 6a), RD is tied low.
The rising edge of CONVST starts the conversion. The data
outputs are always enabled. The MSB of the data output
is available after the conversion. In mode 2 (Figure 6b),
CONVST and RD are tied together. The rising edge of the
CONVST signal starts the conversion. Data outputs are in
three-state at this time. When the conversion is complete
(BUSY goes high), CONVST and RD go low to enable the
data output for the previous conversion.
Figure 5. LTC1856 Histogram for 4096 Conversions
CODE
–4 –3
0
COUNT
200
600
800
1000
2 3
1800
185456 F05
400
–2 –1 0 1 4
1200
1400
1600
LTC1854/LTC1855/LTC1856
17
1854565af
applicaTions inFormaTion
Figure 6a. Mode 1 for the LTC1856*. CONVST Starts a Conversion, Data Output is Always Enabled (RD = 0)
SGL/
DIFF
1
t4
RD = 0
SCK
SDI
SDO
CONVST
BUSY
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0X X NAP SLEEP DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 B1 B0
tACQ
t7
t6
t2
tCONV
t1
t10 t11
SHIFT CONFIGURATION WORD IN
SGL/
DIFF
1 2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0X X NAP SLEEP DON’T CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 B1 B0
18545 F06a
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
t5
t3
t12 t12
SGL/
DIFF
1
t4
CONVST = RD
SCK
SDI
Hi-Z
SDO
BUSY
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0X X NAP SLEEP DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8
tACQ
t13
t2
tCONV
Hi-Z
t10 t11
SHIFT CONFIGURATION WORD IN
SGL/
DIFF
1 2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0X X NAP SLEEP DON’T CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 Hi-Z
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
t5
t3
t9
t8
t7
t6
185456 F06b
B1 B0 B1 B0
SGL/
DIFF
1
t4
RD
SCK
SDI
Hi-Z
SDO
BUSY
CONVST
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0X X NAP SLEEP DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8
tACQ
t13
t2
t1
tCONV
Hi-Z
t10 t11
SHIFT CONFIGURATION WORD IN
SGL/
DIFF
1 2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0X X NAP SLEEP DON’T CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 Hi-Z
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
t5
t3
t9
t8
t7
t6
185456 F07
B1 B0 B1 B0
Figure 6b. Mode 2 for the LTC1856*. CONVST and RD Tied Together. CONVST Starts a Conversion, Data is Read by RD
Figure 7. Operating Sequence for the LTC1856*
*For the 12-bit LTC1854 and the LTC1855 the last four and two bits of the SDO will output zeros, respectively.
LTC1854/LTC1855/LTC1856
18
185456fa
applicaTions inFormaTion
SERIAL DATA INPUT (SDI) INTERFACE
The
LTC1854/LTC1855/LTC1856
communicate with micro-
processors and other external circuitry via a synchronous,
full duplex, 3-wire serial interface (see Figure 7). The shift
clock (SCK) synchronizes the data transfer with each bit
being transmitted on the falling SCK edge and captured
on the rising SCK edge in both transmitting and receiving
systems. The data is transmitted and received simultane-
ously (full duplex).
An 8-bit input word is shifted into the SDI input which
configures the LTC1854/LTC1855
/LTC1856
for the next
conversion. Simultaneously, the result of the previous
conversion is output on the SDO line. At the end of the
data exchange the requested conversion begins by ap-
plying a rising edge on CONVST. After tCONV, the conver-
sion is complete and the results will be available on the
next data transfer cycle. As shown below, the result of a
conversion is delayed by one conversion from the input
word requesting it.
INPUT DATA WORD
The LTC1854/LTC1855/LTC1856 8-bit data word is clocked
into the SDI input on the first eight rising SCK edges. Fur-
ther inputs on the SDI pin are then ignored until the next
conversion. The eight bits of the input word are defined
as follows:
SDI
SDO SDO WORD 0
SDI WORD 1
DATA
TRANSFER
SDO WORD 2
SDI WORD 3
SDO WORD 1
SDI WORD 2
DATA
TRANSFER
tCONV
A/D
CONVERSION
tCONV
A/D
CONVERSION
185456 AI02
SGL/
DIFF
SELECT
1
SELECT
0
DON'T
CARE
DON'T
CARE
MUX ADDRESS
185456 AI03
ODD
SIGN NAP
POWER DOWN
SELECTION
SLEEP
Table 1. Multiplexer Channel Selection
MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION MUX ADDRESS SINGLE-ENDED CHANNEL SELECTION
SGL/
DIFF
ODD
SIGN
SELECT
1 0 01234567SGL/
DIFF
ODD
SIGN
SELECT
1 0 0 1 2 3 4 5 6 7 COM
0 0 0 0 + – 1 0 0 0 + –
0 0 0 1 + – 1 0 0 1 + –
0 0 1 0 + – 1 0 1 0 + –
0 0 1 1 + – 1 0 1 1 + –
0 1 0 0 – + 1 1 0 0 + –
0 1 0 1 – + 1 1 0 1 + –
0 1 1 0 – + 1 1 1 0 + –
0 1 1 1 – + 1 1 1 1 + –
Figure 8. Examples of Multiplexer Options on the LTC1854/LTC1855/LTC1856
0
1
2
3
4
5
6
7
CHANNEL
COM (–)
8 Single-Ended
+
+
+
+
+
+
+
0,1
CHANNEL
4 Differential
2,3
4,5
6,7
+ (–)+
+ (–)
+ (–)
+ (–)
– (+)
– (+)
– (+)
– (+)
4
5
6
7
CHANNEL
COM (–)
Combinations of
Differential and Single-Ended
+
+
+
+
+
+
0,1
2,3
–
–
COM (UNUSED)
Changing the
MUX Assignment “On the Fly”
COM (–)
4,5
6,7
4,5
1ST CONVERSION 2ND CONVERSION
+
–
+
–
+
–
+
+
7
6
{
{
{
{
{{
{
{
{
18545 F08
LTC1854/LTC1855/LTC1856
19
1854565af
applicaTions inFormaTion
MUX ADDRESS
The first four bits of the input word assign the MUX
configuration for the requested conversion. For a given
channel selection, the converter will measure the voltage
between the two channels indicated by the + and – signs in
the selected row of Table 1. Note that in differential mode
(SGL/DIFF = 0) measurements are limited to four adjacent
input pairs with either polarity. In single-ended mode, all
input channels are measured with respect to COM. Both
the “+” and “–” inputs are sampled simultaneously so
common mode noise is rejected. Bits 5 and 6 of the input
words are Don’t Care bits.
P
OWER DOWN SELECTION (NAP, SLEEP)
The last two bits of the input word (Nap and Sleep) deter-
mine the power shutdown mode of the LTC1854/LTC1855/
LTC1856. See Table 2. Nap mode is selected when Nap =
1 and Sleep = 0. The previous conversion result will be
clocked out and a conversion will occur before entering
the Nap mode. The Nap mode starts at the end of the
conversion which is indicated by the rising edge of the
BUSY signal. Nap mode lasts until the falling edge of the
2nd SCK (see Figure 9). Automatic nap will be achieved
if Nap = 1 is selected each time an input word is written
to the ADC.
Table 2. Power Down Selection
NAP SLEEP POWER DOWN MODE
0 0 Power On
1 0 Nap
X 1 Sleep
Sleep mode will occur when Sleep = 1 is selected,
regardless of the selection of the Nap input. The previ-
ous conversion result can be clocked out and the Sleep
mode will start on the falling edge of the last (16th) SCK.
Notice that the CONVST should stay either high or low in
sleep mode (see Figure 10). To wake up from the sleep
mode, apply a rising edge on the CONVST signal and
then apply Sleep = 0 on the next SDI word and the part
will wake up on the falling edge of the last (16th) SCK
(see Figure 11).
In Sleep mode, all bias currents are shut down and only the
power on reset circuit and leakage currents (about 10µA)
remain. Sleep mode wake-up time is dependent on the value
of the capacitor connected to the REFCOMP (Pin 16). The
wake-up time is typically 40ms with the recommended
10µF capacitor connected on the REFCOMP pin.
DYNAMIC PERFORMANCE
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental. Figure 12 shows
a typical
LTC1856
FFT plot which yields a SINAD of 87dB
and THD of –101dB.
LTC1854/LTC1855/LTC1856
20
185456fa
applicaTions inFormaTion
Figure 9. Nap Mode Operation for the LTC1856*
Figure 10. Sleep Mode Operation for the LTC1856*
Figure 11. Wake Up from Sleep Mode for the LTC1856*
*For the 12-bit LTC1854 and the LTC1855 the last four and two bits of the SDO will output zeros, respectively.
SGL/
DIFF
1
RD
SCK
SDI
Hi-Z
SDO
BUSY
CONVST
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0X X NAP = 1 SLEEP = 0 DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8
t
CONV
Hi-Z
NAPt
ACQ
t
ACQ
SHIFT CONFIGURATION WORD IN
SGL/
DIFF
1 2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0X X NAP SLEEP DON’T CARE
B14 B13 B12B15 MSB B11 B10 B9 B8 Hi-Z
SHIFT A/D RESULT OUT FROM PREVIOUS CONVERSION AND NEW CONFIGURATION WORD IN
18545 F09
B1 B0B1 B0
SGL/
DIFF
1
RD
SCK
SDI
SDO
BUSY
CONVST
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0X X NAP SLEEP = 1 DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8
SHIFT SLEEP CONFIGURATION WORD IN
A/D RESULT FROM PREVIOUS CONVERSION
CONVST SHOULD STAY EITHER HIGH OR LOW IN SLEEP MODE
tCONV
SLEEP
18545 F10
B1 B0
SGL/
DIFF
1
RD
SCK
SDI
SDO
BUSY
CONVST
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0X X NAP SLEEP = 0 DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8
WAKE-UP
TIME
READY
tCONV
SLEEP
SHIFT WAKE-UP CONFIGURATION WORD IN
SGL/
DIFF
1 2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0X X NAP SLEEP DON’T CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8
A/D RESULT NOT VALID
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
tCONV
18545 F11
B1 B0 B1 B0
LTC1854/LTC1855/LTC1856
21
1854565af
applicaTions inFormaTion
SIGNAL-TO-NOISE AND DISTORTION RATIO
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 12 shows a typical SINAD of 87dB with
a 100kHz sampling rate and a 1kHz input.
TOTAL HARMONIC DISTORTION
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = 20log V22+V32+V42...+VN2
V
1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through Nth harmonics.
BOARD LAYOUT, POWER SUPPLIES
AND DECOUPLING
Wire wrap boards are not recommended for high reso-
lution or high speed A/D converters. To obtain the best
performance from the
LTC1854/LTC1855/LTC1856
, a
printed circuit board is required. Layout for the printed
circuit board should ensure the digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
In applications where the MUX is connected to the ADC, it is
possible to get noise coupling into the ADC from the trace
connecting the MUXOUT to the ADC. Therefore, reducing
the length of the traces connecting the MUXOUT pins (Pins
10, 11) to the ADC pins (Pins 12, 13) can minimize the
problem. The unused MUX inputs should be grounded to
prevent noise coupling into the inputs.
Figure 13 shows the power supply grounding that will help
obtain the best performance from the 12-bit/14-bit/16-bit
ADCs. Pay particular attention to the design of the analog
and digital ground planes. The DGND pin of the
LTC1854/
Figure 12. LTC1856 Nonaveraged 4096 Point FFT Plot
FREQUENCY (kHz)
0 15 25 50
185456 F12
5 10 20 30 40 45
35
MAGNITUDE (dB)
–60
–40
–20
0
–80
–100
–70
–50
–30
–10
–90
–110
–130
–120
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 87dB
THD = –101dB
LTC1854/LTC1855/LTC1856
22
185456fa
applicaTions inFormaTion
LTC1855/LTC1856
can be tied to the analog ground plane.
Placing the bypass capacitor as close as possible to the
power supply pins, the reference and reference buffer out-
put is very important. Low impedance common returns for
these bypass capacitors are essential to low noise operation
of the ADC, and the foil width for these tracks should be
as wide as possible. Also, since any potential difference in
grounds between the signal source and ADC appears as
an error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedance
as much as possible. The digital output latches and the
onboard sampling clock have been placed on the digital
ground plane. The two ground planes are tied together at
the ADC through a wide, low inductance path.
Figure 13. Power Supply Grounding Practice
18545 F13
ADC+
LTC1854/LTC1855/LTC1856 DIGITAL
SYSTEM
OVDD
DGND
24 21
ADC–
10µF
DVDD
20
10µF
AVDD
19
AGND
14, 17, 18
10µF
REFCOMP
16
10µF
VREF
15
12
MUXOUT+
LTC1854/
LTC1855/
LTC1856
MUXOUT–
10
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
11 13
1µF
ANALOG GROUND PLANE
DIGITAL
GROUND PLANE
+
–
LTC1854/LTC1855/LTC1856
23
1854565af
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
G28 SSOP 0204
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
12345678910 11 12 1413
9.90 – 10.50*
(.390 – .413)
2526 22 21 20 19 18 17 16 1523242728
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
LTC1854/LTC1855/LTC1856
24
185456fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2006
LT 0407 REV A • PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
Sampling ADCs
LTC1418 14-Bit, 200ksps, Single 5V or ±5V ADC 15mW, Serial/Parallel I/O
LTC1604 16-Bit, 333ksps, ±5V ADC 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608
LTC1605 16-Bit, 100ksps, Single 5V ADC ±10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606
LTC1606 16-Bit, 250ksps, Single 5V ADC ±10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605
LTC1608 16-Bit, 500ksps, ±5V ADC 90dB SINAD, 270mW Power Dissipation, Pin Compatible with LTC1604
LTC1609 16-Bit, 200ksps Serial ADC Configurable Unipolar/Bipolar Input, Up to 10V Single 5V Supply
LTC1850/LTC1851 10-Bit/12-Bit, 8-Channel, 1.25Msps ADC Programmable MUX and Sequencer, Parallel I/O
LTC1859/LTC1858/
LTC1857
16-Bit, 14-Bit, 12-Bit, 100ksps, SoftSpan ADCs Software-Selectable Spans, Pin Compatible with
LTC1864/LTC1865 16-Bit, 1-/2-Channel, 250ksps ADC in MSOP Single 5V Supply, 850µA with Autoshutdown
LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP Single 3V Supply, 450µA with Autoshutdown
LTC1856/LTC1855/LTC1854
DACs
LTC1588/LTC1589
LTC1592
12-/14-/16-Bit, Serial, SoftSpan IOUT DACs Software-Selectable Spans, ±1LSB INL/DNL
LTC1595 16-Bit Serial Multiplying IOUT DAC in SO-8 ± 1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
LTC1596 16-Bit Serial Multiplying IOUT DAC ±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade
LTC1597 16-Bit Parallel, Multiplying DAC ±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors
LTC1650 16-Bit Serial VOUT ±5V DAC Low Power, Low Glitch, 4-Quadrant Multiplication
LTC2704-16/
LTC2704-14/
LTC2704-12
16-Bit, 14-Bit, 12-Bit, Serial, Quad SoftSpan
VOUT DACs
Software-Selectable Spans, ±2LSB INL, ±1LSB INL,
Force/Sense Output
2.5V
REFERENCE
INTERNAL
CLOCK
1.6384X
4.096V
8k
AGND1
CONTROL
LOGIC
SERIAL I/O
INPUT MUX
AGND3
AGND2
REFCOMP
VREF
ADC–
MUXOUT+
MUXOUT–ADC+DGND
AVDD DVDD
MUX ADDRESS
DATA OUT
CONVST 28
25
22
26
27
21
23
3V TO 5V
SDI
BUSY
SCK
RD
OVDD
SDO
18545 TA03
12-/14-/16-BIT
SAMPLING ADC
+
–
COM
19 20
5V
5V
1
2
3
9CH7
14 11 10 12 13 15 16 17 18 24
1µF 0.1µF
CH1
SINGLE-ENDED
OR DIFFERENTIAL
CHANNEL
SELECTION
(SEE TABLE 1)
INPUT RANGE:
±10V
•
•
•
CH0
10µF
0.1µF10µF
8-BIT SERIAL
DATA INPUT
16 SHIFT CLOCK CYCLES
16-BIT SERIAL DATA OUT
10µF 0.1µF
10µF 0.1µF