MC100E221FNR2 - ON Semiconductor L.L.C.

 Semiconductor Components Industries, LLC, 2004

March, 2004 − Rev. 8 503 Publication Order Number:

MC10E211/D

MC10E211, MC100E211

5VECL 1:6 Differential

Clock Distribution Chip

The MC10E/100E211 is a low skew 1:6 fanout device designed

explicitly for low skew clock distribution applications.

The E211 features a multiplexed clock input to allow for the

distribution o f a l ower s peed s can o r t est clock a long w ith t he high s peed

system clock. When LOW (or left open in which case it will be pulled

LOW by the input pulldown resistor) the SEL pin will select the

differential clock input.

Both a common enable and individual output enables are provided.

When asserted the positive output will go LOW on the next negative

transition of the CLK (or SCLK) input. The enabling function is

synchronous so that the outputs will only be enabled/disabled when the

outputs are already in the LOW state. In this way the problem of runt

pulse generation during the disable operation is avoided. Note that the

internal flip flop is clocked on the falling edge of the input clock edge,

therefore all associated specifications are referenced to the negative

edge of the CLK input.

The output transitions of the E211 are faster than the standard

ECLinPS edge rates. This feature provides a means of distributing

higher frequency signals than c apable w ith t he E111 device. B ecause o f

these edge rates and the tight skew limits guaranteed in the

specification, there are certain termination guidelines which must be

followed. For more details on the recommended termination schemes

please refer to the applications information section of this data sheet.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single−ended input conditions, the unused

differential input is connected to VBB as a switching reference v oltage.

VBB may a lso r ebias A C c oupled i nputs. W hen u sed, d ecouple V BB and

VCC via a 0.01 F capacitor and limit current sourcing or sinking to

0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

•Guaranteed Low Skew Specification

•Synchronous Enabling/Disabling

•Multiplexed Clock Inputs

•VBB Output for Single−Ended Use

•Common and Individual Enable/Disable Control

•High Bandwidth Output Transistors

•PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V

•NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V

•Internal Input 75 k Pulldown Resistors

•ESD Protection: Human Body Model; > 2 kV,

Machine Model; > 100 V

•Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

•Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

•Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

•Transistor Count = 457 devices

MARKING

DIAGRAMS

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

PLCC−28

FN SUFFIX

CASE 776

MC10E211FN

AWLYYWW

MC100E211FN

AWLYYWW

128

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See detailed ordering and shipping information in the package

dimensions section on page 511 of this data sheet.

ORDERING INFORMATION

MC10E211, MC100E211

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504

EN1

EN4 EN5 VCC0 Q5 Q5 Q4 Q4

VCC

Q0VCC0

EN0

EN2

CEN

VBB

CLK

VEE

SCLK

SEL

EN3

25 24 23 22 21 20 19

11109

Figure 10. Pinout: PLCC−28 (Top View)

Warning: All VCC, VCCO, and VEE pins must be externally con-

nected to Power Supply to guarantee proper operation.

*All VCC and VCCO pins are tied together on the die.

VBB

SEL

CEN

EN5

EN1−4

SCLK

CLK

EN0

BITS 1−4

Q1−4

Figure 11. Logic Diagram

Table 1. PIN DESCRIPTION

PIN FUNCTION

EN0−EN5

SEL

SCLK

CLK, CLK

CEN

Q0−Q5, Q0−Q5

VBB

VCC, VCCO

VEE

ECL Enable

ECL Select (Clock)

ECL Single Clock

ECL Differential Clock

ECL Common Enable

ECL Differential Outputs

Reference Voltage Output

Positive Supply

Negative Supply

No Connect

Table 2. FUNCTION TABLE

CLK SCLK SEL ENx Q

H/L

CLK

SCLK

*Z = Negative transition of CLK or SCLK

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Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Mode Power Supply VEE = 0 V 8 V

VEE NECL Mode Power Supply VCC = 0 V −8 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage VEE = 0 V

VCC = 0 V VI  VCC

VI  VEE 6

−6 V

Iout Output Current Continuous

Surge 50

100 mA

IBB VBB Sink/Source ± 0.5 mA

TAOperating Temperature Range 0 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

JA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm PLCC−28

PLCC−28 63.5

43.5 °C/W

°C/W

JC Thermal Resistance (Junction−to−Case) Standard Board PLCC−28 22 to 26 °C/W

VEE PECL Operating Range

NECL Operating Range 4.2 to 5.7

−5.7 to −4.2 V

Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

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Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 2)

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 119 160 119 160 119 160 mA

VOH Output HIGH Voltage (Note 3) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mV

VOL Output LOW Voltage (Note 3) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mV

VIH Input HIGH Voltage (Single−Ended) 3830 3995 4160 3870 4030 4190 3940 4110 4280 mV

VIL Input LOW Voltage (Single−Ended) 3050 3285 3520 3050 3285 3520 3050 3302 3555 mV

VBB Output Voltage Reference 3.62 3.74 3.65 3.75 3.69 3.81 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 4)

2.4 4.6 2.4 4.6 2.4 4.6 V

IIH Input HIGH Current 150 150 150 A

IIL Input LOW Current 0.5 0.3 0.5 0.25 0.3 0.2 A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification

limit values are applied individually under normal operating conditions and not valid simultaneously.

2. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.

3. Outputs are terminated through a 50  resistor to VCC − 2.0 V.

4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VE E= −5.0 V (Note 5)

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 119 160 119 160 119 160 mA

VOH Output HIGH Voltage (Note 6) −1020 −930 −840 −980 −895 −810 −910 −815 −720 mV

VOL Output LOW Voltage (Note 6) −1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595 mV

VIH Input HIGH Voltage (Single−Ended) −1170 −1005 −840 −1130 −970 −810 −1060 −890 −720 mV

VIL Input LOW Voltage (Single−Ended) −1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445 mV

VBB Output Voltage Reference −1.38 −1.27 −1.35 −1.25 −1.31 −1.19 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 7)

−2.6 −0.4 −2.6 −0.4 −2.6 −0.4 V

IIH Input HIGH Current 150 150 150 A

IIL Input LOW Current 0.5 0.3 0.5 0.065 0.3 0.2 A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification

limit values are applied individually under normal operating conditions and not valid simultaneously.

5. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.

6. Outputs are terminated through a 50  resistor to VCC − 2.0 V.

7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

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Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 8)

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 119 160 119 160 137 164 mA

VOH Output HIGH Voltage (Note 9) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mV

VOL Output LOW Voltage (Note 9) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mV

VIH Input HIGH Voltage (Single−Ended) 3835 3975 4120 3835 3975 4120 3835 3975 4120 mV

VIL Input LOW Voltage (Single−Ended) 3190 3355 3525 3190 3355 3525 3190 3355 3525 mV

VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 10)

2.4 4.6 2.4 4.6 2.4 4.6 V

IIH Input HIGH Current 150 150 150 A

IIL Input LOW Current 0.5 0.3 0.5 0.25 0.5 0.2 A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification

limit values are applied individually under normal operating conditions and not valid simultaneously.

8. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.

9. Outputs are terminated through a 50  resistor to VCC − 2.0 V.

10.VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= −5.0 V (Note 11)

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 119 160 119 160 137 164 mA

VOH Output HIGH Voltage (Note 12) −1025 −950 −880 −1025 −950 −880 −1025 −950 −880 mV

VOL Output LOW Voltage (Note 12) −1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620 mV

VIH Input HIGH Voltage (Single−Ended) −1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV

VIL Input LOW Voltage (Single−Ended) −1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV

VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 13)

−2.6 −0.4 −2.6 −0.4 −2.6 −0.4 V

IIH Input HIGH Current 150 150 150 A

IIL Input LOW Current 0.5 0.3 0.5 0.25 0.5 0.2 A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification

limit values are applied individually under normal operating conditions and not valid simultaneously.

11.Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.

12.Outputs are terminated through a 50  resistor to VCC − 2.0 V.

13.VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

MC10E211, MC100E211

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Table 8. AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= −5.0 V (Note 14)

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

fMAX Maximum Toggle Frequency 700 700 700 MHz

tPLH

tPHL Propagation Delay to Output

CLK to Q (Diff)

CLK to Q (SE)

SCLK to Q

SEL to Q

795

745

650

745

930

900

970

1065

1115

1085

1195

805

755

650

755

940

910

980

1075

1125

1095

1205

825

775

650

775

960

930

1000

1095

1145

1115

1225

tPHL Disable Time

CLK or SCLK to Q (Note 16) 600 800 600 800 600 800 ps

tskew Part−to−Part Skew CLK (Diff) to Q

CLK (SE), SCLK to Q

Within−Device Skew (Note 15) 50

270

370

75 50

270

370

270

370

tJITTER Random Clock Jitter (RMS) < 1 < 1 < 1 ps

tsSetup Time ENx to CLK

CEN to CLK (Note 16) 200

200 −100

0200

200 −100

0200

200 −100

thHold Time

CLK to ENx, CEN (Note 16) 900 600 900 160 900 600 ps

VPP Minimum Input Swing (CLK) (Note 17) 0.25 1.0 0.25 1.0 0.25 1.0 V

tfRise/Fall Times

(20 − 80%) 150 400 150 400 150 400 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification

limit values are applied individually under normal operating conditions and not valid simultaneously.

14.10 Series: VEE can vary −0.46 V / +0.06 V.

100 Series: VEE can vary −0.46 V / +0.8 V.

15.Within−Device skew is defined for identical transitions on similar paths through a device.

16.Setup, Hold and Disable times are all relative to a falling edge on CLK or SCLK.

17.Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50 mV input swings.

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509

APPLICATIONS INFORMATION

General Description

The MC10E/100E211 is a 1:6 fanout tree designed

explicitly for low skew high speed clock distribution. The

device was targeted to work in conjunction with the E111

device to provide another level of flexibility in the design

and implementation of clock distribution trees. The

individual synchronous enable controls and multiplexed

clock inputs make the device ideal as the first level

distribution unit in a distribution tree. The device provides

the ability to distribute a lower speed scan or test clock along

with the high speed system clock to ease the design of system

diagnostics and self test procedures. The individual enables

could be used to allow for the disabling of individual cards

on a backplane in fault tolerant designs.

Because of lower fanout and larger skews the E211 will

not likely be used as an alternative to the E111 for the bulk

of the clock fanout generation. Figure 12 shows a typical

application combining the two devices to take advantage of

the strengths of each.

Figure 12. Standard E211 Application

E111

E211

E111

BACKPLANE

Using the E211 in PECL Designs

The E211 device can be utilized very effectively in

designs utilizing only a +5 V power supply. Since the

internal switching reference levels are biased of f o f the VCC

supply the input thresholds for the single−ended inputs will

vary with VCC. As a result the single−ended inputs should be

driven by a device on the same board as the E211. Driving

these inputs across a backplane where significant

differences between the VCC’s of the transmitter and

receiver can occur can lead to AC performance and/or

significant noise margin degradations. Because the

differential I/O does not use a switching reference, and due

to the CMR range of the E211, even under worst case VCC

situations between cards there will be no AC performance or

noise margin loss for the differential CLK inputs.

For situations where TTL clocks are required the E211 can

be interfaced with the H641 or H643 ECL to TTL Clock

Distribution Chips. The H641 is a single supply 1:9 PECL

to TTL device while the H643 is a 1:8 dual supply standard

ECL to TTL device. By combining the superior skew

performance of the E211, or E111, with the low skew

translating capabilities of the H641 and H643 very low skew

TTL clock distribution networks can be realized.

Handling Open Inputs and Outputs

All of the input pins of the E211 have a 50 k to 75 k

pulldown resistor to pull the input to VEE when left open.

This feature can cause a problem if the differential clock

inputs are left open as the input gate current source transistor

will become saturated. Under these conditions the outputs of

the CLK input buffer will go to an undefined state. It is

recommended, if possible,that the SCLK input should be

selected any time the differential CLK inputs are allowed to

float. The SCLK buffer, under open input conditions, will

maintain a defined output state and thus the Q outputs of the

device will be in a defined state (Q = LOW). Note that if all

of the inputs are left open the differential CLK input will be

selected and the state of the Q outputs will be undefined.

With the simultaneous switching characteristics and the

tight skew specifications of the E211 the handling of the

unused outputs becomes critical. To minimize the noise

generated on the die all outputs should be terminated in

pairs, i.e. both the true and compliment outputs should be

terminated even if only one of the outputs will be used in the

system. With both complimentary pairs terminated the

current in the VCC pins will remain essentially constant and

thus inductance induced voltage glitches on VCC will not

occur. VCC glitches will result in distorted output

waveforms and degradations in the skew performance of the

device.

The package parasitics of the PLCC−28 cause the signals

on a given pin to be influenced by signals on adjacent pins.

The E211 is characterized and tested with all of the outputs

switching, therefore the numbers in the data book are

guaranteed only for this situation. If all of the outputs of the

E211 are not needed and there is a desire to save power the

unused output pairs can be left unterminated. Unterminated

outputs can influence the propagation delay on adjacent pins

by 15 ps − 20 ps. Therefore under these conditions this 15 ps

− 20 ps needs to be added to the overall skew of the device.

Pins which are separated by a package corner are not

considered adjacent pins in the context of propagation delay

influence. Therefore as long as all of the outputs on a single

side of the package are terminated the specification limits in

the data sheet will apply.

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APPLICATIONS INFORMATION

Differential versus Single−Ended Use

As can be seen from the data sheet, to minimize the skew

of the E21 1 the device must be used in the differential mode.

In the single−ended mode the propagation delays are

dependent on the relative position of the VBB switching

reference. Any VBB o f fset from the center of the input swing

will add delay to either the T PLH or TPHL and subtract delay

from the other. This increase and decrease in delay will lead

to an increase in the duty cycle skew and thus part−to−part

skew. The within−device skew will be independent of the

VBB and therefore will be the same regardless of whether the

device is driven differentially or single−ended.

For applications where part−to−part skew or duty cycle

skew are not important the advantages of single−ended

clock distribution may lead to its use. Using single−ended

interconnect will reduce the number of signal traces to be

routed, but remember that all of the complimentary outputs

still need to be terminated therefore there will be no

reduction in the termination components required. To use

the E211 with a single−ended input the arrangement pictured

in Figure 14 should be used. If the input to the differential

CLK inputs are AC coupled as pictured in Figure 13 the

dependence on a centered VBB reference is removed. The

situation pictured will ensure that the input is centered

around the bias set by the VBB. As a result when AC coupled

the AC specification limits for a differential input can be

used. For more information on AC coupling please refer to

the interfacing section of the design guide in the ECLinPS

data book.

Using the Enable Pins

Both the common enable (CEN) and the individual

enables (ENx) are synchronous to the CLK or SCLK input

depending on which is selected. The active low signals are

clocked into the enable flip flops on the negative edges of the

E211 clock inputs. In this way the devices will only be

disabled when the outputs are already in the LOW state. The

internal propagation delays are such that the delay to the

output through the distribution buffers is less than that

through the enable flip flops. This will ensure that the

disabling of the device will not slice any time off the clock

pulse. O n initial power up the enable flip flops will randomly

attain a stable state, therefore precautions should be taken o n

initial power up to ensure the E211 is in the desired state.

0.01 F

VBB

50 

0.001F

0.01F

Figure 13. AC Coupled Input

VBB

Figure 14. Single−Ended Input

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Figure 15. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device Receiver

Device

Q D

Zo = 50 

50 50 

VTT

VTT = VCC − 2.0 V

ORDERING INFORMATION

Device Package Shipping†

MC10E221FN PLCC−28 37 Units / Rail

MC10E221FNR2 PLCC−28 500 / Tape & Reel

MC100E221FN PLCC−28 37 Units / Rail

MC100E221FNR2 PLCC−28 500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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Resource Reference of Application Notes

AN1405/D − ECL Clock Distribution Techniques

AN1406/D − Designing with PECL (ECL at +5.0 V)

AN1503/D − ECLinPS I/O SPiCE Modeling Kit

AN1504/D − Metastability and the ECLinPS Family

AN1568/D − Interfacing Between LVDS and ECL

AN1642/D − The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices