0 VirtexTM 2.5 V Field Programmable Gate Arrays R DS003-4 (v2.7) July 19, 2001 0 3 Product Specification Virtex Pin Definitions Table 1: Special Purpose Pins Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 Yes Input Clock input pins that connect to Global Clock Buffers. These pins become user inputs when not needed for clocks. M0, M1, M2 Yes Input Mode pins are used to specify the configuration mode. CCLK Yes Input or Output PROGRAM Yes Input DONE Yes Bidirectional Indicates that configuration loading is complete, and that the start-up sequence is in progress. The output can be open drain. INIT No Bidirectional (Open-drain) When Low, indicates that the configuration memory is being cleared. The pin becomes a user I/O after configuration. BUSY/ No Output In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. Pin Name DOUT The configuration Clock I/O pin: it is an input for SelectMAP and slave-serial modes, and output in master-serial mode. After configuration, it is input only, logic level = Don't Care. Initiates a configuration sequence when asserted Low. In bit-serial modes, DOUT provides header information to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration. D0/DIN, D1, D2, D3, D4, D5, D6, D7 No WRITE No Input In SelectMAP mode, the active-low Write Enable signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. CS No Input In SelectMAP mode, the active-low Chip Select signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. TDI, TDO, TMS, TCK Yes Mixed Boundary-scan Test-Access-Port pins, as defined in IEEE 1149.1. DXN, DXP Yes N/A Temperature-sensing diode pins. (Anode: DXP, cathode: DXN) VCCINT Yes Input Power-supply pins for the internal core logic. VCCO Yes Input Power-supply pins for the output drivers (subject to banking rules) VREF No Input Input threshold voltage pins. Become user I/Os when an external threshold voltage is not needed (subject to banking rules). GND Yes Input Ground Input or Output In SelectMAP mode, D0 - D7 are configuration data pins. These pins become user I/Os after configuration unless the SelectMAP port is retained. In bit-serial modes, DIN is the single data input. This pin becomes a user I/O after configuration. (c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS003-4 (v2.7) July 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 1 R VirtexTM 2.5 V Field Programmable Gate Arrays Virtex Pinout Information Pinout Tables See the Xilinx WebLINX web site (http://www.xilinx.com/partinfo/databook.htm) for updates or additional Pinout information. For convenience, Table 2, Table 3 and Table 4 list the locations of special-purpose and power-supply pins. Pins not listed are either user I/Os or not connected, depending on the device/package combination. See the Pinout Diagrams starting on page 17 for any pins not listed for a particular part/package combination. Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) Pin Name Device CS144 TQ144 PQ/HQ240 GCK0 All K7 90 92 GCK1 All M7 93 89 GCK2 All A7 19 210 GCK3 All A6 16 213 M0 All M1 110 60 M1 All L2 112 58 M2 All N2 108 62 CCLK All B13 38 179 PROGRAM All L12 72 122 DONE All M12 74 120 INIT All L13 71 123 BUSY/DOUT All C11 39 178 D0/DIN All C12 40 177 D1 All E10 45 167 D2 All E12 47 163 D3 All F11 51 156 D4 All H12 59 145 D5 All J13 63 138 D6 All J11 65 134 D7 All K10 70 124 WRITE All C10 32 185 CS All D10 33 184 TDI All A11 34 183 TDO All A12 36 181 TMS All B1 143 2 TCK All C3 2 239 VCCINT All A9, B6, C5, G3, G12, M5, M9, N6 10, 15, 25, 57, 84, 94, 99, 126 16, 32, 43, 77, 88, 104, 137, 148, 164, 198, 214, 225 Module 4 of 4 2 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued) Pin Name VCCO Device All CS144 Banks 0 and 1: A2, A13, D7 Banks 2 and 3: B12, G11, M13 TQ144 No I/O Banks in this package: 1, 17, 37, 55, 73, 92, 109, 128 Banks 4 and 5: N1, N7, N13 PQ/HQ240 No I/O Banks in this package: 15, 30, 44, 61, 76, 90, 105, 121, 136, 150, 165, 180, 197, 212, 226, 240 Banks 6 and 7: B2, G2, M2 VREF, Bank 0 XCV50 C4, D6 5, 13 218, 232 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) XCV100/150 ... + B4 ... + 7 ... + 229 XCV200/300 N/A N/A ... + 236 XCV400 N/A N/A ... + 215 XCV600 N/A N/A ... + 230 XCV800 N/A N/A ... + 222 XCV50 A10, B8 22, 30 191, 205 XCV100/150 ... + D9 ... + 28 ... + 194 XCV200/300 N/A N/A ... + 187 XCV400 N/A N/A ... + 208 XCV600 N/A N/A ... + 193 XCV800 N/A N/A ... + 201 XCV50 D11, F10 42, 50 157, 171 XCV100/150 ... + D13 ... + 44 ... + 168 XCV200/300 N/A N/A ... + 175 XCV400 N/A N/A ... + 154 XCV600 N/A N/A ... + 169 XCV800 N/A N/A ... + 161 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 1 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 2 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. DS003-4 (v2.7) July 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 3 R VirtexTM 2.5 V Field Programmable Gate Arrays Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued) Pin Name VREF, Bank 3 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Device CS144 TQ144 PQ/HQ240 XCV50 H11, K12 60, 68 130, 144 XCV100/150 ... + J10 ... + 66 ... + 133 XCV200/300 N/A N/A ... + 126 XCV400 N/A N/A ... + 147 XCV600 N/A N/A ... + 132 XCV800 N/A N/A ... + 140 XCV50 L8, L10 79, 87 97, 111 XCV100/150 ... + N10 ... + 81 ... + 108 XCV200/300 N/A N/A ... + 115 XCV400 N/A N/A ... + 94 XCV600 N/A N/A ... + 109 XCV800 N/A N/A ... + 101 XCV50 L4, L6 96, 104 70, 84 XCV100/150 ... + N4 ... + 102 ... + 73 XCV200/300 N/A N/A ... + 66 XCV400 N/A N/A ... + 87 XCV600 N/A N/A ... + 72 XCV800 N/A N/A ... + 80 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 4 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 5 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Module 4 of 4 4 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued) Pin Name VREF, Bank 6 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Device CS144 TQ144 PQ/HQ240 XCV50 H2, K1 116, 123 36, 50 XCV100/150 ... + J3 ... + 118 ... + 47 XCV200/300 N/A N/A ... + 54 XCV400 N/A N/A ... + 33 XCV600 N/A N/A ... + 48 XCV800 N/A N/A ... + 40 XCV50 D4, E1 133, 140 9, 23 XCV100/150 ... + D2 ... + 138 ... + 12 XCV200/300 N/A N/A ... + 5 XCV400 N/A N/A ... + 26 XCV600 N/A N/A ... + 11 XCV800 N/A N/A ... + 19 All A1, B9, B11, C7, D5, E4, E11, F1, G10, J1, J12, L3, L5, L7, L9, N12 9, 18, 26, 35, 46, 54, 64 120, 129, 136, 144, 1, 8, 14, 22, 29, 37, 45, 51, 59, 69, 75, 83, 91, 98, 106, 112, 119, 129, 135, 143, 151, 158, 166, 172, 182, 190, 196, 204, 211, 219, 227, 233 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 7 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. GND DS003-4 (v2.7) July 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 5 R VirtexTM 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) Pin Name Device BG256 BG352 BG432 BG560 GCK0 All Y11 AE13 AL16 AL17 GCK1 All Y10 AF14 AK16 AJ17 GCK2 All A10 B14 A16 D17 GCK3 All B10 D14 D17 A17 M0 All Y1 AD24 AH28 AJ29 M1 All U3 AB23 AH29 AK30 M2 All W2 AC23 AJ28 AN32 CCLK All B19 C3 D4 C4 PROGRAM All Y20 AC4 AH3 AM1 DONE All W19 AD3 AH4 AJ5 INIT All U18 AD2 AJ2 AH5 BUSY/DOUT All D18 E4 D3 D4 D0/DIN All C19 D3 C2 E4 D1 All E20 G1 K4 K3 D2 All G19 J3 K2 L4 D3 All J19 M3 P4 P3 D4 All M19 R3 V4 W4 D5 All P19 U4 AB1 AB5 D6 All T20 V3 AB3 AC4 D7 All V19 AC3 AG4 AJ4 WRITE All A19 D5 B4 D6 CS All B18 C4 D5 A2 TDI All C17 B3 B3 D5 TDO All A20 D4 C4 E6 TMS All D3 D23 D29 B33 TCK All A1 C24 D28 E29 DXN All W3 AD23 AH27 AK29 DXP All V4 AE24 AK29 AJ28 Module 4 of 4 6 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name VCCINT Notes: * Superset includes all pins, including the ones in bold type. Subset excludes pins in bold type. * In BG352, for XCV300 all the VCCINT pins in the superset must be connected. For XCV150/200, VCCINT pins in the subset must be connected, and pins in bold type can be left unconnected (these unconnected pins cannot be used as user I/O.) * In BG432, for XCV400/600/800 all VCCINT pins in the superset must be connected. For XCV300, VCCINT pins in the subset must be connected, and pins in bold type can be left unconnected (these unconnected pins cannot be used as user I/O.) * In BG560, for XCV800/1000 all VCCINT pins in the superset must be connected. For XCV400/600, VCCINT pins in the subset must be connected, and pins in bold type can be left unconnected (these unconnected pins cannot be used as user I/O.) Device BG256 BG352 BG432 BG560 XCV50/100 C10, D6, D15, F4, F17, L3, L18, R4, R17, U6, U15, V10 N/A N/A N/A XCV150/200/300 Same as above A20, C14, D10, J24, K4, P2, P25, V24, W2, AC10, AE14, AE19, A10, A17, B23, C14, C19, K3, K29, N2, N29, T1, T29, W2, W31, AB2, AB30, AJ10, AJ16, AK13, AK19, AK22, N/A B16, D12, L1, L25, R23, T1, AF11, AF16 XCV400/600/800/1000 N/A N/A B26, C7, F1, F30, AE29, AF1, AH8, AH24 Same as above A21, B14, B18, B28, C24, E9, E12, F2, H30, J1, K32, N1, N33, U5, U30, Y2, Y31, AD2, AD32, AG3, AG31, AK8, AK11, AK17, AK20, AL14, AL27, AN25, B12, C22, M3, N29, AB2, AB32, AJ13, AL22 VCCO, Bank 0 All D7, D8 A17, B25, D19 A21, C29, D21 A22, A26, A30, B19, B32 VCCO, Bank 1 All D13, D14 A10, D7, D13 A1, A11, D11 A10, A16, B13, C3, E5 VCCO, Bank 2 All G17, H17 B2, H4, K1 C3, L1, L4 B2, D1, H1, M1, R2 VCCO, Bank 3 All N17, P17 P4, U1, Y4 AA1, AA4, AJ3 V1, AA2, AD1, AK1, AL2 VCCO, Bank 4 All U13, U14 AC8, AE2, AF10 AH11, AL1, AL11 AM2, AM15, AN4, AN8, AN12 VCCO, Bank 5 All U7, U8 AC14, AC20, AF17 AH21, AJ29, AL21 AL31, AM21, AN18, AN24, AN30 VCCO, Bank 6 All N4, P4 U26, W23, AE25 AA28, AA31, AL31 W32, AB33, AF33, AK33, AM32 DS003-4 (v2.7) July 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 7 R VirtexTM 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name Device BG256 BG352 BG432 BG560 VCCO, Bank 7 All G4, H4 G23, K26, N23 A31, L28, L31 C32, D33, K33, N32, T33 VREF, Bank 0 XCV50 A8, B4 N/A N/A N/A XCV100/150 ... + A4 A16,C19, C21 N/A N/A XCV200/300 ... + A2 ... + D21 B19, D22, D24, D26 N/A XCV400 N/A N/A ... + C18 A19, D20, (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 1 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 2 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Module 4 of 4 8 D26, E23, E27 XCV600 N/A N/A ... + C24 ... + E24 XCV800 N/A N/A ... + B21 ... + E21 XCV1000 N/A N/A N/A ... + D29 XCV50 A17, B12 N/A N/A N/A XCV100/150 ... + B15 B6, C9, N/A N/A A13, B7, N/A C12 XCV200/300 ... + B17 ... + D6 C6, C10 XCV400 N/A N/A ... + B15 A6, D7, D11, D16, E15 XCV600 N/A N/A ... + D10 ... + D10 XCV800 N/A N/A ... + B12 ... + D13 XCV1000 N/A N/A N/A ... + E7 XCV50 C20, J18 N/A N/A N/A XCV100/150 ... + F19 E2, H2, N/A N/A E2, G3, N/A M4 XCV200/300 ... + G18 ... + D2 J2, N1 XCV400 N/A N/A ... + R3 G5, H4, L5, P4, R1 XCV600 N/A N/A ... + H1 ... + K5 XCV800 N/A N/A ... + M3 ... + N5 XCV1000 N/A N/A N/A ... + B3 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name VREF, Bank 3 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 4 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 5 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 6 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. DS003-4 (v2.7) July 19, 2001 Product Specification Device BG256 BG352 BG432 BG560 XCV50 M18, V20 N/A N/A N/A XCV100/150 ... + R19 R4, V4, Y3 N/A N/A XCV200/300 ... + P18 ... + AC2 V2, AB4, AD4, AF3 N/A XCV400 N/A N/A ... + U2 V4, W5, AD3, AE5, AK2 XCV600 N/A N/A ... + AC3 ... + AF1 XCV800 N/A N/A ... + Y3 ... + AA4 XCV1000 N/A N/A N/A ... + AH4 XCV50 V12, Y18 N/A N/A N/A XCV100/150 ... + W15 AC12, AE5, AE8, N/A N/A XCV200/300 ... + V14 ... + AE4 AJ7, AL4, AL8, AL13 N/A XCV400 N/A N/A ... + AK15 AL7, AL10, AL16, AM4, AM14 XCV600 N/A N/A ... + AK8 ... + AL9 XCV800 N/A N/A ... + AJ12 ... + AK13 XCV1000 N/A N/A N/A ... + AN3 XCV50 V9, Y3 N/A N/A N/A XCV100/150 ... + W6 AC15, AC18, N/A N/A AJ18, AJ25, N/A AD20 XCV200/300 ... + V7 ... + AE23 AK23, AK27 XCV400 N/A N/A ... + AJ17 AJ18, AJ25, AL20, AL24, AL29 XCV600 N/A N/A ... + AL24 ... + AM26 XCV800 N/A N/A ... + AH19 ... + AN23 XCV1000 N/A N/A N/A ... + AK28 XCV50 M2, R3 N/A N/A N/A XCV100/150 ... + T1 R24, Y26, AA25, N/A N/A XCV200/300 ... + T3 ... + AD26 V28, AB28, AE30, AF28 N/A XCV400 N/A N/A ... + U28 V29, Y32, AD31, AE29, AK32 XCV600 N/A N/A ... + AC28 ... + AE31 XCV800 N/A N/A ... + Y30 ... + AA30 XCV1000 N/A N/A N/A ... + AH30 www.xilinx.com 1-800-255-7778 Module 4 of 4 9 R VirtexTM 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name VREF, Bank 7 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Device BG256 BG352 BG432 BG560 XCV50 G3, H1 N/A N/A N/A XCV100/150 ... + D1 D26, G26, N/A N/A F28, F31, N/A L26 XCV200/300 ... + B2 ... + E24 J30, N30 XCV400 N/A N/A ... + R31 E31, G31, K31, P31, T31 XCV600 N/A N/A ... + J28 ... + H32 XCV800 N/A N/A ... + M28 ... + L33 XCV1000 N/A N/A N/A ... + D31 GND All C3, C18, D4, D5, D9, D10, D11, D12, D16, D17, E4, E17, J4, J17, K4, K17, L4, L17, M4, M17, T4, T17, U4, U5, U9, U10, U11, U12, U16, U17, V3, V18 A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1, AF2, AF5, AF8, AF13, AF19, AF22, AF25, AF26 A2, A3, A7, A9, A14, A18, A23, A25, A29, A30, B1, B2, B30, B31, C1, C31, D16, G1, G31, J1, J31, P1, P31, T4, T28, V1, V31, AC1, AC31, AE1, AE31, AH16, AJ1, AJ31, AK1, AK2, AK30, AK31, AL2, AL3, AL7, AL9 AL14, AL18 AL23, AL25, AL29, AL30 A1, A7, A12, A14, A18, A20, A24, A29, A32, A33, B1, B6, B9, B15, B23, B27, B31, C2, E1, F32, G2, G33, J32, K1, L2, M33, P1, P33, R32, T1, V33, W2, Y1, Y33, AB1, AC32, AD33, AE2, AG1, AG32, AH2, AJ33, AL32, AM3, AM7, AM11, AM19, AM25, AM28, AM33, AN1, AN2, AN5, AN10, AN14, AN16, AN20, AN22, AN27, AN33 GND (1) All J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12 N/A N/A N/A No Connect All N/A N/A N/A C31, AC2, AK4, AL3 Notes: 1. 16 extra balls (grounded) at package center. Module 4 of 4 10 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) Pin Name Device FG256 FG456 FG676 FG680 GCK0 All N8 W12 AA14 AW19 GCK1 All R8 Y11 AB13 AU22 GCK2 All C9 A11 C13 D21 GCK3 All B8 C11 E13 A20 M0 All N3 AB2 AD4 AT37 M1 All P2 U5 W7 AU38 M2 All R3 Y4 AB6 AT35 CCLK All D15 B22 D24 E4 PROGRAM All P15 W20 AA22 AT5 DONE All R14 Y19 AB21 AU5 INIT All N15 V19 Y21 AU2 BUSY/DOUT All C15 C21 E23 E3 D0/DIN All D14 D20 F22 C2 D1 All E16 H22 K24 P4 D2 All F15 H20 K22 P3 D3 All G16 K20 M22 R1 D4 All J16 N22 R24 AD3 D5 All M16 R21 U23 AG2 D6 All N16 T22 V24 AH1 D7 All N14 Y21 AB23 AR4 WRITE All C13 A20 C22 B4 CS All B13 C19 E21 D5 TDI All A15 B20 D22 B3 TDO All B14 A21 C23 C4 TMS All D3 D3 F5 E36 TCK All C4 C4 E6 C36 DXN All R4 Y5 AB7 AV37 DXP All P4 V6 Y8 AU35 DS003-4 (v2.7) July 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 11 R VirtexTM 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name Device FG256 FG456 FG676 FG680 VCCINT All C3, C14, D4, D13, E5, E12, M5, M12, N4, N13, P3, P14 E5, E18, F6, F17, G7, G8, G9, G14, G15, G16, H7, H16, J7, J16, P7, P16, R7, R16, T7, T8, T9, T14, T15, T16, U6, U17, V5, V18 G7, G20, H8, H19, J9, J10, J11, J16, J17, J18, K9, K18, L9, L18, T9, T18, U9, U18, V9, V10, V11, V16, V17, V18, W8, W19, Y7, Y20 AD5, AD35, AE5, AE35, AL5, AL35, AM5, AM35, AR8, AR9, AR15, AR16, AR24, AR25, AR31, AR32, E8, E9, E15, E16, E24, E25, E31, E32, H5, H35, J5, J35, R5, R35, T5, T35 VCCO, Bank 0 All E8, F8 F7, F8, F9, F10 G10, G11 H9, H10, H11, H12, J12, J13 E26, E27, E29, E30, E33, E34 VCCO, Bank 1 All E9, F9 F13, F14, F15, F16, G12, G13 H15, H16, H17, H18, J14, J15 E6, E7, E10, E11, E13, E14 VCCO, Bank 2 All H11, H12 G17, H17, J17, K16, K17, L16 J19, K19, L19, M18, M19, N18 F5, G5, K5, L5, N5, P5 VCCO, Bank 3 All J11, J12 M16, N16, N17, P17, R17, T17 P18, R18, R19, T19, U19, V19 AF5, AG5, AN5, AK5, AJ5, AP5 VCCO, Bank 4 All L9. M9 T12, T13, U13, U14, U15, U16, V14, V15, W15, W16, W17, W18 AR6, AR7, AR10, AR11, AR13, AR14 VCCO, Bank 5 All L8, M8 T10, T11, U7, U8, U9, U10 V12, V13, W9,W10, W11, W12 AR26, AR27, AR29, AR30, AR33, AR34 VCCO, Bank 6 All J5, J6 M7, N6, N7, P6, R6, T6 P9, R8, R9, T8, U8, V8 AF35, AG35, AJ35, AK35, AN35, AP35 VCCO, Bank 7 All H5, H6 G6, H6, J6, K6, K7, L7 J8, K8, L8, M8, M9, N9 F35, G35, K35, L35, N35, P35 VREF, Bank 0 XCV50 B4, B7 N/A N/A N/A XCV100/150 ... + C6 A9, C6, E8 N/A N/A XCV200/300 ... + A3 ... + B4 N/A N/A XCV400 N/A N/A A12, C11, D6, E8, G10 XCV600 N/A N/A ... + B7 A33, B28, B30, C23, C24, D33 XCV800 N/A N/A ... + B10 ... + A26 XCV1000 N/A N/A N/A ... + D34 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Module 4 of 4 12 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name VREF, Bank 1 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 2 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 3 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. DS003-4 (v2.7) July 19, 2001 Product Specification Device FG256 FG456 FG676 FG680 XCV50 B9, C11 N/A N/A N/A XCV100/150 ... + E11 A18, B13, E14 N/A N/A XCV200/300 ... + A14 ... + A19 N/A N/A XCV400 N/A N/A A14, C20, C21, D15, G16 N/A XCV600 N/A N/A ... + B19 B6, B8, B18, D11, D13, D17 XCV800 N/A N/A ... + A17 ... + B14 XCV1000 N/A N/A N/A ... + B5 XCV50 F13, H13 N/A N/A N/A XCV100/150 ... + F14 F21, H18, K21 N/A N/A XCV200/300 ... + E13 ... + D22 N/A N/A XCV400 N/A N/A F24, H23, K20, M23, M26 N/A XCV600 N/A N/A ... + G26 G1, H4, J1, L2, V5, W3 XCV800 N/A N/A ... + K25 ... + N1 XCV1000 N/A N/A N/A ... + D2 XCV50 K16, L14 N/A N/A N/A XCV100/150 ... + L13 N21, R19, U21 N/A N/A XCV200/300 ... + M13 ... + U20 N/A N/A XCV400 N/A N/A R23, R25, U21, W22, W23 N/A XCV600 N/A N/A ... + W26 AC1, AJ2, AK3, AL4, AR1, Y1 XCV800 N/A N/A ... + U25 ... + AF3 XCV1000 N/A N/A N/A ... + AP4 www.xilinx.com 1-800-255-7778 Module 4 of 4 13 R VirtexTM 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name Device FG256 FG456 FG676 FG680 XCV50 P9, T12 N/A N/A N/A (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) XCV100/150 ... + T11 AA13, AB16, AB19 N/A N/A XCV200/300 ... + R13 ... + AB20 N/A N/A XCV400 N/A N/A AC15, AD18, AD21, AD22, AF15 N/A Within each bank, if input reference voltage is not required, all VREF pins are general I/O. XCV600 N/A N/A ... + AF20 AT19, AU7, AU17, AV8, AV10, AW11 XCV800 N/A N/A ... + AF17 ... + AV14 XCV1000 N/A N/A N/A ... + AU6 XCV50 T4, P8 N/A N/A N/A XCV100/150 ... + R5 W8, Y10, AA5 N/A N/A XCV200/300 ... + T2 ... + Y6 N/A N/A XCV400 N/A N/A AA10, AB8, AB12, AC7, AF12 N/A XCV600 N/A N/A ... + AF8 AT27, AU29, AU31, AV35, AW21, AW23 XCV800 N/A N/A ... + AE10 ... + AT25 XCV1000 N/A N/A N/A ... + AV36 XCV50 J3, N1 N/A N/A N/A XCV100/150 ... + M1 N2, R4, T3 N/A N/A XCV200/300 ... + N2 ... + Y1 N/A N/A XCV400 N/A N/A AB3, R1, R4, U6, V5 N/A XCV600 N/A N/A ... + Y1 AB35, AD37, AH39, AK39, AM39, AN36 XCV800 N/A N/A ... + U2 ... + AE39 XCV1000 N/A N/A N/A ... + AT39 VREF, Bank 4 VREF, Bank 5 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 6 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Module 4 of 4 14 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name VREF, Bank 7 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. GND DS003-4 (v2.7) July 19, 2001 Product Specification Device FG256 FG456 FG676 FG680 XCV50 C1, H3 N/A N/A N/A XCV100/150 ... + D1 E2, H4, K3 N/A N/A XCV200/300 ... + B1 ... + D2 N/A N/A XCV400 N/A N/A F4, G4, K6, M2, M5 N/A XCV600 N/A N/A ... + H1 E38, G38, L36, N36, U36, U38 XCV800 N/A N/A ... + K1 ... + N38 XCV1000 N/A N/A N/A ... + F36 All A1, A16, B2, B15, F6, F7, F10, F11, G6, G7, G8, G9, G10, G11, H7, H8, H9, H10, J7, J8, J9, J10, K6, K7, K8, K9, K10, K11, L6, L7, L10, L11, R2, R15, T1, T16 A1, A22, B2, B21, C3, C20, J9, J10, J11, J12, J13, J14, K9, K10, K11, K12, K13, K14, L9, L10, L11, L12, L13, L14, M9, M10, M11, M12, M13, M14, N9, N10, N11, N12, N13, N14, P9, P10, P11, P12, P13, P14, Y3, Y20, AA2, AA21, AB1, AB22 A1, A26, B2, B9, B14, B18, B25, C3, C24, D4, D23, E5, E22, J2, J25, K10, K11, K12, K13, K14, K15, K16, K17, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, M17, N2, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, P25, R10, R11, R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16, U17, V2, V25, AB5, AB22, AC4, AC23, AD3, AD24, AE2, AE9, AE13, AE18, AE25, AF1, AF26 A1, A2, A3, A37, A38, A39, AA5, AA35, AH4, AH5, AH35, AH36, AR5, AR12, AR19, AR20, AR21, AR28, AR35, AT4, AT12, AT20, AT28, AT36, AU1, AU3, AU20, AU37, AU39, AV1, AV2, AV38, AV39, AW1, AW2, AW3, AW37, AW38, AW39, B1, B2, B38, B39, C1, C3, C20, C37, C39, D4, D12, D20, D28, D36, E5, E12, E19, E20, E21, E28, E35, M4, M5, M35, M36, W5, W35, Y3, Y4, Y5, Y35, Y36, Y37 www.xilinx.com 1-800-255-7778 Module 4 of 4 15 R VirtexTM 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name No Connect Device FG256 FG456 FG676 FG680 XCV800 N/A N/A A2, A3, A15, A25, B1, B6, B11, B16, B21, B24, B26, C1, C2, C25, C26, F2, F6, F21, F25, L2, L25, N25, P2, T2, T25, AA2, AA6, AA21, AA25, AD1, AD2, AD25, AE1, AE3, AE6, AE11, AE14, AE16, AE21, AE24, AE26, AF2, AF24, AF25 N/A XCV600 N/A N/A same as above N/A XCV400 N/A N/A ... + A9, A10, A13, A16, A24, AC1, AC25, AE12, AE15, AF3, AF10, AF11, AF13, AF14, AF16, AF18, AF23, B4, B12, B13, B15, B17, D1, D25, H26, J1, K26, L1, M1, M25, N1, N26, P1, P26, R2, R26, T1, T26, U26, V1 N/A XCV300 N/A D4, D19, W4, W19 N/A N/A XCV200 N/A ... + A2, A6, A12, B11, B16, C2, D1, D18, E17, E19, G2, G22, L2, L19, M2, M21, R3, R20, U3, U18, Y22, AA1, AA3, AA11, AA16, AB7, AB12, AB21, N/A N/A XCV150 N/A ... + A13, A14, C8, C9, E13, F11, H21, J1, J4, K2, K18, K19, M17, N1, P1, P5, P22, R22, W13, W15, AA9, AA10, AB8, AB14 N/A N/A (No-connect pins are listed incrementally. All pins listed for both the required device and all larger devices listed in the same package are no connects.) Module 4 of 4 16 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays Pinout Diagrams The following diagrams, CS144 Pin Function Diagram, page 17 through FG680 Pin Function Diagram, page 27, illustrate the locations of special-purpose pins on Virtex FPGAs. Table 5 lists the symbols used in these diagrams. The diagrams also show I/O-bank boundaries. Table 5: Pinout Diagram Symbols Symbol Table 5: Pinout Diagram Symbols (Continued) Symbol Pin Function , , M0, M1, M2 , , , , D0/DIN, D1, D2, D3, D4, D5, D6, D7 , , , Pin Function General I/O Device-dependent general I/O, n/c on smaller devices B DOUT/BUSY D DONE P PROGRAM V VCCINT I INIT v Device-dependent VCCINT, n/c on smaller devices K CCLK W WRITE O VCCO S CS R VREF T Boundary-scan Test Access Port r Device-dependent VREF, remains I/O on smaller devices + Temperature diode, anode G Ground - Temperature diode, cathode n No connect O, 1, 2, 3 Global Clocks CS144 Pin Function Diagram Bank 1 1 2 3 4 5 6 7 8 9 10 11 12 13 Bank 0 Bank 7 GO 3 2 V R T T O A T O r V RGGO K B T R V G W B C r RGRO r S R r D R G G E G CS144 R F O V (Top view) G O V G R H R G r r G J R O R K GRGRGR GR P I L O V 1 V DO M O r V O r GO N Bank 2 Bank 3 1 2 3 4 5 6 7 8 9 10 11 12 13 Bank 6 A B C D E F G H J K L M N Bank 5 Bank 4 Figure 1: CS144 Pin Function Diagram DS003-4 (v2.7) July 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 17 R VirtexTM 2.5 V Field Programmable Gate Arrays 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 TQ144 Pin Function Diagram O T R r G V R V 3 O G 2 R V G r R W S T G T G T R r GR GO V R G r R G O Bank 7 Bank 6 Bank 0 Bank 5 TQ144 (Top view) Bank 1 Bank 4 Bank 2 Bank 3 O K B R r G R G O V R G r R I P 108 R r G V R V 1 O G O R V G r R G D O 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Figure 2: TQ144 Pin Function Diagram Module 4 of 4 18 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays 239 237 235 233 231 229 227 225 223 221 219 217 215 213 211 209 207 205 203 201 199 197 195 193 191 189 187 185 183 181 PQ240/HQ240 Pin Function Diagram T G r G V G r 3 G R r O r R r W T T O r R r O r R V O 2 r G V G r G S G 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 G Bank 0 T r G R r r G O V r G R r G O V r R G r V O G r r R G r G O Bank 1 B G Bank 7 Bank 2 PQ240/HQ240 (Top view) Pins are shown staggered for readability Bank 6 Bank 3 Bank 5 Bank 4 K 179 177 175 173 r R r r G O V r G R r G O V r R G r V O G r r R G r I P O 171 169 167 165 163 161 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 r R r O r R V O O r G V G r G D O G r G V G r 1 G R r O r R r G Figure 3: PQ240/HQ240 Pin Function Diagram DS003-4 (v2.7) July 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 19 R VirtexTM 2.5 V Field Programmable Gate Arrays 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BG256 Pin Function Diagram T r R r r r R G T R V R r G - R r R G G V O O G G G G O O V G G + G V R O O G Bank 0 2 3 V G G R G O O Bank 1 r V G BG256 Bank 7 Bank 2 G G G G Bank 6 G V r G G G G G G G G G G G G (Top View) Bank 5 O O G r R G V 1 G O Bank 3 Bank 4 G O O R r V r G R r T G G V O O G G G G O O V G G S G B r R V R r I G R W T K R r r R D P A B C D E F G H J K L M N P R T U V W Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y DS003_18_100300 Figure 4: BG256 Pin Function Diagram Module 4 of 4 20 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 BG352 Pin Function Diagram G G G O r G R G R O V G V V O GV G r I G O G G G T K S T W B O V R O R R R O P D r R G R r O G R O V R V O G 2 V 3 Bank 1 R V O G R O V R r G Bank 0 Bank 2 Bank 7 BG352 (Top View) Bank 3 Bank 6 Bank 4 O R G V O V Bank 5 R O G O V 1 R V O R V G O R G T O O V O - r T r V R V + G O V V R O G G G R G R G O R G O G R G r G G A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF DS003_19_100600 Figure 5: BG352 Pin Function Diagram DS003-4 (v2.7) July 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 21 R VirtexTM 2.5 V Field Programmable Gate Arrays 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BG432 Pin Function Diagram O G G V G r G O R G V G O G G V G G O G G R R V r R V V I G G G T O B R V r r r r R P O G W T K O G O R R D R S R G R V G V R r O O r R G V r 2 G V 3 G r R V Bank 1 O r O R G V r R G V R Bank 0 Bank 2 Bank 7 BG432 (Top View) Bank 3 Bank 6 Bank 4 R G V r R G V O O Bank 5 r V R G r G V 1 O r R G r V O O V R G V r R G - R T R r O r G r R O R r R G O T V V V V O + G G G V R R r V R G G O G G R G G O G r G V O G G G G O A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL DS003_21_100300 Figure 6: BG432 Pin Function Diagram Module 4 of 4 22 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 BG560 Pin Function Diagram G G O G O V G O V G R G O G G O r G O P G S O G V G G O G V O V n V G G R O O G R G O r G G OK B T W R r R O T r V Bank 1 R R r Bank 2 R V r R V R R r Bank 3 R R V Bank 4 r I D n V V n R r R G R G G r O G O G G V V O r G V G R O R 3 2 G V R O G R V r O V G G V R r Bank 0 O R G R V Bank 7 BG560 (Top View) Bank 6 Bank 5 O V r V R G O R G 1 V O R O G V R G O V G r R O R G V r V G + r G G r T V R R - R O V V r r O G n r R R R R R V R r V O G O O G r G V O G O R V G V G R G O G T O G O r G V G O G G O G O G O G G A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN DS003_22_100300 Figure 7: BG560 Pin Function Diagram DS003-4 (v2.7) July 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 23 R VirtexTM 2.5 V Field Programmable Gate Arrays FG256 Pin Function Diagram Bank 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Bank 0 G r r T G A r GRR 3 RS T G B R V T r 2 R W V B C r T V V K D V OO r V r E GGOOGGR r F GGGGGG G R OOGGGGOOR H R O O G G G G O O J GGGGGGR K GGOOGG r R L r V OO V r M R r V O V I N V + RRV P P G - r 1 r DG R G r R r R G T Bank 2 Bank 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C Bank 7 D E F G H J K L M Bank 6 N P R T Bank 5 Bank 4 FG256 (Top view) Figure 8: FG256 Pin Function Diagram Module 4 of 4 24 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays FG456 Pin Function Diagram Bank 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Bank 0 Bank 7 G R 2 R r WT G A G r R T G K B G T R 3 SGB C r T n n r D RV R R V E V OOOO OOOO V R F O V V V OOOO V V V O G VOR H R O V O V GGGGGG V O J R OO GGGGGG OO R K O GGGGGG O L O GGGGGG O M R OO GGGGGG OO R N O V GGGGGG V O P VOR R R O V R O V V V OOOO V V V O T V OOOOOOOO V r R U V + V I V n R O n P W r G - r R 1 DG Y G R R G AA G R R r G AB Bank 2 Bank 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Bank 6 A B C D E F G H J K L M N P R T U V W Y AA AB Bank 5 Bank 4 FG456 (Top view) Figure 9: FG456 Pin Function Diagram Notes: Packages FG456 and FG676 are layout compatible. DS003-4 (v2.7) July 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 25 R VirtexTM 2.5 V Field Programmable Gate Arrays FG676 Pin Function Diagram n O V V V O O O O V V V R O V G G G G G G G G V r O V G G G G G G G G V n R O V G G G G G G G G V 2 3 O G G G G G G G G O W T G R n R S n R T G B R R R n G K V O O O O O O O O V R R r V + V I W R O V G G G G G G G G V R n R r Bank 5 V R n D R R G n r R n G n P n G G R G n n G n n n G Bank 2 Bank 3 Y AA AB AC AD AE AF 22 23 24 25 26 0 R 1 r n G n R R n R O O G G G G G G G G O r V O O O O O O O O A B C D E F G H J K L M N P R T U V - R R G r R G O G G G G G G G G O G O V V V O O O O V V V G n n n r G r n R n G R n r G V R O O G G G G G G G G O 22 23 24 25 26 r 19 20 21 G 19 20 21 n R 17 18 n G G n n G n G n n G n r 16 Y AA AB AC AD AE AF R V O O O O O O O O 17 18 W R R R r 16 n R T n R R R 1 2 3 4 5 6 7 8 Bank 6 n G n R G n n r G n G G T R G n n r r R 9 10 11 12 13 14 15 Bank 7 n G n G A B C D E F G H J K L M N P R T U V 9 10 11 12 13 14 15 Bank 1 1 2 3 4 5 6 7 8 Bank 0 Bank 4 FG676 (Top view) fg676a Figure 10: FG676 Pin Function Diagram Notes: Packages FG456 and FG676 are layout compatible. Module 4 of 4 26 www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays FG680 Pin Function Diagram 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 R T U 16 M N P 15 R V 14 O 13 8 R O 12 7 r S G O O V V O O 11 6 G G G T W G T r G B K R R 9 5 G G G R R Bank 0 10 4 3 2 A B C D E F G H J K L V O R O G G R O r O V V R R G 3 G G G 2 G R R V V r O O R G G O R O V V R R O r O G O O V V O O T G T r R G G G G R R G G G A B C D E F G H J K L G G r O O G G O R r O M N P V V V V R R R T U V R V W R G G W Y R G G G AA G AB AC AD AE AF AG R R R AH AJ AK AL AM AN Bank 3 AP AR FG680 ( Top V V r O O View) Bank 7 Bank 2 G G R R r O O V V O O G O O V V O O G O O V V G G G V V O O G O O V V O O G G G Y G AA R r AB AC AD AE AF AG G O O V V O O G G R R R R AH AJ AK AL AM AN AP Bank 6 AR G P G R G r R G AU G G r + G G AU AV AW G G R R r R r G G G G G R 0 R R G G G AV AW I G D r R R G 1 R R AT 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 - Bank 4 Bank 7 R V V O O AT 2 Bank 2 1 Bank 1 Bank 5 Note: AA3, AA4, and AB2 are in Bank 2 Note: AA37 is in Bank 7 fg680_12a Figure 11: FG680 Pin Function Diagram DS003-4 (v2.7) July 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 27 R VirtexTM 2.5 V Field Programmable Gate Arrays Revision History Date Version Revision 11/98 1.0 Initial Xilinx release. 01/99 1.2 Updated package drawings and specs. 02/99 1.3 Update of package drawings, updated specifications. 05/99 1.4 Addition of package drawings and specifications. 05/99 1.5 Replaced FG 676 & FG680 package drawings. 07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19. Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate. Added IOB Input Switching Characteristics Standard Adjustments. 09/99 1.7 Speed grade update to preliminary status, Power-on specification and Clock-to-Out Minimums additions, "0" hold time listing explanation, quiescent current listing update, and Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE. 01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479, 117153, 117154, and 117612. Modified notes for Recommended Operating Conditions (voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43. 01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. 03/00 2.0 New TBCKO values; corrected FG680 package connection drawing; new note about status of CCLK pin after configuration. 05/00 2.1 Modified "Pins not listed ..." statement. Speed grade update to Final status. 05/00 2.2 Modified Table 18. 09/00 2.3 10/00 2.4 04/02/01 2.5 04/19/01 2.6 07/19/01 2.7 * * * * * * * * Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices. Corrected Units column in table under IOB Input Switching Characteristics. Added values to table under CLB SelectRAM Switching Characteristics. Corrected pinout info for devices in the BG256, BG432, and BG560 pkgs in Table 18. Corrected BG256 Pin Function Diagram. Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL. Converted file to modularized format. See section Virtex Data Sheet, below. Corrected pinout information for FG676 device in Table 4. (Added AB22 pin.) * * Clarified VCCINT pinout information and added AE19 pin for BG352 devices in Table 3. Changed pinouts listed for BG352 XCV400 devices in banks 0 thru 7. Virtex Data Sheet The Virtex Data Sheet contains the following modules: * DS003-1, Virtex 2.5V FPGAs: * Introduction and Ordering Information (Module 1) * DS003-2, Virtex 2.5V FPGAs: Functional Description (Module 2) Module 4 of 4 28 DS003-3, Virtex 2.5V FPGAs: DC and Switching Characteristics (Module 3) * DS003-4, Virtex 2.5V FPGAs: Pinout Tables (Module 4) www.xilinx.com 1-800-255-7778 DS003-4 (v2.7) July 19, 2001 Product Specification