INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT138 3-to-8 line decoder/demultiplexer; inverting Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 The 74HC/HCT138 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES * Demultiplexing capability * Multiple input enable for easy expansion * Ideal for memory chip select decoding The "138" features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. * Active LOW mutually exclusive outputs * Output capability: standard This multiple enable function allows easy parallel expansion of the "138" to a 1-of-32 (5 lines to 32 lines) decoder with just four "138" ICs and one inverter. * ICC category: MSI The "138" can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The "138" is identical to the "238" but has inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER UNIT CONDITIONS HC HCT CL = 15 pF; VCC = 5 V propagation delay tPHL/ tPLH An to Yn 12 17 ns tPHL/ tPLH E3 to Yn En to Yn 14 19 ns 3.5 3.5 pF 67 67 pF CI input capacitance CPD power dissipation capacitance per package notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". September 1993 2 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 2, 3 A0 to A2 address inputs 4, 5 E1, E2 enable inputs (active LOW) 6 E3 enable input (active HIGH) 8 GND ground (0 V) 15, 14, 13, 12, 11, 10, 9, 7 Y0 to Y7 outputs (active LOW) 16 VCC positive supply voltage handbook, halfpage 1 A0 Y0 2 A1 Y1 14 3 A2 Y2 13 Y3 12 15 Y4 11 4 E1 Y5 10 5 E2 Y6 9 6 E3 Y7 7 MLB312 Fig.1 Pin configuration. (a) Fig.2 Logic symbol. (b) Fig.3 IEC logic symbol. September 1993 Fig.4 Functional diagram. 3 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 FUNCTION TABLE INPUTS OUTPUTS E1 E2 E3 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H X X X H X X X L X X X X X X X X X H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H L H L H L L H H L L L L L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H L L L L L L L L H H H H L H L H L L H H H H H H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care Fig.5 Logic diagram. September 1993 4 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. -40 to +85 max. min. max. -40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay An to Yn 41 15 12 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay E3 to Yn 47 17 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay En to Yn 47 17 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Figs 6 and 7 September 1993 5 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT An 1.50 En 1.25 E3 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. typ. -40 to +85 max. min. max. -40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay An to Yn 20 35 44 53 ns 4.5 Fig.6 tPHL/ tPLH propagation delay E3 to Yn 18 40 50 60 ns 4.5 Fig.6 tPHL/ tPLH propagation delay En to Yn 19 40 50 60 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 6 and 7 September 1993 6 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the address input (An) and enable input (E3) to output (Yn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". September 1993 7 74HC/HCT138; 3-to-8 line decoder/demultiplexer; inverting Product Categories General description Analog and * mixed-signal devices * Audio * Bus devices Clocks & * Watches Data * Communications * Discrete modules * Discretes * Display drivers Identification & * Security * Logic * Microcontrollers * Peripherals * Video Wired * Communications Wireless * Communications Block diagram Products & packages Features Buy online Parametrics Applications Support & tools Similar products Information as of 2004-04-09 Stay informed Download datasheet Leadfree Datasheet Email/translate Disclaimer General description The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT138 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). The '138' features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the '138' to a 1-of-32 (5 lines to 32 lines) decoder with just four '138' ICs and one inverter. The '138' can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The '138' is identical to the '238' but has inverting outputs. Features Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Active LOW mutually exclusive outputs Output capability: standard ICC category: MSI Datasheet Datasheet title Publication release Datasheet status date 74HC/HCT138; 3-to-8 line decoder/demultiplexer; inverting 01-Sep-93 Page count Product specification 7 File size (kB) Datasheet 47 Download Additional datasheet info To complete the device datasheet with package and family information, also download the following PDF files. The "Logic Package Information" document is required to determine in which package(s) this device is available. Document Description 1 HCT_FAMILY_SPECIFICATIONS HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic Family Specifications 2 HCT_PACKAGE_INFO HC/T Package Info, The IC06 74HC/HCT/HCMOS Logic Package Information 3 HCT_PACKAGE_OUTLINES HC/T Package Outlines, The IC06 74HC/HCT/HCMOS Logic Package Outlines Parametrics Type number Package Description Propagation Voltage No. Power Logic Output Delay(ns) of Dissipation Switching Drive Pins Considerations Levels Capability 74HC138BQ SOT763 3-to-8 Line Decoder/Demultiplexer; 12@5V Inverting 2.0-6.0 16 V Low Power or Battery Applications CMOS +/- 5.2 mA 74HC138D SOT109-1 3-to-8 Line Decoder/Demultiplexer; 12@5V (SO16) Inverting 2.0-6.0 16 V Low Power or Battery Applications CMOS +/- 5.2 mA 74HC138DB 3-to-8 Line SOT338-1 Decoder/Demultiplexer; 12@5V (SSOP16) Inverting 2.0-6.0 16 V Low Power or Battery Applications CMOS +/- 5.2 mA 74HC138N SOT38-4 (DIP16) 3-to-8 Line Decoder/Demultiplexer; 12@5V Inverting 2.0-6.0 16 V Low Power or Battery Applications CMOS +/- 5.2 mA 74HC138PW 3-to-8 Line SOT403-1 Decoder/Demultiplexer; 12@5V (TSSOP16) Inverting 2.0-6.0 16 V Low Power or Battery Applications CMOS +/- 5.2 mA 74HCT138D SOT109-1 3-to-8 Line Decoder/Demultiplexer; 17 (SO16) Inverting; TTL Enabled 4.5-5.5 16 V Low Power TTL +/- 4 mA 74HCT138DB 3-to-8 Line SOT338-1 Decoder/Demultiplexer; 17 (SSOP16) Inverting; TTL Enabled 4.55.5V 16 Low Power TTL +/- 4 mA 74HCT138N SOT38-4 (DIP16) 3-to-8 Line Decoder/Demultiplexer; 17 Inverting; TTL Enabled 4.55.5V 16 Low Power TTL +/- 4 mA 74HCT138PW 3-to-8 Line SOT403-1 Decoder/Demultiplexer; 17 (TSSOP16) Inverting; TTL Enabled 4.55.5V 16 Low Power TTL +/- 4 mA Products, packages, availability and ordering Type number North Ordering code American type (12NC) number Product status Buy online IC packing info Standard Marking 9352 737 78115 * Reel Pack, SMD, SOT763 7" 74HC138BQ 74HC138D Marking/Packing Package Standard Marking * Tube, CECC SOT109-1 (SO16) Full production 74HC138D 9337 134 00652 74HC138D-T Standard Marking SOT109-1 9337 134 00653 * Reel Pack, SMD, (SO16) 13", CECC Full production 74HC138DB 9351 744 10112 SOT338-1 (SSOP16) Full production 74HC138DB-T Standard Marking SOT338-1 9351 744 10118 * Reel Pack, SMD, (SSOP16) 13" Full production 74HC138N 74HC138N 9336 692 90652 Standard Marking * Tube, CECC SOT38-4 (DIP16) 74HC138PW 74HC138PW 9351 743 80112 Standard Marking * Tube SOT403-1 Full production (TSSOP16) 74HC138PW-T Standard Marking SOT403-1 9351 743 80118 * Reel Pack, SMD, Full production (TSSOP16) 13" 74HC138DB Standard Marking 9352 744 71115 * Reel Pack, SMD, SOT763 7" 74HCT138BQ 74HCT138D Standard Marking * Tube, CECC SOT109-1 (SO16) Full production Full production Full production 74HCT138D 9337 134 10652 74HCT138D-T Standard Marking SOT109-1 9337 134 10653 * Reel Pack, SMD, (SO16) 13", CECC Full production SOT338-1 (SSOP16) Full production 74HCT138DBT Standard Marking SOT338-1 9351 744 20118 * Reel Pack, SMD, (SSOP16) 13" Full production 74HCT138N 9336 699 20652 Standard Marking * Tube, CECC SOT38-4 (DIP16) 9351 873 20112 Standard Marking * Tube SOT403-1 Full production (TSSOP16) 74HCT138DB 74HCT138DB 74HCT138N Standard Marking * Tube 74HCT138PW 74HCT138PW 74HCT138PWT 9351 744 20112 Standard Marking * Tube - Full production Full production Standard Marking SOT403-1 9351 873 20118 * Reel Pack, SMD, Full production (TSSOP16) 13" - Similar products 74HC/HCT138 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category. Support & tools HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic Family Specifications(date 1998-03-01) HC/T User Guide(date 1997-11-01) Email/translate this product information Email this product information. Translate this product information page from English to: French Translate The English language is the official language used at the semiconductors.philips.com website and webpages. All translations on this website are created through the use of Google Language Tools and are provided for convenience purposes only. No rights can be derived from any translation on this website. Disclaimer The information published on product information pages of the www.semiconductors.philips.com or www.semiconductors.com websites is an extract from product data sheets and is for information purposes only. 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