CY7C1347C-16BGC - Cypress Semiconductor Corp.

256K x 18/128K x 36 Synchronous-Pipelined

Cache RAM

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Cypress Semiconductor Corporation • 39 01 North First Street • San Jose • CA 95134 • 408-943-2600

July 21, 2000

Features

• Fast access tim es: 2. 5 and 3.5 ns

• Fast clock speed: 250, 225, 200, and 166 MHz

• 1-ns set-up time and hold time

•Fast OE

access times: 2.5 ns and 3.5 ns

• Optimal for depth expansion (one cycle chip deselect

to eli m inat e bus contenti on)

• 3.3V –5% and +10% power supply

• 3.3V or 2.5V I/O supply

• 5V tolerant inputs except I/Os

• Clamp diodes to VSS at all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Glob al Write control

• Three chip enabl es for depth expansion and add ress

pipeline

• Address, data, and control registers

• Internally sel f-timed Write Cycle

• Burst contr ol pins (i nterlea ved or linear burst se-

quence)

• Automatic power-down for portable a ppli cations

• JTAG boundary scan

• JEDEC standard pinout

• Low profile 119-lead, 14-m m x 22-mm BGA (Ball Grid

Array) and 100-pin TQFP packages

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced tri-

ple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The CY7C1347C/GVT71128DA36 and CYC7C1327C/

GVT71256DA18 SRAMs integrate 131,072x36 and

262,144x18 SRAM cells with advanced synchronous periph-

eral circui try and a 2-bi t counter f or internal b urst oper ation. All

synchro nous inputs are gated b y registe rs controlled by a pos-

itive-edge-triggered clock input (CLK). The synchronous in-

puts include all addresses, all data inputs, address-pi pelining

Chip Enable (CE), depth-expansion Chip Enables (CE2 and

CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write

Enabl es (BW a, BWb , BWc, BWd, and BWE) , and Global Write

(GW).

Asynchronous inputs include the Output Enable (OE) and

Burst Mode Control (MODE). The data outputs (Q), enabled

by OE, are also asynchronous.

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) inpu t pi ns. Subsequent burst addresses can be inter-

nally g enerat ed as co ntrol led b y the Burst Advan ce pi n ( ADV).

Address , data inputs, and write cont rols are regis tered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wi de as controlled by the write control inputs. Indi-

vidual byt e write allo ws indi vidual byt e to be writte n. BW a con -

trols DQa. BWb controls DQb. BWc controls DQc. BWd con-

trols DQ d. BWa, BWb , BWc , and BWd can be active only with

BWE being LO W. GW being LOW causes all bytes to be writ-

ten. The x18 version only has 18 data inputs/outputs (DQa and

DQb) along with BWa and BWb (no BWc, BWd, DQc, and

DQd).

Four pins are used to implement JTAG test capabilities: Test

Mode Select (TMS), Tes t Data-in (T DI), Te st Cloc k (TCK), and

Test Dat a-out (T DO). The JTAG circui try is used to seri ally shif t

data to and from t he device. JTA G input s use LVTTL/LVCMOS

levels to shift data during thi s testing mode of operation.

The CY7C1347C/GVT71128DA36 and CY7C1327C/

GVT71256 DA18 operate from a +3.3 V powe r supply. All input s

and outputs are LVTTL compatible

Selection Gu ide

7C1347C-250

71128DA36-4

7C1327C-250

71256DA18-4

7C1347C-225

71128DA36-4.4

7C1327C-225

71256DA18-4.4

7C1347C-200

71128DA36-5

7C1327C-200

71256DA18-5

7C1347C-166

71128DA36-6

7C1327C-166

71256DA18-6

Maximum Access Time (ns) 2.5 2.5 2.5 3.5

Maxim um Ope rating Current (mA) 450 400 360 300

Maximum CMOS Stan dby Current (mA) 10 10 10 10

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Note:

1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.

Functional Block Diagram —128Kx36[1]

Functional Block Diagram —256Kx18[1]

BWc#

BWE#

BWd#

CE#

CE2

CE2#

BYTE c WRITE

BYTE d WRITE

OUTPUT

OE#

byte c write

ADSP#

ADSC#

Address

Binary

Counter

& Logic

CLR

A1-A0

ADV#

MODE

128K x 9 x 4

SRAM Array

Output Buffers

Input

byte d write

DQa,DQb

DQc,DQd

BWa#

BWb#

GW#

BYTE a WRITE

BYTE b WRITE

CLK

byte b write

byte a write

ENABLE

Power Down LogicZZ

BWb#

BWE#

BWa#

GW#

CE#

CE2

CE2#

BYTE b

WRITE

BYTE a

WRITE

OUTPUT

OE#

byte b write

ADSP#

ADSC#

Address

Binary

Counter

& Logic

CLR

A1-A0

ADV#

MODE

256K x 9 x 2

SRAM Array

Output Buffers

Input

byte a write

DQa,DQb

DQ DQ

ENABLE

Power Down LogicZZ

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Pin Configurations

TMS

TDI

TCK

CCQ

DQa

CCQ

DQa

CCQ

DQa

CCQ

DQb

CCQ

CE2

BWb

BWa

CE2

CLK

BWE

ADSP

100

AADV

ADSC

TDO

MODE

100-Pin TQFP

CY7C1327C/

Top View

DQb

TMS

TDI

TCK

DQb

CCQ

DQb

CCQ

DQb

DQa

CCQ

DQa

CCQ

DQa

DQc

CCQ

DQc

CCQ

DQd

CCQ

DQd

CE2

BWd

BWc

BWb

BWa

CE2

CLK

BWE

ADSP

100

AADV

ADSC

TDO

MODE

CY7C1347C/

DQc

DQd

GVT71128DA36 GVT71256DA18

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Pin Configurations (continued)

119-Ball BGA

Top View

CY7C1347C/GVT71128DA36

1234567

AVCCQ A A ADSP AAV

CCQ

BNC CE2 A ADSC ACE2NC

CNC A A VCC AANC

DDQc DQc VSS NC VSS DQb DQb

EDQc DQc VSS CE VSS DQb DQb

FVCCQ DQc VSS OE VSS DQb VCCQ

GDQc DQc BWc ADV BWb DQb DQb

HDQc DQc VSS GW VSS DQb DQb

JVCCQ VCC NC VCC NC VCC VCCQ

KDQd DQd VSS CLK VSS DQa DQa

LDQd DQd BWd NC BWa DQa DQa

MVCCQ DQd VSS BWE VSS DQa VCCQ

NDQd DQd VSS A1 VSS DQa DQa

PDQd DQd VSS A0 VSS DQa DQa

AMODEV

CC NC A NC

TNC NC A A A NC ZZ

UVCCQ

706 7',

TCK

7'2 1&

VCCQ

1234567

AVCCQ A A ADSP AAV

CCQ

BNC CE2 A ADSC ACE2NC

CNC A A VCC AANC

DDQb NC VSS NC VSS DQa NC

ENC DQb VSS CE VSS NC DQa

FVCCQ NC VSS OE VSS DQa VCCQ

GNC DQb BWb ADV VSS NC DQa

HDQb NC VSS GW VSS DQa NC

JVCCQ VCC NC VCC NC VCC VCCQ

KNC DQb VSS CLK VSS NC DQa

LDQb NC VSS NC BWa DQa NC

MVCCQ DQb VSS BWE VSS NC VCCQ

NDQb NC VSS A1 VSS DQa NC

PNC DQb VSS A0 VSS NC DQa

AMODEV

CC NC A NC

TNC A A NC A A ZZ

UVCCQ

706 7',

TCK

7'2 1&

VCCQ

256Kx18

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

128K X 3 6 Pin Descriptions

X36 BGA Pins X36 QFP Pins Name Type Description

2A, 3A, 5A, 6A,

3B, 5B, 2C, 3C,

5C, 6C, 2R, 6R,

3T, 4T, 5 T

35, 34, 33, 32,

100, 99 , 82, 81,

44, 45, 46, 47,

48, 49, 50

Input-

Synchronous Addresses: These inputs are registered and must meet the

set-up and hold times around the rising edge of CLK. The burst

count er gen erate s internal addr esse s asso ciated wi th A0 and

A1, durin g burst cycl e and wait cycl e.

BWa

BWb

BWc

BWd

Input-

Synchronous Byte Write: A byt e write is LOW fo r a Write c ycle a nd HIG H f or

a Read cycle. BWa controls DQa. BWb controls DQb. BWc

controls DQc. BWd controls DQd. Data I/O are high impedance

if either of these inputs are LOW, co nditioned by BW E being

LOW.

4M 87 BWE Input-

Synchronous Write Enab le: This acti ve LOW input gates byte writ e opera-

tions and must meet t he set-up and hold times ar ound t he

rising edge of CLK.

4H 88 GW Input-

Synchronous Global Write: This active LOW input a ll ows a f ull 36-bit Write

to occur independe nt of the BW E and BWn l ines and must

meet t he s et-up a nd ho ld tim es aroun d the ri sing ed ge of CLK.

4K 89 CLK Input-

Synchronous Cloc k: This signal registe rs the addres ses, data , chip enable s,

write con trol and bu rst control inputs o n it s rising edge. All

synchronous inputs must meet set-up and hold times around

the clock’s rising edge.

4E 98 CE Input-

Synchronous Chip Enable: This ac ti ve LO W input is u sed to en able the

device and to gate ADSP

6B 92 CE2 Input-

Synchronous Chip Enable: This ac ti ve LO W input is u sed to en able the

device.

TMS

TDI

TCK

Input IEEE 1149.1 test i nputs. LVTTL-level inputs.

5U 42 TDO Output IEEE 1149.1 test output. LVTTL- level output.

1B, 7B, 1C, 7C,

4D, 3J, 5J, 4L,

1 R, 5R, 7R, 1T,

2T, 6T, 6U

14, 16, 66 NC - No Connect: These signals are not int ernally connected.

256K X 1 8 Pin Descriptions

X18 BGA Pins X18 QFP Pins Name Type Description

2A, 3A, 5A, 6A,

3B, 5B, 2C, 3C,

5C, 6C, 2R, 6R,

2T, 3T, 5T, 6T

35, 34, 33, 32,

100, 99 , 82, 81,

80, 48, 47, 46,

45, 44, 49, 50

Input-

Synchronous Addresses: These inputs are registered and must meet the

set-up and hold times around the rising edge of CLK. The burst

count er gen erate s internal addr esse s asso ciated wi th A0 and

A1, durin g burst cycl e and wait cycl e.

3G 93

94 BWa

BWb Input-

Synchronous Byte W rite Enables: A byte write enable is LOW for a Write

cycle a nd H IGH for a Re ad cycle. BWa controls DQa. BWb

controls DQb . Data I/O are high imp edance if either of these

inputs are LOW, conditi oned by BWE being LOW.

4M 87 BWE Input-

Synchronous Write Enab le: This acti ve LOW input gates byte writ e opera-

tions and must meet the setup and hold times around the rising

edge of CLK.

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

4H 88 GW Input-

Synchronous Global Write: This active LOW input a ll ows a f ull 18-bit Write

to occur independe nt of the BW E and WEn lines and must

meet t he s et-up a nd ho ld tim es aroun d the ri sing ed ge of CLK.

4K 89 CLK Input-

Synchronous Cloc k: This signal registe rs the addres ses, data , chip enable s,

write con trol and bu rst control inputs o n it s rising edge. All

synchronous inputs must meet set-up and hold times around

the clock’s rising edge.

4E 98 CE Input-

Synchronous Chip Enable: This ac ti ve LO W input is u sed to en able the

device and to gate ADSP

6B 92 CE2 Input-

Synchronous Chip Enable: This ac ti ve LO W input is u sed to en able the

device.

2B 97 CE2 input-

Synchronous Chip enable: This acti ve HIGH input is used to enable the

device.

4F 86 OE Input Output Enable: T his active LO W asynchronous input en ables

the data output drivers.

4G 83 ADV Input-

Synchronous Addres s Advance: This a ctiv e LOW i nput is us ed to control the

int ernal bur st counter . A HI GH on thi s pin gene rates wai t cycle

(no address advance).

4A 84 ADSP Input-

Synchronous Address Status Processor: This active LOW in put, along wit h

CE being LOW, causes a new external address to be registered

and a READ cycle is initiated usi ng the new address.

4B 85 ADSC Input-

Synchronous Address Status Controll er: This acti ve LO W input causes de-

vice to be de-select ed or select ed along with new e xt ernal ad-

dress to be registered. A Read or Write cycle is initia ted de-

pending u pon write control inputs.

3R 31 MODE Input-

Static M ode: This input sel ects the burst sequence. A LOW on this

pin sel ects Linear Burst . A NC or HIGH on this pin selects

Interlea ved Burst.

256K X 1 8 Pin Descriptions

X18 BGA Pins X18 QFP Pins Name Type Description

Burst Addre ss Table (MO DE = NC/VCC)

First

Address

(external)

Second

Address

(internal)

Third

Address

(internal)

Fourth

Address

(internal)

A...A00 A...A01 A...A10 A...A11

A...A01 A...A00 A...A11 A...A10

A...A10 A...A11 A...A00 A...A01

A...A11 A...A10 A...A01 A...A00

Burs t Addres s Table (MODE = G ND)

First

Address

(external)

Second

Address

(internal)

Third

Address

(internal)

Fourth

Address

(internal)

A...A00 A...A01 A...A10 A...A11

A...A01 A...A10 A...A11 A...A00

A...A10 A...A11 A...A00 A...A01

A...A11 A...A00 A...A01 A...A10

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Truth Table[ 2, 3, 4, 5, 6, 7, 8]

Operation Address

Used CE CE2 CE2 ADSP ADSC ADV WRITE OE CLK DQ

Deselected Cycle, Power Down None H X X X L X X X L-H High-Z

Deselected Cycle, Power Down None L X L L X X X X L-H High-Z

Deselected Cycle, Power Down None L H X L X X X X L-H High-Z

Deselected Cycle, Power Down None L X L H L X X X L-H High-Z

Deselected Cycle, Power Down None L H X H L X X X L-H High-Z

READ Cycle, Begi n Burst External L L H L X X X L L-H Q

READ Cycle, Begi n Burst External L L H L X X X H L-H High-Z

WRITE Cycle, Begin Burst External L L H H L X L X L-H D

READ Cycle, Begi n Burst External L L H H L X H L L-H Q

READ Cycle, Begi n Burst External L L H H L X H H L-H High-Z

REA D C ycl e, C ont i nu e Bu rs t Next X X X H H L H L L-H Q

READ Cycle, Continue Bur st Next X X X H H L H H L-H High-Z

REA D C ycl e, C ont i nu e Bu rs t Next H X X X H L H L L-H Q

READ Cycle, Continue Bur st Next H X X X H L H H L-H High-Z

WRITE Cycle, Continue Burst Ne xt X X X H H L L X L-H D

WRITE Cycle, Continue Burst Ne xt H X X X H L L X L-H D

READ Cycle, Suspend Burst Current X X X H H H H L L-H Q

READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z

READ Cycle, Suspend Burst Current H X X X H H H L L- H Q

READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z

WRITE Cycle, Suspend Burst Current X X X H H H L X L-H D

WRITE Cycle, Suspend Burst Current H X X X H H L X L-H D

Partial Truth Table for RE AD/WRITE[9]

FUNCTION GW BWE BWa BWb BWc BWd

READ HHXXXX

READ HLHHHH

WRITE one b yte H L L H H H

WRITE all bytes H L L L L L

WRITE all bytes LXXXXX

Note:

2. X means “don’t care.” H means logic HIGH. L means logic LOW.

For X36 product, WRITE = L means [BWE + B Wa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.

For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equal s L OW. WR ITE = H means [BWE + BWa*BWb]*GW equals HIGH.

3. BWa enables write to DQa. BWb enables write to DQb . BWc enables write to DQc. BWd enables write to DQd.

4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.

5. Suspending burst generates wait cycle.

6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH

throughout the input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8. ADSP LOW along with chip being selected alwa ys initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW

for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.

9. For X18 product, there are only BWa and BWb.

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

IEEE 11 49.1 Serial Boundar y Scan (JTAG)

Overview

This device incorporates a serial boundary scan access por t

(TAP). This p ort is des igned t o opera te in a mann er c onsist ent

with IEEE Standard 1149.1-1990 (commonly referred to as

JTAG) , but does not implement all of the f unct ions req uired f or

IEEE 1149.1 compliance. Certain functions have been modi-

fied or eliminated because their implementation places extra

delays in the critical speed path of the device. Nevertheless,

the device suppor ts the standard TAP controller architecture

(the TAP controll er is the state machine that cont rols the TAPs

operation) and can be expected to function in a manner that

does not con flict wi th th e operat ion of de vic es with IEEE Stan-

dard 1149.1 compliant TAPs. The TAP operates using

LVTTL/LVCMOS logi c level signaling.

Disabling t he JTAG Feature

It is poss ib le t o use t his device wit hout using the JTA G f eat ure.

To disable the TAP controller without interfering with normal

oper at ion of the de v ice, TCK sh ould be t ied LO W ( VSS) to pr e-

v ent cloc king th e de vic e. TDI and TMS are int ernally pulled u p

and may be unconnected. They may alternately be pulled up

to VCC through a resistor. TDO should be left unconnected.

Upon power-up the dev ice will come up in a reset state wh ich

wil l not int erfere with the operation of the device.

Test Access Port (TAP)

TCK - Test Clock (INPUT)

Clocks all TAP events. All inputs are captured on the rising

edge of TCK and all outpu ts propagate from the f alling edge of

TCK.

TMS - Test Mode Select (INPUT)

The TMS input is sampled on the rising edge of TCK. This is

the command input for the TAP controller state machine. It i s

all owab le to leave this pin unconnected if t he TAP is not used.

The pin i s pulled up internally, resulting in a logic HIGH level.

TDI - Test Data In (INPUT)

The TDI i nput is sampled on the rising edge of TCK. Thi s is th e

input side of the serial regi sters place d betw een TDI and TDO .

The register placed between TDI and TDO is determined by

the state of t he TAP controll er state machi ne and the instruc-

tion that is currently loaded in the TAP instruction register (refer

to Figure 1, TAP Controller State Diagram). It is allowable to

leave this pin unconnected if it is not used in an application.

The pin is pulled up internally, resulting in a logic HIGH level.

TDI is connected to the most significant bit (MSB) of any reg-

ister. (See Figure 2.)

TDO - Test Dat a Out (OUTPUT)

The TDO output pi n is used to s eria ll y clock data-out from th e

registers. The output that is active depending on the st ate of

the TAP state ma chine (refer to Figure 1, TAP Controll er State

Diagram). Output changes in response to the falling edge of

TCK. This is the output side of the serial registers placed be-

tween TDI and TDO. TDO is connected to the least significant

bit (LSB) of any register. (See Figure 2.)

P erfor ming a TAP Res et

The TAP circuitry does not have a reset pin (TRST, which is

optional in the IEEE 1149.1 specification). A RESET can be

performed for the TAP controll er by forcing TM S HIGH (VCC)

for five ris ing ed ges of TCK and pre-loads the instruction reg -

ister with t he IDCODE command. This type of reset does not

affect the operation of the system logic. The reset affects test

logic only.

At power-up, the TAP is reset internally to ensure that TDO is

in a High-Z state.

Test Access Port (TAP) Registers

Overview

The various TAP registers are selected (one at a tim e) v ia t he

sequences of ones and z e ros in put to th e TMS pin as t he TCK

is st robed. Each of the TAPs registers ar e serial shift registers

that capture serial input data on the rising edge of TCK and

push seri al dat a o ut on s ubseq uent falling edge of TCK. W hen

a register is selected, it is connected between the TDI and

TDO pins.

Instr ucti on Register

The instru ction register holds the inst ructions that are ex ecut-

ed by the TAP controller when it is moved int o the run t est/idle

or the various data register states. The instructi ons are three

bits long. The register can be loaded when it is placed between

the TDI and TDO pins. The parallel outputs of the instruction

regis ter are a utomat icall y prel oaded with the IDCODE instruc-

tion upon po wer-u p or whenever the control ler is placed in t he

test-logic reset state. When the TAP controller is in the Cap-

ture- IR state , the t wo least significant bits of the seria l instruc-

tion register are loaded with a binary “01” pattern to allow for

fault isolation of the boar d-le vel serial test d ata path.

Bypass Register

The bypass register is a single-bit register that can be placed

between TDI and TDO. It all ows serial test data to be passed

through the device TAP to another device in the scan chain

with minimum delay. The bypass register is set LOW (VSS)

when the BYPASS instruct ion is e xecuted.

Boundary Scan Regist er

The Boundary scan regist er is connected to all the input and

bidirectional I/O pin s (not cou nting th e TAP pins) on the de vic e.

This also includes a number of NC pins that are reser ved for

futur e needs . Th ere are a total of 70 bi ts for x36 de vi ce and 51

bits f or x18 devic e. The bounda ry scan re giste r, under the con -

trol of the TAP controller, is loaded with the contents of the

device I /O ri ng when the controller is in Capture-DR state and

then is placed between the TDI and TDO pins when the con-

troller is moved to Shift-DR state. The EXTEST, SAMPLE/

PRELOAD and SAMPLE-Z instructions can be used to cap-

ture the contents of the I/O ring.

The Boundary Scan Order table describes the order in which

the bit s are connect ed. The first column def ines the bi t’s posi -

tion in the boundary scan register. The MSB of the register is

connected to TDI, and LSB is connected to TDO. The second

column is the signal name and the third column is the bump

number. The third column is the TQFP pin number and the

fourth co lu mn is th e BGA bump n u mber.

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Identification (I D) Regi ster

The ID Regi ster is a 32- bit r egist er that is loa ded with a dev ic e

and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the

instruction register. The register is then placed between the

TDI and TDO pins when the controll er is moved into Shift-DR

stat e. Bit 0 in the re gister i s the LSB an d the f irst to r each TDO

when shi f ting begins . The code is l oaded from a 32- bit o n-chi p

ROM. It describes various attrib utes of the device as described

in the Identificat ion Register Definitions table.

TAP Controller Instruction Se t

Overview

There are two cl asses of ins truc tions defined i n the IEEE St an-

dard 1149.1-1990; the standard (public) instructions and de-

vice specific (private) instructions. Some public instructions

are mandatory for IEEE 1149.1 compliance. Optional public

instructions must be implemented in prescrib ed w ays.

Although the TAP controller in this device follows the IEEE

1149.1 conventions, it is not IEEE 1149.1 compliant because

some of the man dat ory inst ructi ons are not f ully im plement ed.

The TAP on this device may be used to monitor all input and

I/O pad s, but can not be u sed to loa d a ddress , da ta, or co ntrol

signals into the device or to preload the I/O buffers. In other

wor ds, the device will not perform IEEE 1149.1 EXTEST, IN-

TEST, or the preload portion of the SAMPLE/PRELOAD com-

mand.

When t he TAP controller is plac ed in Capt ure-I R state , the tw o

least significant bits of the inst ruction register are loaded with

01. When the controller is moved to the Shift-IR state the in-

struction is serially loaded through the TDI input (while the

previous conte nts are shi ft ed out at TDO) . For all instructions,

the TAP executes newly loaded instructions only when the con-

troller is moved to Update-IR state. The TAP instruction sets

for this devic e are l isted in the f ollowing table s.

EXTEST

EXTEST is an IEEE 1149 .1 mandatory public instruction. It is

to be e x ecuted whene ver the instruction r egister is loade d with

all 0s. EXTEST is not implement ed in this dev ice.

The TAP controll er does recognize an all-0 inst ruction. W hen

an EXTEST instruction is loaded into the instruction register,

the device responds as if a SAMPLE/PRELOAD instruction

has been l oaded. There is one diff erence between two inst ruc-

ti ons. Un lik e SAMPLE/PRELO AD i nstructio n, EXTEST pl aces

the device outputs in a High-Z state.

IDCODE

The IDCODE i nstruction caus es a ve ndor-speci fic , 32-bit code

to be loaded into the ID r egister when the contr oller is i n Cap-

ture-DR mode and p laces the ID regis ter betw een the TDI and

TDO pins in Shift-DR mode. The IDCODE instruction is the

def ault ins tructi on loaded in the ins truction upo n power-u p and

at any time the TAP controller is placed in the test-logic reset

state.

SAMPLE-Z

If the High- Z instruct ion is load ed in the in struction r egi ster , all

output pins are f orced to a High-Z state and t he boundary scan

TAP controller is in a Shift- DR stat e.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.

The PRELO AD portion of the comman d is not implemen ted in

this device, so the device TAP controller is not fully IEEE

1149.1-compliant .

When the SAMPLE/ PRELOAD instruction i s loaded in the in-

struction register and the TAP controller is in the Capture-DR

state, a snap shot of the data in the device’s input and I/O

buf f ers i s load ed into the boundary scan r egiste r . Beca use the

device system clock(s) are independent from the TAP clock

(TCK), it i s possib le for the TAP to attempt to cap ture th e inpu t

and I/O ring contents while the buffers are in transition (i.e., in

a metastable state). Although allowing the TAP to sample

metastable inputs will not harm the device, repeatable results

can not be expected. To guarantee that the boundary scan

input signal s m ust be stabilized long eno ugh to me et the TAP

controller’s capture setup plus hold time (tCS plus tCH). The

device clock input(s) need not be paused for any other TAP

operat ion e x cept capt uring th e input an d I/O ring c ontents into

the boundary scan register.

Mov ing the co ntrolle r to Shif t-DR st ate then p laces t he bound -

ary scan r egist er betw een the TDI and TDO pins . Be cause t he

PRELO AD portion of the command is not implemented in this

device, moving t he controller to the Updat e-DR state with the

SAMPLE/PRELOAD i nstruction loaded in the instruction reg-

ister has the s am e effect as the Pause-DR command.

BYPASS

When t he BYPASS instruction is loaded in the instructi on reg-

ister an d t he TAP control ler is i n the Sh ift-DR s tate , the b ypa ss

level scan path to be shortened to facilitate testing of other

devices in the scan path.

Reserved

Do not use these instructions. They are reserved for future

use.

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Note:

10. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Figure 1. TAP Cont roller State Diagram [10]

TEST-LOGIC

RESET

REUN-TEST/

IDLE SELECT

DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT

IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Figure 2. TAP Contr oller Block Diagram

012..

3031

Boundary Scan Regist er

Identificat ion Register

012..

012

Instruction Register

Bypass Register

Selection

Circuitry Selection

Circuitry

TAP Controller

TDI TDO

TDI

[11]

TAP DC Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3 V unless otherwise noted)

Parameter Description Test Conditions Min. Max. Unit

VIH Input High ( Logic 1) Voltage[12, 13] 2.0 VCC + 0.3 V

VIl Input Low (Logic 0) Voltage[12, 13] –0.3 0.8 V

ILIInput Leakage Current 0V < VIN < VCC –5.0 5.0 µA

ILITMS a nd TDI In put Le akage Current 0V < VIN < VCC –30 30 µA

ILOOutput Leakage Current Output disabled,

0V < VIN < VCCQ –5.0 5.0 µA

VOLC LVCMOS Output Low Vo ltage[12, 14] IOLC = 100 µA0.2 V

VOHC LVCMOS Output High Voltage[12, 14] IOHC = 100 µA VCC – 0.2 V

VOLT LVTTL Output Low Voltage[12] IOLT = 8.0 mA 0.4 V

VOHT LVTTL Output High Voltage[12] IOHT = 8. 0 mA 2.4 V

Notes:

11. X = 69 for the x36 configuration. X = 50 for the x18 configuration.

12. All Voltage referenced to VSS (GND).

13. Overshoot: VIH(AC)<VCC+1.5V f or t<tKHKH/2, Undershoot: VIL(AC)<–0.5V for t<tKHKH/2, Power-up: VIH<3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms.

During normal operation, VCCQ must not exceed VCC. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than tKHKL (min.).

14. This parameter is sampled.

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

TAP AC Switching Characteristics Over the Oper ati ng Range[15, 16]

Parameter Description Min. Max Unit

Clock

tTHTH Clock Cycle Time 20 ns

fTF Clock Frequency 50 MHz

tTHTL Clock HIGH Time 8ns

tTLTH Clock LO W Time 8ns

Output Times

tTLQX TCK LOW to TDO Unknown 0ns

tTLQV TCK LOW to TDO Valid 10 ns

tDVTH TDI Valid to TCK HIGH 5ns

tTHDX TCK H I G H to TDI Invali d 5ns

Set-up Times

tMVTH TMS Set -up 5ns

tCS Cap ture Set-up 5ns

Hold Times

tTHMX TMS Hold 5ns

tCH Cap ture Hold 5ns

Notes:

15. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

16. Test conditions are specified using the load in TAP AC Test Conditions.

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

TAP Timing and Test Conditions

(a)

3.0V

VSS

ALL INPUT PULSES

1.5V

1.5 ns

7(67 &/2&.

7&.

7+7+

7+7/

7/7+

7(67 02'( 6(/(&7

706

7(67 '$7$ ,1

7',

7(67 '$7$ 287

7'2

097+

7+0;

'97+

7+';

7/4;

7/49

Vt = 1.5V

TDO

= 50

Ω

20 pF

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Identif ication Register Definiti ons

Instruction Field 512K x 18 Description

REVISION NUMBER

(31:28) XXXX Reserved for re vision number .

DEVICE DEPTH

(27:23) 00111 Defines depth of words.

DEVICE WIDTH

(22:18) 00011 Defines width of bits.

RESERVED

(17:12) XXXXXX Reserved for future use.

CYPRESS JEDEC ID CODE (11:1) 00011100100 All ows unique ide ntification of DEVICE vendor.

ID Regist er Presence

Indicato r (0) 1Indicates the presence of an ID register.

Scan Regi ster Si z es

Instruction 3

Bypass 1

ID 32

Boundary Scan 51

Instruction Codes

Instruction Code Description

EXTEST 000 Captures I/O ring cont ents. Pla ces the bounda ry scan regist er between TDI

and TDO . Forces all device outputs to High-Z state. This instruc tion is not

IEEE 1149.1- com pliant.

IDCODE 001 Preloads ID register with vendor ID code and places it between TDI and

TDO. This instruction does not affect devi ce operati ons.

SAMPLE-Z 010 Ca ptures I/O ring content s. Places the bounda ry scan regist er between TDI

and TDO . Forces all device outputs to High-Z state.

RESERVED 011 Do not use these instructions; the y are reserved for future use.

SAMPLE/PRELOAD 100 Captu res I/O ring content s. Places the bounda ry scan register betwee n TDI

and TDO . This instruction does not aff ect d evice operati ons. Thi s instruction

does not impl em ent IEEE 1149.1 PRELOAD funct ion and is therefore not

1149.1-compliant.

RESERVED 101 Do not use these instructions; the y are reserved for future use.

RESERVED 110 Do not use these instructions; the y are reserved for future use.

BYPASS 111 Places the byp ass re gister betw een TDI and TDO. This instruction does not

affect de vice oper ations .

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Boundary Scan Order (1 28K x 36)

Bit# Sign al Name TQFP Bump ID

1 A 44 2R

2 A 45 3T

3 A 46 4T

4 A 47 5T

5 A 48 6R

6 A 49 3B

7 A 50 5B

8 DQa 51 6P

9 DQa 52 7N

10 DQa 53 6M

11 DQa 56 7L

12 DQa 57 6K

13 DQa 58 7P

14 DQa 59 6N

15 DQa 62 6L

16 DQa 63 7K

17 ZZ 64 7T

18 DQb 68 6H

19DQb697G

20 DQb 72 6F

21 DQb 73 7E

22 DQb 74 6D

23 DQb 75 7H

24DQb786G

25 DQb 79 6E

26 DQb 80 7D

27 A 81 6A

28 A 82 5A

29 ADV 83 4G

30 ADSP 84 4A

31 ADSC 85 4B

32 OE 86 4F

33 BWE 87 4M

34 GW 88 4H

35 CLK 89 4K

36 CE292 6B

37 BWa 93 5L

38 BWb 94 5G

39 BWc 95 3G

40 BWd 96 3L

41 CE297 2B

42 CE 98 4E

43 A 99 3A

44 A 100 2A

45 DQc 1 2D

46 DQc 2 1E

47 DQc 3 2F

48 DQc 6 1G

49 DQc 7 2H

50 DQc 8 1D

51 DQc 9 2E

52 DQc 12 2G

53 DQc 13 1H

54 NC 14 5R

55 DQd 18 2K

56 DQd 19 1L

57 DQd 22 2M

58 DQd 23 1N

59 DQd 24 2P

60 DQd 25 1K

61 DQd 28 2L

62 DQd 29 2N

63 DQd 30 1P

64 MODE 31 3R

65 A 32 2C

66 A 33 3C

67 A 34 5C

68 A 35 6C

69 A1 36 4N

70 A0 37 4P

Boundary Scan Order (128K x 3 6)

Bit# Signal Name TQFP Bump ID

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Ma xi mu m Ra ti n gs

(Above which the useful life may be impaired. For user guide-

lines , not tested.)

Volt age on V CC Supply Relative to VSS..........–0.5V to +4. 6V

VIN ..........................................................–0.5V to VCC+0.5V

Storage Temperature (plastic) ......................–55°C to +150°

Junction Temperature ..................................................+150°

Powe r D is si p at io n. .. ..... .. ..... ..... ... .... ... ..... ..... .. ..... .. ..... ... . 1 .0 W

Short Circuit Output Current........................................50 mA

Note:

17. TA is the case temperature .

Boundary Scan Order (2 56K x 18)

Bit# Signal

Name TQFP Bump ID

1 A 44 2R

2 A 45 2T

3 A 46 3T

4 A 47 5T

5 A 48 6R

6 A 49 3B

7 A 50 5B

8 DQa 58 7P

9 DQa 59 6N

10 DQa 62 6L

11 DQa 63 7K

12 ZZ 64 7T

13 DQa 68 6H

14 DQa 69 7G

15 DQa 72 6F

16 DQa 73 7E

17 DQa 74 6D

18 A 80 6T

19 A 81 6A

20 A 82 5A

21 ADV 83 4G

22 ADSP 84 4A

23 ADSC 85 4B

24 OE 86 4F

25 BWE 87 4M

26 GW 88 4H

27 CLK 89 4K

28 CE2 92 6B

29 BWa 93 5L

30 BWb 94 3G

31 CE2 97 2B

32 CE 98 4E

33 A 99 3A

34 A 100 2A

35 DQb 8 1D

36 DQb 9 2E

37 DQb 12 2G

38 DQb 13 1H

39 NC 14 5R

40 DQb 18 2K

41 DQb 19 1L

42DQb222M

43 DQb 23 1N

44 DQb 24 2P

45 MODE 31 3R

46 A 32 2C

47 A 33 3C

48 A 34 5C

49 A 35 6C

50 A1 36 4N

51 A0 37 4P

Operating Range

Range Ambient

Temperature[17] VDD

Com’l 0°C to +70 °C 3.3V −5%/+10%

Boundary Scan Order (256K x 1 8)

Bit# Signal

Name TQFP Bump ID

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Electrical Characteristics Over t he Operating Range

Parameter Description Test Condi tions Min. Max. Unit

VIHD Input High (Logic 1) Vol tage[ 12, 18] Data Inputs ( D Qx) 2.0 VCC+0.3 V

VIH All Other Inputs 2.0 4.6 V

VIl Input Lo w (Logic 0) Voltag e[12, 18] –0.5 0.8 V

ILIInput Leakage Current 0V < VIN < VCC –5 5 µA

ILIMODE and ZZ Input Lea kage

Current[19] 0V < VIN < VCC –30 30 µA

ILOOutput Leakage Current Output(s ) disab l ed, 0V < VOUT < VCC –5 5 µA

VOH Output High Voltage[12] IOH = –5.0 mA 2.4 V

VOL Output Low Voltage[12] IOL = 8.0 mA 0.4 V

VCC Supply Vol tage[12] 3.135 3.6 V

VCCQ I/O Supply Voltage[12] 3.135 VCC V

Parameter Description Conditions Typ. -4 -4.4 -5 -6 Unit

ICC Power Supply

Current:

Operating[20, 21, 22]

Device selected; all inputs < VILor > VIH;

cycle time > tKC min.; VCC = Max.;

outp uts op en

150 450 400 360 300 mA

ISB2 CMOS St andby[2 1, 22] Device deselected; VCC = Max.;

all inputs < VSS + 0. 2 or >VCC – 0.2 ;

all inputs static; CLK frequency = 0

5 10101010mA

ISB3 TTL Standby[21, 22] Device deselected; all inputs < VIL

or > VIH; all inputs s tatic;

VCC = M ax.; CLK frequency = 0

10 20 20 20 20 mA

ISB4 Clock Running[21, 22] Device deselecte d;

all inputs < VIL or > VIH; VCC = Max.;

CLK cycle time > tKC min.

40 140 125 110 90 mA

Capacitance[14]

Parameter Description Test Conditions Typ. Max. Unit

CIInput Capac it ance TA = 25°C, f = 1 MHz,

VCC = 3.3V 5 7 pF

COInput/ O utput Capacitance (DQ) 7 8 pF

Thermal Resistance

Descript ion Test Conditions Symbol TQFP Typ. Unit

Thermal Resistance (Junction to Ambient) Still Air, so ldered on a 4.25 x 1.125 inch,

4-l ayer PCB ΘJA 25 °C/W

Thermal Resistance (Junction to Case) ΘJC 9°C/W

Notes:

18. Overshoot: VIH ≤ +6.0V fo r t ≤ tKC /2.

Undershoot:VIL ≤ –2.0V for t ≤ tKC /2.

19. Output loading is specified with CL = 5 pF as in AC Test Loads.

20. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.

21. “Devi ce Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.

22. Typical values are measured at 3.3V, 25°C, and 20-ns cycle time.

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

AC Test Loads and W aveforms

317Ω

351Ω

5pF

(a) (b)

50Ω

Z0=50Ω

Vt= 1. 5V

3.3V ALL INPUT PULSES

3.0V

90%

10% 90%

10%

≤1.5 ns ≤1.5 ns

(c)

Switching Characteristics Over the Operating Range[23]

-4

250 MHz -4.4

225 MHz -5

200 MHz -6

166 MHz

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

Clock

tKC Clock C y cle T im e 4.0 4.4 5.0 6.0 ns

tKH Clock HIGH Time 1.6 1.7 2.0 2.4 ns

tKL Clo ck LOW Time 1.6 1.7 2.0 2.4 ns

Output Times

tKQ Clock to Output Valid 2.5 2.5 2.5 3.5 ns

tKQX Clock to Output Invalid 1.25 1.25 1.25 1.25 ns

tKQLZ Clock to Output in Low-Z[ 14, 19 , 24 ] 0 0 0 0 ns

tKQHZ Clock to Output in High-Z[14, 19, 24] 1.25 3.0 1.25 3.0 1.25 3.0 1.25 4.0 ns

tOEQ OE to Output Valid[25] 2.5 2.5 2.5 3.5 ns

tOELZ OE to Output in Low-Z[14, 19, 24] 0 0 0 0 ns

tOEHZ OE to Output in High-Z[14, 19, 24] 2.5 2.5 2.5 3.5 ns

Set-up Times

tSAddress, Controls, and Data In[26] 1.0 1.0 1.0 1.0 ns

Hold Times

tHAddress, Controls, and Data In[26] 1.0 1.0 1.0 1.0 ns

Typ i cal Ou tp u t B u ffer C h ar acte ristics

Output High Vol tage Pull-Up Current Output Low Vol tage Pull-Down Current

VOH (V ) IOH (mA ) Min. IOH (mA) Max. V OL (V) IOL (mA) Min. IOL(mA) Max.

–0.5 –38 –105 –0.5 0 0

0–38 –105 0 0 0

0.8 –38 –105 0.4 10 20

1.25 –26 –83 0.8 20 40

1.5 –20 –70 1.25 31 63

2.3 0 –30 1.6 40 80

2.7 0 –10 2.8 40 80

2.9 0 0 3.2 40 80

3.4 0 0 3.4 40 80

Notes:

23. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.

24. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ.

25. OE is a “don’t care” when a byte write enable is sampled LOW.

26. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except f or “don’t care” as defined in the truth table.

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Swi t ch ing Waveforms

Read Timing[27 , 2 8 ]

Notes:

27. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active.

28. For X18 product, there are only BWa and BWb for byte write control.

CLK

ADSP#

ADSC#

ADDRESS

BWa#, BWb#,

BWc#, BWd#,

BWE#, GW#

CE#

ADV#

OE#

A1 A2

Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1)

tKQ

tKQLZ tOELZ tKQ

tKH

tKL

tKC

tOEQ

SINGLE READ BURST READ

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Write Timing[27, 28]

Swi t ch ing Waveforms (continued)

CLK

ADSP#

ADSC#

ADDRESS

CE#

ADV#

OE#

A1 A2

D(A2) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2)

GW#

D(A1) D(A2+1)

tKQX

tOEHZ

QD(A2+1)

SINGLE WRITE BURST WRITE BURST WRITE

BWa#, BWb#,

BWc#, BWd#,

BWE#, GW#

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Read/Write Timing[27, 28]

Swi t ch ing Waveforms (continued)

CLK

ADSP#

ADSC#

ADDRESS

CE#

ADV#

OE#

A2 A3

Q(A1) Q(A2)

D(A3) Q(A4) Q(A4+1) Q(A4+2) D(A5) D(A5+1)

Single Write Burst Read Burst WriteSingle Reads

BWa#, BWb#,

BWc#, BWd#,

BWE#, GW#

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Document #: 38-01000

Ordering Information

Speed

(MHz) Or dering Code Package

Name Pack age Type Operating

Range

250 CY7C1347C-250AC/

GVT71128DA36T-4 A101 100-Lead 14 x 20 x 1.4 mm Thin Qua d Fl at Pack Commercial

CY7C1347C-250BGC/

GVT71128DA36B-4 BG119 119-Lead FBG A (14 x 22 x 2.4 mm)

225 CY7C1347C-225AC/

GVT71128DA36T-4.4 A101 100-Lea d 14 x 20 x 1. 4 mm Thi n Qua d Flat P ac k

CY7C1347C-225BGC/

GVT71128DA36B-4.4 BG119 119-Lead FBGA (14 x 22 x 2.4 mm)

200 CY7C1347C-200AC/

GVT71128DA36T-5 A101 100-Lead 14 x 20 x 1.4 mm Thin Qua d Fl at Pack

CY7C1347C-200BGC/

GVT71128DA36B-5 BG119 119-Lead FBG A (14 x 22 x 2.4 mm)

166 CY7C1347C-166AC/

GVT71128DA36T-6 A101 100-Lead 14 x 20 x 1.4 mm Thin Qua d Fl at Pack

CY7C1347C-16BGC/

GVT71128DA36B-6 BG119 119-Lead FBG A (14 x 22 x 2.4 mm)

250 CY7C1327C-250AC/

GVT71256DA18T-4 A101 100-Lead 14 x 20 x 1.4 mm Thin Qua d Fl at Pack Commercial

CY7C1327C-250BGC/

GVT71256DA18B-4 BG119 119-Lead FBG A (14 x 22 x 2.4 mm)

225 CY7C1327C-225AC/

GVT71256DA18T-4.4 A101 100-Lea d 14 x 20 x 1. 4 mm Thi n Qua d Flat P ac k

CY7C1327C-225BGC/

GVT71256DA18B-4.4 BG119 119-Lead FBGA (14 x 22 x 2.4 mm)

200 CY7C1327C-200AC/

GVT71256DA18T-5 A101 100-Lead 14 x 20 x 1.4 mm Thin Qua d Fl at Pack

CY7C1327C-200BGC/

GVT71256DA18B-5 BG119 119-Lead FBG A (14 x 22 x 2.4 mm)

166 CY7C1327C-166AC/

GVT71256DA18T-6 A101 100-Lead 14 x 20 x 1.4 mm Thin Qua d Fl at Pack

CY7C1327C-16BGC/

GVT71256DA18B-6 BG119 119-Lead FBG A (14 x 22 x 2.4 mm)

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

Packag e Diagram s

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

of any circui try other than circuitry embodied in a Cypress Semiconductor pr oduct. Nor does it conv ey or imply any lice nse under patent or other rights . Cypress Semi conductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of s u ch use and in doing so indemnifies Cypress Semiconductor against all charges.

Packag e Diagram s (continued)

119-Lead FBGA (14 x 22 x 2.4 mm) BG119

51-85115