MMBT4403LT1G - ON Semiconductor

Switching Transistor

PNP Silicon

MAXIMUM RATINGS

Rating Symbol Value Unit

Collector–Emitter Voltage VCEO –40 Vdc

Collector–Base Voltage VCBO –40 Vdc

Emitter–Base V oltage VEBO –5.0 Vdc

Collector Current — Continuous IC–600 mAdc

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Total Device Dissipation FR–5 Board(1)

TA = 25°C

Derate above 25°C

PD225

1.8

mW/°C

Thermal Resistance, Junction to Ambient RJA 556 °C/W

Total Device Dissipation

Alumina Substrate,(2) TA = 25°C

Derate above 25°C

PD300

2.4

mW/°C

Thermal Resistance, Junction to Ambient RJA 417 °C/W

Junction and Storage Temperature TJ, Tstg –55 to +150 °C

DEVICE MARKING

MMBT4403LT1 = 2T

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS

Collector–Emitter Breakdown Voltage(3)

(IC = –1.0 mAdc, IB = 0) V(BR)CEO –40 — Vdc

Collector–Base Breakdown Voltage

(IC = –0.1 mAdc, IE = 0) V(BR)CBO –40 — Vdc

Emitter–Base Breakdown Voltage

(IE = –0.1 mAdc, IC = 0) V(BR)EBO –5.0 — Vdc

Base Cutoff Current

(VCE = –35 Vdc, VEB = –0.4 Vdc) IBEV — –0.1 µAdc

Collector Cutoff Current

(VCE = –35 Vdc, VEB = –0.4 Vdc) ICEX — –0.1 µAdc

1. FR–5 = 1.0  0.75  0.062 in.

2. Alumina = 0.4  0.3  0.024 in. 99.5% alumina.

3. Pulse Test: Pulse Width  300 s, Duty Cycle  2.0%.

ON Semiconductor

 Semiconductor Components Industries, LLC, 2001

March, 2001 – Rev. 1 1Publication Order Number:

MMBT4403LT1/D

MMBT4403LT1

CASE 318–08, STYLE 6

SOT–23 (TO–236)

COLLECTOR

BASE

EMITTER

MMBT4403LT1

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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)

Characteristic Symbol Min Max Unit

ON CHARACTERISTICS

DC Current Gain

(IC = –0.1 mAdc, VCE = –1.0 Vdc)

(IC = –1.0 mAdc, VCE = –1.0 Vdc)

(IC = –10 mAdc, VCE = –1.0 Vdc)

(IC = –150 mAdc, VCE = –2.0 Vdc)(3)

(IC = –500 mAdc, VCE = –2.0 Vdc)(3)

hFE 30

100

—

300

—

Collector–Emitter Saturation Voltage(3)

(IC = –150 mAdc, IB = –15 mAdc)

(IC = –500 mAdc, IB = –50 mAdc)

VCE(sat) —

—–0.4

–0.75

Vdc

Base–Emitter Saturation Voltage (3)

(IC = –150 mAdc, IB = –15 mAdc)

(IC = –500 mAdc, IB = –50 mAdc)

VBE(sat) –0.75

—–0.95

–1.3

Vdc

SMALL–SIGNAL CHARACTERISTICS

Current–Gain — Bandwidth Product

(IC = –20 mAdc, VCE = –10 Vdc, f = 100 MHz) fT200 — MHz

Collector–Base Capacitance

(VCB = –10 Vdc, IE = 0, f = 1.0 MHz) Ccb — 8.5 pF

Emitter–Base Capacitance

(VBE = –0.5 Vdc, IC = 0, f = 1.0 MHz) Ceb — 30 pF

Input Impedance

(IC = –1.0 mAdc, VCE = –10 Vdc, f = 1.0 kHz) hie 1.5 15 kΩ

Voltage Feedback Ratio

(IC = –1.0 mAdc, VCE = –10 Vdc, f = 1.0 kHz) hre 0.1 8.0 X 10–4

Small–Signal Current Gain

(IC = –1.0 mAdc, VCE = –10 Vdc, f = 1.0 kHz) hfe 60 500 —

Output Admittance

(IC = –1.0 mAdc, VCE = –10 Vdc, f = 1.0 kHz) hoe 1.0 100 mhos

SWITCHING CHARACTERISTICS

Delay Time (VCC = –30 Vdc, VEB = –2.0 Vdc, td— 15

Rise Time

(VCC

Vdc

VEB

Vdc

IC = –150 mAdc, IB1 = –15 mAdc) tr— 20 ns

Storage Time (VCC = –30 Vdc, IC = –150 mAdc, ts— 225

Fall Time

(VCC

Vdc

150

mAdc

IB1 = IB2 = –15 mAdc) tf— 30 ns

3. Pulse Test: Pulse Width  300 s, Duty Cycle  2.0%.

Figure 1. Turn–On Time Figure 2. Turn–Off Time

SWITCHING TIME EQUIVALENT TEST CIRCUIT

Scope rise time < 4.0 ns

*Total shunt capacitance of test jig connectors, and oscilloscope

+2 V

-16 V 10 to 100 µs,

DUTY CYCLE = 2%

1.0 kΩ

-30 V

200 Ω

CS* < 10 pF 1.0 kΩ

-30 V

200 Ω

CS* < 10 pF

+4.0 V

< 2 ns

1.0 to 100 µs,

DUTY CYCLE = 2%

< 20 ns

+14 V

-16 V

MMBT4403LT1

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Figure 3. Capacitances

REVERSE VOLTAGE (VOLTS)

7.0

5.0

Figure 4. Charge Data

IC, COLLECTOR CURRENT (mA)

0.1 2.0 5.0 10 20

2.0

CAPACITANCE (pF)

Q, CHARGE (nC)

2.0

3.0

5.0

7.0

1.0

10 20 50 70 100 200

0.1 300 500

0.7

0.5

VCC = 30 V

IC/IB = 10

Figure 5. Turn–On Time

IC, COLLECTOR CURRENT (mA)

5.0

7.0

Figure 6. Rise Time

IC, COLLECTOR CURRENT (mA)

Figure 7. Storage Time

IC, COLLECTOR CURRENT (mA)

Ceb

25°C100°C

TRANSIENT CHARACTERISTICS

3.01.00.50.30.2

0.3

0.2

ts, STORAGE TIME (ns)

′

t, TIME (ns)

Ccb

100

10 20 50 70 100 200 300 500

IC/IB = 10

tr @ VCC = 30 V

tr @ VCC = 10 V

td @ VBE(off) = 2 V

td @ VBE(off) = 0 20

5.0

7.0

100

10 20 50 70 100 200 300 500

VCC = 30 V

IC/IB = 10

10 20 50 70 100 200 300 500

100

200

0.7 7.0

tr, RISE TIME (ns)

IC/IB = 10

IC/IB = 20

IB1 = IB2

ts′ = ts - 1/8 tf

MMBT4403LT1

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0.1 2.0 5.0 10 20 50

1.00.50.20.01 0.02 0.05 100

Figure 8. Frequency Effects

f, FREQUENCY (kHz)

SMALL–SIGNAL CHARACTERISTICS

NOISE FIGURE

VCE = –10 Vdc, TA = 25°C; Bandwidth = 1.0 Hz

NF, NOISE FIGURE (dB)

IC = 1.0 mA, RS = 430 Ω

IC = 500 µA, RS = 560 Ω

IC = 50 µA, RS = 2.7 kΩ

IC = 100 µA, RS = 1.6 kΩ

RS = OPTIMUM SOURCE RESISTANCE

50 100 200 500 1k 2k 5k 10k 20k 50k

NF, NOISE FIGURE (dB)

Figure 9. Source Resistance Effects

RS, SOURCE RESISTANCE (OHMS)

f = 1 kHz

IC = 50 µA

100 µA

500 µA

1.0 mA

h PARAMETERS

VCE = –10 Vdc, f = 1.0 kHz, TA = 25°C

This group of graphs illustrates the relationship between

hfe and other “h” parameters for this series of transistors. To

obtain these curves, a high–gain and a low–gain unit were

selected from the MMBT4403LT1 lines, and the same units

were used to develop the correspondingly–numbered curves

on each graph.

Figure 10. Current Gain

IC, COLLECTOR CURRENT (mAdc)

0.1 0.2 0.5 0.7 1.0 2.0 3.0 10

0.3

300

700

200

100

1000

hfe, CURRENT GAIN

hie, INPUT IMPEDANCE (OHMS)

Figure 11. Input Impedance

IC, COLLECTOR CURRENT (mAdc)

100k

100

5.0 7.0

20k

10k

5k

2k

1k

0.1 0.2 0.5 0.7 1.0 2.0 3.0 10

0.3 5.0 7.0

Figure 12. Voltage Feedback Ratio

IC, COLLECTOR CURRENT (mAdc)

0.1 0.2 0.5 0.7 1.0 2.0 3.0 10

0.3

0.1

Figure 13. Output Admittance

IC, COLLECTOR CURRENT (mAdc)

500

1.0

5.0 7.0

5.0

2.0

5.0

2.0

1.0

0.5

0.2

h , OUTPUT ADMITTANCE ( mhos)

h , VOLTAGE FEEDBACK RATIO (X 10 )



-4

MMBT4403LT1 UNIT 1

MMBT4403LT1 UNIT 2

0.1 0.2 0.5 0.7 1.0 2.0 3.0 10

0.3 5.0 7.0

500

50k

500

200

100

MMBT4403LT1 UNIT 1

MMBT4403LT1 UNIT 2

MMBT4403LT1 UNIT 1

MMBT4403LT1 UNIT 2

MMBT4403LT1 UNIT 1

MMBT4403LT1 UNIT 2

MMBT4403LT1

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STATIC CHARACTERISTICS

Figure 14. DC Current Gain

IC, COLLECTOR CURRENT (mA)

Figure 15. Collector Saturation Region

IB, BASE CURRENT (mA)

0.4

0.6

0.8

1.0

0.2

0.1

V , COLLECTOR-EMITTER VOLTAGE (VOLTS)

0.5 2.0 3.0 500.2 0.3

1.00.7 5.0 7.0

IC = 1.0 mA

0.070.050.030.020.01

10 mA 100 mA

10 20 30

0.3

0.5

0.7

1.0

3.0

0.1

h , NORMALIZED CURRENT GAIN

0.5 2.0 3.0 10 50 70

0.2 0.3

0.2

100

1.00.7 500

30205.0 7.0

TJ = 125°C

-55°C

2.0

200 300

25°C

VCE = 1.0 V

VCE = 10 V

Figure 16. “On” Voltages

IC, COLLECTOR CURRENT (mA)

0.4

0.6

0.8

1.0

0.2

Figure 17. Temperature Coefficients

IC, COLLECTOR CURRENT (mA)

VOLTAGE (VOLTS)

1.0 2.0 5.0 10 20 50

100

0.5

1.0

1.5

2.0

500

TJ = 25°C

VBE(sat) @ IC/IB = 10

VCE(sat) @ IC/IB = 10

VBE(sat) @ VCE = 10 V

VC for VCE(sat)

VS for VBE

200

0.1 0.2 0.5

COEFFICIENT (mV/ C)°

2.5 1.0 2.0 5.0 10 20 50 100 500

200

0.1 0.2 0.5

500 mA

0.005

MMBT4403LT1

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The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values

into the equation for an ambient temperature TA of 25°C,

one can calculate the power dissipation of the device which

in this case is 225 milliwatts.

INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the

total design. The footprint for the semiconductor packages

must be the correct size to insure proper solder connection

interface between the board and the package. With the

correct pad geometry, the packages will self align when

subjected to a solder reflow process.

SOT–23

inches

0.037

0.95

0.037

0.95

0.079

2.0

0.035

0.9

0.031

0.8

SOT–23 POWER DISSIPATION

PD = TJ(max) – TA

RθJA

PD = 150°C – 25°C

556°C/W = 225 milliwatts

The power dissipation of the SOT–23 is a function of the

pad size. This can vary from the minimum pad size for

soldering to a pad size given for maximum power dissipa-

tion. Power dissipation for a surface mount device is deter-

mined b y T J(max), the maximum rated junction temperature

of the die, RθJA, the thermal resistance from the device

junction to ambient, and the operating temperature, TA.

Using the values provided on the data sheet for the SOT–23

package, PD can be calculated as follows:

The 556°C/W for the SOT–23 package assumes the use

of the recommended footprint on a glass epoxy printed

circuit board to achieve a power dissipation of 225 milli-

watts. There are other alternatives to achieving higher

power dissipation from the SOT–23 package. Another

alternative would be to use a ceramic substrate or an

aluminum core board such as Thermal Clad. Using a

board material such as Thermal Clad, an aluminum core

board, the power dissipation can be doubled using the same

footprint.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the

rated temperature of the device. When the entire device is

heated to a high temperature, failure to complete soldering

within a short time could result in device failure. There-

fore, the following items should always be observed in

order to minimize the thermal stress to which the devices

are subjected.

•Always preheat the device.

•The delta temperature between the preheat and

soldering should be 100°C or less.*

•When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering

method, the difference shall be a maximum of 10°C.

•The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

•When shifting from preheating to soldering, the

maximum temperature gradient shall be 5°C or less.

•After soldering has been completed, the device should

be allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and

result in latent failure due to mechanical stress.

•Mechanical stress or shock should not be applied

during cooling.

* Soldering a device without preheating can cause exces-

sive thermal shock and stress which can result in damage

to the device.

MMBT4403LT1

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PACKAGE DIMENSIONS

CASE 318–08

ISSUE AF

SOT–23 (TO–236)

DIM

MIN MAX MIN MAX

MILLIMETERS

0.1102 0.1197 2.80 3.04

INCHES

B0.0472 0.0551 1.20 1.40

C0.0350 0.0440 0.89 1.11

D0.0150 0.0200 0.37 0.50

G0.0701 0.0807 1.78 2.04

H0.0005 0.0040 0.013 0.100

J0.0034 0.0070 0.085 0.177

K0.0140 0.0285 0.35 0.69

L0.0350 0.0401 0.89 1.02

S0.0830 0.1039 2.10 2.64

V0.0177 0.0236 0.45 0.60

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH THICKNESS. MINIMUM LEAD THICKNESS

IS THE MINIMUM THICKNESS OF BASE

MATERIAL.

STYLE 6:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

MMBT4403LT1

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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

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MMBT4403LT1/D

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