Data Sheet R1QAA7236ABB / R1QAA7218ABB R1QDA7236ABB / R1QDA7218ABB 72-Mbit QDRTMII+ SRAM 4-word Burst R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Description The R1Q#A7236 is a 2,097,152-word by 36-bit and the R1Q#A7218 is a 4,194,304-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS sixtransistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package. # = A: Read Latency =2.5, w/o ODT # = D: Read Latency =2.5, w/ ODT Features Power Supply * 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ) Clock * * * * Fast clock cycle time for high bandwidth Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems Clock-stop capability with s restart I/O * * * * * * Separate independent read and write data ports with concurrent transactions 100% bus utilization DDR read and write operation HSTL I/O User programmable output impedance DLL/PLL circuitry for wide output data valid window and future frequency scaling Data valid pin (QVLD) to indicate valid data on the output Function * * * * Four-tick burst for reduced address frequency Internally self-timed write control Simple control logic for easy depth expansion JTAG 1149.1 compatible test access port Package * 165 FBGA package (13 x 15 x 1.4 mm) * RoHS Compliance Level = 6/6 R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 1 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Part Number Definition Column No. Example 0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16 R 1 Q A A 7 2 1 8 A B - 1 9 B 1 - 0-1 R1 Renesas Memory Prefix Q2 QDR II B2[*1] (L15)[*2] Q3 Comments No. - 9 A 10-11 BB PKG = BGA 13x15 mm QDR II B4 (L15) 40 Frequency = 250MHz Q4 DDR II B2 (L15) 33 Frequency = 300MHz QA QDR II+ B4 L25 25 Frequency = 400MHz QB DDR II+ B2 L25 20 Frequency = 500MHz 19 Frequency = 533MHz 12-13 ODT[*3] QD QDR II+ B4 L25 w/ QE DDR II+ B2 L25 w/ ODT QG QDR II+ B2 L20 QH DDR II+ B2 L20 4 A VDD = 1.8 V 5-6 72 Density = 72Mb 09 Data width = 9bit 18 Data width = 18bit 36 Data width = 36bit 7-8 I The above part number is just example for 72M QDRII+ B4 x18 533MHz, 13x15mm PKG, Pb-free part. No. 2-3 B Comments 2nd Generation 14 I Industrial temp. Ta range = -40oC to 85oC 15 B Pb-free and Tray 16 0 to 9, A to Z Renesas internal use or None Notes[*] 1. B=Burst length (B2: Burst length=2, B4: Burst length=4) 2. L=Read Latency (L15: Read Latency = 1.5 cycle, L20: 2.0 cycle, L25: 2.5 cycle) 3. ODT=On Die Termination R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 2 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB 72M QDR/DDR SRAM (R1Q*A72 Series) Lineup Renesas supports or plans to support the parts listed below. No Product Type Burst Length Latency (Cycle) ODT 1 2 3 B2 QDRII 4 B4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DDRII QDRII+ 1.5 No B2 B4 No DDRII+ B2 2.5 QDRII+ B4 Yes DDRII+ QDRII+ B2 B4 2.0 DDRII+ B2 No Organization Frequency (max) (MHz) 533 500 400 300 250 Cycle Time (min) (ns) 1.875 2.00 2.50 3.30 4.00 x9 R1Q2A7209ABB-yy x18 R1Q2A7218ABB-yy x36 R1Q2A7236ABB-yy x18 R1Q3A7218ABB-yy x36 R1Q3A7236ABB-yy x18 R1Q4A7218ABB-yy x36 R1Q4A7236ABB-yy x18 R1QAA7218ABB-yy x36 R1QAA7236ABB-yy x18 R1QBA7218ABB-yy x36 R1QBA7236ABB-yy x18 R1QDA7218ABB-yy x36 R1QDA7236ABB-yy x18 R1QEA7218ABB-yy x36 R1QEA7236ABB-yy x18 R1QGA7218ABB-yy x36 R1QGA7236ABB-yy x18 R1QHA7218ABB-yy x36 R1QHA7236ABB-yy -40 -33 -33 -19 -20 -19 -20 -19 -20 -19 -20 -25 -25 Notes 1. "yy" represents the speed bin. "R1QDA7236ABB-20" can operate at 500 MHz(max) of frequency, for example. 2. The part which is not listed above is not supported, as of the day when this datasheet was issued, in spite of the existence of the part number or datasheet. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 3 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Pin Arrangement R1QAA7236 series (Top View) 1 2 3 4 5 6 7 8 9 10 11 A /CQ NC SA /W /BW2 /K /BW1 /R SA NC CQ B Q27 Q18 D18 SA /BW3 K /BW0 SA D17 Q17 Q8 C D27 Q28 D19 VSS SA NC SA VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H /DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1 P Q35 D35 Q26 SA SA QVLD SA SA Q9 D0 Q0 R TDO TCK SA SA SA NC SA SA SA TMS TDI Notes 1. Address expansion order for future higher density SRAMs: 10A 2A 7A 5B. 2. NC pins can be left floating or connected to 0V VDDQ. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 4 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB R1QAA7218 series (Top View) 1 2 3 4 5 6 7 8 9 10 11 A /CQ NC SA /W /BW1 /K NC /R SA SA CQ B NC Q9 D9 SA NC K /BW0 SA NC NC Q8 C NC NC D10 VSS SA NC SA VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H /DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS SA SA SA VSS NC NC D1 P NC NC Q17 SA SA QVLD SA SA NC D0 Q0 R TDO TCK SA SA SA NC SA SA SA TMS TDI Notes 1. Address expansion order for future higher density SRAMs: 10A 2A 7A 5B. 2. NC pins can be left floating or connected to 0V VDDQ. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 5 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB R1QDA7236 series (Top View) 1 2 3 4 5 6 7 8 9 10 11 A /CQ NC SA /W /BW2 /K /BW1 /R SA NC CQ B Q27 Q18 D18 SA /BW3 K /BW0 SA D17 Q17 Q8 C D27 Q28 D19 VSS SA NC SA VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H /DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1 P Q35 D35 Q26 SA SA QVLD SA SA Q9 D0 Q0 R TDO TCK SA SA SA NC SA SA SA TMS TDI Notes 1. Address expansion order for future higher density SRAMs: 10A 2A 7A 5B. 2. NC pins can be left floating or connected to 0V VDDQ. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 6 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB R1QDA7218 series (Top View) 1 2 3 4 5 6 7 8 9 10 11 A /CQ NC SA /W /BW1 /K NC /R SA SA CQ B NC Q9 D9 SA NC K /BW0 SA NC NC Q8 C NC NC D10 VSS SA NC SA VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H /DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS SA SA SA VSS NC NC D1 P NC NC Q17 SA SA QVLD SA SA NC D0 Q0 R TDO TCK SA SA SA NC SA SA SA TMS TDI Notes 1. Address expansion order for future higher density SRAMs: 10A 2A 7A 5B. 2. NC pins can be left floating or connected to 0V VDDQ. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 7 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Pin Description Name SA I/O type Input /R Input /W Input /BW x Input K, /K Input /DOFF Input TMS TDI TCK Input ZQ Input ODT Input Input R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Descriptions Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. All transactions operate on a burst-of-four words (two clock periods of bus activity). These inputs are ignored when device is deselected. Synchronous read: When low, this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K, and is ignored on the subsequent rising edge of K. Synchronous write: When low, this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K, and is ignored on the subsequent rising edge of K. Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. These balls cannot remain VREF level. DLL/PLL disable: When low, this input causes the DLL/PLL to be bypassed for stable, low frequency operation. IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG function is not used in the circuit. IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to V SS if the JTAG function is not used in the circuit. Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. Q and CQ output impedance are set to 0.2 RQ, where RQ is a resistor from this ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by ODT control input. ODT control: When low; [Option 1] Low range mode is selected. The impedance range is between 52 and 105 (Thevenin equivalent), which follows 0.3 x RQ for 175 RQ 350 . [Option 2] ODT is disabled. When high; High range mode is selected. The impedance range is between 105 and 150 (Thevenin equivalent), which follows 0.6 x RQ for 175 RQ 250 . When floating; [Option 1] High range mode is selected. [Option 2] ODT is disabled. Notes 1 Page 8 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Name D0 to Dn I/O type Input CQ, /CQ Output TDO Q0 to Qn Output Output QVLD Output VDD Supply VDDQ Supply VSS VREF Supply - NC - Descriptions Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K and /K during WRITE operations. See Pin Arrangement figures for ball site location of individual signals. The x9 device uses D0~D8. D9~D35 should be treated as NC pin. The x18 device uses D0~D17. D18~D35 should be treated as NC pin. The x36 device uses D0~D35. Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tristates. IEEE 1149.1 test output: 1.8 V I/O level. Synchronous data outputs: Output data is synchronized to the respective C and /C, or to the respective K and /K if C and /C are tied high. This bus operates in response to /R commands. See Pin Arrangement figures for ball site location of individual signals. The x9 device uses Q0~Q8. Q9~Q35 should be treated as NC pin. The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin. The x36 device uses Q0~Q35. Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and /CQ. Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating Conditions for range. Power supply: Ground. HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise margin. Provides a reference voltage for the HSTL input buffers. No connect: These pins can be left floating or connected to 0V VDDQ. Notes 2 2 2 Notes 1. Renesas status: Option 1 = Available, Option 2 = Possible. 2. All power supply and ground balls must be connected for proper operation of the device R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 9 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Block Diagram R1QAA7236 / R1QAA7218 / R1QDA7236 / R1QDA7218 series 19/20/21 Address Address Registry and Logic 19/20/21 ZQ /R K /K K 72 /36 /18 144 /72 /36 Q (Data out) Output Select Output Buffer Memory Array 72 /36 /18 Output Register 72 Data /36 D 36/18/9 Registry /18 (Data in) and Logic Sense Amp /BWx Write Register 4/2/1 Write Driver /W MUX 72 /36 /18 MUX /R /W K /K 36/18/9 2 CQ /CQ C or K C,/C or K,/K Note 1. C and /C pins do not exist in II+ series parts. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 10 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB General Description Power-up and Initialization Sequence - VDD must be stable before K, /K clocks are applied. - Recommended voltage application sequence : VSS VDD VDDQ & VREF VIN. (0 V to VDD, VDDQ < 200 ms) - Apply VREF after VDDQ or at the same time as VDDQ. - Then execute either one of the following three sequences. 1. Single Clock Mode (C and /C tied high) - Drive /DOFF high (/DOFF can be tied high from the start). - Then provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series). These meet the QDR common specification of 20 us. When the operating frequency is less than 180 MHz, 2048 cycles are required (II series). Status Power Up & Unstable Stage NOP & Set-up Stage Normal Operation VDD VDDQ VREF Fix High (=VDDQ) /DOFF SET-UP Cycle K, /K R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 11 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB 2. Double Clock Mode (C and /C control outputs) (II series only) - Drive /DOFF high (/DOFF can be tied high from the start) - Then provide stable clocks (K, /K, C, /C) for at least 1024 cycles. This meets the QDR common specification of 20 us. When the operating frequency is less than 180 MHz, 2048 cycles are required. Status Power Up & Unstable Stage NOP & Set-up Stage Normal Operation VDD VDDQ VREF /DOFF Fix High (=VDDQ) SET-UP Cycle K, /K C, /C 3. DLL/PLL Off Mode (/DOFF tied low) - In the "NOP and setup stage", provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series). These meet the QDR common specification of 20 us. DLL/PLL Constraints 1. DLL/PLL uses K clock as its synchronizing input. The input should have low phase jitter which is specified as tKC var. 2. The lower end of the frequency at which the DLL/PLL can operate is 120 MHz. (Please refer to AC Characteristics table for detail.) 3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again. Programmable Output Impedance 1. Output buffer impedance can be programmed by terminating the ZQ ball to V SS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is 250 typical. The total external capacitance of ZQ ball must be less than 7.5 pF. QVLD (Valid data indicator) 1. QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop capturing the data. QVLD is edge aligned with CQ and /CQ. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 12 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB ODT (On Die Termination) R1QD, R1QE series 1. To reduce reflection which produces noise and lowers signal quality, the signals should be terminated, especially at high frequency. Renesas offers ODT on the input signals to QDR-II+ and DDR-II+ family of devices. (See the ODT pin table) 2. In ODT enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by ODT control input. (See the ODT range table) 3. In DDR-II+ devices having common I/O bus, ODT is automatically enabled when the device inputs data and disabled when the device outputs data. 4. There is no difference in AC timing characteristics between the SRAMs with ODT and SRAMs without ODT. 5. There is no increase in the IDD of SRAMs with ODT, however, there is an increase in the IDDQ (current consumption from the I/O voltage supply) with ODT. ODT range ODT control pin Thevenin equivalent resistance (RTHEV) Unit Notes Option 1 Option 2 - 6 Low 0.3 RQ (ODT disable) 1, 4 High 0.6 RQ 0.6 RQ 2, 5 Floating 0.6 RQ (ODT disable) 3 Notes 1. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of 20 % is 175 RQ 350 . 2. Allowable range of RQ to guarantee impedance matching a tolerance of 20 % is 175 RQ 250 . 3. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of 20 % is 175 RQ 250 . 4. At option 1, ODT control pin is connected to VDDQ through 3.5 k. Therefore it is recommended to connect it to VSS through less than 100 to make it low. 5. At option 2, ODT control pin is connected to VSS through 3.5 k. Therefore it is recommended to connect it to VDDQ through less than 100 to make it high. 6. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2, please contact Renesas sales office. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 13 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Thevenin termination Other LSI SRAM with ODT VDDQ 2 RTHEV ZQ RQ Output Buffer 2 RTHEV Input Buffer VSS VSS ODT pin R1QD, R1QE series ODT On/Off timing Notes Option 2 Pin name Option 1 ODT pin = High D0 ~ Dn in separate I/O devices Always On ODT pin = Low 3 or Floating Always Off 1 Always Off 2 Off: First Read Command + Read Latency DQ0 ~ DQn in common I/O devices - 0.5 cycle On: Last Read Command + Read Latency + BL/2 cycle + 0.5 cycle (See below timing chart) /BWx Always On Always Off K, /K Always On Always Off Notes 1. Separate I/O devices is R1QD series. 2. Common I/O devices is R1QE series. 3. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2, please contact Renesas sales office. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 14 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB K Truth Table Operation K Write Cycle : Load address, input write data on consecutive K and /K rising edges /LD R-/W D or Q Data in H*7 L*8 Input data D(A+0) D(A+1) D(A+2) D(A+3) Input clock K(t+1) /K(t+1) K(t+2) /K(t+2) Q(A+0) Q(A+1) Q(A+2) Q(A+3) RL*9 = 1.5 /C(t+1) C(t+2) /C(t+2) C(t+3) RL = 2.0 C(t+2) /C(t+2) C(t+3) /C(t+3) RL = 2.5 /C(t+2) C(t+3) /C(t+3) C(t+4) Data out Output data Read Cycle : Load address, output read data on consecutive C and /C rising edges Input clock for Q H H D = or Q = High-Z Stopped Previous state NOP (No operation) Standby (Clock stopped) L*8 Notes 1. H: high level, L: low level, : don't care, : rising edge. 2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges, except if C and /C are high, then data outputs are delivered at K and /K rising edges. 3. /R and /W must meet setup/hold times around the rising edges (low to high) of K and are registered at the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. If this signal was low to initiate the previous cycle, this signal becomes a "don't care" for this operation; however, it is strongly recommended that this signal be brought high, as shown in the truth table. 8. This signal was high on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The device will ignore the second request. 9. RL = Read Latency (unit = cycle). R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 15 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Byte Write Truth Table (x36) Operation Write D0 to D35 Write D0 to D8 Write D9 to D17 Write D18 to D26 Write D27 to D35 Write nothing K /K /BW0 /BW1 /BW2 /BW3 - L L L L - L L L L - L H H H - L H H H - H L H H - H L H H - H H L H - H H L H - H H H L - H H H L - H H H H - H H H H Notes 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Byte Write Truth Table (x18) Operation Write D0 to D17 Write D0 to D8 Write D9 to D17 Write nothing K /K /BW0 /BW1 - L L - L L - L H - L H - H L - H L - H H - H H Notes 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 16 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Bus Cycle State Diagram /R = H & RCount = 4 /R = H Read Port NOP /R = L RInit = 0 Supply voltage provided Load New Always Read Double Read Address RCount RCount = 0 = R Count + 2 RInit = 1 /R = L & RCount = 4 RCount =2 Increment Read Address by Two*1 RInit = 0 Always Power Up Supply voltage provided Always Write Double Load New Write Port NOP Write Address WCount WCount = 0 = WCount + 2 /W = L /W = L RInit = 0 & WCount = 4 /W = H /W = H & WCount = 4 WCount =2 Always Increment Write Address by Two*1 Notes 1. The address is concatenated with two additional internal LSBs to facilitate burst operation. The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3. Bus cycle is terminated at the end of this sequence (burst count = 4). 2. Read and write state machines can be active simultaneously. Read and write cannot be simultaneously initiated. Read takes precedence. 3. State machine control timing sequence is controlled by K. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 17 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Absolute Maximum Ratings Parameter Symbol Rating Unit Notes Input voltage on any ball VIN -0.5 to VDD + 0.5 (2.5 V max.) V 1, 4 Input/output voltage VI/O -0.5 to VDDQ + 0.5 (2.5 V max.) V 1, 4 Core supply voltage VDD -0.5 to 2.5 V 1, 4 Output supply voltage VDDQ -0.5 to VDD V 1, 4 5 Junction temperature Tj +125 (max) oC Storage temperature TSTG -55 to +125 oC Notes 1. All voltage is referenced to VSS. 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: V SS, VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the instantaneous value of VDDQ. 5. Some method of cooling or airflow should be considered in the system. (Especially for high frequency or ODT parts) Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Notes Power supply voltage - core VDD 1.7 1.8 1.9 V 1 Power supply voltage - I/O VDDQ 1.4 1.5 VDD V 1, 2 Input reference voltage - I/O VREF 0.68 0.75 0.95 V 3 Input high voltage VIH(DC) VREF + 0.1 - VDDQ + 0.3 V 1, 4, 5 Input low voltage VIL(DC) -0.3 - VREF - 0.1 V 1, 4, 5 Notes 1. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ. During normal operation, VDDQ must not exceed VDD. 2. Please pay attention to Tj not to exceed the temperature shown in the absolute maximum ratings table due to current from VDDQ. 3. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF. 4. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing parameters. 5. Overshoot: VIH(AC) VDDQ + 0.5 V for t tKHKH/2 Undershoot: VIL(AC) -0.5 V for t tKHKH/2 During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 18 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB DC Characteristics Ta = -40 ~ +85C VDD = 1.8V 0.1V, VDDQ = 1.5V, VREF = 0.75V Operating Supply Current (Write / Read) Symbol = IDD. Unit = mA. No Product Type Burst Length Latency ODT (Cycle) 1 2 3 B2 QDR II 4 1.5 No Organization Frequency (max) (MHz) 533 500 400 300 250 200 Cycle Time (min) (ns) 1.875 2.00 2.50 3.30 4.00 5.00 Speed bin -19 -20 -25 -33 -40 x9 R1Q2A7209ABB-yy 760 670 x18 R1Q2A7218ABB-yy 890 780 x36 R1Q2A7236ABB-yy 950 830 x18 R1Q3A7218ABB-yy 820 730 x36 R1Q3A7236ABB-yy 850 750 x18 R1Q4A7218ABB-yy 700 630 x36 R1Q4A7236ABB-yy 760 680 x18 R1QAA7218ABB-yy 1220 1160 1070 x36 R1QAA7236ABB-yy 1280 1220 1130 x18 R1QBA7218ABB-yy 1030 990 920 x36 R1QBA7236ABB-yy 1110 1060 990 x18 R1QDA7218ABB-yy 1220 1160 1070 x36 R1QDA7236ABB-yy 1280 1220 1130 x18 R1QEA7218ABB-yy 1030 990 920 x36 R1QEA7236ABB-yy 1110 1060 990 x18 R1QGA7218ABB-yy 980 x36 R1QGA7236ABB-yy 1060 x18 R1QHA7218ABB-yy 850 x36 R1QHA7236ABB-yy 910 B4 5 6 DDR II B2 7 8 QDR II+ B4 9 No 10 DDR II+ B2 11 2.0 12 QDR II+ B4 13 Yes 14 DDR II+ B2 15 16 QDR II+ B4 17 2.5 18 DDR II+ No B2 19 Notes 1. "yy" represents the speed bin. "R1QDA7236ABB-20" can operate at 500 MHz(max) of frequency, for example. 2. All inputs (except ZQ, VREF) are held at either VIH or VIL. 3. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. 4. Operating supply currents (IDD) are measured at 100% bus utilization. IDD of QDR family is current of device with 100% write and 100% read cycle. I DD of DDR family is current of device with 100% write cycle (if IDD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)). R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 19 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Standby Supply Current (NOP) Symbol = ISB1. Unit = mA. No Product Type Burst Length Latency ODT (Cycle) 1 2 3 B2 QDR II 4 1.5 No Organization Frequency (max) (MHz) 533 500 400 300 250 200 Cycle Time (min) (ns) 1.875 2.00 2.50 3.30 4.00 5.00 Speed bin -19 -20 -25 -33 -40 x9 R1Q2A7209ABB-yy 570 510 x18 R1Q2A7218ABB-yy 670 600 x36 R1Q2A7236ABB-yy 710 630 x18 R1Q3A7218ABB-yy 590 520 x36 R1Q3A7236ABB-yy 610 540 x18 R1Q4A7218ABB-yy 610 560 x36 R1Q4A7236ABB-yy 670 610 x18 R1QAA7218ABB-yy 870 830 780 x36 R1QAA7236ABB-yy 910 870 810 x18 R1QBA7218ABB-yy 870 840 780 x36 R1QBA7236ABB-yy 960 920 860 x18 R1QDA7218ABB-yy 870 830 780 x36 R1QDA7236ABB-yy 910 870 810 x18 R1QEA7218ABB-yy 870 840 780 x36 R1QEA7236ABB-yy 960 920 860 x18 R1QGA7218ABB-yy 720 x36 R1QGA7236ABB-yy 770 x18 R1QHA7218ABB-yy 720 x36 R1QHA7236ABB-yy 790 B4 5 6 DDR II B2 7 8 QDR II+ B4 9 No 10 DDR II+ B2 11 2.0 12 QDR II+ B4 13 Yes 14 DDR II+ B2 15 16 QDR II+ B4 17 2.5 18 DDR II+ No B2 19 Notes 1. "yy" represents the speed bin. "R1QDA7236ABB-20" can operate at 500 MHz(max) of frequency, for example. 2. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. 3. All address / data inputs are static at either VIN > VIH or VIN < VIL. 4. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.) R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 20 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Leakage Currents & Output Voltage Parameter Symbol Min Max Unit Input leakage current ILI -2 2 A 10 Output leakage current ILO -5 5 A 11 VOH (Low) VOH VDDQ - 0.2 VDDQ V Output high voltage VDDQ/2 - 0.12 VDDQ/2 + 0.12 V VSS 0.2 V VDDQ/2 - 0.12 VDDQ/2 + 0.12 V VOL (Low) VOL Output low voltage Test condition |IOH| 0.1 mA Notes 8, 9 6, 8, 9 IOL 0.1 mA 8, 9 7, 8, 9 Notes 1. All inputs (except ZQ, VREF) are held at either VIH or VIL. 2. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. 3. Operating supply currents (IDD) are measured at 100% bus utilization. IDD of QDR family is current of device with 100% write and 100% read cycle. I DD of DDR family is current of device with 100% write cycle (if IDD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)). 4. All address / data inputs are static at either VIN > VIH or VIN < VIL. 5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.) 6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 8. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 9. HSTL outputs meet JEDEC HSTL Class I and Class II standards. 10. 0 VIN VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball). If R1QD and R1QE series, balls with ODT do not follow this spec. 11. 0 VOUT VDDQ (except TDO ball), output disabled. Thermal Resistance Parameter Symbol Airflow Typ Junction to Ambient JA 1 m/s 11.0 Junction to Case JA - 4.4 Unit Test condition Notes oC/W EIA/JEDEC JESD51 1 Notes 1. These parameters are calculated under the condition. These are reference values. 2. Tj = Ta + JA x Pd Tj = Tc + JC x Pd where Tj : Junction temperature when the device has achieved a steady-state after application of Pd (C) Ta : Ambient temperature (C) Tc : Temperature of external surface of the package or case (C) JA : Thermal resistance from junction-to-ambient (C/W) JC : Thermal resistance from junction-to-case (package) (C/W) Pd : Power dissipation that produced change in junction temperature (W) (cf.JESD51-2A) R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 21 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Capacitance Ta = +25C, Frequency = 1.0MHz, VDD = 1.8V, VDDQ = 1.5V Parameter Symbol Min Typ Max Unit Test condition Notes Input capacitance (SA, /R, /W, /BW, D(separate)) Clock input capacitance (K, /K, C, /C) Output capacitance (Q(separate), DQ(common), CQ, /CQ) CIN - 4 5 pF VIN = 0 V 1, 2 CCLK - 4 5 pF VCLK = 0 V 1, 2 CI/O - 5 6 pF VI/O = 0 V 1, 2 Notes 1. These parameters are sampled and not 100% tested. 2. Except JTAG (TCK, TMS, TDI, TDO) pins. AC Test Conditions Input waveform Rise/fall time 0.3 ns 1.25V 0.75V Test points 0.75V VDDQ/2 Test points VDDQ/2 0.25V Output waveform R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 22 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Output load conditions 1.8V0.1V VDDQ / 2 = 0.75 V 1.5V VDD VDDQ SRAM VDDQ / 2 = 0.75V VREF 50 Z0 = 50 Q 250 ZQ VSS AC Operating Conditions Parameter Symbol Min Typ Max Unit Notes Input high voltage VIH(AC) VREF + 0.2 - - V 1, 2, 3, 4 Input low voltage VIL(AC) - - VREF - 0.2 V 1, 2, 3, 4 Notes 1. All voltages referenced to VSS (GND). During normal operation, VDDQ must not exceed VDD. 2. These conditions are for AC functions only, not for AC parameter test. 3. Overshoot: VIH(AC) VDDQ + 0.5 V for t tKHKH/2 Undershoot: VIL(AC) -0.5 V for t tKHKH/2 Control input signals may not have pulse widths less than tKHKL(min) or operate at cycle rates less than tKHKH(min). 4. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 23 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB AC Characteristics (QDR-II+, DDR-II+ series, Read Latency = 2.5cycle) Ta = -40 ~ +85C VDD = 1.8V 0.1V, VDDQ = 1.5V, VREF = 0.75V -19 Parameter Symbol -20 533 MHz Min Max 500 MHz Min Max 450 MHz Min Max Min Max Min Max Min Max U n I t 200 MHz 375 MHz 333 MHz N o t e s Clock Average clock cycle time (K, /K) tKHKH 1.875 4.00 2.00 4.00 2.22 4.00 2.50 4.00 2.66 4.00 3.00 4.00 ns Clock high time (K, /K) tKHKL 0.40 - 0.40 - 0.40 - 0.40 - 0.40 - 0.40 - Cy cle Clock low time (K, /K) tKLKH 0.40 - 0.40 - 0.40 - 0.40 - 0.40 - 0.40 - Cy cle Clock to /clock (K to /K) tKH/KH 0.425 - 0.425 - 0.425 - 0.425 - 0.425 - 0.425 - Cy cle /Clock to clock (/K to K) t/KHKH 0.425 - 0.425 - 0.425 - 0.425 - 0.425 - 0.425 - Cy cle DLL / PLL timing Clock phase jitter (K, /K) tKC var - 0.15 - 0.15 - 0.15 - 0.20 - 0.20 - 0.20 ns 3 Lock time (K) tKC lock 20 - 20 - 20 - 20 - 20 - 20 - us 2 K static to DLL/PLL reset tKC reset 30 - 30 - 30 - 30 - 30 - 30 - ns 7 Output times K, /K high to output valid tCHQV - 0.45 - 0.45 - 0.45 - 0.45 - 0.45 - 0.45 ns K, /K high to output hold tCHQX -0.45 - -0.45 - -0.45 - -0.45 - -0.45 - -0.45 - ns K, /K high to echo clock valid tCHCQV - 0.45 - 0.45 - 0.45 - 0.45 - 0.45 - 0.45 ns K, /K high to echo clock hold tCHCQX -0.45 - -0.45 - -0.45 - -0.45 - -0.45 - -0.45 - ns CQ, /CQ high to output valid tCQHQV - 0.15 - 0.15 - 0.15 - 0.20 - 0.20 - 0.20 ns 4, 7 CQ, /CQ high to output hold tCQHQX -0.15 - -0.15 - -0.15 - -0.20 - -0.20 - -0.20 - ns 4, 7 K, /K high to output highZ tCHQZ - 0.45 - 0.45 - 0.45 - 0.45 - 0.45 - 0.45 ns 5, 6 K, /K high to output low-Z tCHQX1 -0.45 - -0.45 - -0.45 - -0.45 - -0.45 - -0.45 - ns 5 CQ high to QVLD valid tQVLD -0.15 0.15 -0.15 0.15 -0.15 0.15 -0.20 0.20 -0.20 0.20 -0.20 0.20 ns 7 R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 24 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB -19 Parameter Symbol -20 533 MHz Min Max 500 MHz Min 450 MHz Max Min Max 200 MHz 375 MHz 333 MHz Min Max Min Max Min Max U n I t N o t e s Setup times Address valid to K rising edge tAVKH 0.3 - 0.33 - 0.4 - 0.4 - 0.4 - 0.4 - ns 1, 8 Control inputs valid to K rising edge tIVKH 0.3 - 0.33 - 0.4 - 0.4 - 0.4 - 0.4 - ns 1, 8 Data-in valid to K, /K rising edge tDVKH 0.2 - 0.22 - 0.25 - 0.28 - 0.28 - 0.28 - ns 1, 9 Hold times K rising edge to address hold tKHAX 0.3 - 0.33 - 0.4 - 0.4 - 0.4 - 0.4 - ns 1, 8 K rising edge to control inputs hold tKHIX 0.3 - 0.33 - 0.4 - 0.4 - 0.4 - 0.4 - ns 1, 8 K, /K rising edge to data-in hold tKHDX 0.2 - 0.22 - 0.25 - 0.28 - 0.28 - 0.28 - ns 1, 9 Notes 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. VDD and VDDQ slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention. DLL/PLL lock time begins once VDD, VDDQ and input clock are stable. It is recommended that the device is kept inactive during these cycles. This specification meets the QDR common spec. of 20 us. 3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations. 5. Transitions are measured 100 mV from steady-state voltage. 6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQV. 7. These parameters are sampled. 8. tAVKH, tIVKH, tKHAX, tKHIX spec is determined by the actual frequency regardless of Part Number (Marking Name). The following is the spec for the actual frequency. 0.30 ns for 533MHz & >500MHz 0.33 ns for 500MHz & >450MHz 0.40 ns for 450MHz & 250MHz R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 25 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB 9. tDVKH, tKHDX spec is determined by the actual frequency regardless of Part Number (Marking Name). The following is the spec for the actual frequency. 0.20 ns for 533MHz & >500MHz 0.22 ns for 500MHz & >450MHz 0.25 ns for 450MHz & >400MHz 0.28 ns for 400MHz & 250MHz Remarks 1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 2. Control input signals may not be operated with pulse widths less than t KHKL (min). 3. VDDQ is +1.5 V DC. VREF is +0.75 V DC. 4. Control signals are /R, /W (QDR series), /LD, R-/W (DDR series), /BW, /BW0, /BW1, /BW2 and /BW3. Setup and hold times of /BWx signals must be the same as those of Data-in signals. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 26 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Timing Waveforms Read and Write Timing (QDRII+, B4, Read Latency = 2.5 cycle) 1 2 NOP 3 4 READ WRITE 5 READ 6 WRITE 7 NOP 8 NOP 9 NOP K tKHKL tKHKH tKH/KH t/KHKH tKLKH /K /R tIVKH tKHIX /W tIVKH Address A0 tAVKH A1 A2 tKHAX tKHIX A3 D10 D11 D12 D13 D30 D31 D32 D33 Data in tDVKH tKHDX Qx1 Qx2 Qx3 tDVKH tKHDX Q00 Q01 Q02 Q03 Q20 Q21 Q22 Q23 tCHQZ Data out -tCHQX1 tCHQV -tCHQX tCHQV -tCHQX tCQHQV -tCQHQX CQ tCHCQV -tCHCQX /CQ tCHCQV -tCHCQX QVLD tQVLD -tQVLD R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 tQVLD -tQVLD Page 27 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Notes 1. Q00 refers to output from address A0+0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1. 2. Outputs are disabled (High-Z) N clock cycle after the last read cycle. Here, N = Read Latency + Burst Length 0.5. 3. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11. Write data is forwarded immediately as read results. 4. To control read and write operations, /BW signals must operate at the same timing as Data-in signals. JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are internally pulled up and may be unconnected, or may be connected to V DD through a pull up resistor. TDO should be left unconnected. Test Access Port (TAP) Pins Symbol I/O Pin assignments Description Notes TCK 2R Test clock input. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS 10R Test mode select. This is the command input for the TAP controller state machine. TDI 11R Test data input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO 1R Test data output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note 1. The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 28 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB TAP DC Operating Characteristics Ta = -40 ~ +85C VDD = 1.8V 0.1V Parameter Symbol Min Typ Max Unit Input high voltage VIH +1.3 - VDD + 0.3 V Input low voltage VIL -0.3 - +0.5 V Input leakage current ILI -5.0 - +5.0 A 0 V VIN VDD Output leakage current ILO -5.0 - +5.0 A 0 V VIN VDD, output disabled VOL1 - - 0.2 V IOLC = 100 A VOL2 - - 0.4 V IOLT = 2 mA VOH1 1.6 - - V |IOHC| = 100 A VOH2 1.4 - - V |IOHT| = 2 mA Output low voltage Output high voltage Notes Notes 1. All voltages referenced to VSS (GND). 2. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ. During normal operation, VDDQ must not exceed VDD. TAP AC Test Conditions Parameter Symbol Conditions Unit Input timing measurement reference levels VREF 0.9 V Input pulse levels VIL, VIH 0 to 1.8 V Input rise/fall time tr, tf 1.0 ns Output timing measurement reference levels 0.9 V Test load termination supply voltage (VTT) 0.9 V Output load See figures Notes Input waveform 1.8V 0.9V Test points 0.9V 0V R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 29 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Output waveform 0.9V Test points 0.9V Output load condition VTT = 0.9V DUT 50 TDO Z0 = 50 20pF External Load at Test TAP AC Operating Characteristics Ta = -40 ~ +85C VDD = 1.8V 0.1V Parameter Symbol Min Typ Max Unit Notes Test clock (TCK) cycle time tTHTH 50 - - ns TCK high pulse width tTHTL 20 - - ns TCK low pulse width tTLTH 20 - - ns Test mode select (TMS) setup tMVTH 5 - - ns TMS hold tTHMX 5 - - ns Capture setup tCS 5 - - ns 1 Capture hold tCH 5 - - ns 1 TDI valid to TCK high tDVTH 5 - - ns TCK high to TDI invalid tTHDX 5 - - ns TCK low to TDO unknown tTLQX 0 - - ns TCK low to TDO valid tTLQV - - 10 ns Note 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 30 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB TAP Controller Timing Diagram tTHTH tTHTL tTLTH TCK tMVTH tTHMX TMS tDVTH tTHDX TDI tTLQV TDO tTLQX tCS tCH PI (SRAM) Test Access Port Registers Register name Length Symbol Instruction register 3 bits IR [2:0] Bypass register 1 bit BP ID register 32 bits ID [31:0] Boundary scan register 109 bits BS [109:1] R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Notes Page 31 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB TAP Controller Instruction Set IR2 IR1 IR0 Instruction 0 0 0 EXTEST 0 0 1 IDCODE 0 1 0 SAMPLE-Z 0 1 1 RESERVED 1 0 0 SAMPLE (/PRELOAD) 1 1 0 1 1 0 RESERVED RESERVED 1 1 1 BYPASS Description Notes The EXTEST instruction allows circuitry external to the component package to be tested. Boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the Update-IR state of EXTEST, the output driver is turned on and the PRELOAD data is driven onto the output balls. The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO balls in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (High-Z), moving the TAP controller into the captureDR state loads the data in the RAMs input into the boundary scan register, and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. The RESERVED instructions are not implemented but are reserved for future use. Do not use these instructions. When the SAMPLE instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable input will not harm the device, repeatable results cannot be expected. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO balls. The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shiftDR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. 1, 2, 3, 5 3, 4, 5 3, 5 Notes 1. Data in output register is not guaranteed if EXTEST instruction is loaded. 2. After performing EXTEST, power-up conditions are required in order to return part to normal operation. 3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. 4. Clock recovery initialization cycles are required after boundary scan. 5. For R1QD and R1QE series, ODT is disabled in EXTEST, SAMPLE-Z or SAMPLE mode. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 32 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Boundary Scan Order Signal names Bit # Ball ID Signal names Bit # x18 x36 Ball ID x18 x36 1 6R NC / ODT NC / ODT 36 10E D6 D6 2 6P QVLD QVLD 37 10D NC D15 3 6N SA SA 38 9E NC Q15 4 7P SA SA 39 10C Q7 Q7 5 7N SA SA 40 11D D7 D7 6 7R SA SA 41 9C NC D16 7 8R SA SA 42 9D NC Q16 8 8P SA SA 43 11B Q8 Q8 9 9R SA SA 44 11C D8 D8 10 11P Q0 Q0 45 9B NC D17 11 10P D0 D0 46 10B NC Q17 12 10N NC D9 47 11A CQ CQ 13 9P NC Q9 48 10A SA NC 14 10M Q1 Q1 49 9A SA SA 15 11N D1 D1 50 8B SA SA 16 9M NC D10 51 7C SA SA 17 9N NC Q10 52 6C NC NC 18 11L Q2 Q2 53 8A /R /R 19 11M D2 D2 54 7A NC /BW1 20 9L NC D11 55 7B /BW0 /BW0 21 10L NC Q11 56 6B K K 22 11K Q3 Q3 57 6A /K /K 23 10K D3 D3 58 5B NC /BW3 24 9J NC D12 59 5A /BW1 /BW2 25 9K NC Q12 60 4A /W /W 26 10J Q4 Q4 61 5C SA SA 27 11J D4 D4 62 4B SA SA 28 11H ZQ ZQ 63 3A SA SA 29 10G NC D13 64 2A NC NC 30 9G NC Q13 65 1A /CQ /CQ 31 11F Q5 Q5 66 2B Q9 Q18 32 11G D5 D5 67 3B D9 D18 33 9F NC D14 68 1C NC D27 34 10F NC Q14 69 1B NC Q27 35 11E Q6 Q6 70 3D Q10 Q19 R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 33 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Signal names Bit # Ball ID Signal names Bit # x18 x36 Ball ID x18 x36 71 3C D10 D19 91 2L Q15 Q24 72 1D NC D28 92 3L D15 D24 73 2C NC Q28 93 1M NC D33 74 3E Q11 Q20 94 1L NC Q33 75 2D D11 D20 95 3N Q16 Q25 76 2E NC D29 96 3M D16 D25 77 1E NC Q29 97 1N NC D34 78 2F Q12 Q21 98 2M NC Q34 79 3F D12 D21 99 3P Q17 Q26 80 1G NC D30 100 2N D17 D26 81 1F NC Q30 101 2P NC D35 82 3G Q13 Q22 102 1P NC Q35 83 2G D13 D22 103 3R SA SA 84 1H /DOFF /DOFF 104 4R SA SA 85 1J NC D31 105 4P SA SA 86 2J NC Q31 106 5P SA SA 87 3K Q14 Q23 107 5N SA SA 88 3J D14 D23 108 5R SA SA 89 2K NC D32 109 - Internal Internal 90 1K NC Q32 Notes In boundary scan mode, 1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for reliable operation. 2. CQ and /CQ data are synchronized to the respective C and /C (except EXTEST, SAMPLE-Z). 3. If C and /C tied high, CQ is generated with respect to K and /CQ is generated with respect to /K (except EXTEST, SAMPLE-Z). R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 34 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB ID Register # Symbol Revision Type number Start bit (0) Vendor JEDEC code number (28 : 12) (31 :29) (11 : 1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R 0 C M M M A W W 0 1 Q Q Q B O S 0 0 1 0 0 0 1 0 0 0 1 1 1 R R R 0 0 0 0 0 1 0 1 0 0 1 1 : Q Revison 0 II (QDR-II, DDR-II) 0 Revison 1 1 II+ (QDR-II+, DDR-II+) Revison 2 Q Revison 3 DDR 0 : QDR 1 C Q Latency=1.5 (@II), Latency=2.0 (@II+) 0 36M&72M w/o ODT, 144M,288M 0 1 36M&72M w/ ODT 1 Latency=2.5 (@II+) M M M B Density = 36Mb Burst Length = 2 word burst 0 1 0 0 0 1 1 Density = 72Mb 1 Burst Length = 4 word burst 1 0 1 Density = 144Mb O 1 1 0 Density = 288Mb 0 without ODT A 1 with ODT 0 144M&288M w/o ODT, 36M,72M S 1 144M&288M w/ ODT 0 Common I/O W W 1 Separate I/O x9 0 0 x18 1 0 1 1 x36 TAP Controller State Diagram 1 Test Logic Reset 0 Run Test/Idle 0 1 1 Select DR Scan 1 0 1 Capture DR 0 Capture IR 0 Shift DR Exit1 DR 0 1 1 Exit1 IR 0 1 Exit2 DR 0 1 0 Pause IR 0 1 Exit2 IR 1 1 Update DR 1 0 Shift IR Pause DR 0 0 0 1 1 Select IR Scan 0 Update IR 1 0 Note 1. The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter TestLogic-Reset when TMS is held high for at least five rising edges of TCK. R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 Page 35 of 37 R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB Package Dimensions and Marking Information JEITA Package Code Renesas Code Previous Code Mass (typ.) P-LBGA165-13x15-1.00 PLBG0165FE-A 165FHG 0.5g D A B Top View R1QAA7218ABB-19I YWWXXXX JAPAN H PB-F Index Mark (Laser Mark) This part number or mark is just one example. Marking Information 1st row : Vender name (RENESAS) 2nd row: Part number 3rd row : Y : Year code WW : Week code E XXXX : Renesas internal use 4th row : Country name (JAPAN) + "H" --- Non-Halogenated + "PB-F" --- Pb-free parts S A Side View A1 - y S ZD [e] R Bottom View C D E F G H J K L M N P [e] A B ZE 1 2 3 4 5 6 Ob Index Mark R10DS0169EJ0203 Rev. 2.03 Feb 01, 2019 7 8 9 10 11 - Ox(M) S AB Reference Symbol D E A A1 [e] b x y ZD ZE Dimension in mm Min Nom Max 12.9 13.0 13.1 14.9 15.0 15.1 1.4 0.31 0.36 0.41 1.0 0.45 0.5 0.6 0.2 0.15 2.5 - 1.5 - Page 36 of 37 R1QAA7236ABB, R1QAA7218ABB R1QDA7236ABB, R1QDA7218ABB Revision History Description Rev. 1.00 Date - Page - 2.00 '17.05.15 - 2.01 '17.06.09 P.15 - 2.02 2.03 '18.12.01 '19.02.01 P.15 - Summary Applied new document format. Reflected the information related change to non-halogenated package and merger some speed bin. Deleted ODT on / off Timing Chart. Fixed some typo. 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