CODEC Features
Functional Block Diagram
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Doc# PBR-202964
© 2012 Conexant Systems, Inc. All Rights
Reserved. Conexant and the Conexant logo
are registered trademarks of Conexant
Systems, Inc. All other trademarks are owned
by their respective owners. Although
Conexant strives for accuracy in all its
publications, this material may contain errors
or omissions and is subject to change without
notice. THIS MATERIAL IS PROVIDED AS IS
AND WITHOUT ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING MERCHANT
ABILITY, FITNESS FOR A PARTICULAR
PURPOSE AND NON-INFRINGEMENT.
Conexant shall not be liable for any special,
indirect, incidental or consequential damages
as a result of its use.
DMA
DSP X2
Memory DMA
DAC
DAC
DAC
ADC
ADC
PCM/I2S PCM/I2S
Controller
SPI
I2C Slave UART
Jack
Sense
Clock
Circuitry
Bias
Generator
MON
ADC
I2S_PCM_1_CLK
I2S_PCM_1_RX_WS
I2S_PCM_1_RX_DAT
I2S_PCM_1_TX_WS/SPDIF_OUT
USB
I2S_PCM_1_TX_DAT
I2S_PCM_2_WS
I2S_PCM_2_CLK/DMIC_CLK
I2S_PCM_2_RX_DAT/DMIC_IN/SPDIF_IN
I2S_PCM_2_TX_DAT
USB_DP
USB_DM
USB_5VDET
I2C_SPI_SCL
UART_RX
UART_TX
NVCLK
NVDAT
I2C_SPI_CSN
SPI_MISO
I2C_SDA/SPI_MOSI
GPO 0
GPO 1
KS0
KS1
KS2
Volume
LINE_OUT_LP
LINE_OUT_LN
(SE or Diff, LINE_OUT_LN
10 kΩ line)
CLASSD_LP
CLASSD_LN
(2.5W Class-D 4 Ω Out)
HP_OUT_R
(Capless HP Out 32 Ω)
MONO_OUT_N
(SE or Diff, 600 Ω or 10 kΩ line)
HP_OUT_L
(Capless HP Out 32 Ω)
MIC_IN_L
MIC_IN_R
MICBIAS_L
MICBIAS_R
XTLI
XTLO
SENSE_A
Σ
ADC
LINE_IN_1L_LP (SE or Diff Line In)
MIC_IN2_L/LINE_IN_3L
M
M
M
Σ
ADC
LINE_IN_1R_RP (SE or Diff Line In)
MIC_IN2_R/LINE_IN_3R
M
M
M
GPO2
GPO3
GPO4
(SE or Diff Line In)
LINE_IN_2L_LN
(SE or Diff Line In)
LINE_IN_2R_RN
PASS_THRU
PASS_THRU
VOLT_MON
MONO_OUT_P
(SE or Diff, 600 Ω or 10 kΩ line)
CLASSD_RP
CLASSD_RN
(2.5W Class-D 4 Ω Out)
LINE_OUT_RP
LINE_OUT_RN
(SE or Diff, LINE_OUT_LN
10 kΩ line)
I2C_EN/MCLK
DMIC_IN
DMIC_CLK
DMA
L
R
MCLK
4-wire and 5-wire digit al a udio I/ O (I 2S/
PCM/SPDIF), supporting full dup lex
independent sampling rates, master
clock for optional PCM/I2S slave codec
(SPDIF-in available in CX20709-21Z)
One 2-wire I2C and one 4-wire SPI
slave interfa c e for external MCU
USB 2.0 Compliant full speed UAC
Interface
Supporting dual USB playback end
points (available in CX20709-21Z)
Stereo Digital Microphone, up to
12 MHz clock rate (available in
CX20709-21Z)
Eight GPIO pi ns
2.8 W x 2 BTL filter-less stereo Class-
D Speaker Amplifier
– Low EMI Class-D amplifier output
with Spread Spectrum and
common mode scrambler
Integrated 50 mW headphone driver
with jack sense
Single-ended or differential line output
Separate mixed mono line-output for
sub-woofer or intercom usage
Three single-ended stereo or one
differential stereo analog audio input
Up to 4 microphone interfaces with on-
chip bias supply (availa ble in
CX20709-21Z)
24-bit DAC/ADC, SNR 102 dB, THD -
92 dB at 48 kHz 3.3 V
– In DSP mode, the processing will
be limited the input and output to
16-bit effective resolution
Audio sample rat e: 8,16, 22.05, 24, 3 2,
44.1, 48, 88.2, 96 kHz
90 dB Dynamic Range with 0.1%
THD+N at 4 Ω load
12-bit ADC multiplexed to support
analog volume potentiometer and DC
level det ec tion
Flexible Power Management
Variable master clock rates
Configurable On-Chip proprietary
Voice/Audio Processing
– Subband Acoustic Echo
Cancellation
– Dual Microphone Beam Forming
– Noise Reduction
– Dynamic Loudness Adaptor
– Microphone Automatic Gain
Control
– Subband Line Echo Cancellation
(2-way intercom applications)
– Digital Equalizer (10 bands/
channel)
– Dynamic Range Compression
– 4th Order Digital Crossover for
Subwoofer Line-out
– Conexant sound-bar algorithm for
USB 5.1 channel sound-bar
enhancement (available in
CX20709-21Z)
SPoC Configuration Toolbox
– Fast configuration via USB-to-I2C
from PC
– Data path, I/O setup, and DSP
parameter adjustmen t
– Output log for convenient MCU
programming