Vishay Siliconix
Si3460BDV
Document Number: 74412
S09-1498-Rev. C, 10-Aug-09
www.vishay.com
1
N-Channel 20-V (D-S) MOSFET
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Load Switch for Portable Applications
• Load Switch for Low Voltage Bus
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)ID (A)aQg (Typ.)
20
0.027 at VGS = 4.5 V 8
9 nC
0.032 at VGS = 2.5 V 8
0.040 at VGS = 1.8 V 8
Marking Code
AF XXX
Lot Traceability
and Date Code
Part # Code
Ordering Information: Si3460BDV-T1-E3 (Lead (Pb)-free)
Si3460BDV-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET
G
D
S
TSOP-6
Top View
6
4
1
2
3
5
3 mm
2.85 mm
D
D
D
D
S
G
(1, 2, 5, 6)
(3)
(4)
Notes:
a. Package limited
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 110 °C/W.
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
Drain-Source Voltage VDS 20 V
Gate-Source Voltage VGS ± 8
Continuous Drain Current (TJ = 150 °C)
TC = 25 °C
ID
8a
A
TC = 70 °C 7.1
TA = 25 °C 6.7b, c
TA = 70 °C 5.4b, c
Pulsed Drain Current IDM 20
Continuous Source-Drain Diode Current TC = 25 °C IS
2.9
TA = 25 °C 1.7b, c
Maximum Power Dissipation
TC = 25 °C
PD
3.5
W
TC = 70 °C 2.2
TA = 25 °C 2b, c
TA = 70 °C 1.3b, c
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
Soldering Recommendations (Peak Temperature)d, e 260
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambientb, d t ≤ 5 s RthJA 50 62.5 °C/W
Maximum Junction-to-Foot (Drain) Steady State RthJF 30 36
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Document Number: 74412
S09-1498-Rev. C, 10-Aug-09
Vishay Siliconix
Si3460BDV
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 20 V
VDS Temperature Coefficient ΔVDS/TJID = 250 µA 22.5 mV/°C
VGS(th) Temperature Coefficient ΔVGS(th)/TJ- 2.9
Gate-Source Threshold Voltage VGS(th) VDS = VGS , ID = 250 µA 0.45 1.0 V
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 8 V ± 100 ns
Zero Gate Voltage Drain Current IDSS
VDS = 20 V, VGS = 0 V 1µA
VDS = 20 V, VGS = 0 V, TJ = 70 °C 10
On-State Drain CurrentaID(on) V
DS ≤ 5 V, VGS = 4.5 V 20 A
Drain-Source On-State ResistanceaRDS(on)
VGS = 4.5 V, ID = 5.1 A 0.023 0.027
Ω
VGS = 2.5 V, ID = 4.7 A 0.027 0.032
VGS = 1.8 V, ID = 2.5 A 0.033 0.040
Forward Transconductanceagfs VDS = 10 V, ID = 5.1 A 22 S
Dynamicb
Input Capacitance Ciss
VDS = 10 V, VGS = 0 V, f = 1 MHz
860
pFOutput Capacitance Coss 110
Reverse Transfer Capacitance Crss 65
Total Gate Charge Qg VDS = 10 V, VGS = 8 V, ID = 8 A 16 24
nC
VDS = 10 V, VGS = 4.5 V, ID = 8 A
9 13.5
Gate-Source Charge Qgs 1.4
Gate-Drain Charge Qgd 1.4
Gate Resistance Rgf = 1 MHz 3.2 Ω
Tur n - O n D e l ay Time td(on)
VDD = 10 V, RL = 1.9 Ω
ID ≅ 5.4 A, VGEN = 4.5 V, Rg = 1 Ω
715
ns
Rise Time tr 60 90
Turn-Off Delay Time td(off) 25 40
Fall Time tf610
Tur n - O n D e l ay Time td(on)
VDD = 10 V, RL = 1.9 Ω
ID ≅ 5.4 A, VGEN = 8 V, Rg = 1 Ω
510
Rise Time tr 15 25
Turn-Off Delay Time td(off) 25 40
Fall Time tf510
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISTC = 25 °C 8A
Pulse Diode Forward Current ISM 20
Body Diode Voltage VSD IS = 5.4 A, VGS = 0 V 0.8 1.2 V
Body Diode Reverse Recovery Time trr
IF = 5.4 A, dI/dt = 100 A/µs, TJ = 25 °C
20 40 ns
Body Diode Reverse Recovery Charge Qrr 920nC
Reverse Recovery Fall Time ta12 ns
Reverse Recovery Rise Time tb8
Document Number: 74412
S09-1498-Rev. C, 10-Aug-09
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Vishay Siliconix
Si3460BDV
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
0
5
10
15
20
0.0 0.4 0.81.2 1.6 2.0
VGS = 5 V thru 2 V
1 V
VDS
- Drain-to-Source Voltage (V)
)A( tnerruC niarDID -
1.5 V
0.020
0.030
0.040
0.050
0
.
060
0 5 10 15 20
(Ω) e c n a t s i s e R - n O
RDS(on) -
I
D
- Drain Current
(
A
)
V
GS
= 4.5 V
V
GS
= 1.8 V
V
GS
= 2.5 V
0
1
2
3
4
5
6
7
8
0 3 6 9 12 15 18
)V( egatloV e
cruoS-ot-et
a
G
-
Q
g
- Total Gate Charge (nC)
VGS
VDS = 16 V
ID = 8 A
VDS = 10 V
ID = 8 A
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
2
4
6
8
10
0.0 0.3 0.6 0.9 1.2 1.5 1.8
25 °C
T
C
= 125 °C
- 55 °C
VGS - Gate-to-Source Voltage (V)
)A( tnerruC niarD ID -
0
300
600
900
1200
04812 16 20
C
oss
C
iss
V
DS
- Drain-to-Source Voltage (V)
)Fp( ecnaticapaC C -
C
rss
0.6
0.8
1.0
1.2
1.4
1.6
1.8
- 50 - 25 0 25 50 75 100 125 150
I
D
= 5.1 A
T
J - Junction Temperature (°C)
R)
n
o ( S D e c n a t s
i s e R - n O -
) d e z
i l a m
r o
N
(
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Document Number: 74412
S09-1498-Rev. C, 10-Aug-09
Vishay Siliconix
Si3460BDV
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Source-Drain Diode Forward Voltage
Threshold Voltage
Source Current (A) -
1
100
V
SD - Source-to-Drain Voltage (V)
I
S
0 0.2
0.4 0.6 0.8 1
10
1.2
T
J
= 150 °C
T
J
= 25 °C
0.2
0.3
0.4
0.5
0.6
0.7
0
.
8
- 50 - 25 0 25 50 75 100 125 150
I
D
= 250 µA
VGS(th) (V)
T
J
- Temperature (°C)
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power (Junction-to-Ambient)
0.00
0.02
0.04
0.06
0
.
08
012345
e (Ω)
c
n
a
t
s i s
e
R
-
n O
RDS(on) -
V
GS
- Gate-to-Source Voltage (V)
I
D
= 5.1 A
125 °C
0.01
0.03
0.05
0.07 I
D
= 5.1 A
25 °C
0
30
50
10
20
) W ( r e w o P
Time (s)
40
1 100 600 10 10
- 1
10
- 2
10
- 3
Safe Operating Area, Junction-to-Ambient
100
1
0.1 1 10 100
0.01
10
) A ( t n e
r r u C
n i
a
r D
- I D
0.1 T
A
= 25 °C
Single Pulse
BVDSS Limited
10 s
DC
1 s
100 ms
10 ms
1 ms
V
DS
- Drain-to-Source Voltage (V)
* VGS minimum V
GS
at which RDS(on) is specified
Limited by RDS(on)*
Document Number: 74412
S09-1498-Rev. C, 10-Aug-09
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5
Vishay Siliconix
Si3460BDV
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Current Derating*
0
2
4
6
8
10
0 25 50 75 100 125 150
Foot (Drain) Temperature ( C)
)
A
(
t n e r r
u C
n i a r
D
Package Limited
Power Derating
0
1
2
3
4
25 50 75 100 125 150
Foot (Drain) Temperature ( C)
) W (
n o i t a
p
i s s i D r e
w
o P
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Document Number: 74412
S09-1498-Rev. C, 10-Aug-09
Vishay Siliconix
Si3460BDV
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for
Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?74412.
Normalized Thermal Transient Impedance, Junction-to-Ambient
10
- 3 10
- 2 1 10 600 10
- 1
10
- 4 100
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
e
v i t c e
E d e z
i
l a m
r
o
N t n e i s n a r T
e c n a d e p m
I
l a m r
e
h T
1. Duty Cycle, D =
2. Per Unit Base = R
thJA
= 90 °C/W
3. T
JM - T
A
= P
DM
Z
thJA
(t)
t
1
t
2
t
1
t
2
Notes:
4. Surface Mounted
P
DM
Normalized Thermal Transient Impedance, Junction-to-Foot
10
- 3 10
- 2 1 10 10
- 1
10
- 4
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
e v i
t
c e
f
f
E d e z i l a m r o N t n e i s n a r T
e
c n a d e p m I l a m r e h T
Vishay Siliconix
Package Information
Document Number: 71200
18-Dec-06
www.vishay.com
1
1 2 3
Gauge Plane
L
5 4
R
R
C 0.15 M B A
b
C 0.08
0.17 Ref
Seating Plane
-C-
Seating Plane
A
1
A
2 A
-A-
D
-B-
E
1 E
L
2
(L
1
)
c
4x 1
4x 1
e
e1
1 2 3
6 5 4
C 0.15 M B A
b
-B-
E
1 E
e
e1
5-LEAD TSOP 6-LEAD TSOP
TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A 0.91 - 1.10 0.036 - 0.043
A
1 0.01 - 0.10 0.0004 - 0.004
A
2 0.90 - 1.00 0.035 0.038 0.039
b 0.30 0.32 0.45 0.012 0.013 0.018
c 0.10 0.15 0.20 0.004 0.006 0.008
D 2.95 3.05 3.10 0.116 0.120 0.122
E 2.70 2.85 2.98 0.106 0.112 0.117
E
1 1.55 1.65 1.70 0.061 0.065 0.067
e 0.95 BSC 0.0374 BSC
e
1 1.80 1.90 2.00 0.071 0.075 0.079
L 0.32 - 0.50 0.012 - 0.020
L
1 0.60 Ref 0.024 Ref
L
2 0.25 BSC 0.010 BSC
R 0.10 - - 0.004 - -
0 4 8 0 4 8
1 7 Nom 7 Nom
ECN: C-06593-Rev. I, 18-Dec-06
DWG: 5540
AN823
Vishay Siliconix
Document Number: 71743
27-Feb-04
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1
Mounting LITTLE FOOTR TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages. Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFETs. Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What has remained the same is the footprint of the
packages.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package
outline drawing see http://www.vishay.com/doc?71200 and see
http://www.vishay.com/doc?72610 for the minimum pad footprint.
In converting the footprint to the pad set for a power MOSFET, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches wide. Since the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate. The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.
FIGURE 1. Recommended Copper Spreading Footprint
0.049
1.25
0.010
0.25
0.014
0.35
0.074
1.875 0.122
3.1
0.026
0.65
0.167
4.25
0.049
1.25
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used. Even if additional planar copper area is
used, there should be no problems in the soldering process. The
actual solder connections are defined by the solder mask
openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAST, or pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Ramp-Up Rate +6_C/Second Maximum
Temperature @ 155 " 15_C120 Seconds Maximum
Temperature Above 180_C70 − 180 Seconds
Maximum Temperature 240 +5/−0_C
Time at Maximum Temperature 20 − 40 Seconds
Ramp-Down Rate +6_C/Second Maximum
FIGURE 2. Solder Reflow Temperature Profile
AN823
Vishay Siliconix
www.vishay.com
2Document Number: 71743
27-Feb-04
255 − 260_C
1X4_C/s (max) 3-6_C/s (max)
10 s (max)
Reflow Zone
Pre-Heating Zone
3_C/s (max)
140 − 170_C
Maximum peak temperature at 240_C is allowed.
FIGURE 3. Solder Reflow Temperature and Time Durations
60-120 s (min)
217_C
60 s (max)
THERMAL PERFORMANCE
A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, Rqjc, or the
junction-to-foot thermal resistance, Rqjf. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted. Table 1 shows the thermal performance
of the TSOP-6.
TABLE 1.
Equivalent Steady State Performance—TSOP-6
Thermal Resistance Rqjf 30_C/W
SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 4).
0.6
0.8
1.0
1.2
1.4
1.6
−50 −25 0 25 50 75 100 125 150
VGS = 4.5 V
ID = 6.1 A
On-Resistance vs. Junction Temperature
TJ − Junction Temperature (_C)
FIGURE 4. Si3434DV
rDS(on) − On-Resiistance
(Normalized)
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72610
26 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR TSOP-6
0.119
(3.023)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.099
(2.510)
0.064
(1.626)
0.028
(0.699)
0.039
(1.001)
0.020
(0.508)
0.019
(0.493)
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Revision: 02-Oct-12 1Document Number: 91000
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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