DC1805A-F - Linear Technology

LTC6362

6362fa

TYPICAL APPLICATION

FEATURES DESCRIPTION

Precision, Low Power

Rail-to-Rail Input/Output

Differential Op Amp/SAR

ADC Driver

The LTC

6362 is a low power, low noise differential op

amp with rail-to-rail input and output swing that has been

optimized to drive low power SAR ADCs. The LTC6362

draws only 1mA of supply current in active operation, and

features a shutdown mode in which the current consump-

tion is reduced to 70μA.

The amplifier may be configured to convert a single-

ended input signal to a differential output signal, and is

capable of being operated in an inverting or noninverting

configuration.

Low offset voltage, low input bias current, and a stable

high impedance configuration make this amplifier suit-

able for use not only as an ADC driver but also earlier in

the signal chain, to convert a precision sensor signal to

a balanced (differential) signal for processing in noisy

industrial environments.

The LTC6362 is available in an 8-lead MSOP package and

also in a compact 3mm × 3mm 8-pin leadless DFN pack-

age, and operates with guaranteed specifications over a

–40°C to 125°C temperature range.

DC-Coupled Interface from a Ground-Referenced

Single-Ended Input to an LTC2379-18 SAR ADC

APPLICATIONS

n 1mA Supply Current

n Single 2.8V to 5.25V supply

n Fully Differential Input and Output

n 200μV Max Offset Voltage

n 260nA Max Input Bias Current

n Fast Settling: 550ns to 18-Bit, 8VP-P Output

n Low Distortion: –116dBc at 1kHz, 8VP-P

n Rail-to-Rail Inputs and Outputs

n 3.9nV/√Hz Input-Referred Noise

n 180MHz Gain-Bandwidth Product

n 34MHz –3dB Bandwidth

n Low Power Shutdown: 70µA

n 8-Lead MSOP and 3mm × 3mm 8-Lead DFN Packages

n 16-Bit and 18-Bit SAR ADC Drivers

n Single-Ended-to-Differential Conversion

n Low Power Pipeline ADC Driver

n Differential Line Drivers

n Battery-Powered Instrumentation

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

–

3.9nF

AIN+VREF VDD

LTC2379-18

SAR ADC

2.5V

GND

AIN–

18-BIT

1.6Msps

6362 TA01a

35.7Ω

LTC6362

VOCM

0.1µF

VIN

1k 1k

SHDN

LTC6362 Driving LTC2379-18

fIN = 2kHz, –1dBFS, 16384-Point FFT

FREQUENCY (kHz)

–150

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

100 200 500 600 700

–20

–60

–130

–110

–90

–10

–50

–30

–70

300 400 800

6362 TA01b

VS = 5V, 0V

VOUTDIFF = 8.9VP-P

HD2 = –116.0dBc

HD3 = –114.9dBc

SFDR = 110.1dB

THD = –108.0dB

SNR = 101.2dB

SINAD = 99.9dB

LTC6362

6362fa

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

Total Supply Voltage (V+ – V–) .................................5.5V

Input Current (+IN, –IN, VOCM, SHDN) (Note 2) ... ±10mA

Output Short-Circuit Duration (Note 3) ............ Indefinite

Operating Temperature Range (Note 4)

LTC6362C/LTC6362I ............................–40°C to 85°C

LTC6362H .......................................... –40°C to 125°C

(Note 1)

–IN

VOCM

V+

+OUT

+IN

SHDN

V–

–OUT

TOP VIEW

MS8 PACKAGE

8-LEAD PLASTIC MSOP

TJMAX = 150°C, θJA = 273°C/W, θJC = 45°C/W

TOP VIEW

V–

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

1–IN

VOCM

V+

+OUT

+IN

SHDN

V–

–OUT

TJMAX = 150°C, θJA = 39.7°C/W, θJC = 45°C/W

EXPOSED PAD (PIN 9) IS V–, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE

LTC6362CMS8#PBF LTC6362CMS8#TRPBF LTGCN 8-Lead Plastic MSOP 0°C to 70°C

LTC6362IMS8#PBF LTC6362IMS8#TRPBF LTGCN 8-Lead Plastic MSOP –40°C to 85°C

LTC6362HMS8#PBF LTC6362HMS8#TRPBF LTGCN 8-Lead Plastic MSOP –40°C to 125°C

LTC6362CDD#PBF LTC6362CDD#TRPBF LGCM 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C

LTC6362IDD#PBF LTC6362IDD#TRPBF LGCM 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LTC6362HDD#PBF LTC6362HDD#TRPBF LGCM 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Specified Temperature Range (Note 5)

LTC6362C ................................................ 0°C to 70°C

LTC6362I .............................................–40°C to 85°C

LTC6362H .......................................... –40°C to 125°C

Maximum Junction Temperature .......................... 150°C

Storage Temperature Range .................. –65°C to 150°C

LTC6362

6362fa

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 2.5V, VSHDN = open. VS is defined

as (V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOSDIFF (Note 6) Differential Offset Voltage (Input Referred) VS = 3V

VICM =1.5V

VICM = 2.75V

200

350

250

600

µV

VS = 5V

VICM = 2.5V

VICM = 4.5V

200

350

260

600

µV

∆VOSDIFF/∆T (Note 7) Differential Offset Voltage Drift (Input Referred) VS = 3V

VS = 5V

0.9

0.9 2.5

2.5 µV/°C

µV/°C

IB (Note 8) Input Bias Current VS = 3V

VICM =1.5V

VICM = 2.5V

±100

±75

±350

±500

±350

±850

VS = 5V

VICM = 2.5V

VICM = 4.5V

±75

±260

±460

±350

±850

∆IB/∆TInput Bias Current Drift VS = 3V

VS = 5V

1.1

0.9 nA/°C

nA/°C

IOS (Note 8) Input Offset Current VS = 3V

VICM =1.5V

VICM = 2.5V

±75

±125

±325

±650

±425

±1200

VS = 5V

VICM =2.5V

VICM = 4.5V

±75

±125

±325

±500

±425

±1200

RIN Input Resistance Common Mode

Differential Mode 14

32 MΩ

kΩ

CIN Input Capacitance Differential Mode 2 pF

enDifferential Input Noise Voltage Density f = 100kHz, Not Including RI/RF Noise 3.9 nV/√Hz

inInput Noise Current Density f = 100kHz, Not Including RI/RF Noise 0.8 pA/√Hz

envocm Common Mode Noise Voltage Density f = 100kHz 14.3 nV/√Hz

VICMR (Note 9) Input Common Mode Range VS = 3V

VS = 5V

CMRRI (Note 10) Input Common Mode Rejection Ratio

(Input Referred) ∆VICM/∆VOSDIFF

VS = 3V, VICM from 0V to 3V

VS = 5V, VICM from 0V to 5V

73 95

98 dB

CMRRIO (Note 10) Output Common Mode Rejection Ratio

(Input Referred) ∆VOCM/∆VOSDIFF

VS = 3V, VOCM from 0.5V to 2.5V

VS = 5V, VOCM from 0.5V to 4.5V

55 100

90 dB

PSRR (Note 11) Differential Power Supply Rejection

(∆VS/∆VOSDIFF)VS = 2.8V to 5.25V l80 105 dB

PSRRCM (Note 11) Output Common Mode Power Supply Rejection

(∆VS/∆VOSCM)VS = 2.8V to 5.25V l58 72 dB

LTC6362

6362fa

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 2.5V, VSHDN = open. VS is defined

as (V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

GCM Common Mode Gain (∆VOUTCM/∆VOCM) VS = 3V, VOCM from 0.5V to 2.5V

VS = 5V, VOCM from 0.5V to 4.5V

1V/V

V/V

∆GCM Common Mode Gain Error 100 • (GCM – 1) VS = 3V, VOCM from 0.5V to 2.5V

VS = 5V, VOCM from 0.5V to 4.5V

±0.07

±0.07 ±0.16

±0.4 %

BAL Output Balance (∆VOUTCM/∆VOUTDIFF)∆VOUTDIFF = 2V

Single-Ended Input

Differential Input

–57

–35

AVOL Open-Loop Voltage Gain 95 dB

VOSCM Common Mode Offset Voltage

(VOUTCM – VOCM)VS = 3V

VS = 5V

±6

±6 ±30

±30 mV

∆VOSCM/∆TCommon Mode Offset Voltage Drift l45 μV/°C

VOUTCMR (Note 9) Output Signal Common Mode Range

(Voltage Range for the VOCM Pin) VOCM Driven Externally, VS = 3V

VOCM Driven Externally, VS = 5V

0.5

0.5 2.5

4.5 V

VOCM Self-Biased Voltage at the VOCM Pin VOCM Not Connected, VS = 3V

VOCM Not Connected, VS = 5V

1.475

2.475 1.5

2.5 1.525

2.525 V

RINVOCM Input Resistance, VOCM Pin l110 170 230 kΩ

VOUT Output Voltage, High, Either Output Pin IL= 0mA, VS = 3V

IL = –5mA, VS = 3V

2.85

2.75 2.93

2.85 V

IL= 0mA, VS = 5V

IL = –5mA, VS = 5V

4.8

4.7 4.93

4.85 V

Output Voltage, Low , Either Output Pin IL= 0mA, VS = 3V

IL = 5mA, VS = 3V

0.05

0.13 0.15

0.3 V

IL= 0mA, VS = 5V

IL = 5mA, VS = 5V

0.05

0.13 0.2

0.4 V

ISC Output Short-Circuit Current, Either Output Pin VS = 3V

VS = 5V

15 25

35 mA

SR Slew Rate Differential 8VP-P Output 45 V/μs

GBWP Gain-Bandwidth Product fTEST = 200kHz

145

90 180 MHz

MHz

f–3dB –3dB Bandwidth RI = RF = 1k 34 MHz

HD2/HD3 2nd/3rd Order Harmonic Distortion

Single-Ended Input f = 1kHz, VOUT = 8VP-P

f = 10kHz, VOUT = 8VP-P

f = 100kHz, VOUT = 8VP-P

–120/–116

–106/–103

–84/–76

dBc

tsSettling Time to a 2VP-P Output Step 0.1%

0.01%

0.0015% (16-Bit)

4ppm (18-Bit)

160

180

230

440

Settling Time to a 8VP-P Output Step 0.1%

0.01%

0.0015% (16-Bit)

4ppm (18-Bit)

230

300

460

550

VS (Note 12) Supply Voltage Range l2.8 5.25 V

ISSupply Current VS = 3V, Active

0.9 0.96

1.05 mA

VS = 3V, Shutdown l55 130 µA

VS = 5V, Active

1 1.06

1.18 mA

VS = 5V, Shutdown l70 140 µA

LTC6362

6362fa

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 2.5V, VSHDN = open. VS is defined

as (V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Input pins (+IN, –IN, VOCM and SHDN) are protected by steering

diodes to either supply. If the inputs should exceed either supply voltage,

the input current should be limited to less than 10mA. In addition, the

inputs +IN, –IN are protected by a pair of back-to-back diodes. If the

differential input voltage exceeds 1.4V, the input current should be limited

to less than 10mA.

Note 3: A heat sink may be required to keep the junction temperature

below the absolute maximum rating when the output is shorted

indefinitely.

Note 4: The LTC6362C and LTC6362I are guaranteed functional over

the operating temperature range of –40°C to 85°C. The LTC6362H is

guaranteed functional over the operating temperature range of –40°C to

125°C.

Note 5: The LTC6362C is guaranteed to meet specified performance from

0°C to 70°C.The LTC6362I is guaranteed to meet specified performance

from –40°C to 85°C. The LTC6362C is designed, characterized and

expected to meet specified performance from –40°C to 85°C, but is not

tested or QA sampled at these temperatures. The LTC6362H is guaranteed

to meet specified performance from –40°C to 125°C.

Note 6: Differential input referred offset voltage includes offset due to

input offset current across 1k source resistance.

Note 7: Maximum differential input referred offset voltage drift is

determined by a large sampling of typical parts. Drift is not guaranteed by

test or QA sampled at this value.

Note 8: Input bias current is defined as the maximum of the input currents

flowing into either of the input pins (–IN and +IN). Input Offset current is

defined as the difference between the input currents (IOS = IB+ – IB–).

Note 9: Input common mode range is tested by verifying that at the limits

stated in the Electrical Characteristics table, the differential offset (VOSDIFF)

and common mode offset (VOSCM) have not deviated by more than ±1mV

and ±35mV respectively compared to the VICM = 2.5V (at VS = 5V) and

VICM = 1.5V (at VS = 3V) cases.

Output common mode range is tested by verifying that at the limits stated

in the Electrical Characteristics table, the common mode offset (VOSCM)

has not deviated by more than ±15mV compared to the VOCM = 2.5V

(at VS = 5V) and VOCM = 1.5V (at VS = 3V) cases.

Note 10: Input CMRR is defined as the ratio of the change in the input

common mode voltage at the pins +IN or –IN to the change in differential

input referred offset voltage. Output CMRR is defined as the ratio of

the change in the voltage at the VOCM pin to the change in differential

input referred offset voltage. This specification is strongly dependent on

feedback ratio matching between the two outputs and their respective

inputs and it is difficult to measure actual amplifier performance (see

Effects of Resistor Pair Mismatch in the Applications Information section

of this data sheet). For a better indicator of actual amplifier performance

independent of feedback component matching, refer to the PSRR

specification.

Note 11: Differential power supply rejection (PSRR) is defined as the

ratio of the change in supply voltage to the change in differential input

referred offset voltage. Common mode power supply rejection (PSRRCM)

is defined as the ratio of the change in supply voltage to the change in the

common mode offset voltage.

Note 12: Supply voltage range is guaranteed by power supply rejection

ratio test.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIL SHDN Input Logic Low l0.8 V

VIH SHDN Input Logic High l2 V

tON Turn-On Time 2 μs

tOFF Turn-Off Time 2 μs

LTC6362

6362fa

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current vs SHDN Voltage

Shutdown Supply Current

vs Supply Voltage

Input Bias Current vs Input

Common Mode Voltage Supply Current vs Temperature

Supply Current

vs Supply Voltage

Common Mode Offset Voltage

vs Temperature

TEMPERATURE (°C)

–50

COMMON MODE OFFSET VOLTAGE (mV)

–5

050 75

6362 G04

–10

–15 –25 25 100 125

VS = ±2.5V

VICM = 0V

VOCM = 0V

FIVE TYPICAL UNITS

INPUT COMMON MODE VOLTAGE (V)

INPUT BIAS CURRENT (nA)

–400

400

800 VS = 5V

6362 G05

–800

–1200

–600

–200

200

600

–1000

–1400

–1600 1235

TEMPERATURE (°C)

–50

0.7

SUPPLY CURRENT (mA)

0.9

1.2

050 75

6362 G06

0.8

1.1

1.0

–25 25 100 125

VS = 5V

VS = 3V

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

0.6

0.8

1.0

1.2

6362 G07

0.4

0.2

01235

TA = 125°C

TA = 25°C

TA = –40°C

SHDN VOLTAGE (V)

SUPPLY CURRENT (mA)

0.6

0.8

1.0

1.2

6362 G08

0.4

0.2

01235

TA = 125°C

TA = 25°C

TA = –40°C

VS = 5V

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

3 4

6362 G09

1 2 5

TA = 125°C

TA = 25°C

TA = –40°C

VSHDN = V–

Differential Input Offset Voltage

vs Temperature

Differential Input Offset Voltage

vs Input Common Mode Voltage

Input Offset Current

vs Temperature

TEMPERATURE (°C)

–50

–200

DIFFERENTIAL INPUT OFFSET VOLTAGE (µV)

–150

–50

300

150

050 75

6362 G01

–100

200

250

100

–25 25 100 125

VS = ±2.5V

VICM = 0V

VOCM = 0V

FIVE TYPICAL UNITS

TEMPERATURE (°C)

–50

INPUT OFFSET CURRENT (nA)

6362 G02

–50

–25 0 50

–75

–100

100

–25

75 100 125

VS = ±2.5V

VICM = 0V

VOCM = 0V

FIVE TYPICAL UNITS

INPUT COMMON MODE VOLTAGE (V)

DIFFERENTIAL INPUT OFFSET VOLTAGE (µV)

100

200

300

6362 G03

–100

150

250

–50

–150

–200 1235

TA = 125°C

TA = 25°C

TA = –40°C

VS = 5V, 0V

VOCM = 2.5V

TYPICAL UNIT

LTC6362

6362fa

TYPICAL PERFORMANCE CHARACTERISTICS

Input Noise Density vs Frequency

Differential Output Impedance

vs Frequency

Common Mode Rejection Ratio

vs Frequency

Differential Power Supply

Rejection Ratio vs Frequency Slew Rate vs Temperature

Small-Signal Step Response Large-Signal Step Response

Turn-On and Turn-Off

Transient Response

Overdriven Output Transient

Response

5µs/DIV

1V/DIV

6362 G10

VSHDN

VOUTDIFF

FREQUENCY (Hz)

10 100 1k 10k 100k 1M

0.1

INPUT VOLTAGE NOISE DENSITY (nV/√Hz)

INPUT CURRENT NOISE DENSITY (pA/√Hz)

100

0.1

100

10M

6362 G11

VS = ±2.5V

VICM = VOCM = 0V

FREQUENCY (Hz)

OUTPUT IMPEDANCE (Ω)

100

100k 10M 100M 1G

6362 G12

11M

1000

VS = ±2.5V

RI = RF = 1k

FREQUENCY (Hz)

1k 10k

COMMON MODE REJECTION RATIO (dB)

100

100k 1M 10M 100M 1G

6362 G13

VS = ±2.5V

FREQUENCY (Hz)

1k 10k

POWER SUPPLY REJECTION RATIO (dB)

110

100

120

100k 1M 10M 100M 1G

6362 G14

VS = ±2.5V

PSRR+

PSRR–

TEMPERATURE (°C)

–50

SLEW RATE (V/µs)

6362 G15

–25 0 50

VS = ±2.5V

RI = RF = 1k

VOUTDIFF = 8VP-P

DIFFERENTIAL INPUT

SLEW MEASURED 10% TO 90%

75 100 125

FALLING

RISING

20mV/DIV

6362 G16

100ns/DIV

V+OUT

V–OUT

VS = ±2.5V

VINDIFF = 200mVP-P

RI = RF = 1k

RLOAD = 1k

500mV/DIV

6362 G17

100ns/DIV

VS = ±2.5V

VINDIFF = 8VP-P

RLOAD = 1k

V+OUT

V–OUT

1V/DIV

1µs/DIV

VS = ±2.5V

VINDIFF = 13VP-P

RLOAD = 1k

6362 G18

VINDIFF

VOUTDIFF

LTC6362

6362fa

TYPICAL PERFORMANCE CHARACTERISTICS

Harmonic Distortion vs Input

Common Mode Voltage

Harmonic Distortion vs Output

Amplitude

Harmonic Distortion vs Frequency

Settling Time to 8VP-P

Output Step DC LinearitySettling Time vs Output Step

DIFFERENTIAL OUTPUT STEP (VP-P)

SETTLING TIME (ns)

100

200

300

700

500

347

600

400

568

18-BIT

VS = 5V, 0V

RI = RF = 1k

6362 G21

16-BIT

0.5µs/DIV

DIFFERENTIAL OUTPUT VOLTAGE (V)

ERROR (µV) 1 DIV = 18-BIT ERROR

6362 G22

–1

–3

–2

–4

–5

150

–30

–90

120

–60

–120

–150

VS = 5V, 0V

RI = RF = 1k

ERROR

VOUTDIFF

VINDIFF (V)

–5

DIFFERENTIAL OUTPUT ERROR

FROM LINEAR FIT (µV)

100

6362 G23

–20

–60

–40

–80

–100 –3–4 –1–2 1 2 4

VS = ±2.5V

VICM = VOCM = 0V

RI = RF = 1k

NO LOAD

LINEAR FIT FOR –4V < VINDIFF < 4V

FREQUENCY (kHz)

–130

DISTORTION (dBc)

–120

–110

–100

–90

–70

10 100

HD3

HD2

6362 G24

–80

VS = 5V, 0V

VOCM = 2.5V

RI = RF = 1k

VOUTDIFF = 8VP-P

SINGLE-ENDED INPUT,

GROUND REFERENCED

INPUT COMMON MODE VOLTAGE (V)

–140

DISTORTION (dBc)

–130

–120

–110

–70

–90

–80

–100

345

6362 G25

VS = 5V, 0V

VOCM = 2.5V

RI = RF = 1k

VOUTDIFF = 8VP-P

fIN = 2kHz

DIFFERENTIAL INPUTS

HD3

HD2

VOUTDIFF (VP-P)

DISTORTION (dBc)

–100

–90

–80

6362 G26

–110

–120

–130 24610

VS = 5V, 0V

VOCM = 2.5V

RI = RF = 1k

fIN = 2kHz

SINGLE-ENDED INPUT,

GROUND REFERENCED

HD3

HD2

Frequency Response

vs Closed-Loop Gain

Frequency Peaking

vs Load Capacitance

FREQUENCY (Hz)

GAIN (dB)

100k 10M 100M 1G

6362 G19

–20 1M

–10

AV = 1, RI = 1k, RF = 1k

AV = 2, RI = 500Ω, RF = 1k

AV = 5, RI = 400Ω, RF = 2k

AV = 10, RI = 200Ω, RF = 2k

AV = 20, RI = 100Ω, RF = 2k

AV = 100, RI = 20Ω, RF = 2k

VS = ±2.5V

VICM = VOCM = 0V

RLOAD = 1k

CAPACITIVE LOAD (pF)

1.00

FREQUENCY PEAKING (dB)

1.50

2.00

100 1000 10000

6362 G20

0.50

0.75

1.25

1.75

0.25

VS = ±2.5V

VICM = 0V

VOCM = 0V

RI = RF = 1k

RLOAD = 1k

CAPACITOR VALUES ARE

FROM EACH OUTPUT TO

GROUND THROUGH 35Ω

SERIES RESISTANCE

LTC6362

6362fa

PIN FUNCTIONS

–IN (Pin 1): Inverting Input of Amplifier. Valid input range

is from V– to V+.

VOCM (Pin 2): Output Common Mode Reference Voltage.

The voltage on this pin sets the output common mode

voltage level. If left floating, an internal resistor divider

develops a default voltage of 2.5V with a 5V supply.

V+ (Pin 3): Positive Power Supply. Operational supply

range is 2.8V to 5.25V when V– = 0V.

+OUT (Pin 4): Positive Output Pin. Output capable of

swinging rail-to-rail.

–OUT (Pin 5): Negative Output Pin. Output capable of

swinging rail-to-rail.

V– (Pin 6/Exposed Pad Pin 9): Negative Power Supply,

Typically 0V. Negative supply can be negative as long as

2.8V ≤ (V+ – V–) ≤ 5.25V still holds.

SHDN (Pin 7): When SHDN is floating or directly tied to

V+ the LTC6362 is in the normal (active) operating mode.

When the SHDN pin is connected to V–, the part is disabled

and draws approximately 70µA of supply current.

+IN (Pin 8): Noninverting Input of Amplifier. Valid input

range is from V– to V+.

BLOCK DIAGRAM

–

8 567

1 432

V+

340k

VOCM

V–

+IN

–IN +OUT

6362 BD

V+

V–

VOCM

–OUTV–

SHDN

V–V+

V–V+V–V+V–V+

V–V+V–V+

LTC6362

6362fa

APPLICATIONS INFORMATION

Functional Description

The LTC6362 is a low power, low noise, high DC accuracy

fully differential operational amplifier/ADC driver. The

amplifier is optimized to convert a fully differential or

single-ended signal to a low impedance, balanced differ-

ential output suitable for driving high performance, low

power differential successive approximation register (SAR)

ADCs. The balanced differential nature of the amplifier

also provides even-order harmonic distortion cancella-

tion, and low susceptibility to common mode noise (like

power supply noise).

The outputs of the LTC6362 are capable of swinging rail-

to-rail and can source or sink up to 35mA of current. The

LTC6362 is optimized for high bandwidth and low power

applications. Load capacitances above 10pF to ground or

5pF differentially should be decoupled with 10Ω to 100Ω

of series resistance from each output to prevent oscilla-

tion or ringing. Feedback should be taken directly from

the amplifier output. Higher voltage gain configurations

tend to have better capacitive drive capability than lower

gain configurations due to lower closed-loop bandwidth.

Input Pin Protection

The LTC6362 input stage is protected against differential

input voltages which exceed 1.4V by two pairs of series

diodes connected back-to-back between +IN and –IN.

Moreover, all pins have clamping diodes to both power

supplies. If any pin is driven to voltages which exceed

either supply, the current should be limited to under 10mA

to prevent damage to the IC.

SHDN Pin

The LTC6362 has a SHDN pin which when driven to within

0.8V above the negative rail, will shut down amplifier op-

eration such that only 70µA is drawn from the supplies.

Pull-down circuitry should be capable of sinking at least

4µA to guarantee complete shutdown across all condi-

tions. For normal operation, the SHDN pin should be left

floating or tied to the positive rail.

General Amplifier Applications

In Figure 1, the gain to VOUTDIFF from VINP and VINM is

given by:

VOUTDIFF =V+OUT −V–OUT ≈RF









•VINP – VINM

( )

Note from the previous equation, the differential output

voltage (V+OUT – V–OUT) is completely independent of

input and output common mode voltages, or the voltage

at the common mode pin. This makes the LTC6362 ideally

suited for pre-amplification, level shifting and conversion

of single-ended signals to differential output signals for

driving differential input ADCs.

Output Common Mode and VOCM Pin

The output common mode voltage is defined as the aver-

age of the two outputs:

VOUTCM =VOCM =V+OUT +V–OUT











As the equation shows, the output common mode voltage

is independent of the input common mode voltage, and

is instead determined by the voltage on the VOCM pin, by

means of an internal common mode feedback loop.

If the VOCM pin is left open, an internal resistor divider

develops a default voltage of 2.5V with a 5V supply. The

VOCM pin can be overdriven to another voltage if desired.

For example, when driving an ADC, if the ADC makes a

reference available for setting the common mode volt-

age, it can be directly tied to the VOCM pin, as long as

the ADC is capable of driving the 170k input resistance

presented by the VOCM pin. The Electrical Characteristics

table specifies the valid range that can be applied to the

VOCM pin (VOUTCMR).

LTC6362

6362fa

APPLICATIONS INFORMATION

Input Common Mode Voltage Range

The LTC6362’s input common mode voltage (VICM) is

defined as the average of the two input pins, V+IN and

V–IN. The inputs of the LTC6362 are capable of swinging

rail-to-rail and as such the valid range that can be used for

VICM is V– to V+. However, due to external resistive divider

action of the gain and feedback resistors, the effective

range of signals that can be processed is even wider. The

input common mode range at the op amp inputs depends

on the circuit configuration (gain), VOCM and VCM (refer to

Figure 1). For fully differential input applications, where

VINP = –VINM, the common mode input is approximately:

VICM =V+IN

V–IN

2≈VOCM •RI

RI+RF

+VCM •RF

RI+RF

With single-ended inputs, there is an input signal compo-

nent to the input common mode voltage. Applying only

VINP (setting VINM to zero), the input common voltage is

approximately:

VICM =V+IN +V–IN

≈VOCM •RI

RI+RF

+VCM •RF

RI+RF

+VINP

2•RF

RI+RF

This means that if, for example, the input signal (VINP)

is a sine, an attenuated version of that sine signal also

appears at the op amp inputs.

current follows ∆IB/∆VICM = 75nA/V, with IB at VICM = 2.5V

typically below 75nA on a 5V supply. For common mode

voltages ranging from 1.1V below the positive supply to

0.2V below the positive supply, input bias current follows

∆IB/∆VICM = 25nA/V, with IB at VICM = 4.5V typically below

75nA on a 5V supply. Operating within these ranges allows

the amplifier to be used in applications with high source

resistances where errors due to voltage drops must be

minimized. For applications where VICM is within 0.2V of

either rail, input bias current may reach values over 1µA.

Input Impedance and Loading Effects

The low frequency input impedance looking into the VINP

or VINM input of Figure 1 depends on how the inputs are

driven. For fully differential input sources (VINP = –VINM),

the input impedance seen at either input is simply:

RINP = RINM = RI

For single-ended inputs, because of the signal imbalance

at the input, the input impedance actually increases over

the balanced differential case. The input impedance looking

into either input is:

RINP =RINM =RI

1– 1









•RF

RI+RF











Input signal sources with non-zero output impedances can

also cause feedback imbalance between the pair of feedback

networks. For the best performance, it is recommended

that the input source output impedance be compensated.

If input impedance matching is required by the source, a

termination resistor R1 should be chosen (see Figure2)

such that:

R1=RINM •RS

RINM –RS

According to Figure 2, the input impedance looking into

the differential amp (RINM) reflects the single-ended source

case, given above. Also, R2 is chosen as:

R2=R1||RS=R1•RS

R1+RS

Figure 1. Definitions and Terminology

–

RFV–OUT

V+OUT

VOCM

VINP

VINM

VOCM

6362 F01

RIV–IN

V+IN

–

VCM +

–

Input Bias Current

Input bias current varies according to VICM. For common

mode voltages ranging from 0.2V above the negative

supply to 1.1V below the positive supply, input bias

LTC6362

6362fa

APPLICATIONS INFORMATION

Effects of Resistor Pair Mismatch

Figure 3 shows a circuit diagram which takes into consid-

eration that real world resistors will not match perfectly.

Assuming infinite open-loop gain, the differential output

relationship is given by the equation:

VOUT(DIFF) =V+OUT – V–OUT

≈VINDIFF •RF

+VCM •∆β

βAVG

– VOCM •∆β

βAVG

where RF is the average of RF1 and RF2, and RI is the

average of RI1 and RI2.

βAVG is defined as the average feedback factor from the

outputs to their respective inputs:



βAVG =1

2•RI1

RI1 +RF1

+RI2

RI2 +RF2











∆β is defined as the difference in the feedback factors:

∆β = RI2

RI2 +RF2

–RI1

RI1 +RF1

Here, VCM and VINDIFF are defined as the average and

the difference of the two input voltages VINP and VINM,

respectively:

VCM =VINP +VINM

VINDIFF = VINP – VINM

When the feedback ratios mismatch (Δβ), common mode

to differential conversion occurs. Setting the differential

input to zero (VINDIFF = 0), the degree of common mode

to differential conversion is given by the equation:

VOUTDIFF ≈ (VCM – VOCM) • ∆β/βAVG

In general, the degree of feedback pair mismatch is a

source of common mode to differential conversion of

both signals and noise. Using 0.1% resistors or better will

mitigate most problems. A low impedance ground plane

should be used as a reference for both the input signal

source and the VOCM pin.

Noise

The LTC6362’s differential input referred voltage and current

noise densities are 3.9nV/√Hz and 0.8pA/√Hz, respectively.

In addition to the noise generated by the amplifier, the

surrounding feedback resistors also contribute noise. A

simplified noise model is shown in Figure 4. The output

noise generated by both the amplifier and the feedback

components is given by the equation:

eno =

eni •1+RF























+2•in•RF

( )

+2•enRI •RF











+2•enRF

For example, if RF = RI = 1k, the output noise of the circuit

eno = 12nV/√Hz.

If the circuits surrounding the amplifier are well balanced,

common mode noise (envocm) does not appear in the dif-

ferential output noise equation given above.

Figure 2. Optimal Compensation for Signal Source Impedance

–

RINM

R2 = RS || R1

R1 CHOSEN SO THAT R1 || RINM = RS

R2 CHOSEN TO BALANCE R1 || RS

6405 F04

–

RF2 V–OUT

V+OUT

VVOCM

VINP

VINM

VOCM

6362 F03

RF1

RI2

RI1 V–IN

V+IN

–

VCM +

–

Figure 3. Real-World Application with

Feedback Resistor Pair Mismatch

LTC6362

6362fa

The LTC6362’s input referred voltage noise contributes the

equivalent noise of a 920Ω resistor. When the feedback

network is comprised of resistors whose values are larger

than this, the output noise is resistor noise and amplifier

current noise dominant. For feedback networks consisting

of resistors with values smaller than 920Ω, the output

noise is voltage noise dominant.

Lower resistor values always result in lower noise at the

penalty of increased distortion due to increased loading of

the feedback network on the output. Higher resistor values

will result in higher output noise, but typically improved

distortion due to less loading on the output. For this rea-

son, when LTC6362 is configured in a differential gain of

1, using feedback resistors of at least 1k is recommended.

GBW vs f–3dB

Gain-bandwidth product (GBW) and –3dB frequency

(f–3dB) have been specified in the Electrical Characteristics

table as two different metrics for the speed of the LTC6362.

GBW is obtained by measuring the open-loop gain of the

amplifier at a specific frequency (fTEST), then calculating

gain • fTEST. GBW is a parameter that depends only on the

internal design and compensation of the amplifier and is

a suitable metric to specify the inherent speed capability

of the amplifier.

f–3dB, on the other hand, is a parameter of more practical

interest in different applications and is by definition the

frequency at which the closed-loop gain is 3dB lower than

its low frequency value. The value of f–3dB depends on the

APPLICATIONS INFORMATION

Figure 4. Simplified Noise Model

–

eno2

enRI2

enRF2

enRI2eni2

enRF2

in+2

in–2

6362 F04

speed of the amplifier as well as the feedback factor. Since

the LTC6362 is designed to be stable in a differential signal

gain of 1 (where RI = RF or β = 1/2), the maximum f–3dB

is obtained and measured in this gain setting, as reported

in the Electrical Characteristics table.

In most amplifiers, the open-loop gain response exhibits a

conventional single-pole roll-off for most of the frequencies

before the unity-gain crossover frequency, and the GBW and

unity-gain frequency are close to each other. However, the

LTC6362 is intentionally compensated in such a way that

its GBW is significantly larger than its f–3dB. This means

that at lower frequencies where the amplifier inputs gen-

erally operate, the amplifier’s gain and thus the feedback

loop gain is larger. This has the important advantage of

further linearizing the amplifier and improving distortion

at those frequencies.

Feedback Capacitors

In cases where the LTC6362 is connected such that the

combination of parasitic capacitances (device + PCB) at the

inverting input forms a pole whose frequency lies within

the closed-loop bandwidth of the amplifier, a capacitor

(CF) can be added in parallel with the feedback resistor

(RF) to cancel the degradation on stability. CF should be

chosen such that it generates a zero at a frequency close

to the frequency of the pole.

In general, a larger value for CF reduces the peaking (over-

shoot) of the amplifier in both frequency and time domains,

but also decreases the closed-loop bandwidth (f–3dB).

Board Layout and Bypass Capacitors

For single supply applications, it is recommended that

high quality 0.1µF ceramic bypass capacitors be placed

directly between the V+ and the V– pin with short con-

nections. The V– pins (including the exposed pad in the

DD8 package) should be tied directly to a low impedance

ground plane with minimal routing. For dual (split) power

supplies, it is recommended that additional high quality

0.1µF ceramic capacitors be used to bypass V+ to ground

and V– to ground, again with minimal routing. Small

geometry (e.g., 0603) surface mount ceramic capacitors

have a much higher self-resonant frequency than leaded

capacitors, and perform best with LTC6362.

LTC6362

6362fa

APPLICATIONS INFORMATION

To prevent degradation in stability response, it is highly

recommended that any stray capacitance at the input pins,

+IN and –IN, be kept to an absolute minimum by keeping

printed circuit connections as short as possible.

At the output, always keep in mind the differential nature of

the LTC6362, because it is critical that the load impedances

seen by both outputs (stray or intended), be as balanced

and symmetric as possible. This will help preserve the

balanced operation of the LTC6362 that minimizes the

generation of even-order harmonics and maximizes the

rejection of common mode signals and noise.

The VOCM pin should be bypassed to the ground plane with

a high quality 0.1µF ceramic capacitor. This will prevent

common mode signals and noise on this pin from being

inadvertently converted to differential signals and noise

by impedance mismatches both externally and internally

to the IC.

Interfacing to ADCs

When driving an ADC, an additional passive filter should be

used between the outputs of the LTC6362 and the inputs

of the ADC. Depending on the application, a single-pole

RC filter will often be sufficient. The sampling process

of ADCs creates a charge transient that is caused by the

switching in of the ADC sampling capacitor. This mo-

mentarily “shorts” the output of the amplifier as charge

is transferred between amplifier and sampling capacitor.

The amplifier must recover and settle from this load

transient before the acquisition period has ended, for a

valid representation of the input signal. The RC network

between the outputs of the driver and the inputs of the

ADC decouples the sampling transient of the ADC (see

Figure 5). The capacitance serves to provide the bulk

of the charge during the sampling process, while the

two resistors at the outputs of the LTC6362 are used to

dampen and attenuate any charge injected by the ADC.

The RC filter gives the additional benefit of band limiting

broadband output noise.

The selection of an appropriate filter depends on the specific

ADC, however the following procedure is suggested for

choosing filter component values. Begin by selecting an

appropriate RC time constant for the input signal. Gener-

ally, longer time constants improve SNR at the expense of

settling time. Output transient settling to 18-bit accuracy

will typically require over twelve RC time constants. To

select the resistor value, remember the resistors in the

decoupling network should be at least 10Ω. Keep in mind

that these resistors also serve to decouple the LTC6362

outputs from load capacitance. Too large of a resistor will

leave insufficient settling time. Too small of a resistor will

not properly dampen the load transient of the sampling

process, prolonging the time required for settling. For

lowest distortion, choose capacitors with low dielectric

absorption (such as a C0G multilayer ceramic capacitor). In

general, large capacitor values attenuate the fixed nonlinear

charge kickback, however very large capacitor values will

detrimentally load the driver at the desired input frequency

and thus cause driver distortion. Smaller input swings will

in general allow for larger filter capacitor values due to

decreased loading demands on the driver. This property

however may be limited by the particular input amplitude

dependence of differential nonlinear charge kickback for

the specific ADC used.

In some applications, placing series resistors at the inputs

of the ADC may further improve distortion performance.

These series resistors function with the ADC sampling

capacitor to filter potential ground bounce or other high

speed sampling disturbances. Additionally the resistors

limit the rise time of residual filter glitches that manage to

propagate to the driver outputs. Restricting possible glitch

propagation rise time to within the small signal bandwidth

of the driver enables less disturbed output settling.

For the specific application of LTC6362 driving the

LTC2379-18 SAR ADC in a gain of AV = –1 configuration,

the recommended component values of the RC filter for

varying filter bandwidths are provided in Figure 5. These

component values are chosen for optimal distortion per-

formance. Broadband output noise will vary with filter

bandwidth.

LTC6362

6362fa

APPLICATIONS INFORMATION

–

8 567

1 432

V+

LTC6362

340k

VOCM

V–

+IN

VIN

5V RFILT

CCM

–IN +OUTV+

VOCM

–OUTV–

SHDN

1k RFILT

CCM

6362 F05

1k1k

0.1µF 0.1µF

CDIFF

AIN+VREF VDD

LTC2379-18

SAR ADC

2.5V

GND

AIN–

FILTER BW

(Hz)

110k

380k

1.1M

3.0M

10M

29M

RFILT

(Ω)

125

35.7

100

175

100

CCM

(pF)

3900

470

100

CDIFF

(pF)

3900

470

100

(Ω)

Figure 5. Recommended Interface Solutions for Driving the LTC2379-18 SAR ADC

TYPICAL APPLICATIONS

Single-Ended-to-Differential Conversion of a 20VP-P Ground-Referenced Input with Gain of AV = –0.4 to Drive an ADC

–

5V 3.9nF

3.9nF

AIN+VREF VDD

LTC2379-18

SAR ADC

2.5V

GND

AIN–

6362 TA02

35.7Ω

35.7Ω 0Ω

0Ω

LTC6362

VOCM

0.1µF

VIN

10V

–10V

VIN

2k 806Ω

806Ω

SHDN

4.5V

0.5V

V–OUT

V+OUT

LTC6362

6362fa

TYPICAL APPLICATIONS

Single-Ended-to-Differential Conversion of a 4VP-P Input with Gain of AV = 2 to Drive an ADC for Applications Where

the Importance of High Input Impedance Justifies Some Degradation in Distortion, Noise, and DC Accuracy. Input Is

True High Impedance, However Common Mode Noise and Offset Are Present on the Output. Additionally, When the

Input Signal Exceeds 2.8VP-P, a Step in Input Offset Will Occur That Will Degrade Distortion Performance

–

5V 3.9nF

3.9nF

AIN+VREF VDD

LTC2379-18

SAR ADC

2.5V

GND

AIN–

6362 TA05

35.7Ω

0Ω

LTC6362

VOCM

0.1µF

4.5V

0.5V

VIN

SHDN

4.5V

0.5V

V–OUT

V+OUT

Differentially Driving an ADC with ∆VIN = 8VP-P and Gain of AV = 1

Single-Ended-to-Differential Conversion of a 5VP-P, 2.5V Referenced Input with Gain of AV = –1.6 to Drive an ADC

–

5V 3.9nF

3.9nF

VCM

2.5V

AIN+VREF VDD

LTC2379-18

SAR ADC

2.5V

GND

AIN–

6362 TA03

35.7Ω

0Ω

LTC6362

VOCM

0.1µF

619Ω

VIN

619Ω 1k

SHDN

4.5V

0.5V

V–OUT

V+OUT

–

5V 3.9nF

3.9nF

AIN+VREF VDD

LTC2379-18

SAR ADC

2.5V

GND

AIN–

6362 TA04

35.7Ω

0Ω

LTC6362

VOCM

0.1µF

4.5V

0.5V

VINM

1k 1k

SHDN

4.5V

0.5V

VINP 4.5V

4.5V

0.5V

V–OUT

V+OUT

LTC6362

6362fa

TYPICAL APPLICATIONS

Differential Line Driver Connected in Gain of AV = –1

Differentially Driving a Pipeline ADC with AV = 1

–

6362 TA06

49.9Ω

100Ω

LTC6362

VOCM

0.1µF

VIN

–1V

VIN

1k 1k

SHDN

V–OUT

V+OUT

–

3.3V 1.5nF

0.1µF

1.5nF

AIN+VDD VCM

1.8V

VCM = 0.9V

LTC2160

PIPELINE ADC

GND

AIN–

16 BIT

25Msps

6362 TA08

30Ω

5Ω

100Ω

5Ω

LTC6362

VOCM

INPUT BW = 1.2MHz

FULL SCALE = 2VP-P

0.1µF

1k 1k

SHDN

VIN

V–OUT

V+OUT

MEASURED PERFORMANCE FOR LTC6362 DRIVING LTC2160:

INPUT: fIN = 2kHz, –1dBFS

SNR: 77.0dB

HD2: –98.9dBc

HD3: –102.3dBc

THD: –96.3dB

LTC6362

6362fa

TYPICAL APPLICATIONS

LTC6362 Used as Lowpass Filter/Driver with 10VP-P Singled-Ended Input, Driving a SAR ADC

Differential AV = 1 Configuration Using an LT

5400 Quad-Matched Resistor Network

CMRR Comparison Using the LT5400 and 1% 0402 Resistors

–

1.8nF

0.1µF

1.8nF

AIN+VREF VDD

LTC2380-16

SAR ADC

2.5V

GND

AIN–

16 BIT

2Msps

6362 TA09

100Ω

LTC6362

0.1µF

1.8nF

1.27k

VCM

4-POLE FILTER

f–3dB = 50kHz

VCM

VIN

–5V

1.27k

1.27k 4.5V

4.5V

0.5V

LT5400

6362 TA10a

–

+–

LTC6362

VOCM V+OUT

V–OUT

VINM

VINP

SHDN

0.1µF 4.5V

0.5V

4.5V

0.5V

4.5V

0.5V

4.5V

0.5V

FREQUENCY (Hz)

CMRR (dB)

100

10 1k 10k 100k

6362 TA10b

0100

USING LT5400 MATCHED RESISTORS

USING 1% 0402 RESISTORS

VS = 5V, 0V

LTC6362

6362fa

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MSOP (MS8) 0307 REV F

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.18

(.007)

0.254

(.010)

1.10

(.043)

MAX

0.22 – 0.38

(.009 – .015)

TYP

0.1016 ±0.0508

(.004 ±.002)

0.86

(.034)

REF

0.65

(.0256)

BSC

0° – 6° TYP

DETAIL “A”

GAUGE PLANE

1 2 34

4.90 ±0.152

(.193 ±.006)

8765

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0.52

(.0205)

REF

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.42 ± 0.038

(.0165 ±.0015)

TYP

0.65

(.0256)

BSC

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660 Rev F)

LTC6362

6362fa

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ±0.10

(2 SIDES)

0.75 ±0.05

R = 0.125

TYP

2.38 ±0.10

PIN 1

TOP MARK

(NOTE 6)

0.200 REF

0.00 – 0.05

(DD8) DFN 0509 REV C

0.25 ±0.05

2.38 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

1.65 ±0.05

(2 SIDES)2.10 ±0.05

0.50

BSC

0.70 ±0.05

3.5 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50 BSC

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698 Rev C)

LTC6362

6362fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 05/12 Added DFN package

Added typical spec for 2VP-P tS

1, 2, 9, 13, 20

LTC6362

6362fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LINEAR TECHNOLOGY CORPORATION 2012

LT 0612 REV A • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

Single-Ended-to-Differential Conversion of a 10VP-P Ground-Referenced Input with Gain of AV = –0.8

to Drive a 5V Reference SAR ADC

–

5V 3.9nF

3.9nF

AIN+VREF VDD

LTC2379-18

SAR ADC

2.5V

GND

AIN–

18 BIT

1.6Msps

6362 TA07

35.7Ω

0Ω

LTC6362

VOCM

0.1µF

VIN

1.24k

–5V

VIN

1.24k 1k

SHDN

4.5V

0.5V

V–OUT

V+OUT

PART NUMBER DESCRIPTION COMMENTS

Operational Amplifiers

LT6350 Low Noise, Single-Ended to Differential Converter/

ADC Driver 4.8mA, –97dBc Distortion at 100kHz, 4VP–P Output

LTC6246/LTC6247/

LTC6248 Single/Dual/Quad 180MHz Rail-to-Rail Low Power

Op Amps 1mA/Amplifier, 4.2nV/√Hz

LTC6360 1GHz Very Low Noise Single-Ended SAR ADC Driver

with True Zero Output 13.6mA, HD2/HD3 = –103dBc/–109dBc at 40kHz, 4VP-P Output

LTC1992/LTC1992-X 3MHz to 4MHz Fully Differential Input/Output

Amplifiers Internal Feedback Resistors Available (G =1, 2, 5,10)

LT1994 70MHz Low Noise, Low Distortion Fully Differential

Input/Output Amplifier/Driver 13mA, –94dBc Distortion at 1MHz, 2VP-P Output

ADCs

LTC2379-18/LTC2378-18

LTC2377-18/LTC2376-18 18-Bit, 1.6Msps/1Msps/500ksps/250ksps Serial,

Low Power ADC 2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC,

Pin Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2380-16/LTC2378-16

LTC2377-16/LTC2376-16 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial,

Low Power ADC 2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC,

Pin Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2383-16/LTC2382-16/

LTC2381-16 16-Bit, 1Msps/500ksps/250ksps Serial, Low

Power ADC 2.5V Supply, Differential Input, 92dB SNR, ±2.5V Input Range, Pin

Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2393-16/LTC2392-16/

LTC2391-16 16-Bit, 1Msps/500ksps/250ksps Parallel/Serial ADC 5V Supply, Differential Input, 94dB SNR, ±4.096V Input Range, Pin

Compatible Family in 7mm × 7mm LQFP-48 and QFN-48 Packages

LTC2355-14/LTC2356-14 14-Bit, 3.5Msps Serial ADC 3.3V Supply, 1-Channel, Unipolar/Bipolar, 18mW, MSOP-10 Package

LTC2366 12-Bit, 3Msps Serial ADC 2.35V to 3.6V Supply 6- and 8-Lead TSOT-23 Packages

LTC2162/LTC2161/

LTC2160 16-Bit, 65/40/25Msps Low Power ADC 1.8V Supply, Differential Input, 77dB SNR, 2VP-P Input Range, Pipeline

Converter in 7mm × 7mm QFN-48 Package