1
Features
•High-performance, High-density, Electrically-erasable Programmable Logic Device
•Fully Connected Logic Array with 416 Product Terms
•10 ns Maximum Pin-to-pin Delay for 5V Operation
•Low-power Edge-sensing “L” Option with <1 mA Standby Current
•24 Flexible Output Macrocells
– 48 Flip-flops – Two per Macrocell
–72 Sum Terms
– All Flip-flops, I/O Pins Feed in Independently
•D- or T-type Flip-flops
•Product Term or Direct Input Pin Clocking
•Registered or Combinatorial Internal Feedback
•Backward Compatible with ATV2500B/BQL and ATV2500H/L Software
•Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
•44-lead Surface Mount Package
Block Diagram
Description
The ATF2500C is the highest-density PLD available in a 44-pin package. With its fully
connected logic array and flexible macrocell structure, high gate utilization is easily
obtainable. The ATF2500C is a high-performance CMOS (electrically-erasable) pro-
grammable logic device (PLD) that utilizes Atmel’s proven electrically-erasable
technology.
ATF2500C
CPLD Family
Datasheet
ATF2500C
ATF2500CL
ATF2500CQ
ATF2500CQL
Preliminary
Rev. 0777G–12/01
Pin Configurations
Pin Name Function
IN Logic Inputs
CLK/IN Pin Clock and Input
I/O Bi-directional Buffers
I/O 0,2,4... “Even” I/O Buffers
I/O 1,3,5... “Odd” I/O Buffers
GND Ground
VCC +5V Supply
DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
IN
IN
IN
IN
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
IN
IN
IN
PLCC/LCC/JLCC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
I/O12
IN
IN
IN
IN
IN
IN
IN
IN
I/O18
I/O19
I/O1
I/O0
GND
IN
IN
CLK/IN
IN
IN
IN
IN
I/O6
Note: For ATF2500CQ and ATF2500CQL
(PLCC/LCC/JLCC packages) pin 4 and pin 26
GND connections are not required.
2ATF2500C Family
0777G–12/01
The ATF2500C is organized around a single universal array. All pins and feedback terms are
always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out-
puts of each flip-flop.
In the ATF2500C, four product terms are input to each sum term. Furthermore, each macro-
cell’s three sum terms can be combined to provide up to 12 product terms per sum term with
no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, pro-
viding further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal
combinatorial feedback to the logic array.
Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-
flops may also be individually configured to have direct input pin clocking. Each output has its
own enable product term. Eight synchronous preset product terms serve local groups of either
four or eight flip-flops. Register preload functions are provided to simplify testing. All registers
automatically reset upon power-up.
The Atmel-unique “L” low-power feature is an edge-sensing option that is now field program-
mable for the ATF2500C family. The “L” feature utilizes Atmel-patented Input Transition
Detection (ITD) circuitry and is activated by selecting the “L” option from the program menu.
Using the
ATF2500C
Family’s Many
Advanced
Features
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:
•Fully Connected Logic Array – Each array input is always available to every product
term. This makes logic placement a breeze.
•Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are
also easily created. These options allow more efficient product term usage.
•Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to
feed its input (D/T2) directly back to the logic array. This provides further logic expansion
capability without using precious pin resources.
•Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops
has a dedicated clock product term. This removes the constraint that all registers use the
same clock. Buried state machines, counters and registers can all coexist in one device
while running on separate clocks. Individual flip-flop clock source selection further allows
mixing higher performance pin clocking and flexible product term clocking within one
design.
•A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of
48. Each register has its own clock and reset terms, as well as its own sum term.
•Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a
dedicated input path. Each of the 48 registers has its own feedback term into the array as
well. These features, combined with individual product terms for each I/O’s output enable,
facilitate true bi-directional I/O design.
•Combinable Sum Terms – Each output macrocell’s three sum terms may be combined
into a single term. This provides a fan in of up to 12 product terms per sum term with no
speed penalty.
3
ATF2500C Family
0777G–12/01
Power-up Reset The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed
slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises
in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin or terms high, and
3. The clock pin, and any signals from which clock terms are derived, must remain stable
during tPR.
Parameter Description Typ Max Units
tPR Power-up Reset Time 600 1000 ns
VRST Power-up Reset Voltage 3.8 4.5 V
Level Forced on
Odd I/O Pin during
PRELOAD Cycle
Q Select Pin
State
Even/Odd
Select
Even Q1 State
after Cycle
Even Q2 State
after Cycle
Odd Q1 State
after Cycle
Odd Q2 State
after Cycle
VIH/VIL Low Low High/Low X X X
VIH/VIL High Low X High/Low X X
VIH/VIL Low High X X High/Low X
VIH/VIL High High X X X High/Low
4ATF2500C Family
0777G–12/01
Preload and
Observability of
Registered
Outputs
The ATF2500Cs registers are provided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A VIH level on the odd I/O pins will force the
appropriate register high; a VIL will force it low, independent of the polarity or other configura-
tion bit settings.
The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When
the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12
registers chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2.
In this mode, the contents of the buried register bank will appear on the associated outputs
when the OE control signals are active.
Programming
Software
Support
All family members of the ATF2500C can be designed with Atmel-Synario™ and Atmel-Win-
CUPL™. ProChip™ designer support will be available Q102.
Additionally, the ATF2500C may be programmed to perform the ATV2500H/Ls functional sub-
set (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H/L JEDEC file. In
this case, the ATF2500C becomes a direct replacement or speed upgrade for the
ATV2500H/L. The ATF2500CQ/CQL are direct replacements for the ATV2500BQ/BQL and
the AT2500H/L, including the lack of extra grounds on P4 and P26.
Security Fuse
Usage
A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once
programmed, the outputs will read programmed during verify.
The security fuse should be programmed last, as its effect is immediate.
The security fuse also inhibits Preload and Q2 observability.
Input and I/O
Pull-ups
All ATF2500C family members have programmable internal input and I/O pinkeeper circuits.
The default condition, including when using the AT2500CQ/CQL family to replace the
AT2500BQ/BQL or AT2500H/L, is that the pinkeepers are not activated.
When pinkeepers are active, inputs or I/Os not being driven externally will maintain their last
driven state. This ensures that all logic array inputs and device outputs are known states.
Pinkeepers are relatively weak active circuits that can be easily overridden by TTL-compatible
drivers (see input and I/O diagrams below).
5
ATF2500C Family
0777G–12/01
Input Diagram
I/O Diagram
Functional
Logic Diagram
Description
The ATF2500C functional logic diagram describes the interconnections between the input,
feedback pins and logic cells. All interconnections are routed through the single global bus.
The ATF2500Cs are straightforward and uniform PLDs. The 24 macrocells are numbered 0
through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five
lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous
reset and clock per flip-flop, and an output enable. The top 12 product terms are grouped into
three sum terms, which are used as shown in the macrocell diagrams.
Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share
Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing
Preset 7.
The 14 dedicated inputs and their complements use the numbered positions in the global bus
as shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2(1)
true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by
these signals in the global bus are the six numbers in the bus diagram next to each macrocell.
Note: 1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATF2500Cs.
INPUT
6ATF2500C Family
0777G–12/01
Functional Logic Diagram ATV2500C
Notes: 1. Pin 4 and Pin 26 are “ground” connections and are not required for PLCC, LCC and JLCC versions of ATF2500CQ or
ATF2500CQL, making them compatible with ATV2500H and ATV2500L as well as ATV2500BQ and ATV2500BQL pinouts.
2. For DIP package, VCC = P10 and GND = P30. For, PLCC, LCC and JLCC packages, VCC = P11 and P12, GND1 = P33 and
P34, and GND2 = P4, P26 (See Note 1, above).
7
ATF2500C Family
0777G–12/01
Output Logic, Registered(1)
Output Logic, Combinatiorial(1)
Note: 1. These diagrams show equivalent logic functions, not
necessarily the actual circuit implementation.
Note: 1. These four terms are shared with D/T1.
Clock Option
S2 = 0 Terms in
Output ConfigurationS1 S0 D/T1 D/T2
0084Registered (Q1); Q2 FB
10124
(1) Registered (Q1); Q2 FB
1184Registered (Q1); D/T2 FB
S3
Output
Configuration S6 Q1 CLOCK
0 Active Low 0 CK1
1 Active High 1 CK1 • PIN1
S4 Register 1 Type S7 Q2 CLOCK
0D 0CK2
1T 1CK2 • PIN1
S5 Register 2 Type
0D
1T
S2 = 1 Terms in
Output ConfigurationS5 S1 S0 D/T1 D/T2
X004
(1) 4Combinatorial (8 Terms);
Q2 FB
X0144
Combinatorial (4 Terms);
Q2 FB
X104
(1) 4(1) Combinatorial (12 Terms);
Q2 FB
1114
(1) 4Combinatorial (8 Terms);
D/T2 FB
01144
Combinatorial (4 Terms);
D/T2 FB
8ATF2500C Family
0777G–12/01
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note: 1. Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC
which may overshoot to +7.0V for pulses of less
than 20 ns.
Storage Temperature..................................... -65°C to +150°C
Junction Temperature .............................................150°C Max
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC and AC Operating Conditions
Commercial Industrial Military
Operating Temperature 0°C - 70°C
(Ambient)
-40°C - 85°C
(Ambient)
-55°C - 125°C
(Case)
VCC Power Supply 5V ± 5% 5V ± 10% 5V ± 10%
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ Max Units Conditions
CIN 46pFV
IN = 0V
COUT 812pFV
OUT = 0V
Test Waveforms and Measurement Levels Output Test Load
9
ATF2500C Family
0777G–12/01
AC Waveforms(1) Input Pin Clock
AC Waveforms(1) Product Term Clock
AC Waveforms(1) Combinatorial Outputs and Feedback
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
10 ATF2500C
0777G–12/01
Note: 1. See ICC versus frequency characterization curves.
ATF2500C DC Characteristics
Symbol Parameter Condition Min Typ Max Units
IIL Input Load Current VIN = -0.1V to VCC + 1V 10 µA
ILO
Output Leakage
Current VOUT = -0.1V to VCC + 0.1V 10 µA
ICC
Power Supply
Current Standby
VCC = MAX,
VIN = GND or
VCC f = 0 MHz,
Outputs Open
ATF2500C
Com. 110 190 mA
Ind., Mil. 110 210 mA
IOS
Output Short
Circuit Current VOUT = 0.5V -120 mA
VIL Input Low Voltage MIN ≤ VCC ≤ MAX -0.6 0.8 V
VIH Input High Voltage 2.0 VCC + 0.75 V
VOL
Output Low
Voltage
VIN = VIH or VIL,
VCC = 4.5V
IOL = 8 mA Com., Ind. 0.5 V
IOL = 6 mA Mil. 0.5 V
VOH
Output High
Voltage VCC = MIN IOH = -100 µA VCC - 0.3 V
IOH = -4.0 mA 2.4
ATF2500C AC Characteristics
Symbol Parameter
-10 -15
UnitsMinMaxMinMax
tPD1 Input to Non-registered Output 10 15 ns
tPD2 Feedback to Non-registered Output 10 15 ns
tPD3 Input to Non-registered Feedback 6 11 ns
tPD4 Feedback to Non-registered Feedback 6 11 ns
tEA1 Input to Output Enable 10 15 ns
tER1 Input to Output Disable 10 15 ns
tEA2 Feedback to Output Enable 10 15 ns
tER2 Feedback to Output Disable 10 15 ns
tAW Asynchronous Reset Width 4 8 ns
tAP Asynchronous Reset to Registered Output 13 18 ns
tAPF Asynchronous Reset to Registered Feedback 10 15 ns
11
ATF2500C
0777G–12/01
ATF2500C Register AC Characteristics, Input Pin Clock
Symbol Parameter
-10 -15
Units
Min Max Min Max
tCOS Clock to Output 5.5 10 ns
tCFS Clock to Feedback 0 2 0 5 ns
tSIS Input Setup Time 2 9 ns
tSFS Feedback Setup Time 2 9 ns
tHS Hold Time 0 0 ns
tWS Clock Width 3 6 ns
tPS Clock Period 8 12 ns
FMAXS
External Feedback 1/(tSIS + tCOS)7552MHz
Internal Feedback 1/(tSFS + tCFS)10071MHz
No Feedback 1/(tPS)11083MHz
tARS Asynchronous Reset/Preset Recovery Time 5 12 ns
ATF2500C Register AC Characteristics, Product Term Clock
Symbol Parameter
-10 -15
UnitsMin Max Min Max
tCOA Clock to Output 10 15 ns
tCFA Clock to Feedback 2 5 5 12 ns
tSIA Input Setup Time 2 5 ns
tSFA Feedback Setup Time 2 5 ns
tHA Hold Time 1 5 ns
tWA Clock Width 3 7.5 ns
tPA Clock Period 9 15 ns
FMAXA
External Feedback 1/(tSIA + tCOA)75.550MHz
Internal Feedback 1/(tSFA + tCFA)10058MHz
No Feedback 1/(tPS)10066MHz
tARA Asynchronous Reset/Preset Recovery Time 2 8 ns
12 ATF2500C
0777G–12/01
STAND-BY ICC VS.
SUPPLY VOLTAGE (TA = 25°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
I
CC
(µA)
TBD
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
0.000
20.000
40.000
60.000
80.000
100.000
120.000
140.000
0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0
FREQUENCY (MHz)
I
CC
(mA)
TBD
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
-50
-40
-30
-20
-10
0
4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
I
OH
(mA)
TBD
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
0
0
0
1
1
1
4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
Iol (mA)
TBD
NORMALIZED ICC VS. TEMP
0.4
0.6
0.8
1.0
1.2
1.4
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED Icc
TBD
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
0.000
0.200
0.400
0.600
0.800
1.000
0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0
FREQUENCY (MHz)
I
CC
(mA)
TBD
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
VOH (V)
I
OH
(mA)
TBD
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
I
OL
(mA)
TBD
13
ATF2500C
0777G–12/01
INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
-120
-100
-80
-60
-40
-20
0
0.0 -0.2 -0.4 -0.6 -0.8 -1.0
INPUT VOLTAGE (V)
INPUT
CURRENT (mA)
TBD
NORMALIZED TPD VS. VCC
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
PD
TBD
NORMALIZED TCO VS. VCC
0.8
0.9
1.0
1.1
1.2
1.3
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
CO
TBD
NORMALIZED TPD VS. VCC
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
PD
TBD
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0
0
0
1
1
1
0.01.02.03.04.05.06.0
INPUT VOLTAGE (V)
INPUT CURRENT
(uA)
TBD
NORMALIZED TPD VS. TEMP
0.8
0.9
1.0
1.1
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED T
PD
TBD
NORMALIZED TCO VS. TEMP
0.8
0.9
1.0
1.1
-40.0 0.0 25.0 75.0
TEMPERATURE (V)
NORMALIZED T
CO
TBD
NORMALIZED TSU VS. TEMP
0.8
0.9
1.0
1.1
1.2
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED T
CO
TBD
14 ATF2500C
0777G–12/01
DELTA TPD VS.
OUTPUT LOADING
-2
0
2
4
6
8
0 50 100 150 200 250 300
OUTPUT LOADING (PF)
DELTA T
PD
(ns)
TBD
DELTA TPD VS. # OF OUTPUT SWITCHING
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
1.02.03.04.05.06.07.08.09.010.0
NUMBER OF OUTPUTS SWITCHING
DELTA T
PD
(ns)
TBD
DELTA TCO VS.
OUTPUT LOADING
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
50 100 150 200 250 300
NUMBER OF OUTPUTS LOADING
DELTA T
CO
(ns)
TBD
DELTA TCO VS. # OF OUTPUT SWITCHING
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
NUMBER OF OUTPUTS SWITCHING
DELTA T
PD
(ns)
TBD
15
ATF2500CL
0777G–12/01
Note: 1. See ICC versus frequency characterization curves.
ATF2500CL DC Characteristics
Symbol Parameter Condition Min Typ Max Units
IIL Input Load Current VIN = -0.1V to VCC + 1V 10 µA
ILO
Output Leakage
Current VOUT = -0.1V to VCC + 0.1V 10 µA
ICC
Power Supply
Current Standby
VCC = MAX,
VIN = GND or
VCC f = 0 MHz,
Outputs Open
ATF2500CL
Com. 25 mA
Ind., Mil. 210 mA
IOS
Output Short
Circuit Current VOUT = 0.5V -120 mA
VIL Input Low Voltage MIN ≤ VCC ≤ MAX -0.6 0.8 V
VIH Input High Voltage 2.0 VCC + 0.75 V
VOL Output Low Voltage VIN = VIH or VIL,
VCC = 4.5V
IOL = 8 mA Com., Ind. 0.5 V
IOL = 6 mA Mil. 0.5 V
VOH
Output High
Voltage VCC = MIN IOH = -100 µA VCC - 0.3 V
IOH = -4.0 mA 2.4
ATF2500CL AC Characteristics
Symbol Parameter
-20
UnitsMin Max
tPD1 Input to Non-registered Output 20 ns
tPD2 Feedback to Non-registered Output 20 ns
tPD3 Input to Non-registered Feedback 15 ns
tPD4 Feedback to Non-registered Feedback 15 ns
tEA1 Input to Output Enable 20 ns
tER1 Input to Output Disable 20 ns
tEA2 Feedback to Output Enable 20 ns
tER2 Feedback to Output Disable 20 ns
tAW Asynchronous Reset Width 12 ns
tAP Asynchronous Reset to Registered Output 22 ns
tAPF Asynchronous Reset to Registered Feedback 19 ns
16 ATF2500CL
0777G–12/01
ATF2500CL Register AC Characteristics, Input Pin Clock
Symbol Parameter
-20
Units
Min Max
tCOS Clock to Output 11 ns
tCFS Clock to Feedback 0 6 ns
tSIS Input Setup Time 14 ns
tSFS Feedback Setup Time 14 ns
tHS Hold Time 0 ns
tWS Clock Width 7 ns
tPS Clock Period 14 ns
FMAXS
External Feedback 1/(tSIS + tCOS)40MHz
Internal Feedback 1/(tSFS + tCFS)50MHz
No Feedback 1/(tPS)71 MHz
tARS Asynchronous Reset/Preset Recovery Time 15 ns
ATF2500CL Register AC Characteristics, Product Term Clock
Symbol Parameter
-20
Units
Min Max
tCOA Clock to Output 20 ns
tCFA Clock to Feedback 10 16 ns
tSIA Input Setup Time 10 ns
tSFA Feedback Setup Time 8 ns
tHA Hold Time 10 ns
tWA Clock Width 11 ns
tPA Clock Period 22 ns
FMAXA
External Feedback 1/(tSIA + tCOA)33MHz
Internal Feedback 1/(tSFA + tCFA)38MHz
No Feedback 1/(tPS)45 MHz
tARA Asynchronous Reset/Preset Recovery Time 12 ns
17
ATF2500CL
0777G–12/01
STAND-BY ICC VS.
SUPPLY VOLTAGE (TA = 25°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
I
CC
(µA)
TBD
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
0.000
20.000
40.000
60.000
80.000
100.000
120.000
140.000
0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0
FREQUENCY (MHz)
I
CC
(mA)
TBD
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
-50
-40
-30
-20
-10
0
4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
I
OH
(mA)
TBD
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
0
0
0
1
1
1
4.04.55.05.56.0
SUPPLY VOLTAGE (V)
Iol (mA)
TBD
NORMALIZED ICC VS. TEMP
0.4
0.6
0.8
1.0
1.2
1.4
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED Icc
TBD
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
0.000
0.200
0.400
0.600
0.800
1.000
0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0
FREQUENCY (MHz)
I
CC
(mA)
TBD
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
VOH (V)
I
OH
(mA)
TBD
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
I
OL
(mA)
TBD
18 ATF2500CL
0777G–12/01
INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
-120
-100
-80
-60
-40
-20
0
0.0 -0.2 -0.4 -0.6 -0.8 -1.0
INPUT VOLTAGE (V)
INPUT
CURRENT (mA)
TBD
NORMALIZED TPD VS. VCC
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
PD
TBD
NORMALIZED TCO VS. VCC
0.8
0.9
1.0
1.1
1.2
1.3
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
CO
TBD
NORMALIZED TSU VS. VCC
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
SU
TBD
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0
0
0
1
1
1
0.0 1.0 2.0 3.0 4.0 5.0 6.0
INPUT VOLTAGE (V)
INPUT CURRENT
(uA)
TBD
NORMALIZED TCO VS. TEMP
0.8
0.9
1.0
1.1
-40.0 0.0 25.0 75.0
TEMPERATURE (V)
NORMALIZED T
CO
TBD
NORMALIZED TSU VS. TEMP
0.8
0.9
1.0
1.1
1.2
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED T
CO
TBD
NORMALIZED TSU VS. TEMP
0.8
0.9
1.0
1.1
1.2
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED T
CO
TBD
19
ATF2500CL
0777G–12/01
DELTA TPD VS.
OUTPUT LOADING
-2
0
2
4
6
8
0 50 100 150 200 250 300
OUTPUT LOADING (PF)
DELTA T
PD
(ns)
TBD
DELTA TPD VS. # OF OUTPUT SWITCHING
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
1.02.03.04.05.06.07.08.09.010.0
NUMBER OF OUTPUTS SWITCHING
DELTA T
PD
(ns)
TBD
DELTA TCO VS.
OUTPUT LOADING
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
50 100 150 200 250 300
NUMBER OF OUTPUTS LOADING
DELTA T
CO
(ns)
TBD
DELTA TCO VS. # OF OUTPUT SWITCHING
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
NUMBER OF OUTPUTS SWITCHING
DELTA T
PD
(ns)
TBD
20 ATF2500CQ
0777G–12/01
Note: 1. See ICC versus frequency characterization curves.
ATF2500CQ DC Characteristics
Symbol Parameter Condition Min Typ Max Units
IIL Input Load Current VIN = -0.1V to VCC + 1V 10 µA
ILO
Output Leakage
Current VOUT = -0.1V to VCC + 0.1V 10 µA
ICC
Power Supply
Current Standby
VCC = MAX,
VIN = GND or
VCC f = 0 MHz,
Outputs Open
ATF2500CQ
Com. 30 70 mA
Ind., Mil. 30 85 mA
IOS
Output Short
Circuit Current VOUT = 0.5V -120 mA
VIL Input Low Voltage MIN ≤ VCC ≤ MAX -0.6 0.8 V
VIH Input High Voltage 2.0 VCC + 0.75 V
VOL
Output Low
Voltage
VIN = VIH or VIL,
VCC = 4.5V
IOL = 8 mA Com., Ind. 0.5 V
IOL = 6 mA Mil. 0.5 V
VOH
Output High
Voltage VCC = MIN IOH = -100 µA VCC - 0.3 V
IOH = -4.0 mA 2.4
ATF2500CQ AC Characteristics
Symbol Parameter
-20
UnitsMin Max
tPD1 Input to Non-registered Output 20 ns
tPD2 Feedback to Non-registered Output 20 ns
tPD3 Input to Non-registered Feedback 15 ns
tPD4 Feedback to Non-registered Feedback 15 ns
tEA1 Input to Output Enable 20 ns
tER1 Input to Output Disable 20 ns
tEA2 Feedback to Output Enable 20 ns
tER2 Feedback to Output Disable 20 ns
tAW Asynchronous Reset Width 12 ns
tAP Asynchronous Reset to Registered Output 22 ns
tAPF Asynchronous Reset to Registered Feedback 19 ns
21
ATF2500CQ
0777G–12/01
ATF2500CQ Register AC Characteristics, Input Pin Clock
Symbol Parameter
-20
UnitsMin Max
tCOS Clock to Output 11 ns
tCFS Clock to Feedback 0 6 ns
tSIS Input Setup Time 14 ns
tSFS Feedback Setup Time 14 ns
tHS Hold Time 0 ns
tWS Clock Width 7 ns
tPS Clock Period 14 ns
FMAXS
External Feedback 1/(tSIS + tCOS)40MHz
Internal Feedback 1/(tSFS + tCFS)50MHz
No Feedback 1/(tPS)71MHz
tARS Asynchronous Reset/Preset Recovery Time 15 ns
ATF2500CQ Register AC Characteristics, Product Term Clock
Symbol Parameter
-20
UnitsMin Max
tCOA Clock to Output 20 ns
tCFA Clock to Feedback 10 16 ns
tSIA Input Setup Time 10 ns
tSFA Feedback Setup Time 8 ns
tHA Hold Time 10 ns
tWA Clock Width 11 ns
tPA Clock Period 22 ns
FMAXA
External Feedback 1/(tSIA + tCOA)33MHz
Internal Feedback 1/(tSFA + tCFA)38MHz
No Feedback 1/(tPS)45MHz
tARA Asynchronous Reset/Preset Recovery Time 12 ns
22 ATF2500CQ
0777G–12/01
STAND-BY ICC VS.
SUPPLY VOLTAGE (TA = 25°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
I
CC
(µA)
TBD
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
0.000
20.000
40.000
60.000
80.000
100.000
120.000
140.000
0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0
FREQUENCY (MHz )
I
CC
(mA)
TBD
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
-50
-40
-30
-20
-10
0
4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
I
OH
(mA)
TBD
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
0
0
0
1
1
1
4.04.55.05.56.0
SUPPLY VOLTAGE (V)
Iol (mA)
TBD
NORMALIZED ICC VS. TEMP
0.4
0.6
0.8
1.0
1.2
1.4
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED Icc
TBD
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
0.000
0.200
0.400
0.600
0.800
1.000
0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0
FREQUENCY (MHz)
I
CC
(mA)
TBD
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
VOH (V)
I
OH
(mA)
TBD
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
I
OL
(mA)
TBD
23
ATF2500CQ
0777G–12/01
INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
-120
-100
-80
-60
-40
-20
0
0.0 -0.2 -0.4 -0.6 -0.8 -1.0
INPUT VOLTAGE (V)
INPUT
CURRENT (mA)
TBD
NORMALIZED TPD VS. VCC
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
PD
TBD
NORMALIZED TCO VS. VCC
0.8
0.9
1.0
1.1
1.2
1.3
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
CO
TBD
NORMALIZED TSU VS. VCC
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
SU
TBD
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0
0
0
1
1
1
0.0 1.0 2.0 3.0 4.0 5.0 6.0
INPUT VOLTAGE (V)
INPUT CURRENT
(uA)
TBD
NORMALIZED TCO VS. TEMP
0.8
0.9
1.0
1.1
-40.0 0.0 25.0 75.0
TEMPERATURE (V)
NORMALIZED T
CO
TBD
NORMALIZED TCO VS. TEMP
0.8
0.9
1.0
1.1
-40.0 0.0 25.0 75.0
TEMPERATURE (V)
NORMALIZED T
CO
TBD
NORMALIZED TSU VS. TEMP
0.8
0.9
1.0
1.1
1.2
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED T
CO
TBD
24 ATF2500CQ
0777G–12/01
DELTA TPD VS.
OUTPUT LOADING
-2
0
2
4
6
8
0 50 100 150 200 250 300
OUTPUT LOADING (PF)
DELTA T
PD
(ns)
TBD
DELTA TPD VS. # OF OUTPUT SWITCHING
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
NUMBER OF OUTPUTS SWITCHING
DELTA T
PD
(ns)
TBD
DELTA TCO VS.
OUTPUT LOADING
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
50 100 150 200 250 300
NUMBER OF OUTPUTS LOADING
DELTA T
CO
(ns)
TBD
DELTA TCO VS. # OF OUTPUT SWITCHING
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
NUMBER OF OUTPUTS SWITCHING
DELTA T
PD
(ns)
TBD
25
ATF2500CQL
0777G–12/01
ATF2500CQL DC Characteristics
Symbol Parameter Condition Min Typ Max Units
IIL Input Load Current VIN = -0.1V to VCC + 1V 10 µA
ILO
Output Leakage
Current VOUT = -0.1V to VCC + 0.1V 10 µA
ICC
Power Supply
Current Standby
VCC = MAX,
VIN = GND or
VCC f = 0 MHz,
Outputs Open
ATF2500CQL
Com. 2 4 mA
Ind., Mil. 2 5 mA
IOS
Output Short
Circuit Current VOUT = 0.5V -120 mA
VIL Input Low Voltage MIN ≤ VCC ≤ MAX -0.6 0.8 V
VIH Input High Voltage 2.0 VCC + 0.75 V
VOL
Output Low
Voltage
VIN = VIH or VIL,
VCC = 4.5V
IOL = 8 mA Com., Ind. 0.5 V
IOL = 6 mA Mil. 0.5 V
VOH
Output High
Voltage VCC = MIN IOH = -100 µA VCC - 0.3 V
IOH = -4.0 mA 2.4
ATF2500CQL AC Characteristics
Symbol Parameter
-25
UnitsMin Max
tPD1 Input to Non-registered Output 25 ns
tPD2 Feedback to Non-registered Output 25 ns
tPD3 Input to Non-registered Feedback 18 ns
tPD4 Feedback to Non-registered Feedback 18 ns
tEA1 Input to Output Enable 25 ns
tER1 Input to Output Disable 25 ns
tEA2 Feedback to Output Enable 25 ns
tER2 Feedback to Output Disable 25 ns
tAW Asynchronous Reset Width 15 ns
tAP Asynchronous Reset to Registered Output 28 ns
tAPF Asynchronous Reset to Registered Feedback 25 ns
26 ATF2500CQL
0777G–12/01
ATF2500CQL Register AC Characteristics, Input Pin Clock
Symbol Parameter
-25
UnitsMin Max
tCOS Clock to Output 12 ns
tCFS Clock to Feedback 0 7 ns
tSIS Input Setup Time 20 ns
tSFS Feedback Setup Time 20 ns
tHS Hold Time 0ns
tWS Clock Width 8ns
tPS Clock Period 146 ns
FMAXS
External Feedback 1/(tSIS + tCOS)31MHz
Internal Feedback 1/(tSFS + tCFS)37MHz
No Feedback 1/(tPS)62 MHz
tARS Asynchronous Reset/Preset Recovery Time 20 ns
ATF2500CQL Register AC Characteristics, Product Term Clock
Symbol Parameter
-25
UnitsMin Max
tCOA Clock to Output 22 ns
tCFA Clock to Feedback 12 18 ns
tSIA Input Setup Time 15 ns
tSFA Feedback Setup Time 10 ns
tHA Hold Time 12 ns
tWA Clock Width 14 ns
tPA Clock Period 28 ns
FMAXA
External Feedback 1/(tSIA + tCOA)27MHz
Internal Feedback 1/(tSFA + tCFA)36MHz
No Feedback 1/(tPS)36 MHz
tARA Asynchronous Reset/Preset Recovery Time 15 ns
27
ATF2500CQL
0777G–12/01
STAND-BY ICC VS.
SUPPLY VOLTAGE (TA = 25°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
I
CC
(µA)
TBD
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
0.000
20.000
40.000
60.000
80.000
100.000
120.000
140.000
0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0
FREQUENCY
(
MHz
)
I
CC
(mA)
TBD
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
-50
-40
-30
-20
-10
0
4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
I
OH
(mA)
TBD
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
0
0
0
1
1
1
4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
Iol (mA)
TBD
NORMALIZED ICC VS. TEMP
0.4
0.6
0.8
1.0
1.2
1.4
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED Icc
TBD
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
0.000
0.200
0.400
0.600
0.800
1.000
0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0
FREQUENCY (MHz)
I
CC
(mA)
TBD
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
VOH (V)
I
OH
(mA)
TBD
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
I
OL
(mA)
TBD
28 ATF2500CQL
0777G–12/01
INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
-120
-100
-80
-60
-40
-20
0
0.0 -0.2 -0.4 -0.6 -0.8 -1.0
INPUT VOLTAGE (V)
INPUT
CURRENT (mA)
TBD
NORMALIZED TPD VS. VCC
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
PD
TBD
NORMALIZED TCO VS. VCC
0.8
0.9
1.0
1.1
1.2
1.3
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
CO
TBD
NORMALIZED TSU VS. VCC
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED T
SU
TBD
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0
0
0
1
1
1
0.0 1.0 2.0 3.0 4.0 5.0 6.0
INPUT VOLTAGE (V)
INPUT CURRENT
(uA)
TBD
NORMALIZED TPD VS. TEMP
0.8
0.9
1.0
1.1
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED T
PD
TBD
NORMALIZED TCO VS. TEMP
0.8
0.9
1.0
1.1
-40.0 0.0 25.0 75.0
TEMPERATURE (V)
NORMALIZED T
CO
TBD
NORMALIZED TSU VS. TEMP
0.8
0.9
1.0
1.1
1.2
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED T
CO
TBD
29
ATF2500CQL
0777G–12/01
DELTA TPD VS.
OUTPUT LOADING
-2
0
2
4
6
8
0 50 100 150 200 250 300
OUTPUT LOADING (PF)
DELTA T
PD
(ns)
TBD
DELTA TPD VS. # OF OUTPUT SWITCHING
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
NUMBER OF OUTPUTS SWITCHING
DELTA T
PD
(ns)
TBD
DELTA TCO VS.
OUTPUT LOADING
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
50 100 150 200 250 300
NUMBER OF OUTPUTS LOADING
DELTA T
CO
(ns)
TBD
DELTA TCO VS. # OF OUTPUT SWITCHING
0.0
0.2
0.4
0.6
0.8
1.0
1.02.03.04.05.06.07.08.09.010.0
NUMBER OF OUTPUTS SWITCHING
DELTA T
CO
(ns)
TBD
30 ATF2500CQL
0777G–12/01
Ordering Information
tPD
(ns)
tCOS
(ns)
Ext. fMAXS
(MHz) Ordering Code Package Operation Range
120 5.5 75 ATF2500C-10JC 44J Commercial
15 10 52 ATF2500C-15JC 44J Commercial
(0°C to 70°C)
ATF2500C-15JI 44J Industrial
(-40°C to 85°C)
ATF2500C-15KM/883
ATF2500C-15NM/883
44K
44L
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
5962 - 0152201M4X
5962 - 0152201M3X
44K
44L
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
20 11 40 ATF2500CL-20JC 44J Commercial
(0°C to 70°C)
ATF2500CL-20JI 44J Industrial
(-40°C to 85°C)
ATF2500CL-20KM/883
ATF2500CL-20NM/883
44K
44L
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
5962 - 0152202M4X
5962 - 0152202M3X
44K
44L
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
20 11 40 ATF2500CQ-20JC
ATF2500CQ-20PC
44J
40P6
Commercial
(0°C to 70°C)
ATF2500CQ-20JI
ATF2500CQ-20PI
44J
40P6
Industrial
(-40°C to 85°C)
ATF2500CQ-20GM/883
ATF2500CQ-20KM/883
ATF2500CQ-20NM/883
40D6
44K
44L
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
5962 - 0152203M2X
5962 - 0152203M4X
5962 - 0152203M3X
40D6
44K
44L
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
31
ATF2500CQL
0777G–12/01
Note: *SMD numbers are TBD.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and derate power by 30%.
25 12 31 ATF2500CQL-25JC
ATF2500CQL-25PC
44J
40P6
Commercial
(0°C to 70°C)
ATF2500CQL-25JI
ATF2500CQL-25PI
44J
40P6
Industrial
(-40°C to 85°C)
ATF2500CQL-25GM/883
ATF2500CQL-25KM/883
ATF2500CQL-25NM/883
40D6
44K
44L
Military/883C
(-55°C to 125°C)
Class B. Fully Compliant
5962 - 0152204M2X
5962 - 0152204M4X
5962 - 0152204M3X
40D6
44K
44L
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
Ordering Information (Continued)
tPD
(ns)
tCOS
(ns)
Ext. fMAXS
(MHz) Ordering Code Package Operation Range
Package Type
40D6 40-pin, 0.600" Wide, Ceramic, Dual Inline Package (Cerdip)
44J 44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
44K 44-lead, Ceramic J-leaded Chip Carrier (JLCC)
40P6 40-pin, 0.600" Wide, Plastic, Dual Inline Package OTP (PDIP)
44L 44-pad, Ceramic Leadless Chip Carrier (LCC)
32 ATF2500CQL
0777G–12/01
Packaging Information
40D6 – Cerdip
53.09(2.090)
51.82(2.040) PIN
1
15.49(0.610)
12.95(0.510)
0.127(0.005)MIN
1.78(0.070)
0.38(0.015)
0.66(0.026)
0.36(0.014)
1.65(0.065)
1.14(0.045)
15.70(0.620)
15.00(0.590)
17.80(0.700) MAX
0.46(0.018)
0.20(0.008)
2.54(0.100)BSC
5.08(0.200)
3.18(0.125)
SEATING
PLANE
5.72(0.225)
MAX
48.26(1.900) REF
0º~ 15º REF
Dimension in Millimeters and (Inches)
Controlling dimension: Inches
04/11/01
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
40D6, 40-lead (0.600" Wide), Non-windowed, Ceramic Dual Inline
Package (Cerdip) A
40D6
MIL-STD-1835 D-5 CONFIG A (Glass Sealed)
33
ATF2500CQL
0777G–12/01
44J – PLCC
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) B
44J
10/04/01
45˚ MAX (3X)
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 17.399 – 17.653
D1 16.510 – 16.662 Note 2
E 17.399 – 17.653
E1 16.510 – 16.662 Note 2
D2/E2 14.986 – 16.002
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
A
A1
B1 D2/E2
B
e
E1 E
D1
D
34 ATF2500CQL
0777G–12/01
44K – JLCC
SYMBOL MIN NOM MAX NOTE
A 3.93 4.36 4.57
2.28 2.66 3.04
A1
E
E1
16.38 16.63 16.89D1
D
A2 0.89 - 1.14
17.40 17.52 17.65
D2 15.00 15.50 16.00
1.14 X 45˚
0.89 X 45˚
.025(.635) RADIUS MAX (3X)
D
D1
E1 E
b
e
b1 E2
A2
A1
A
D2
E2
b
b1
c
17.40 17.52 17.65
16.38 16.63 16.89
15.00 15.50 16.00
e
1.27 TYP
0.66 0.73 0.81
0.43 - 0.58
0.15 - 0.30
C
Note : Refer to MIL-STD-1835C-J1
0.20 C
SEATING PLANE
c
COMMON DIMENSIONS
(Unit of Measure = mm)
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
09/18/01
44K, 44-lead, Non-windowed, Ceramic J-leaded Chip Carrier (JLCC)
A
44K
35
ATF2500CQL
0777G–12/01
40P6 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP) B
40P6
09/28/01
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
0º ~ 15º
D
e
eB
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A––4.826
A1 0.381 ––
D 52.070 –52.578 Note 2
E 15.240 –15.875
E1 13.462 –13.970 Note 2
B 0.356 –0.559
B1 1.041 –1.651
L 3.048 –3.556
C 0.203 – 0.381
eB 15.494 –17.526
e 2.540 TYP
Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
36 ATF2500CQL
0777G–12/01
44L – LCC
16.81(0.662)
16.26(0.640)
16.81(0.662)
16.26(0.640)
2.74(0.108)
2.16(0.085)
2.03(0.080)
1.40(0.055)
INDEX CORNER
0.635(0.025)
0.381(0.015) X 45˚
0.305(0.012)
0.178(0.007)RADIUS
0.737(0.029)
0.533(0.021)
1.02(0.040) X 45˚
PIN 1
1.40(0.055)
1.14(0.045)
2.41(0.095)
1.91(0.075)
2.16(0.085)
1.65(0.065)
12.70(0.500) BSC
1.27(0.050) TYP
12.70(0.500) BSC
Dimensions in Millimeters and (Inches)
Controlling dimension: Inches
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
44L, 44-pad (0.600" Wide), Non-windowed, Ceramic Lid, Leadless
Chip Carrier (LCC) A
44L
04/11/01
MIL-STD-1835 C-5
Printed on recycled paper.
© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
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0777G–12/01/0M