ICS843253AGI-45 REVISION A JULY 20, 2009 1 ©2009 Integrated Device Technology, Inc.
FemtoClock™ Crystal-to-3.3V LVPECL
Frequency Synthesizer
ICS843253I-45
General Description
The ICS843253I-45 is a two LVPECL output and
one LVCMOS output Synthesizer optimized to
generate Ethernet reference clock frequencies and
is a member of the HiPerClocks™ family of high
performance clock solutions from IDT. Using a
25MHz, 18pF parallel resonant crystal, the following frequencies
can be generated: 25MHz, 125MHz, and 156.25MHz. The
ICS843253I-45 uses IDT’s 3rd generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase jitter,
easily meeting Ethernet jitter requirements. The ICS843253I-45 is
packaged in a small 16-pin TSSOP package.
Features
•Two differential LVPECL output pairs and
one LVCMOS reference clock output
•Crystal oscillator interface designed for a 25MHz, 18pF parallel
resonant crystal
•A 25MHz crystal generates output frequencies of: 25MHz,
125MHz and 156.25MHz
•VCO frequency: 625MHz
•RMS Phase Jitter @ 156.25MHz, (1.875MHz – 20MHz) using a
25MHz crystal: 0.46ps (typical)
•Full 3.3V supply mode
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
Block Diagram
OSC Phase
Detector
VCO
625MHz
Feedback Divider
÷25
÷4
÷5
25MHz
QA
nQA
QB
nQB
REF_OUT
CLK_ENA
XTAL_IN
XTAL_OUT
CLK_ENB
Pullup
Pullup
Pin Assignment
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF_OUT
VCC
VCCA
VCCOA
nQA
QA
VEE
CLK_ENA CLK_ENB
VEE
QB
nQB
VCCOB
XTAL_IN
XTAL_OUT
V
EE
ICS843253I-45
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 2 ©2009 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Tables
Table 3A. CLK_ENA Function Table Table 3B. CLK_ENB Function Table
Number Name Type Description
1 CLK_ENA Input Pullup Output enable pin for QA/nQA outputs. LVCMOS/LVTTL interface levels.
See Table 3A.
2, 9, 15 VEE Power Negative supply pins.
3, 4 QA, nQA Output Differential output pair. LVPECL interface levels.
5V
CCOA Power Output supply pin for QA/nQA outputs.
6V
CCA Power Analog supply pin.
7V
CC Power Core supply pin.
8 REF_OUT Output Single-ended reference clock output. LVCMOS/LVTTL interface level.
20Ω typical output impedance.
10
11
XTAL_OUT
XTAL_IN Input Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
12 VCCOB Power Output supply pin for QB/nQB outputs.
13, 14 nQB, QB Output Differential output pair. LVPECL interface levels.
16 CLK_ENB Input Pullup Output enable pin for QB/nQB outputs. LVCMOS/LVTTL interface levels.
See Table 3B.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4pF
RPULLUP Input Pullup Resistor 51 kΩ
ROUT Output impedance REF_OUT 20 Ω
Input Outputs
CLK_ENA QA nQA
0LOWHIGH
1 (default) Active Active
Input Outputs
CLK_ENB QB nQB
0LOWHIGH
1 (default) Active Active
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 3 ©2009 Integrated Device Technology, Inc.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCOA = VCCOB = 3.3V ± 5%, TA = -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics,VCC = 3.3V ± 5%, TA = -40°C to 85°C
Item Rating
Supply Voltage, VCC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA 92.4°C/W (0 mps)
Storage Temperature, TSTG -65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 3.135 3.3 3.465 V
VCCA Analog Supply Voltage VCC – 0.12 3.3 VCC V
VCCOA,
VCCOB
Power Supply Voltage 3.135 3.3 3.465 V
ICCA Analog Supply Current 12 mA
IEE Power Supply Current 66 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 VCC + 0.3 V
VIL Input Low Voltage -0.3 0.8 V
IIH Input High Current CLK_ENA,
CLK_ENB VCC = VIN = 3.465V 5 µA
IIL Input Low Current CLK_ENA,
CLK_ENB VCC = 3.465V, VIN = 0V -150 µA
VOH Output High Voltage VCC = 3.465V, IOH = -12mA 2.6 V
VOL Output Low Voltage VCC = 3.465V, IOL = 12mA 0.5 V
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 4 ©2009 Integrated Device Technology, Inc.
Table 4C. LVPECL DC Characteristics, VCC = VCCOA = VCCOB = 3.3V ± 5%, TA = -40°C to 85°C
NOTE 1: Output termination with 50Ω to VCCOA,B – 2V.
Table 5. Crystal Characteristics
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = VCCOA = VCCOB = 3.3V ± 5%, TA = -40°C to 85°C
Using a 25MHz, 18pF quartz crystal.
NOTE 1: Please refer to the Phase Noise plots.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.9 V
VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.7 V
VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 25 MHz
Equivalent Series Resistance (ESR) 50 Ω
Shunt Capacitance 7pF
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency
QB/nQB 156.25 MHz
QA/nQA 125 MHz
REF_OUT 25 MHz
tjit(Ø) RMS Phase Jitter
(Random); NOTE 1
125MHz, Integration Range:
1.875MHz – 20MHz 0.44 ps
156.25MHz, Integration Range:
1.875MHz – 20MHz 0.57 ps
tR / tFOutput Rise/Fall Time QA, QB 20% to 80% 200 700 ps
REF_OUT 500 1400 ps
odc Output Duty Cycle QA, QB 48 52 %
REF_OUT 46 54 %
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 5 ©2009 Integrated Device Technology, Inc.
Typical Phase Noise at 125MHz
Typical Phase Noise at 156.25MHz
Ethernet Filter
Phase Noise Result by adding
an Ethernet filter to raw data
Raw Phase Noise Data
←
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.44ps (typical)
Noise Power dBc
Hz
Offset Frequency (Hz)
←
←
Ethernet Filter
Phase Noise Result by adding
an Ethernet filter to raw data
Raw Phase Noise Data
←
←
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.57ps (typical)
Noise Power dBc
Hz
Offset Frequency (Hz)
←
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 6 ©2009 Integrated Device Technology, Inc.
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
RMS Phase Jitter
LVCMOS Output Duty Cycle/Pulse Width/Period
3.3V LVCMOS Output Load AC Test Circuit
LVPECL Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
SCOPE
Qx
nQx
LVPECL
VEE
VCC,
2V
-1.3V± 0.165
VCCA
VCCOA,
VCCOB
2V
Phase Noise Mas
k
Offset Frequency
f1f2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
tPERIOD
tPW
tPERIOD
odc =
V
DD
2
x 100%
tPW
REF_OUT
SCOPE
Qx
LVCMOS
GND
1.65V±5
-1.65V±5
VCCA
VCC
1.65V±5
tPW
tPERIOD
tPW
tPERIOD
odc = x 100%
nQA, nQB
QA, QB
20%
80% 80%
20%
tRtF
VSWING
nQA, nQB
QA, QB,
REF_OUT
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 7 ©2009 Integrated Device Technology, Inc.
Application Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
LVCMOS Output
The unused LVCMOS output can be left floating. There should be no
trace attached.
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform- ance,
power supply isolation is required. The ICS843253I-45 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VCC, VCCA, VCCOA and VCCOB should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VCC pin and also shows that VCCA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VCCA pin.
Figure 1. Power Supply Filtering
Crystal Input Interface
The ICS843253I-45 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in Figure
2 below were determined using a 25MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum C1
and C2 values can be slightly adjusted for different board layouts.
Figure 2. Crystal Input Interface
VCC
VCCA
3.3V
10Ω
10µF.01µF
.01µF
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27p
C2
27p
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 8 ©2009 Integrated Device Technology, Inc.
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and R2
can be 100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination
XTAL_IN
XTAL_OUT
Ro Rs
Zo = Ro + Rs
50Ω0.1µf
R1
R2
V
CC
V
CC
3.3V
VCC - 2V
R1
50Ω
R2
50Ω
RTT
Zo = 50Ω
Zo = 50Ω
+
_
RTT = * Zo
1
((VOH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL Input
R1
84Ω
R2
84Ω
3.3V
R3
125Ω
R4
125Ω
Zo = 50Ω
Zo = 50Ω
LVPECL Input
3.3V
3.3V
+
_
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 9 ©2009 Integrated Device Technology, Inc.
Schematic Example
Figure 5 shows an example of ICS843253I-45 application schematic.
In this example, the device is operated at VCC = 3.3V. The 18pF
parallel resonant 25MHz is used. The C1= 27pF and C2 = 27pF are
recommended for frequency accuracy. For different board layout, the
C1 and C2 may be slightly adjusted for optimizing frequency accuacy.
Two examples of LVPECL terminations and one example of LVCMOS
are shown in this schematic. Additional termination approaches are
shown in the LVPECL Termination Application Note.
Figure 5. ICS843253I-45 Schematic Layout
Zo = 50
VCCOB
3.3V
VCC=3.3V
nQB
CLK_ENB
Logic Input Pin Examples
18pF
VCC
VCC
U1
ICS843253I_45
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
CLK_ENA
VEE
QA
nQA
VCCOA
VCCA
VCC
REF_OUT VEE
XTAL _O U T
XTAL _I N
VCCOB
nQB
QB
VEE
CLK_ENB
RU2
Not Install
RD2
1K
C1
27pF
Optional
LVPECL
Y-Termination
RU1
1K
To Logic
Input
pins
R9
33
R6
50
Set Logic
Input to
'0'
VCCOA=3.3V
R7
50
C70.1u
nQA
Receiver
+
-
Set Logic
Input to
'1'
VCC
R1
133
+
-
C60.1u
C3
0.1u
To Logic
Input
pins
25MHz
QA
X1
C2
27pF
VCCOB=3.3V
R8
50
R4
82.5
C5
10u
C4
0.1u
R2
133
TL1
Zo = 50 Ohm
Zo = 50 Ohm
RD1
Not Install
CLK_ENA
VCC
REF_OUT
Zo = 50 Ohm
R3
82.5
VCCOA QB
VCCA
TL2
Zo = 50 Ohm
R5
10
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 10 ©2009 Integrated Device Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS843253I-45.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843253I-45 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 66mA = 228.7mW
• Power (LVPECL outputs)MAX = 30mW/Loaded Output pair
• Power (LVPECL output) = 2 * 30mW = 60mW
LVCMOS Output Power Dissipation
• Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2
Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 20Ω)] = 24.75mA
• Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 20Ω * (24.75mA)2 = 12.25mW per output
Total Power Dissipation
•Total Power
= Power (core) + Power (LVPECL output) + Power (ROUT)
= 228.7mW + 60mW + 12.25mW = 301.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 92.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.301W * 92.4°C/W = 112.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board.
Table 7. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 92.4°C/W 88.0°C/W 85.9°C/W
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 11 ©2009 Integrated Device Technology, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
VCC – 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
• For logic low, VOUT = VOL_MAX = VCO_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
VOUT
VCCO
VCCO - 2V
Q1
RL
50Ω
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 12 ©2009 Integrated Device Technology, Inc.
Reliability Information
Table 8. θJA vs. Air Flow Table for a 16 Lead TSSOP
Transistor Count
The transistor count for ICS843253I-45 is: 2042
Package Outline and Package Dimensions
Package Outline - G Suffix for 16-Lead TSSOP Table 9. Package Dimensions for 16 Lead TSSOP
Reference Document: JEDEC Publication 95, MO-153
θJA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 92.4°C/W 88.0°C/W 85.9°C/W
All Dimensions in Millimeters
Symbol Minimum Maximum
N16
A1.20
A1 0.05 0.15
A2 0.80 1.05
b0.19 0.30
c0.09 0.20
D4.90 5.10
E6.40 Basic
E1 4.30 4.50
e0.65 Basic
L0.45 0.75
α0° 8°
aaa 0.10
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 13 ©2009 Integrated Device Technology, Inc.
Ordering Information
Table 10. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
843253AGI-45LF 253AI45L “Lead-Free” 16 Lead TSSOP Tube -40°C to 85°C
843253AGI-45LFT 253AI45L “Lead-Free” 16 Lead TSSOP 2500 Tape & Reel -40°C to 85°C
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843253AGI-45 REVISION A JULY 20, 2009 14 ©2009 Integrated Device Technology, Inc.
Revision History Sheet
Rev Table Page Description of Change Date
AT10
8
13
Updated Figures 4A & 4B.
Ordering Information Table - corrected marking. 7/20/09
ICS843253I-45 FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2009. All rights reserved.
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