CY2XF24
High Performance L VPECL Oscillator with
Frequency Margining – I2C Control
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-53146 Rev . *H Revised January 23, 2013
Features
■Low jitter crystal oscillator (XO)
■Less than 1 ps typical root mean square (RMS) phase jitter
■Differential low-voltage positive emitter coupled logic
(LVPECL) output
■Output frequency from 50 MHz to 690 MHz
■Frequency margining through I2C bus
■Factory-configured or field-programmable
■Integrated phase-locked loop (PLL)
■Pb-free package: 5.0 × 3.2 mm leadless chip carrier (LCC)
■Supply voltage: 3.3 V or 2.5 V
■Commercial and industrial temperature ranges
Functional Description
The CY2XF24 is a high-performance and high-frequency XO. It
uses a Cypress-proprietary low-noise PLL to synthesize the
frequency from an integrated crystal. The output frequency can
be changed using the I2C bus serial interface, allowing easy
frequency margin testing in applications.
The CY2XF24 is available as a factory-configured device or as
a field-programmable device. Factory-configured devices are
configured for general use (see “S tandard and
Application-Specific Factory Configurations” on page 4) or they
can be customer speci fi c.
Logic Block Diagram
PROGRAMMABLE
CONFIGURATION
OUTPUT
DIVIDER
1
SDA
CRYSTAL
OSCILLATOR LOW-NOISE
PLL
4
CLK
5
CLK#
2
SCL
I2C
INTERFACE
CY2XF24
Document Number: 001-53146 Rev. *H Page 2 of 17
Pinouts
Figure 1. Pin Diagram – 6-pin Ceramic LCC
1
3
SDA
VSS
VDD
CLK
6
4
25CLK#SCLK
Table 1. Pin Definitions
Pin Name I/O Type Description
1SDA I/OI
2C serial data
2 SCLK CMOS input I2C serial clock
4, 5 CLK, CLK# LVPECL output Differential output clock
6V
DD Power Supply voltage: 2.5 V or 3.3 V
3V
SS Power Ground
CY2XF24
Document Number: 001-53146 Rev. *H Page 3 of 17
Contents
Standard and Application-Spec ific
Factory Configurations ....................................................4
Functional Description ................... ... .............. ... .. ............4
Configuration Software ....................................................4
Programming Description ...............................................4
Field-Programmable CY2XF24F .................................4
Factory-Configured CY2XF24 .....................................5
Programming Variables ...................................................5
Output Frequencies .....................................................5
Industrial versus Commercial Device Performance ....5
Memory Map ......................... .............. ... .............. ..............5
Serial Interface Protocol and Timing ........................ ...5
Device Address ...........................................................5
Data Valid .................................. ... .............. ... ..............5
Data Frame .................... .............. ... .............. .. ............6
Acknowledge Pulse .....................................................6
Write Operations ................................ ... .............. .. ............6
Writing Individual Bytes ...............................................6
Writing Multiple Bytes ..................................................6
Read Operations ................................ ... .............. .. ............6
Current Address Read .................................................6
Random Read .............................................................6
Sequential Read ..........................................................6
Absolute Maximum Conditions .......................................8
Operating Conditions .......................................................8
DC Electrical Characteristics ............ ... ................. ..........8
AC Electrical Characteristics ..........................................9
I2C Bus Timing Specifications ......................................10
Typical Output Characteristics ............ ................. ........10
Measurement Definitions ...............................................12
Termination Circuits ....... ... .............. ... ... .............. ... ........12
Ordering Information ......................................................13
Possible Configurations ........... ............................. .. ...13
Package Drawings and Dimensions .............................14
Acronyms ........................................................................ 15
Document Conventions ............. .............. ... .............. .. ...15
Units of Measure ..................... ............... .. ... ..............15
Document History Page ............... ............... .. ... ..............16
Sales, Solutions, and Legal Information ......................17
Worldwide Sales and Design Support .......................17
Products .................................................................... 17
PSoC Solutions ................................ ... ... .............. .. ...17
CY2XF24
Document Number: 001-53146 Rev. *H Page 4 of 17
Functional Description
The CY2XF24 is a PLL-based high-performance clock
generator. It uses an internal crystal oscillator as a reference,
and outputs one differential LVPECL clock. It has an I2C bus
serial interface[1], which is used to change the output frequency.
The CY2XF24 comes configured for four different frequencies.
At power-on, the four configurations are transparently loaded
into an internal volatile memory which, in turn, controls the PLL.
You can switch between the four frequencies through the I2C
bus. You can also configure the CY2XF24 with new output
frequencies by shifting new data into the internal memory.
Frequency margining is a common application for this feature.
One frequency is used for the standard operating mode of the
device, while additional frequencies are available for margin
testing, either during product development or in-system
manufacturing test.
Note that all configuration changes made using I2C are
temporary and are lost when power is removed from the device.
At power-on, the device returns to its original state.
The configuration for a particular frequency is stored in a 6-byte
block of memory, known as a word. The CY2XF24 has four such
words, labeled ‘Frequency Word 0’ through ‘Frequency Word 3’.
An additional register byte contains a 2-bit field, which selects
one of the four frequen cy words. By writing to this Select Byte,
you can switch back and forth between the four programmed
frequencies. The select byte can be configured to select any of
the four frequency words at power-on.
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency
excursions beyond the start frequency and the new frequency.
Glitches and runt pulses are possible, and time must be allowed
for the PLL to relock.
If more than four frequencies are needed, the I2C bus can be
used to change any of the four frequency words. When writing
frequency words through I2C, you should not change the
currently selected word. Instead, write one of the three
unselected words before changing the select byte to select th at
new word.
Figure 2 shows how the frequency words are arranged and
selected.
Figure 2. Frequency Words
Configuration Software
Cypress provides CyClockWizard™ software that enables the
users to create data values for shifting into the frequency words.
This software is required because the algorithm is too compli-
cated to be described here.
The user specifies the output frequency. The software then
calculates the bit stream for up to four frequency words, as
outlined by the register addresses for each word seen in
Figure 2.
Programming Description
The CY2XF24 is a programmable device. Before being used in
an application, it must be programmed with the output
frequencies and other variables described in Programming
Variables on page 5. Two different device types are available,
each with its own programming flow. They are described in the
following section.
Field-Programmable CY2 XF24F
Field programmable devices are shipped unprogrammed and
must be programmed before being installed on a printed circuit
board (PCB). Customers use CyClockWizard™ Software to
specify the device configuration and generate a joint electron
devices engineering council (JEDEC - extension .jed)
programming file. Programming of samples and prototype
quantities is availabl e using the CyClockWizard software along
with a CY3675-CLKMAKER1 CyClockMaker Clock Programm er
Kit with a CY3675-LCC6A socket adapter. Cypress’s value
added distribution partners also prov ide programming services.
Field programmable devices are designated with an ‘F’ in the
part number. They are intended for quick prototyping and
inventory reduction. The software and programmer kit hardware
can be downloaded from www.cypress.com by clicking the
hyperlinks above.
Standard and Application-Specific Factory Configurations
Part Number Output Frequency Frequency Word RMS Phase Jitter (Random)
Offset Range Jitter (Typical)
CY2XF24LXI009T 100 MHz (default)
156.25 MHz
350 MHz
400 MHz
0
1
2
3
12 kHz to 20 MHz
12 kHz to 20 MHz
12 kHz to 20 MHz
12 kHz to 20 MHz
0.85 ps
0.76 ps
0.71 ps
0.69 ps
10h – 15h Freque nc y W o rd 0
PLL
Freque nc y W o rd 1
Freque nc y W o rd 2
Freque nc y W o rd 3
16h – 1Bh
1Ch – 21h
22h – 27h
Select Byte40h
00
01
10
11
Bits [1:0]
Register
Address
Sel
Control
Note
1. The serial interface i s I2C Bus compliant, with the following exceptions: SDA input leakage current, SDA input capacitance, SDA and SCLK are clamped
to VDD, setup time, and output hold time.
CY2XF24
Document Number: 001-53146 Rev. *H Page 5 of 17
Factory-Configured CY2XF24
For ready-to-use devices, the CY2XF24 is available with no field
programming required. Pre-configured devices (see “Standard
and Application-S pecific Factory Configurations” on page 4) are
available for samples or orders, or a request for a custom config-
uration can be made. All requests are submitted to the local
Cypress field application engineer (F AE) or sales representative.
After the request is processed, the user receives a new part
number, samples, and datasheet with the programmed values.
This part number is used for additional sample requests and
production orders. The CY2XF24 is one-time programmable
(OTP).
Programming Variables
Output Frequencies
The CY2XF24 is programmed with up to four independent output
frequencies, which are then selected using the I2C interface. The
device can synthesize frequencies to a resolution of 1 part per
million (ppm), but the actual accuracy of the output frequency is
limited by the accuracy of the integrated reference crystal.
The CY2XF24 has an output frequency range of 50 MHz to
690 MHz, but the range is not continuous. The CY2XF24 cannot
generate frequencies in the ranges of 521 MHz to 529 MHz, and
596 MHz to 617 MHz.
Industrial versus Commercial Device Performance
Industrial and commercial devices have different internal
crystals. They have a potentially significant impact on
performance levels for applications requiring the lowest possible
phase noise. CyClockWIzard software allows the user to select
between and view the expected performance of both options.
Memory Map
Five fields can be written through the I2C bus. Four frequency
words define the output frequency . As shown in Table 3, each of
these words is a 6-byte field. When writing to a frequency word,
all six bytes should be written. They may be written either as
individual byte writes, or as a block write. The currently selected
frequency word should not be written to. All four words are
symmetrical, meaning that a 6-byte value that is valid for one
word is also valid for any of the other words, and produce the
same frequency.
The fifth field is the select byte, located at byte address 40h. The
value written into the two least significant bits determines the
active frequency word. The other bits of the byte are reserved
and must be written with the values indicated in the table.
The users shoul d never w r it e to an y ad dre ss ot her than the
25 bytes describ e d here .
Serial Interface Protocol and Timing
The CY2XF24 uses pins SDA and SCLK for an I2C bus that
operates up to 100 kbits/sec in read or write mode. The
CY2XF24 is always a slave on this bus, meaning that it never
initiates a bus transaction. The basic write protocol is as follows:
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; and so on, until STOP Bit. The basic serial format
is illustrated in Figure 4 on page 7.
Device Address
The device I2C address is a 7-bit value. The default I2C address,
which appears in CyClockWizard is 69H, which can be changed
to any other value while generating configuration using
CyClockWizard. Note that the Field Programmable
(unprogrammed[2]) devices has default address as 59H.
Data Valid
Data is valid when the clock is HIGH, and may only be
transitioned when th e clock is LOW as illustrated in Fi gure 5 on
page 7.
Table 2. Device Programming Variables
Variable
Output frequency 0
Output frequency 1
Output frequency 2
Output frequency 3
Temperature range (commercial or industrial)
Table 3. Fr equency Words
Frequency
Word Byte Addresses
(hex) Word Select
(Select Byte 40h)
0 10h to 15h 00
1 16h to 1Bh 01
2 1Ch to 21h 10
3 22h to 27h 11
Table 4. Register 40h: Select Byte
Bits Default
Value
(binary) Name Description
7:2 000000 Reserved Reserved. Always write this value
1:0 User-
defined Word
Select Selects the Frequency Word to
determine the output frequency.
00 selects Wo rd 0; 01 select s
Word 1; 10 selects Word 2; 11
selects Word 3
Note
2. Field programmable devices are shi pped unprogrammed and must be pro grammed before being inst alled on a PCB. An unpro grammed device will output the cryst al
frequency of the integrated cryst al (25 MHz for commercial and 38.8 MHz for industrial).
CY2XF24
Document Number: 001-53146 Rev. *H Page 6 of 17
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 6 on page 7.
START sequence - Start frame is indicated by SDA going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
STOP sequence - Stop frame is indicated by SDA going HIGH
when SCLK is HIGH. A stop frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Acknowledge Pulse
During write mode, the CY2XF24 responds with an
Acknowledge (ACK) pulse after every eight bits. This is
accomplished by pulling the SDA line LOW during the N*9th clock
cycle as illustrated in Figure 7 on page 8. (N = the number of
bytes transmitted). After the data packet is sent during read
mode, the master generates the acknowledge.
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master , which is followed
by an acknowledge bit from the slave (SDA = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (SDA = 0/LOW), and the master must end the
write sequence with a STOP condition.
Writing Multiple Bytes
To write more than one byte at a time, the master does not end
the write sequence with a stop condition. Instead, the master can
send multiple contiguous bytes of data to be stored. After each
byte, the slave responds with an ac knowledge bit, just li ke after
the first byte, and accept data until the acknowledge bit is
responded to by the STOP condition. When receiving multiple
bytes, the CY2XF24 internally increments the register address.
Read Operations
Read operations are initi ated the same way as write op erations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Current Address Read
The CY2XF24 has an onboard address counter that retains 1
more than the ad dress of the last word access. If the last word
written or read was word ‘n’, then a current address read
operation would re turn the value stored in locatio n ‘n+1’. When
the CY2XF24 receives the slave address with the R/W bit set to
a ‘1’, the CY2XF24 issues an acknowledge and transmits the
8-bit word. The master device does not acknowledge the
transfer , but does generate a STOP condition, which causes the
CY2XF24 to stop transmission.
Random Read
Through random read operations, the master may access any
memory location. To perform this type of read operation, first the
word address must be set. This is accomplished by sending the
address to the CY2XF24 as part of a write operation. After the
word address is sent, the master genera tes a START condition
following the acknowledge. This terminates the write operation
before any data is stored in the address, but not before the
internal address pointer is set. Next the master reissues the
control byte with the R/W byte set to ‘1’. The CY2XF24 then
issues an acknowledge and transmits the 8-bit word. The master
device does not acknowledge the tra nsfer, but does generate a
STOP condition which causes the CY2XF24 to stop
transmission.
Sequential Read
Sequential read operatio ns follo w the same process a s rand om
reads except that the master issues an acknowledge instea d of
a STOP condition after transmission of the first 8-bit data word.
This action results in an incrementing of the internal address
pointer, and subsequently output of the next 8-bit data word. By
continuing to issue acknowledges instead of STOP conditions,
the master may serially read the entire contents of the slave
device memory. When the internal address po inter poin ts to the
FFh register, after the next increment, the pointer points to the
00h register.
Figure 3. Data Transfer Sequence on the Serial Bus
CY2XF24
Document Number: 001-53146 Rev. *H Page 7 of 17
Figure 4. Data Frame Architecture
Figure 5. Data Valid and Data Transition Periods
Figure 6. Start and Stop Frame
SDA
SCLK
START Transition
to next Bit STOP
CY2XF24
Document Number: 001-53146 Rev. *H Page 8 of 17
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)
SDA
SCLK
DA6 DA5 DA0 R/W ACK RA7 RA6 RA1 RA0 ACK STOP
START ACK D7 D6 D1 D0
+++
+++
Notes
3. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
4. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The int e rn a l laye rs
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
5. IDD includes ~24 mA of current that is dissipated externally in the output termination resistors.
Absolute Maximum Conditions
Parameter Description Condition Min Max Unit
VDD Supply voltage –0.5 4.4 V
VIN[3] Input voltage, DC Relative to VSS –0.5 VDD+0.5 V
TSTemperature, storage Non Operating –55 135 °C
TJTemperature, junction –40 135 °C
ESDHBM Electrostatic discharge (ESD) protection
human body model (HBM) JEDEC STD 22 -A114-B 2000 – V
JA[4] Thermal resistance, junction to ambient 0 m/s airflow 64 °C/W
Operating Conditions
Parameter Description Min Typ Max Unit
VDD 3.3-V supply voltage range 3.135 3.3 3.465 V
2.5-V supply voltage range 2.375 2.5 2.625 V
TPU Power-up time for VDD to reach minimum specified voltage (power ramp is
monotonic) 0.05 – 500 ms
TAAmbient temperature (commercial) 0 – 70 °C
Ambient temperature (industrial) –40 – 85 °C
DC Electrical Characteristics
Parameter Description Condition Min Typ Max Unit
IDD[5] Operating supply current VDD = 3.465 V, CLK = 150 MHz, output
terminated – – 150 mA
VDD = 2.625 V, CLK = 150 MHz, output
terminated – – 145 mA
VOH LVPECL high output voltage VDD = 3.3 V or 2.5 V, RTERM = 50 to
VDD – 2.0 V VDD – 1.15 – VDD –
0.75 V
VOL LVPECL low output voltage VDD = 3.3 V or 2.5 V, RTERM = 50 to
VDD – 2.0 V VDD – 2.0 – VDD –
1.625 V
VOD1 LVPECL output voltage swing
(VOH - VOL)VDD = 3.3 V or 2.5 V, RTERM = 50 to
VDD – 2.0 V 600 – 1000 mV
VOD2 LVPECL output voltage swing
(VOH - VOL)VDD = 2.5 V, RTERM = 50 to VDD –
1.5 V 500 – 1000 mV
VOCM LVPECL output common mode
voltage (VOH + VOL)/2 VDD = 2.5 V, RTERM = 50 to VDD –
1.5 V 1.2 – – V
CY2XF24
Document Number: 001-53146 Rev. *H Page 9 of 17
VOLS Output low voltage (SDA) IOL = 4 mA – – 0.1*VDD V
VIH Input high voltage 0.7*VDD –– V
VIL Input low voltage – – 0.3*VDD V
IIH0 Input high current (SDA) Input = VDD ––115A
IIH1 Input high current (SCLK) Input = VDD ––10A
IIL0 Input low current (SDA) Input = VSS –50 – – A
IIL1 Input low current (SCLK) Input = VSS –20 – – A
CIN0[6] Input capacitance (SDA) – 15 – pF
CIN1[6] Input capacitance (SCLK) – 4 – pF
DC Electrical Characteristics (continued)
Parameter Description Condition Min Typ Max Unit
Notes
6. Not 100% tested, guaranteed by design and characterization.
7. This parameter is specified in CyClockMaker software.
8. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage.
9. Typical phase noise specs for factory programmed devices are listed in the table “Standard and Application-Specific Factory Configurations” on page 4 .
AC Electrical Characteristics[6]
Parameter Description Condition Min Typ Max Unit
FOUT Output frequency[7] 50 – 690 MHz
FSC Frequency stability, commercial
devices[8] TA = 0 °C to 70 °C – – ±35 ppm
FSI Frequency stability, industrial
devices[8] TA = –40 °C to 85 °C – – ±55 ppm
AG Aging, 10 years – – ±15 ppm
TDC Output duty cycle F <= 450 MHz, measured at zero
crossing 45 50 55 %
F > 450 MHz, measured at zero
crossing 40 50 60 %
TR, TFOutput rise and fall time 20% and 80% of full output swing 0.2 0.4 1.0 ns
TLOCK Startup time Time for CLK to reach valid frequency
measured from the time VDD =
VDD(min)
––10ms
TLSER Relock time Time for CLK to reach valid frequency
from serial bus change to select bits in
register 40h, measured from I2C STOP
––10ms
TJitter()RMS phase jitter (random) FOUT = 106.25 MHz (12 kHz to 20 MHz) – 1 – ps
Pre-defined factory configurations[9] See Note 9 ps
CY2XF24
Document Number: 001-53146 Rev. *H Page 10 of 17
Typical Ou tput Characteristics
Figure 8. 2.5-V Supply and Termination to VDD–1.5 V, minimum VDD and maximum TA
I2C Bus Timing Specifications
The I2C Bus Timing Speci fi c ations for part CY2XF24 are as follows [10]
Parameter Description Min Max Unit
fSCLK SCLK frequency – 100 kHz
tHD:STA Start mode time from SDA LOW to SCLK LOW 4 – s
tLOW SCLK LOW period 4.7 – s
tHIGH SCLK HIGH period 4–s
tSU:DAT Input data setup (SDA transition to SCLK rising edge) 1000 – ns
tHD:DAT Input data hold (SCLK falling edge to SDA transition) 0 – ns
tHD:DO Output data hold (SCLK falling edge to SDA transiti on) 200 – ns
tSR Rise time of SCLK and SDA – 300 ns
tSF Fall time of SCLK and SDA – 300 ns
tSU:STO Stop mode time from SCLK HIGH to SDA HIGH 4 – s
tBUF Stop mode to Start mode 4.7 – s
1.20
1.25
1.30
1.35
1.40
0 100 200 300 400 500 600 700
F requency (MHz)
VOCM (V)
0.4
0.5
0.6
0.7
0.8
0.9
0 100 200 300 400 500 600 700
F r equency (MHz)
Swing (V)
Note
10.Not 100% tested, guaranteed by design and characterization.
CY2XF24
Document Number: 001-53146 Rev. *H Page 11 of 17
Figure 9. 2.5-V Sup ply and Termination to VDD–2 V, minimum VDD and maximum TA
Figure 10. 3.3-V Supply and Termination to VDD–2 V, minimum VDD and maximum TA
0.70
0.75
0.80
0.85
0.90
0 100 200 300 400 500 600 700
F requency (MHz)
VOCM (V)
0.4
0.5
0.6
0.7
0.8
0.9
0 100 200 300 400 500 600 700
F reque n cy (MHz)
Swing (V)
0.4
0.5
0.6
0.7
0.8
0.9
0 100 200 300 400 500 600 700
Frequency (MHz)
Swing (V)
1.40
1.45
1.50
1.55
1.60
0 100 200 300 400 500 600 700
Frequency (MHz)
VOCM (V )
CY2XF24
Document Number: 001-53146 Rev. *H Page 12 of 17
Measurement Definitions
Figure 11. Output DC Parameters
Figure 12. Duty Cycle Timing
Figure 13. Outp ut Rise an d Fa ll Time
Termination Circuits
Figure 14. LVPECL Termination
CLK VA
VB
CLK# VOD VOCM = (VA + VB)/2
CLK
TPW
TPERIOD
TDC = TPW
TPERIOD
CLK#
20%
80%
TR
CLK 20%
80%
CLK#
TF
CLK#



BUF
CLK 
VDD - 2V
(VD D = 3.3V )
CLK#



BUF
CLK 
VDD - 2V or VDD - 1.5V
(VDD = 2.5V)
CY2XF24
Document Number: 001-53146 Rev. *H Page 13 of 17
Some product offerings are factory-programmed customer-specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales
representative for more information.
Possible Configurations
Ordering Code Definitions
Ordering Information
Part Number Configuration Package Description Product Flow
Pb-free
CY2XF24FLXCT Field-programmable 6-pin ceramic LCC surface mount device
(SMD) - tape and reel Commercial, 0 °C to 70 °C
CY2XF24FLXIT Field-programmable 6-pin ceramic LCC SMD - tape and reel Industrial, –40 °C to 85 °C
CY2XF24LXI009T[11] Factory-Configured 6-pin ceramic LCC SMD - tape and reel Industrial, –40 °C to 85 °C
Part Number[12] Configuration Package Description Product Flow
Pb-free
CY2XF24LXCxxxT Factory-configured 6-pin ceramic LCC SMD - tape and reel Commercial, 0 °C to 70 °C
CY2XF24LXIxxxT Factory-configured 6-pin ceramic LCC SMD - tape and reel Industrial, –40 °C to 85 °C
CY
Base part number
2XF24
Company ID : CY = Cypress
F
Field programmable device
6-pin LCC package
LX C/I
C = Commercial
I = Industrial
T
Tape and Reel
XXX
Custom part configuration code
Notes
11. Device configuration details are described in the ta ble “Standard and Application-Specific Factory Configurations” on page 4.
12.“xxx” indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or Sales Representative.
CY2XF24
Document Number: 001-53146 Rev. *H Page 14 of 17
Package Drawings and Dimensions
Figure 15. 6-Pin 3.2 × 5.0 mm Ceramic LCC LZ06A
.
001-10044 *B
CY2XF24
Document Number: 001-53146 Rev. *H Page 15 of 17
Acronyms Document Conventions
Units of Measure
Table 5. Acronyms Used in this Document
Acronym Description
ESD electrostatic discharge
FAE field application engineer
HBM human body model
JEDEC joint electron devices engineering council
LCC leadless chip carrier
LVDS Low-voltage differential signaling
OE output enable
PCB printed circuit board
PLL phase-locked loop
RMS root mean square
XO crystal oscillator
Symbol Unit of Measure
% percent
°C degree Celsius
kHz kilohertz
mA milliampere
MHz megahertz
mm millimeter
ms millisecond
mV millivolt
ns nanosecond
pF picofarad
ppm parts per million
ps picosecond
Vvolt
ohms
Wwatt
µA microampere
µs microsecond
CY2XF24
Document Number: 001-53146 Rev. *H Page 16 of 17
Document History Page
Document Title: CY2XF24 High Performance LVPECL Oscillator with Frequency Margining – I2C Control
Document Number: 001-53146
Revision ECN Orig. of
Change Submission
Date Description of Change
** 2704379 KVM/PYRS 05/11/09 New datasheet
*A 2718898 WWZ 06/15/09 Minor ECN to post datasheet to external web
*B 2761926 KVM 09/10/09 Revised maximum output rise and fall times
*C 2896548 KVM 03/19/10 Moved parts with ‘xxx’ into new table, Possible Configura ti ons
Updated package diagram
*D 2973338 CXQ 07/08/10 Added Standard and Application-Specific Factory Configurations table on
page 2.
Added phase jitter specs for pre-defined configurations into the AC Electrical
S pecifications table (note 8 refers users to the new table on page 2 for typical
specs).
Added CY2XF24LXI625T device to the Ordering Information table and added
note 9 to reference the configuration description of the new device.
Changed all references to CyberClocksOnline software to CyClockWizard.
Removed section on phase noise vs jitter SW optimization.
Changed description of Word Select feature from default Word 0 to
user-defined.
*E 3183855 BASH 05/06/11 Updated template as per current Cypress standards.
Added Units table.
Changed status from Preliminary to Final.
*F 3373963 PURU 09/21/11 Updated S t andard and Application-S pecific Factory Configurations on page 4
and Package Drawings and Dimensions on page 14.
Added new MPN CY2XF24LXI009T.
*G 3514245 PURU 02/01/2012 Updated Device Address and added note 2.
Updated Package Drawings and Dimensions.
*H 3847770 AJU 01/23/2013 Updated Standard and Application-Specific Factory Configurations:
Removed CY2XF24LXI625T related information.
Updated Ordering Information:
Removed prune part CY2XF24LXI625T.
Document Number: 001-53146 Rev. *H Revised January 23, 2013 Page 17 of 17
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CY2XF24
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