MB3793-42 Power-Voltage Monitoring IC with Watchdog Timer Description The MB3793 is an integrated circuit to monitor power voltage; it incorporates a watchdog timer. A reset signal is output when the power is cut or falls abruptly. When the power recovers normally after resetting, a power-on reset signal is output to microprocessor units (MPUs). An internal watchdog timer with two inputs for system operation diagnosis can provide a fail-safe function for various application systems. The model number and package code are as shown below. Model No. Marking Code Detection Voltage MB3793-42 3793-A 4.2 V Features Precise detection of power voltage fall: 2.5% Detection voltage with hysteresis Low power dispersion: ICC = 27 A (reference) Internal dual-input watchdog timer Watchdog timer halt function (by inhibition terminal) Independently-set watchdog and reset times Mask option for detection voltage (4.9 to 2.4 V, 0.1-V steps) Two types of packages (SOP-8pin: 2 types) Application Arcade Amusement etc. Cypress Semiconductor Corporation Document Number: 002-08515 Rev. *C * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised June 28, 2017 MB3793-42 Contents Description ...............................................................1 Features ...................................................................1 Application ...............................................................1 8.4 Inhibition operation (Positive clock pulse) ..12 8.5 Clock pulse input (Positive clock pulse) .....13 8.6 Inhibition input rising and falling time .........13 1. PIN ASSIGNMENT ..............................................3 9. OPERATION SEQUENCE .................................14 2. PIN DESCRIPTION ..............................................3 10. TYPICAL CHARACTERISTICS ......................15 3. BLOCK DIAGRAM ..............................................4 11. STANDARD CONNECTION ............................18 4. BLOCK FUNCTIONS ...........................................5 12. APPLICATION EXAMPLE ..............................19 12.1 Monitoring Single Clock ...........................19 12.2 Watchdog Timer Stopping .......................19 5. ABSOLUTE MAXIMUM RATINGS ......................6 6. RECOMMENDED OPERATING CONDITIONS ..6 7. ELECTRICAL CHARACTERISTICS ...................7 7.1 DC Characteristics .......................................7 7.2 AC Characteristics .......................................8 8. TIMING DIAGRAM ...............................................9 8.1 Basic operation (Positive clock pulse) ........9 8.2 Basic operation (Negative clock pulse) ......10 8.3 Single-clock input monitoring (Positive clock pulse) ................................................................11 Document Number: 002-08515 Rev. *C 13. NOTES ON USE ..............................................20 14. ORDERING INFORMATION ...........................20 15. ROHS COMPLIANCE INFORMATION ...........20 16. PACKAGE DIMENSIONS ...............................21 17. MAJOR CHANGES .........................................23 Document History .................................................23 Sales, Solutions, and Legal Information .............24 Page 2 of 24 MB3793-42 1. Pin Assignment (TOP VIEW) RESET 1 8 CK1 CTW 2 7 CK2 CTP 3 6 INH GND 4 5 VCC (SOE008) (SOB008) 2. Pin Description Pin No. Symbol 1 RESET 2 Description Pin No. Symbol Outputs reset 5 VCC Power supply CTW Sets monitoring time 6 INH Inhibits watchdog timer function 3 CTP Sets power-on reset hold time 7 CK2 Inputs clock 2 4 GND Ground 8 CK1 Inputs clock 1 Document Number: 002-08515 Rev. *C Description Page 3 of 24 MB3793-42 3. Block Diagram To VCC of all blocks CTP 3 I1 3 A Q Output buffer VCC 4 GND S RSFF2 Comp. O 5 I2 30 A Q R Q S R1 590 k + RESET 1 - RSFF1 Q INH R 6 Comp. S CTW Watchdog timer 2 Pulse generator 1 CK1 8 Reference voltage generator VREF 1.24 V - VS + R2 240 k Pulse generator 2 CK2 7 Document Number: 002-08515 Rev. *C To GND of all blocks Page 4 of 24 MB3793-42 4. Block Functions 1. Comp. S Comp. S is a comparator with hysteresis to compare the reference voltage with a voltage (VS) that is the result of dividing the power voltage (VCC) by resistors R1 and R2. When VS falls below 1.24 V, a reset signal is output. This function enables the MB3793 to detect an abnormality within 1 s when the power is cut or falls abruptly. 2. Comp. O Comp. O is a comparator to control the reset signal (RESET) output and compares the threshold voltage with the voltage at the CTP terminal for setting the power-on reset hold time. When the voltage at the CTP terminal exceeds the threshold voltage, resetting is canceled. 3. Reset Output Buffer Since the reset (RESET) output buffer has CMOS organization, no pull-up resistor is needed. 4. Pulse Generator The pulse generator generates pulses when the voltage at the CK1 and CK2 input clock terminals changes to High from Low level (positive-edge trigger) and exceeds the threshold voltage; it sends the clock signal to the watchdog timer. 5. Watchdog Timer The watchdog timer can monitor two clock pulses. Short-circuit the CK1 and CK2 clock terminals to monitor a single clock pulse. 6. Inhibition Terminal The inhibition (INH) terminal forces the watchdog timer on/off. When this terminal is High level, the watchdog timer is stopped. 7. Flip-flop Circuit The flip-flop circuit RSFF1 controls charging and discharging of the power-on reset hold time setting capacity (CTP). The flip-flop circuit RSFF2 switches the charging accelerator for charging CTP during resetting on/off. This circuit only functions during resetting and does not function at power-on reset. Document Number: 002-08515 Rev. *C Page 5 of 24 MB3793-42 5. Absolute Maximum Ratings Parameter Rating Symbol Power voltage* VCC Input voltage* Reset output voltage (direct current) Unit Min Max -0.3 +7 V -0.3 +7 V CK1 VCK1 CK2 VCK2 INH VINH RESET IOL IOH -10 +10 mA PD -- 200 mW Tstg -55 +125 C Power dissipation (Ta +85C) Storage temperature *: The power voltage is based on the ground voltage (0 V). WARNING: 1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings.Do not exceed any of these ratings. 6. Recommended Operating Conditions Parameter Symbol Value Min Typ Max Unit Power supply voltage VCC 1.2 5.0 6.0 V Reset (RESET) output current IOL IOH -5 -- +5 mA Power-on reset hold time setting capacity CTP 0.001 0.1 10 F Watchdog timer monitoring time setting capacity CTW 0.001 0.1 1 F Watchdog timer monitoring time tWD 0.1 -- 1500 ms Operating ambient temperature Ta -40 +25 +85 C WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-08515 Rev. *C Page 6 of 24 MB3793-42 7. Electrical Characteristics 7.1 DC Characteristics (VCC = +5 V, Ta = +25C) Parameter Power current Symbol ICC1 Conditions Watchdog timer operation*1 Detection voltage hysteresis difference CK input threshold voltage CK input hysteresis INH input voltage Reset-output minimum power voltage Typ Max Unit -- 27 50 -- 25 45 Ta = +25C 4.10 4.20 4.30 Ta = -40 to +85C 4.05 4.20 4.35 Ta = +25C 4.20 4.30 4.40 Ta = -40 to +85C 4.15 4.30 4.45 50 100 150 mV Watchdog timer halt* VSL VCC falling VSH VCC rising VSHYS VSH - VSL A V V VCIH -- (1.4) 1.9 (2.5) V VCIL -- (0.8) 1.3 (1.8) V VCHYS -- (0.4) 0.6 (0.8) V VIIH -- 3.5 -- VCC V VIIL -- 0 0 0.8 V IIH VCK = VCC -- 0 1.0 A IIL VCK = 0 V -1.0 0 -- A VOH IRESET = -5 mA 4.5 4.75 -- V VOL IRESET = +5 mA -- 0.12 0.4 V VCCL IRESET = +50 A -- 0.8 1.2 V Input current (CK1,CK2,INH) Reset output voltage Min 2 ICC2 Detection voltage Value *1: At clock input terminals CK1 and CK2, the pulse input frequency is 1 kHz and the pulse amplitude is 0 V to VCC. *2: Inhibition input is at High level. Document Number: 002-08515 Rev. *C Page 7 of 24 MB3793-42 7.2 AC Characteristics (VCC = +5 V, Ta = +25C) Parameter Symbol Conditions Value Min Typ Max Unit Power-on reset hold time tPR CTP = 0.1 F 80 130 180 ms Watchdog timer monitoring time tWD CTW = 0.01 F CTP = 0.1 F 7.5 15 22.5 ms Watchdog timer reset time tWR CTP = 0.1F 5 10 15 ms CK input pulse duration tCKW -- 500 -- -- ns CK input pulse cycle tCKT -- 20 -- -- s Reset (RESET) output transition time Rising tr* CL = 50 pF -- -- 500 ns Falling tf* CL = 50 pF -- -- 500 ns *: The voltage range is 10% to 90% at testing the reset output transition time. Document Number: 002-08515 Rev. *C Page 8 of 24 MB3793-42 8. Timing Diagram 8.1 Basic Operation (Positive Clock Pulse) VSH VSL VCC VCCL tCKW CK1 CK2 INH Vth CTP VH CTW VL RESET tPR (1) (2) Document Number: 002-08515 Rev. *C (3) (4) (5) (5) tWD tPR tWR (6) (7) (8) (9) (10) (11) (12) (13) (14) Page 9 of 24 MB3793-42 8.2 Basic Operation (Negative Clock Pulse) VSH VSL VCC VCCL tCKW CK1 CK2 INH Vth CTP VH CTW VL RESET tPR (1) (2) Document Number: 002-08515 Rev. *C tWD (3) (4) (5) (5) tPR tWR (6) (7) (8) (9) (10) (11) (12) (13) (14) Page 10 of 24 MB3793-42 8.3 Single-clock Input Monitoring (Positive Clock Pulse) tCKW CK1 CK2 tCKT Vth CTP VH CTW VL RESET tWD tWR Note: The MB3793 can monitor only one clock. The MB3793 checks the clock signal at every other input pulse. Therefore, set watchdog timer monitor time tWD to the time that allows the MB3793 to monitor the period twice as long as the input clock pulse. Document Number: 002-08515 Rev. *C Page 11 of 24 MB3793-42 8.4 Inhibition Operation (Positive Clock Pulse) VSH VSL VCC VCCL tCKW CK1 CK2 INH Vth CTP VH CTW VL RESET tPR (1) (2) Document Number: 002-08515 Rev. *C (3) (4) (5) (5) tWD tWR (6) (7) tPR (8) (9) (10) (11) (12) (13) (14) Page 12 of 24 MB3793-42 8.5 Clock Pulse Input (Positive Clock Pulse) *1 CK1 *2 CK2 VH CTW VL Note: The MB3793 watchdog timer monitors Clock 1 (CK1) and Clock 2 (CK2) pulses alternately. When a CK2 pulse is detected after detecting a CK1 pulse, the monitoring time setting capacity (CTW) switches to charging from discharging. When two consecutive pulses occur on one side of this alternation before switching, the second pulse is ignored. In the above figure, pulses *1 and *2 are ignored. 8.6 Inhibition Input Rising and Falling Time VCC 90 % 90 % INH 10 % 10 % 0V tri Document Number: 002-08515 Rev. *C tfi Page 13 of 24 MB3793-42 9. Operation Sequence The operation sequence is explained by using "8. Timing Diagram 8.1. Basic Operation (Positive Clock Pulse)". The following item numbers correspond to the numbers in "8.Timing Diagram 8.1. Basic Operation (Positive Clock Pulse)". 1. When the power voltage (VCC) reaches about 0.8 V (VCCL), a reset signal is output. 2. When VCC exceeds the rising-edge detection voltage (VSH), charging of power-on reset hold time setting capacitance (CTP) is started. VSH is about 4.3 V. 3. When the voltage at the CTP terminal setting the power-on reset hold time exceeds the threshold voltage (Vth), resetting is canceled and the voltage at the RESET terminal changes to High level to start charging of the watchdog timer monitoring time setting capacitance (CTW). Vth is about 3.6 V. The power-on reset hold time (tPR) can be calculated by the following equation. tPR (ms) A x CTP (F) Where, A is about 1300. 4. When the voltage at the CTW terminal setting the monitoring time reaches High level (VH), CTW switches to discharging from charging. VH is about 1.24 V (reference value). 5. When clock pulses are input to the CK2 terminal during CTW discharging after clock pulses are input to the CK1 terminal-- positive-edge trigger, CTW switches to charging. 6. If clock pulse input does not occur at either the CK1 or CK2 clock terminals during the watchdog timer monitoring time (tWD), the CTW voltage falls below Low level (VL), a reset signal is output, and the voltage at the RESET terminal changes to Low level. VL is about 0.24 V. tWD can be calculated from the following equation. tWD (ms) B x CTW (F) + C x CTP (F) Where, B is about 1500. C is about 3; it is much smaller than B. Hence, when CTP / CTW 10, the calculation can be simplified as follows: tWD (ms) B x CTW (F) 7. When the voltage of the CTP terminal exceeds Vth again as a result of recharging CTP, resetting is canceled and the watchdog timer restarts monitoring. The watchdog timer reset time (tWR) can be calculated by the following equation. tWR (ms) D x CTP (F) Where, D is about 100. 8. When VCC falls below the rising-edge detection voltage (VSL), the voltage of the CTP terminal falls and a reset signal is output, and the voltage at the RESET terminal changes to Low level. VSL is about 4.2 V. 9. When VCC exceeds VSH, CTP begins charging. 10.When the voltage of the CTP terminal exceeds Vth, resetting is canceled and the watchdog timer restarts. 11.When an inhibition signal is input (INH terminal is High level), the watchdog timer is halted forcibly. In this case, VCC monitoring is continued without the watchdog timer. The watchdog timer does not function unless this inhibition input is canceled. 12.When the inhibition input is canceled (INH terminal is Low level), the watchdog timer restarts. 13.When the VCC voltage falls below VSL after power-off, a reset signal is output. 14.When the power voltage (VCC) falls below about 0.8 V (VCCL) , a reset signal is released. Similar operation is also performed for negative clock-pulse input ("8. Timing Diagram 8.2. Basic operation (Negative clock pulse)"). Short-circuit the clock terminals CK1 and CK2 to monitor a single clock. The basic operation is the same but the clock pulses are monitored at every other pulse (8. Timing Diagram 8.3. Single-clock input monitoring). Document Number: 002-08515 Rev. *C Page 14 of 24 MB3793-42 10. Typical Characteristics Power Current - Power Voltage Detection Voltage - Operating ambient Temperature 4.5 40 Watchdog timer monitoring 35 Power current ICC (A) 25 Watchdog timer stopping (VINH = VCC) 20 Inhibited Reset 15 (VCC < VSH) Detection voltage VSH and VSL (V) (VINH = 0 V) 30 4.4 VSH 4.3 VSL 4.2 10 MB3793-42 f = 1 kHz Duty = 10% VL = 0 V VINH VCC 4.1 CTP CTW 0.01 F 0.1 F 4.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 Operating ambient temperature Ta (C) Power voltage VCC (V) Reset Output Voltage - Reset Output Current (P-MOS side) Ta = +25 C 4.8 4.7 4.6 4.5 4.3 4.2 Ta VRESET RON IRESET -40 C 98 mV 19.6 +25 C 135 mV 27 +5 mA +85 C 167 mV 33.4 500 Ta = -40 C 4.9 4.4 Reset Output Voltage - Reset Output Current (N-MOS side) Ta = +85 C Ta VRESET RON IRESET -40 C 4.800 V 40 +25 C 4.750 V 50 -5 mA +85 C 4.707 V 58.6 Reset output voltage V RESET (mV) Reset output voltage V RESET (V) 5.0 -40 -20 0 +20 +40 +60 +80 +100 400 Ta = +25 C 300 Ta = +85 C 200 100 Ta = -40 C 4.1 4.0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 Reset output current I RESET (mA) Document Number: 002-08515 Rev. *C 0 0 1 2 3 4 5 6 7 8 9 10 Reset output current I RESET(mA) Page 15 of 24 MB3793-42 Reset-on Reset Time - Operating ambient temperature (when VCC rising) Reset Output Voltage - Power Voltage 260 7 Pull-up resistance: 100 k 240 220 200 5 Power-on reset time tPR (ms) Reset output voltage VRESET (V) 6 4 3 Ta = +85 C 2 Ta = +25 C 1 Ta = -40 C 1 2 3 160 140 120 100 80 60 0 0 180 4 Power voltage 5 6 VCC (V) 7 40 20 0 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta (C) Watchdog Timer Monitoring Time Operating ambient temperature 26 26 26 24 24 24 22 22 22 Watchdog timer monitoring time tWD (ms) Watchdog timer monitoring reset time tWR (ms) Watchdog Timer Monitoring Reset Time - Operating ambient temperature (when monitoring) 20 18 16 14 12 10 20 20 18 18 16 16 14 14 12 12 10 10 8 8 6 6 4 4 4 2 2 2 0 0 0 +20 +100 -40-40 -20-20 0 +20 +40+40 +60+60 +80+80 +100 8 6 0 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta (C) Document Number: 002-08515 Rev. *C Operating ambient temperature Ta (C) Page 16 of 24 MB3793-42 Reset Time - CTP Capacitance 103 104 103 102 Ta = -40 C Reset Time tWR (ms) Power-on reset hold time tPR (ms) Power-on Reset Hold Time - CTP Capacitance 102 Ta = +25 C 101 Ta = +85 C 1 10 -1 10-4 10-3 10-2 10-1 Ta = -40 C 101 1 Ta = +25 C Ta = +85 C 10-1 101 1 10-2 10-4 102 10-3 10-2 10-1 1 101 102 Power-on reset time setting capacitance CTP (F) Power-on reset time setting capacitance CTP (F) Watchdog Timer Monitoring Time CTW Capacitance Watchdog Timer Monitoring Time - CTW Capacitance (under Ta condition) 103 Ta = -40 C 102 Ta = +25 C 101 1 Ta = +85 C 10-1 10-5 10-4 10-3 10-2 10-1 1 101 Watchdog timer monitoring time setting capacitance CTW (F) Document Number: 002-08515 Rev. *C Watchdog timer monitoring time tWD (ms) Watchdog timer monitoring time tWD (ms) 104104 103103 1 F CTPC=TP1=F 102102 = 0.1 FF CTPC=TP0.1 101101 1 1 10-1 10-1 CTPC=TP0.01 = 0.01 FF 10-5 10-510-4 10-410-3 10-310-2 10-210-1 10-1 1 1 101101 Watchdog timer monitoring time setting capacitance CTW (F) Page 17 of 24 MB3793-42 11. Standard Connection VCC 5 VCC RESET 2 1 CTW MB3793 3 RESET VCC CK CK CTP CK1 8 CTW RESET VCC Microprocessor 1 CTP GND INH 6 GND 4 Microprocessor 2 GND CK2 7 Equation of time-setting capacitances (CTP and CTW) and set time tPR (ms) A x CTP (F) tWD (ms) B x CTW (F) + C x CTP (F) However, when CTP/CTW 10, tWD (ms) B x CTW (F) tWR (ms) D x CTP (F) Value of A, B, C and D A B C D 1300 1500 3 100 Remark (Example) When CTP = 0.1 F and CTW = 0.01 F, tPR 130 [ms] tWD 15 [ms] tWR 10 [ms] Document Number: 002-08515 Rev. *C Page 18 of 24 MB3793-42 12. Application Example 12.1 Monitoring Single Clock VCC 5 VCC RESET 1 2 CTW RESET VCC MB3793 Microprocessor 3 CTP CK1 8 CTW CK CTP GND INH 6 GND 4 CK2 7 12.2 Watchdog Timer Stopping VCC 5 VCC RESET 1 6 INH 2 CTW MB3793 3 CTP CK1 8 CTW CTP GND 4 Document Number: 002-08515 Rev. *C RESET VCC RESET VCC MicroCK processor1 HALT MicroCK processor2 HALT GND GND CK2 7 Page 19 of 24 MB3793-42 13. Notes on Use Take account of common impedance when designing the earth line on a printed wiring board. Take measures against static electricity. For semiconductors, use antistatic or conductive containers. When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container. The work table, tools and measuring instruments must be grounded. The worker must put on a grounding device containing 250 k to 1 M resistors in series. Do not apply a negative voltage Applying a negative voltage of -0.3 V or less to an LSI may generate a parasitic transistor, resulting in malfunction. 14. Ordering Information Part Number Package Remarks MB3793-42PF-E1 8-pin plastic SOP (SOE008) - MB3793-42PNF-E1 8-pin plastic SOP (SOB008) - 15. RoHS Compliance Information The LSI products of Cypress with "E1" are compliant with RoHS Directive , and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) . The product that conforms to this standard is added "E1" at the end of the part number. Document Number: 002-08515 Rev. *C Page 20 of 24 MB3793-42 16. Package Dimensions Package Code: SOE008 L 0.45 0.47 0.55 0.60 0.75 L 2 0.25 BSC b A' 1 , 3 $ 1 ' (( +7 7$ & 7 , 1' (1 , 6 ($ 5( 35 $ 7 2; 1( ' 6 1 , , 7 , ( + ) /7 1 / , $+ 17 2, ,: 7 3' 2( 7 6 $ , & ( 52 / 8 7( $% (7 )6 8 5 (0 ) 05 ( $, +) , &7 1 6 , ( +' 7, 2 756 21 ( 2 1' , $17 /$$ 3 '5 , * /8 1 * ,( , 7 ) $+1 (72 6*& 1 , ( ( +'* 78$ 0/. & 2;& 5($ 3 )< ' 1 ( &2: 1%2 $' 7( 6*< , $, 7 '. 9 & / $ $$& &3 , 1 7 ( 5+2 (77 91 1( ( 20 + 77 ( 1& 6 , $21 3$ ' + (7 1 16( , )(/ (:$ '20 / 6 5 ( , ( + + $77 Page 21 of 24 Document Number: 002-08515 Rev. *C 1 2 , 6 1 (( /0 7 %, 2 $' 2 ) : E 2 ( / + /( 7 $+ 7 ) 1 2 ) 22 6 , 6 8 6 , 86 ' 5( $ 7& 5 2; 5( 5 3 ( 1 , : 5 2 $/ / %$ 7 02 ( $7 + 7 ' P 1 ( +P 2 7 ' ( 1( 2 '( 7 , 8% $ 7& / , ' &/ 2 1/1/ ,$2 +&( 7 % 26/ 7 1 1$2 2, 6 51 ,( (6 28 7< ' $$ 5 7 00 E 5 20 58 $ 1 230% , 5,0 6 ;$ 1$$' (%0( 00 + ,$7 ''$7 L 1 1.25 REF 0.39 DETAIL A SIDE VIEW b L2 DETAIL A c P P 1 ( ( : 7 ( % ' $ ( / ( + 7 ) 2 1 2 , 7 & ( 6 7 $ / ) 3 (, +7 7' $ 2 7( / < /( 3+ 37 $ 0 1 2 25 ,) 6 1P (P 0 , ' ( +2 77 8 0.20 ' ( , ) , & ( 3 6 ( + 7 5 2 ) 6 1 2 , 7 , 6 2 3 / $ 1 , 0 5 ( 7 ) 2 5 ( % 0 8 1 0 8+ 07 ,* ; 1 $( / 0 ( ( +* 7$ . 6 & , $ 13 0 0.13 + 0 8 7 $ ' 7 $ ' ( 1 , 0 5 ( 7 ( ' ( % 2 7 % $ 6 0 8 7 $ ' 5.30 BSC < *' 12 , % ' 0 & 8, 2 77/7 76+&6 2261$ , / % $7 0 3 /8 (5) ( %+ *(' 7 $7/ + .82 6) 2 & 0$2 $( 3+ )/0 ) 7 2' 2 ( + 7 ( 7 $ 7$9( 7 ' ,/2 6 1 % $(85 +1/(' 7,&71 1$ 0;, 5 (5( /('3 /7<12 $('$7 0'2 ( 6 % 5+ 6( 5 & 5, 7 ( $781 % 6%( <$ ( ( $(/ 7: G 0Q 3$ 7 D (*( 3 +% 2' 76+ 7 5 * ) ( & 1257 *, 8$ $1 6 %0 .2( &, 5 6 $60$, 31(%0 (5< ( 07(1 ; + +, 7'(7$ E1 ( ' ' ( 8 1 / , &60 115 , 2( , 7 7 26( 8 ' 15 7 ( 6 5 (2$ 25 '31 2 5, ( 6 2 1 * 1+( 6 , 0 $, 1 2/' ,) 6 ( 1' ($G Q 0(D ,/ 5 ' ' ( 7 +1 ( 6, ' $ 6 , /1 )25 , ' ( /63 28P 05P 7 2 ( '5 83 / 5 &2 ' 1 ( ,+ ( ' 6 $& * /; 1) (+ , 1' 7 2$20 ,(18 6 /7 / 15 $ ( /' ( 0 $7 + ,76 1 $ ', 7.80 BSC 0 < ( 0 6 $ 5 ( 3 * 1 , & 1 $ 5 ( / 2 7 ' 1 $ * 1 , 1 2 , 6 1 ( 0 , ' E 5 ( 7 ( 0 , / / , 0 1 , ( 5 $ 6 1 2 , 6 1 ( 0 , ' / / $ 6.35 BSC 6 ( 7 2 1 D 1.27 BSC e 2.25 A MAX. NOM. MIN. 0.20 0.05 A1 0.25 H D ; DIMENSION SYMBOL PLANE 8 C A-B D 0.13 b BOTTOM VIEW TOP VIEW c A GAUGE A E E1 SECTION A-A' L L1 e 10 ; 4 SEATING PLANE 0.10 C A1 0.40 C A-B D 5 5 0.25 H D D 4 INDEX AREA 11. JEDEC SPECIFICATION NO. REF : N/A 002-15857 Rev. ** MB3793-42 Package Code: SOB008 0.44 0.52 L 0.60 0.75 L 2 0.25 BSC 1.27 BSC. h 0.40 BSC. Page 22 of 24 Document Number: 002-08515 Rev. *C 2 756 21 ( 2 1' , $17 /$$ 3 '5 , * /8 1 * ,( , 7 ) $+1 (72 6*& 1 , ( ( +'* 78$ 0/. & 2;& 5($ 3 )< ' 1 ( &2: 1%2 $' 7( 6*< , $, 7 '. 9 & / $ $$& &3 , 1 7( 5+2 (77 91 1( ( 20 + 77 ( 1& 6 , $21 3$ ' + (7 1 16( , )(/ (:$ '20 / 6 5 ( , ( + + $77 e 1 , 3 $ 1 ' (( +7 7$ & 7 , 1' (1 , 6 ($ 5( 35 $ 7 2; 1( ' 6 1 , , 7 , ( + ) /7 1 / , $+ 17 2, ,: 7 3' 2( 7 6 $ , & ( 52 / 8 7( $% (7 )6 8 5 (0 ) 05 ( $, +) , &7 1 6 , ( +' 7, 1.05 REF 1 2 , 6 1 (( /0 7 %, 2 $' 2 ) : E 2 ( / + /( 7 $+ 7 ) 1 2 ) 22 6 , 6 8 6 , 86 ' 5( $ 7& 5 2; 5( 5 3 ( 1 , : 5 2 $/ / %$ 7 02 ( + $7 7 ' P 1 ( +P 2 7 ' ( 1( 2 '( 7 , 8% $ 7& / , ' &/ 2 1/1/ ,$2 +&( 7 % 26/ 7 1 1$2 2, 6 51 ,( (6 287< '5$$ 7 00 E 25 50$ 1 8 30 % 2 0 ,5 , 6 ; $ 1$$' (%0( 00 + ,$7 ''$7 0.36 0.45 P P 1 ( ( : 7 ( % ' $ ( / ( + 7 ) 2 1 2 , 7 & ( 6 7 $ / ) 3 (, +7 7' $ 2 7( / < /( 3+ 37 $ 0 1 2 25 ,) 6 1P (P 0 , ' ( +2 77 b 0.25 b c 0.15 c L2 A GAUGE PLANE BOTTOM VIEW SIDE VIEW 8 ' ( , ) , & ( 3 6 ( + 7 5 2 ) 6 1 2 , 7 , 6 2 3 / $ 1 , 0 5 ( 7 ) 2 5 ( % 0 8 1 0 8+ 07 ,* ; 1 $( / 0 ( ( +* 7$ . 6 & , $ 13 0 + 0 8 7 $ ' 7 $ ' ( 1 , 0 5 ( 7 ( ' ( % 2 7 % $ 6 0 8 7 $ ' L 1 < *' 12 , % ' 0 & 8, 2 /7 77& 6 76+1 $ 226, / %0$3 /7 5 ( )8( ( % *7 ' + $8 /+ 7 .2 26) & 0$2 $( 3+ )/0 ) 7 2' 2 ( + 7 ($7 7$9( 7 ' ,/2 6 1 % $(85 +1/(' 7,&71 1$ 0;, 5 (5( ' 3 /(< 12 /7' $ 7 $(2 0'% ( 6 + 6( 57 (5& ,5 %$781 6%( < $( ( ( $ /7 : 0G3$ Q 7 D (*( 3 +% 2' 76+ 7 5 * ) ( & *1257 , 8$ $1 6 %0 .2( &, 5 6 $60$, 31(%0 (5< ( 07(1 ; + +, 7'(7$ ( ' ' ( 8 1 / , &60 115 , 2( , 7 7 26( 8 ' 15 7 ( 6 5 (2$ 25 '31 2 5, ( 6 2 1 * 1+( 6 , 0 $, 1 2/' ,) 6 ( 1' ($G Q 0(D ,/ 5 ' ' ( 7 +1 ( 6, ' $ 6 , /1 )25 ,( '6 /8 3 25 P 07 P 2 ( '5 83 / 5 &2 ' 1 ( ,+ ( ' 6 $& * /; 1) (+ , 1' 7 2$20 ,(18 6 /7 / 15 $ ((/' 0 $7 + ,76 1 $ ', 3.90 BSC E1 0 < ( 0 6 $ 5 ( 3 * 1 , & 1 $ 5 ( / 2 7 ' 1 $ * 1 , 1 2 , 6 1 ( 0 , ' 6.00 BSC. 5 ( 7 ( 0 , / / , 0 1 , ( 5 $ 6 1 2 , 6 1 ( 0 , ' / / $ E 6 ( 7 2 1 1.30 D 5.05 BSC. 1.50 A2 1.40 0.05 0.25 A1 8 SIDE VIEW 45 E1 E A' e SECTION A-A' C A-B D 0.13 b h DIMENSIONS 0.25 H D ; SYMBOL ; 4 L L1 10 SEATING PLANE 0.10 C A1 0.25 H D 1.75 A MAX. NOM. MIN. DETAIL A A2 A 5 0.20 C A-B D 5 D 4 INDEX AREA TOP VIEW DETAIL A 11. JEDEC SPECIFICATION NO. REF : N/A 002-15856 Rev. ** MB3793-42 17. Major Changes Spansion Publication Number: MB3793-42_DS04-27402 Page Section Change Results Revision 6.0 1 Company name and layout design change - Deleted "There is also a mask option that can detect voltages of 4.9 V to 2.4 V in 0.1-V steps." Description Revision 6.1 22 MB3793-42PF-1, MB3793-42PNF-E1 Recommended Conditions of Moisture Sensitivity Level Changed the subtitle text of Figure NOTE: Please see "Document History" about later revised information. Document History Document Title: MB3793-42 Power-Voltage Monitoring IC with Watchdog Timer Document Number: 002-08515 Revision ECN Orig. of Change Submission Date ** -- TAOA 02/27/2015 Migrated to Cypress and assigned document number 002-08515. No change to document contents or format. *A 5199108 TAOA 04/04/2016 Updated to Cypress format. Description of Change *B 5610247 HIXT 01/31/2017 Updated Pin Assignment: Change the package name from FPT-8P-M01 to SOE008 Change the package name from FPT-8P-M02 to SOB008 Updated Ordering Information: Change the package name from FPT-8P-M01 to SOE008 Change the package name from FPT-8P-M02 to SOB008 Deleted the part numbers, MB3793-42PF- and MB3793-42PNF- Deleted the words in the Remarks, "Lead Free version" Updated Package Dimensions: Updated to Cypress format Deleted "Marking Format (Lead Free version)" Deleted "Labeling Sample (Lead free version)" Deleted "MB3793-42PF- E1, MB3793-42PNF- E1 Recommended Conditions of Moisture Sensitivity Level" *C 5788795 MASG 06/28/2017 Adapted Cypress new logo. Document Number: 002-08515 Rev. *C Page 23 of 24 MB3793-42 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R) Solutions Products ARM(R) Cortex(R) Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface Internet of Things Memory cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing USB Controllers Wireless/RF PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/touch cypress.com/usb cypress.com/wireless (c) Cypress Semiconductor Corporation, 1996-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-08515 Rev. *C Revised June 28, 2017 Page 24 of 24