© 2014 Exar Corporation
XR81111
Universal Clock - High Frequency
LVPECL Clock Synthesizer
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Rev 1B
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General Description
The XR81111-CA04 is a clock synthesizer with Integer divider, LVPECL
driver, 3.3V/2.5V supply, taking a 25MHz Xtal input and providing one of four
selectable output frequencies. The device is optimized for use with a 25MHz
crystal (or system clock) and generates a selection of output frequencies -
156.25MHz for 10GE/XAUI, 150MHz for SAS, 125MHz for GE and 100MHz
for PCIe applications.
The application diagram below shows a typical synthesizer configuration
with any standard crystal oscillating in fundamental mode. Internal load
capacitors are optionally available to minimize/eliminate external crystal
loads. A system clock can also be used to overdrive the oscillator for a syn-
chronous timing system.
The typical phase noise plot below shows the jitter integrated over the
12KHz to 20MHz range that is widely used in WAN systems. Most LAN
applications however use the integration range of 1.875MHz to 20MHz.
These clock devices show a very good high frequency noise floor below -
150dB.
The XR81111 is a family of Universal Clock synthesizer devices in QFN-10
packages that are footprint compatible with industry standard 5mm x 7mm
oscillators. The devices generate ANY frequency in the range of 100 MHz to
1.5GHz by utilizing a highly flexible delta sigma modulator and a wide rang-
ing VCO. The high clock frequency LVPECL outputs have very low phase
noise jitter of sub 0.6ps, while consuming extremely low power. These
devices can be used with standard crystals or external system clock and can
be configured to select from four different frequency multiplier settings to
support a wide variety of applications. This family of products have an
extremely low power PLL block with core power consumption less than 40%
of the equivalent devices from competition. By second sourcing several of
the existing sockets, these devices provides a very compelling power effi-
ciency value benefit across all market segments.
Other clock multiplier and/or driver configurations are possible in this clock
family and can be requested from the factory
FEATURES
• XR81111-CA04: Factory Configured
• Footprint compatible with 5mm x 7mm differen-
tial oscillators
• One differential LVPECL output pair
• Crystal oscillator interface which can also be
overdriven using a single-ended reference clock
• Output frequency range: 100MHz - 156.25MHz
• Crystal/input frequency: 25MHz, parallel resonant
crystal
• VCO range: 2GHz - 3GHz
• RMS phase jitter @ 156.25MHz, 12kHz - 20MHz:
<0.60ps
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) package
APPLICATIONS
• 10GE, GE LAN/WAN
• 2.5G/10G SONET/SDH/OTN
• xDSL, PCIe
• Low-jitter Clock Generation
• Synchronized clock systems
Ordering Information – page 12
Typical Application
V
CC
2.5Vor3.3V Q
100 MHzto156.25MHz
V
E E
Q
OE
XTAL_IN
XTAL_OUT
FSEL1
FSEL0
25MHz
Enable
FreqSelect
XR81111ͲCA04
XR81111PHASENOISE(dBc/Hz)
100Hz 1KHz 10KHz 100 KHz 1MHz 10MHz
-120db
-160db
-140db
-100db
-80db
-60db
-180db
-40db
RMS Jitter = 532.3fs
Int Range 12KHz to 20MHz
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Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device.
Exposure to any Maximum Rating condition for extended
periods may affect device reliability and lifetime.
Supply Voltage..........................................................+4.2V
Input Voltage......................................-0.5V to VCC + 0.5V
Output Voltage...................................-0.5V to VCC + 0.5V
Reference Frequency/Input Crystal.........10MHz to 60MHz
Storage Temperature................................-55°C to +125°C
Lead Temperature (Soldering, 10 sec).....................300°C
ESD Rating (HBM - Human Body Model)....................2kV
Operating Conditions
Operating Temperature Range.....................-40°C to +85°C
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Electrical Characteristics
Unless otherwise noted: TA = -40°C to +85°C, VCC = 3.3V±5% or 2.5V±5%, VEE = 0V
Symbol Parameter Conditions * Min Typ Max Units
3.3V Power Supply DC Characteristics
VCC Power Supply Voltage • 3.135 3.3 3.465 V
IEE Power Supply Current Measured at 156.25MHz and includes
the output load current
68 mA
2.5V Power Supply DC Characteristics
VCC Power Supply Voltage • 2.375 2.5 2.625 V
IEE Power Supply Current Measured at 156.25MHz and includes
the output load current
58 mA
LVCMOS/LVTTL DC Characteristics
VIH Input High Voltage VCC = 3.465V • 2.42 VCC + 0.3 V
VCC = 2.625V • 1.83 VCC + 0.3 V
VIL Input Low Voltage VCC = 3.465V • -0.3 1.03 V
VCC = 2.625V • -0.3 0.785 V
IIH Input High Current (OE, FSEL[1:0]) VIN = VCC = 3.465V or 2.625V • 15 µA
IIL Input Low Current (OE, FSEL[1:0]) VIN = 0V, VCC = 3.465V or 2.625V • -10 µA
LVPECL DC Characteristics
VOH Output High Voltage • VCC - 1.3 VCC - 0.4 V
VOL Output Low Voltage • VCC - 2.0 VCC - 1.6 V
VSWING Peak-to-Peak Output Voltage Swing • 0.6 1.2 V
Crystal Characteristics
XMode Mode of Oscillations Fundamental
XfFrequency 25 MHz
ESR Equivalent Series Resistance 50 Ω
CSShunt Capacitance 7 pF
AC Characteristics
fOUT Output Frequency See Table 1. 100 156.25 MHz
Symbol Parameter Conditions * Min Typ Max Units
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* Limits applying over the full operating temperature range are denoted by a “•”.
tjit(I) RMS Phase Jitter 156.25MHz
Integration Range 12kHz-20MHz
0.6 pS
150MHz
Integration Range 12kHz-20MHz
0.6 pS
125MHz
Integration Range 12kHz-20MHz
0.6 pS
100MHz
Integration Range 12kHz-20MHz
0.6 pS
tjit(cc) Cycle-to-Cycle Jitter Using 25MHz, 18pF resonant crystal • 10 pS
tR/tFOutput Rise/Fall Time 20% to 80% • 100 450 pS
Odc Output Duty Cycle • 48 52 %
Symbol Parameter Conditions * Min Typ Max Units
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Pin Configuration
Pin Assignments
Pin No. Pin Name Type Description
1 OE Input
(900K: pull-up)
Output enable pin - LVCMOS/LVTTL active high input. Outputs are enabled when OE = high.
Outputs are disabled when OE = low.
2 Reserved Reserved, leave this pin unconnected.
3 VEE Supply Negative supply pin.
4 XTAL_OUT Output Crystal oscillator output.
5 XTAL_IN Input Crystal oscillator input.
6 Q Output Positive LVPECL output.
7 Q Output Inverted LVPECL output.
8 VCC Supply Power supply pin.
9 FSEL0 Input
(900K: pull-dwn)
Output frequency select pin, LSB (LVCMOS/LVTTL input).
10 FSEL1 Input
(900K: pull-dwn)
Output frequency select pin, MSB (LVCMOS/LVTTL input).
1
2
3
4 5
6
7
8
10 9
OE
Reserved
VEE Q
Q
VCC
FSEL1
FSEL0
XTAL_IN
XTAL_OUT
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Functional Block Diagram
OSC PDF & LPF
VCO
Divide
by N
Divide
by M
Control
Logic
Q
Q
FSEL0
FSEL1
XTAL_IN
XTAL_OUT
OE
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Typical Performance Characteristics
Figures 1,2,3 and 4 show typical phase noise performance plots for 156.25 MHz, 150MHz, 125M, and 100MHz clock out-
puts respectively. The data was taken using the industry standard Agilent E5052B instrument. The integration range is the
widely referenced 12KHz to 20MHz range most often used in WAN applications.
Figure 1: 156.25MHz Operation, Phase Noise at 3.3V
Figure 2: 150MHz Operation, Phase Noise at 3.3V)
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Figure 3: 125MHz Operation, Phase Noise at 3.3V
Figure 4: 100MHz Operation, Phase Noise at 3.3V
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Application Information
Functional Truth Table
The XR81111-CA04 has two frequency select pins,
FSLEL[1:0], that determine the output frequency from the
device. With the two FSEL inputs, one of 4 different clock
rates can be selected. This allows the XR81111-CA04 to
support a variety of applications such as PCI Express,
Ethernet, SAS and 10GE for example. If the FSEL pins are
left floating, the XR81111-CA04 will default (with internal
pull-down resistors on the FSEL inputs) to the 100MHz out-
put configuration.
Termination for LVPECL Outputs
The termination schemes shown in Figure 5 and Figure 6
are typical for LVPECL outputs. Matched impedance layout
techniques should be used for the LVPECL output pairs to
minimize any distortion that could impact your maximum
operating frequency. Figure 7 is an alternate termination
scheme that uses a Y-termination approach.
Figure 5: XR81111 3.3V LVPECL Output Termination
Figure 6: XR81111 2.5V LVPECL Output Termination
Figure 7: XR81111 Alternate LVPECL Output Termination
Using Y-termination
Output Signal Timing Definitions
The following diagrams clarify the common definitions of
the AC timing measurements.
Figure 8: Cycle-to-Cycle Jitter
Table 1: Output Frequency Selection
FSEL[1:0] XTAL
(MHz)
Output Frequency
(MHz)
Applications
00 25 100 PCI Express
01 25 125 Ethernet
10 25 150 SAS
11 25 156.25 10GE, XAUI
3.3V 3.3V 3.3V
50:50:130:130:82:82:LVPECL
Output
LVPECL
Input
2.5V 2.5V 2.5V
50:50:::::LVPECL
Output
LVPECL
Input
VCC VCC
50:50:50:50:LVPECL
Output
LVPECL
Input
RTT
For 3.3V systems RTT = 50:For 2.5V systems RTT = 19:
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Figure 9: Output Rise/Fall Time and Swing
Figure 10: Output Period and Duty Cycle
20%
80%
tRtF
80%
20%
VSWING
Q
nQ
Q
nQ
t
PW
t
PERIOD
odc = x 100%
t
PW
t
PERIOD
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Mechanical Dimensions
10-Pin QFN
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For Further Assistance:
Email: commtechsupport@exar.com
Exar Technical Documentation: http://www.exar.com/techdoc/
Exar Corporation Headquarters and Sales Offices
48720 Kato Road Tel: +1 (510) 668-7000
Fremont, CA 95438 - USA Fax: +1 (510) 668-7001
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation
assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free
of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user’s specific application. While the information
in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to
cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Cor-
poration is adequately protected under the circumstances.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Ordering Information
Revision History
Part Number Package Green Operating Temperature
Range
Shipping Packaging Marking
XR81111-CA04-F 10-pin QFN Yes -40°C to +85°C Tube/Tray T111
XR81111-CA04TR-F 10-pin QFN Yes -40°C to +85°C Tape & Reel T111
XR81111EVB Eval Board N/A N/A N/A N/A
Revision Date Description
1A April 2014 Initial release.
1B April 28, 2014 Updates to general description and package drawing.
[ECN1421-15 l 05/25/2014]
Mouser Electronics
Authorized Distributor
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XR81111-CA04-F XR81111-CA04TR-F XR81111EVB