A2C0005401500 - SPANSION - Datasheet.Live

M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Features

PDF: 09005aef848ee55b / Source: 09005aef848ee58b Micron Technology, Inc., reserves the right to change products or specifications without notice.

M58WRxxxKT/B - 32Mb & 64Mb, 1.8V, x16

Multi Bank Burst, Flash

M58WR032KT, M58WR064KT,

M58WR032KB, M58WR064KB

Features

• Supply voltage

–VDD = 1.7V to 2V for PROGRAM, ERASE and READ

–VDDQ = 1.7V to 2V for I/O buffers

–VPP = 9V for fast program

• SYCHRONOUS/ASYCHRONOUS READ

–SYCHRONOUS BURST READ mode: 66 MHz

–Asynchronous/synchronous page READ mode

–Random access times: 70ns

• SYCHRONOUS BURST READ SUSPEND

•Programming time

–10µs by word typical for fast factory program

–Double/quadruple word program option

–Enhanced factory program options

•Memory blocks

–Multiple bank memory array: 4Mb banks

–Parameter blocks (top or bottom location)

•Dual operations

–PROGRAM ERASE in one bank while read in others

–No delay between read and write operations

• Block locking

–All blocks locked at power-up

–Any combination of blocks can be locked

–WP# for block lock-down

•Security

–128 bit user programmable OTP cells

–64 bit unique device number

• Common Flash interface (CFI)

• 100,000 PROGRAM/ERASE cycles per block

•Electronic signature

• Manufacturer code: 20h

–Device codes:

M58WR032KT (top): 8814h

M58WR032KB (bottom): 8815h

M58WR064KT (top): 8810h

M58WR064KB (bottom): 8811h

• RoHS compliant packages available

• Automotive Certified Parts Available

PDF: 09005aef848ee55b / Source: 09005aef848ee58b Micron Technology, Inc., reserves the right to change products or specifications without notice.

M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Address Inputs (A[MAX:0]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Data Inputs/Outputs (DQ[15:0]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Chip Enable (CE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Output Enable (OE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Write Enable (WE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Reset (RST#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Latch Enable (ADV#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Bus READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Command Interface - Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

READ ARRAY Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

READ STATUS REGISTER Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

READ ELECTRONIC SIGNATURE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

READ CFI QUERY Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

CLEAR STATUS REGISTER Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

BLOCK ERASE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

PROGRAM Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

PROGRAM/ERASE SUSPEND Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

PROGRAM/ERASE RESUME Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

PROTECTION REGISTER PROGRAM Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

SET CONFIGURATION REGISTER Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

BLOCK LOCK Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

BLOCK UNLOCK Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

BLOCK LOCK-DOWN Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Command Interface - Factory PROGRAM Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

DOUBLE WORD PROGRAM Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

QUADRUPLE WORD PROGRAM Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

ENHANCED FACTORY PROGRAM Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Setup Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

PROGRAM Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

QUADRUPLE ENHANCED FACTORY PROGRAM Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Setup Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

PDF: 09005aef848ee55b / Source: 09005aef848ee58b Micron Technology, Inc., reserves the right to change products or specifications without notice.

M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Table of Contents

Load Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

PROGRAM and VERIFY Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

PROGRAM/ERASE CONTROLLER STATUS Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

ERASE SUSPEND STATUS Bit (SR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

ERASE STATUS Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

PROGRAM STATUS Bit (SR4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

PROGRAM SUSPEND STATUS Bit (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Bank Write/Multiple Word PROGRAM Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

READ Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

X-latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Wait Polarity Bit (CR10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Burst Type Bit (CR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Wrap Burst Bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Burst Length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Read Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

ASYCHRONOUS READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

SYCHRONOUS BURST READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

SYCHRONOUS BURST READ Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

SINGLE SYCHRONOUS READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Dual Operations and Multiple Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Lock-down State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Program and Erase Times and Endurance Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

DC and AC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Appendix A: Block Address Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Appendix B: Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Appendix C: Flowcharts and Pseudo Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

ENHANCED FACTORY PROGRAM Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

QUADRUPLE ENHANCED FACTORY PROGRAM Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

PDF: 09005aef848ee55b / Source: 09005aef848ee58b Micron Technology, Inc., reserves the right to change products or specifications without notice.

M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

List of Tables

Table 1: Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 2: M58WR032KT/B Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 3: M58WR064KT/B Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 4: Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 5: Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 6: Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 7: Electronic Signature Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 8: Factory Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 9: Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 10: Latency Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 11: Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 12: Burst Type Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 13: Dual Operations Allowed in Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 14: Dual Operations Allowed in Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 15: Dual Operation Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 16: Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 17: Program, Erase Times and Endurance Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 18: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 19: Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 20: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 21: DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 22: DC Characteristics - Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 23: ASYCHRONOUS READ AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 24: Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 25: Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 26: Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 27: Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 28: VFBGA56 7.7 × 9 mm - 8 × 7 Active Ball Array, 0.75 mm, Package Mechanical Data . . . . . . . . . . . . . .69

Table 29: Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 30: Top Boot Block Addresses, M58WR032KT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 31: Bottom Boot Block Addresses, M58WR032KB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 32: Top Boot Block Addresses, M58WR064KT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 33: Bottom Boot Block Addresses, M58WR064KB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 34: Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Table 35: CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 36: CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 37: Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 38: Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 39: Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 40: Burst Read Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 41: Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 42: Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table 43: Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 44: Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 45: Command Interface States - Modify Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 46: Command Interface States - Lock Table, Next State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 47: Command Interface States - Lock Table, Next Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

List of Figures

Figure 1: Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 2: VFBGA56 Connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 3: M58WR032KT/B Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 4: M58WR064KT/B Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 5: Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 6: X-latency and Data Output Configuration Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 7: Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 8: AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 9: AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 10: ASYCHRONOUS RANDOM ACCESS READ AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 11: Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 12: SYCHRONOUS BURST READ AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 13: SINGLE SYCHRONOUS READ AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 14: SYCHRONOUS BURST READ Suspend AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 15: Clock Input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 16: Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 17: Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 19: VFBGA56 7.7 × 9 mm - 8 × 7 Active Ball Array, 0.75 mm, Package Outline. . . . . . . . . . . . . . . . . . . . . . .68

Figure 20: Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Figure 21: DOUBLE WORD PROGRAM Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Figure 22: QUADRUPLE WORD PROGRAM Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Figure 23: PROGRAM SUSPEND STATUS and RESUME Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . .97

Figure 24: BLOCK ERASE Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Figure 25: ERASE SUSPEND and RESUME Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Figure 26: Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 27: PROTECTION REGISTER PROGRAM Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 28: ENHANCED FACTORY PROGRAM Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 29: QUADRUPLE ENHANCED FACTORY PROGRAM Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Description

The M58WR032KT/B and M58WR064KT/B are 32Mb (2Mb ×16) and 64Mb (4Mb ×16)

non-volatile Flash memories, respectively. They may be erased electrically at block level

and programmed in-system on a word-by-word basis using a 1.7V to 2V VDD supply for

the circuitry and a 1.7V to 2V VDDQ supply for the Input/Output pins. An optional 9 V VPP

power supply is provided to speed up customer programming.

The M58WRxxxKT/B feature an asymmetrical block architecture.

• The M58WR032KT/B has an array of 71 blocks, and is divided into 4Mb banks. There

are 7 banks each containing 8 main blocks of 32 Kwords, and one parameter bank

containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.

• The M58WR064KT/B has an array of 135 blocks, and is divided into 4Mb banks. There

are 15 banks each containing 8 main blocks of 32 Kwords, and one parameter bank

containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.

The multiple bank architecture allows dual operations. While programming or erasing in

one bank, READ operations are possible in other banks. Only one bank at a time is

allowed to be in PROGRAM or erase mode. It is possible to perform burst reads that cross

bank boundaries. The bank architectures are summarized in Table 2 and Ta ble 3 and the

memory maps are shown in Figure 3 and Figure 4. The parameter blocks are located at

the top of the memory address space for the M58WR032KT and M58WR064KT, and at

the bottom for the M58WR032KB and M58WR064KB.

Each block can be erased separately. Erase can be suspended to perform PROGRAM in

any other block, and then resumed. PROGRAM can be suspended to read data in any

other block and then resumed. Each block can be programmed and erased over 100,000

cycles using the supply voltage VDD. Two enhanced factory programming commands are

available to speed up programming.

PROGRAM and erase commands are written to the command interface of the memory.

An internal PROGRAM/ERASE CONTROLLER manages the timings necessary for

PROGRAM and erase operations. The end of a PROGRAM or erase operation can be

detected and any error conditions identified in the Status Register. The command set

required to control the memory is consistent with JEDEC standards.

The device supports synchronous burst read and asynchronous read from all blocks of

the memory array; at power-up the device is configured for asynchronous read. In

synchronous burst mode, data is output on each clock cycle at frequencies of up to

66 MHz. The SYCHRONOUS BURST READ operation can be suspended and resumed.

The device features an automatic standby mode. When the bus is inactive during

ASYCHRONOUS READ operations, the device automatically switches to the automatic

standby mode. In this condition the power consumption is reduced to the standby value

IDD4 and the outputs are still driven.

The M58WRxxxKT/B feature an instant, individual block locking scheme that allows any

block to be locked or unlocked with no latency, enabling instant code and data protec-

tion. All blocks have three levels of protection. They can be locked and locked-down

individually preventing any accidental programming or erasure. There is additional

hardware protection against PROGRAM and erase. When VPP VPPLK all blocks are

protected against PROGRAM or erase. All blocks are locked at power-up.

PDF: 09005aef848ee55b / Source: 09005aef848ee58b Micron Technology, Inc., reserves the right to change products or specifications without notice.

M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Description

The device includes a Protection Register to increase the protection of a system’s design.

The Protection Register is divided into two segments: a 64-bit segment containing a

unique device number written by Micron, and a 128-bit segment one-time-program-

mable (OTP) by the user. The user programmable segment can be permanently

protected. Figure 5 shows the Protection Register memory map.

The memory is offered in either of the following packages:

• VFBGA56 7.7 × 9 mm, 8 × 7 active ball array, 0.75 mm pitch

The device is supplied with all the bits erased (set to 1).

Figure 1: Logic Diagram

Notes: 1. AMAX is equal to A20 in the M58WR032KT/B and, to A21 in the M58WR064KT/B.

Table 1: Signal Names

Signal name Function Direction

A[MAX:0]1Address inputs Inputs

DQ[15:0] Data input/outputs, command inputs I/O

CE# Chip Enable Input

OE# Output Enable Input

WE# Write Enable Input

RST# Reset Input

WP# Write Protect Input

CLK Clock Input

ADV# Latch Enable Input

WAIT Wait Output

VDD Supply voltage Input

VDDQ Supply voltage for input/output buffers Input

AI13420b

A[MAX:0](1)

WE#

DQ[15:0]

VDD

M58WR032KT

M58WR032KB

M58WR064KT

M58WR064KB

CE#

VSS

OE#

RP#

WP#

VDDQ VPP

ADV#

CLK

WAIT

VSSQ

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Description

Figure 2: VFBGA56 Connections (top view through package)

Notes: 1. Ball C3 is A21 in the M58WR064KT/B, it is not connected internally in the M58WR032KT/B.

VPP Optional supply voltage for fast PROGRAM and erase Input

VSS Ground

VSSQ Input/output supply ground

NC Not connected internally

DU Do not use

Notes:

1.AMAX is equal to A20 in the M58WR032KT/B and, to A21 in the M58WR064KT/B.

Table 1: Signal Names (Continued)

Signal name Function Direction

AI13870

DQ1

DQ13

DQ3

DQ12

DQ6

DQ8

D A1

A9A12

A15

C A2

A5A17

A18

A10

A7A19

VPP

A8A11

A13

87654321

A20

VSS VDD

CLK RST#

ADV# WE#

A14 WAIT A16 WP#

VDDQ DQ4 DQ2 CE# A0

VSS

DQ15

DQ14 DQ11 DQ10 DQ9 DQ0 OE#

DQ7 VSSQ DQ5 VDD VDDQ VSSQ

A21/

NC(1)

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Description

Table 2: M58WR032KT/B Bank Architecture

Number Bank size Parameter blocks Main blocks

Parameter bank 4Mb 8 blocks of 4 Kword 7 blocks of 32 Kword

Bank 1 4Mb - 8 blocks of 32 Kword

Bank 2 4Mb - 8 blocks of 32 Kword

Bank 3 4Mb - 8 blocks of 32 Kword

----

Bank 6 4Mb - 8 blocks of 32 Kword

Bank 7 4Mb - 8 blocks of 32 Kword

Table 3: M58WR064KT/B Bank Architecture

Number Bank size Parameter blocks Main blocks

Parameter Bank 4Mb 8 blocks of 4 Kword 7 blocks of 32 Kword

Bank 1 4Mb - 8 blocks of 32 Kword

Bank 2 4Mb - 8 blocks of 32 Kword

Bank 3 4Mb - 8 blocks of 32 Kword

----

Bank 14 4Mb - 8 blocks of 32 Kword

Bank 15 4Mb - 8 blocks of 32 Kword

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Description

Figure 3: M58WR032KT/B Memory Map

AI13421

M58WR032KT - Top Boot Block

Address lines A[20:0]

8 Main

Blocks

Bank 7

M58WR032KB - Bottom Boot Block

Address lines A[20:0]

32 KWord

000000h

007FFFh

32 KWord

038000h

03FFFFh

32 KWord

100000h

107FFFh

32 KWord

138000h

13FFFFh

32 KWord

140000h

147FFFh

32 KWord

178000h

17FFFFh

32 KWord

180000h

187FFFh

32 KWord

1B8000h

1BFFFFh

32 KWord

1C0000h

1C7FFFh

32 KWord

1F0000h

1F7FFFh

4 KWord

1F8000h

1F8FFFh

4 KWord

1FF000h

1FFFFFh

8 Parameter

Blocks

Parameter

Bank

Parameter

Bank

4 KWord

000000h

000FFFh

4KWord

007000h

007FFFh

32 KWord

008000h

00FFFFh

32 KWord

038000h

03FFFFh

32 KWord

040000h

047FFFh

32 KWord

078000h

07FFFFh

32 KWord

080000h

087FFFh

32 KWord

0B8000h

0BFFFFh

32 KWord

0C0000h

0C7FFFh

32 KWord

0F8000h

0FFFFFh

32 KWord

1C0000h

1C7FFFh

32 KWord

1F8000h

1FFFFFh

Bank 3

Bank 2

Bank 1

Bank 7

Bank 3

Bank 2

Bank 1

8 Main

Blocks

8 Main

Blocks

8 Main

Blocks

7 Main

Blocks

8 Parameter

Blocks

7 Main

Blocks

8 Main

Blocks

8 Main

Blocks

8 Main

Blocks

8 Main

Blocks

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Description

Figure 4: M58WR064KT/B Memory Map

AI13784

M58WR064KT - Top Boot Block

Address lines A[21:0]

8 Main

Blocks

Bank 15

M58WR064KB - Bottom Boot Block

Address lines A[21:0]

32 KWord

000000h

007FFFh

32 KWord

038000h

03FFFFh

32 KWord

300000h

307FFFh

32 KWord

338000h

33FFFFh

32 KWord

340000h

347FFFh

32 KWord

378000h

37FFFFh

32 KWord

380000h

387FFFh

32 KWord

3B8000h

3BFFFFh

32 KWord

3C0000h

3C7FFFh

32 KWord

3F0000h

3F7FFFh

4 KWord

3F8000h

3F8FFFh

4 KWord

3FF000h

3FFFFFh

8 Parameter

Blocks

Parameter

Bank

Parameter

Bank

4 KWord

000000h

000FFFh

4KWord

007000h

007FFFh

32 KWord

008000h

00FFFFh

32 KWord

038000h

03FFFFh

32 KWord

040000h

047FFFh

32 KWord

078000h

07FFFFh

32 KWord

080000h

087FFFh

32 KWord

0B8000h

0BFFFFh

32 KWord

0C0000h

0C7FFFh

32 KWord

0F8000h

0FFFFFh

32 KWord

3C0000h

3C7FFFh

32 KWord

3F8000h

3FFFFFh

Bank 3

Bank 2

Bank 1

Bank 15

Bank 3

Bank 2

Bank 1

8 Main

Blocks

8 Main

Blocks

8 Main

Blocks

7 Main

Blocks

8 Parameter

Blocks

7 Main

Blocks

8 Main

Blocks

8 Main

Blocks

8 Main

Blocks

8 Main

Blocks

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Signal Descriptions

See Figure 1: Logic Diagram and Table 1: Signal Names for a brief overview of the signals

connected to this device.

Address Inputs (A[MAX:0])

AMAX is the highest order address input. It is equal to A20 in the M58WR032KT/B and,

to A21 in the M58WR064KT/B. The address inputs select the cells in the memory array to

access during bus read operations. During bus write operations they control the

commands sent to the command interface of the PROGRAM/ERASE CONTROLLER.

Data Inputs/Outputs (DQ[15:0])

The data I/O output the data stored at the selected address during a bus read operation

or input a command or the data to be programmed during a bus write operation.

Chip Enable (CE#)

The Chip Enable input activates the memory control logic, input buffers, decoders and

sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active

mode. When Chip Enable is at VIH the memory is deselected, the outputs are high

impedance and the power consumption is reduced to the standby level.

Output Enable (OE#)

The Output Enable input controls data outputs during the bus read operation of the

memory.

Write Enable (WE#)

The Write Enable input controls the bus write operation of the memory’s command

interface. The data and address inputs are latched on the rising edge of Chip Enable or

Write Enable, whichever occurs first.

Write Protect (WP#)

Write Protect is an input that provides additional hardware protection for each block.

When Write Protect is at VIL, the lock-down is enabled and the protection status of the

locked-down blocks cannot be changed. When Write Protect is at VIH, the lock-down is

disabled and the locked-down blocks can be locked or unlocked. (refer to Table 16: Lock

Status).

Reset (RST#)

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the

memory is in reset mode: the outputs are high impedance and the current consumption

is reduced to the reset supply current IDD2. Refer to Table 21: DC Characteristics -

Currents for the value of IDD2. After Reset all blocks are in the locked state and the

Configuration Register is reset. When Reset is at VIH, the device is in normal operation.

Upon exiting reset mode the device enters ASYCHRONOUS READ mode, but a negative

transition of Chip Enable or Latch Enable is required to ensure valid data outputs.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Signal Descriptions

Latch Enable (ADV#)

Latch Enable latches the address bits on its rising edge. The address latch is transparent

when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable

can be kept Low (also at board level) when the Latch Enable function is not required or

supported.

Clock (CLK)

The clock input synchronizes the memory to the microcontroller during synchronous

read operations; the address is latched on a Clock edge (rising or falling, according to the

configuration settings) when Latch Enable is at VIL. Clock is ‘don't care’ during

ASYCHRONOUS READ and in WRITE operations.

Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on

the output bus are valid. This output is high impedance when Chip Enable is at VIH or

Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in

advance. The WAIT signal is not gated by Output Enable.

VDD Supply Voltage

VDD provides the power supply to the internal core of the memory device. It is the main

power supply for all operations (READ, PROGRAM and ERASE).

VDDQ Supply Voltage

VDDQ provides the power supply to the I/O pins and enables all outputs to be powered

independently of VDD. VDDQ can be tied to VDD or can use a separate supply.

VPP Program Supply Voltage

VPP is both a control input and a power supply pin. The two functions are selected by the

voltage range applied to the pin.

If VPP is kept in a low voltage range (0 V to VDDQ) VPP is seen as a control input. In this

case a voltage lower than VPPLK provides absolute protection against PROGRAM or erase,

while VPP in the VPP1 range enables these functions (see Tables 21 and 22, DC character-

istics for the relevant values). VPP is only sampled at the beginning of a PROGRAM or

erase; a change in its value after the operation has started does not have any effect and

PROGRAM or erase operations continue.

If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be

stable until the PROGRAM/ERASE algorithm is completed.

VSS Ground

VSS ground is the reference for the core supply, and must be connected to the system

ground.

VSSQ Ground

VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be

connected to VSS

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Signal Descriptions

Note: Each device in a system should have VDD, VDDQ and VPP de-coupled with a 0.1µF

ceramic capacitor close to the pin (high-frequency, inherently-low inductance capac-

itors should be as close as possible to the package). See Figure 9: AC Measurement

Load Circuit. The PCB track widths should be sufficient to carry the required VPP PRO-

GRAM and erase currents.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Bus Operations

There are six standard bus operations that control the device. These are bus read, bus

write, address latch, output disable, standby and reset. See Table 4: Bus Operations for a

summary.

Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the

memory and do not affect bus write operations.

Bus READ

Bus READ operations output the contents of the memory array, the electronic signature,

the Status Register and the common Flash interface. Both Chip Enable and Output

Enable must be at VIL in order to perform a READ operation. The Chip Enable input

should be used to enable the device. Output Enable should be used to gate data onto the

output. The data read depends on the previous command written to the memory (see

Section : Command Interface). See Figures 10, 11, 12 and 13, read AC waveforms, and

Tables 23 and 24, read AC characteristics, for details of when the output becomes valid.

Bus Write

Bus write operations write commands to the memory or latch input data to be

programmed. A bus write operation is initiated when Chip Enable and Write Enable are

at VIL with Output Enable at VIH. Commands, input data and addresses are latched on

the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can

also be latched prior to the write operation by toggling Latch Enable. In this case the

Latch Enable should be tied to VIH during the bus write operation.

See Figures 16 and 17, write AC waveforms, and Tables 25 and 26, write AC characteris-

tics for details of the timing requirements.

Address Latch

Address Latch operations input valid addresses. Both Chip enable and Latch Enable

must be at VIL during Address Latch operations. The addresses are latched on the rising

edge of Latch Enable.

Output Disable

The outputs are high impedance when the Output Enable is at VIH.

Standby

Standby disables most of the internal circuitry allowing a substantial reduction of the

current consumption. The memory is in standby when Chip Enable and Reset are at VIH.

The power consumption is reduced to the standby level and the outputs are set to high

impedance, independently from the Output Enable or Write Enable inputs. If Chip

Enable switches to VIH during a PROGRAM or erase operation, the device enters standby

mode when finished.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Bus Operations

Reset

During reset mode the memory is deselected and the outputs are high impedance. The

memory is in reset mode when Reset is at VIL. The power consumption is reduced to the

standby level, independently from the Chip Enable, Output Enable or Write Enable

inputs. If Reset is pulled to VSS during a PROGRAM or erase, this operation is aborted

and the memory content is no longer valid.

Notes: 1. X = ‘don't care’

2. WAIT signal polarity is configured using the SET CONFIGURATION REGISTER command.

3. ADV# can be tied to VIH if the valid address has been previously latched.

4. Depends on OE#.

Table 4: Bus Operations

See Note 1

Operation E G W L RP WAIT2DQ15-DQ0

Bus read VIL VIL VIH VIL3VIH Data output

Bus write VIL VIH VIL VIL3VIH Data input

Address latch VIL XV

IH VIL VIH Data output or Hi-Z 4

Output disable VIL VIH VIH XV

IH Hi-Z

Standby VIH XXXV

IH Hi-Z Hi-Z

Reset XXXXV

IL Hi-Z Hi-Z

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface

All bus write operations to the memory are interpreted by the command interface.

Commands consist of one or more sequential bus write operations. An internal

PROGRAM/ERASE CONTROLLER manages all timings and verifies the correct execution

of the PROGRAM and erase commands. The PROGRAM/ERASE CONTROLLER provides

a Status Register whose output may be read at any time to monitor the progress or the

result of the operation.

The command interface is reset to read mode when power is first applied, when exiting

from Reset, or whenever VDD is lower than VLKO. Command sequences must be followed

exactly. Any invalid combination of commands is ignored.

Refer to Table 5: Command Codes, and Appendix A, Tables 44, 45, 46 and 47, command

interface states - modify and lock tables, for a summary of the command interface.

The command interface is split into two types of commands: standard commands and

factory PROGRAM commands. The following sections explain in detail how to perform

each command.

Table 5: Command Codes

Hex Code Command

01h Block Lock Confirm

03h Set Configuration Register Confirm

10h Alternative Program Setup

20h Block Erase Setup

2Fh Block Lock-Down Confirm

30h Enhanced Factory Program Setup

35h Double Word Program Setup

40h Program Setup

50h Clear Status Register

56h Quadruple Word Program Setup

60h Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup

70h Read Status Register

75h Quadruple Enhanced Factory Program Setup

90h Read Electronic Signature

98h Read CFI Query

B0h Program/Erase Suspend

C0h Protection Register Program

D0h Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm or Enhanced Factory Program

Confirm

FFh Read Array

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Standard Commands

The following commands are the basic commands used to read, write to and configure

the device. Refer to Table 6: Standard Commands, in conjunction with the following

descriptions in this section.

READ ARRAY Command

The READ ARRAY command returns the addressed bank to READ ARRAY mode. One bus

write cycle is required to issue the READ ARRAY command and return the addressed

bank to READ ARRAY mode. Subsequent READ operations read the addressed location

and output the data. A READ ARRAY command can be issued in one bank while

programming or erasing in another bank. However, if a READ ARRAY command is issued

to a bank currently executing a PROGRAM or ERASE operation the command is

executed but the output data is not guaranteed.

READ STATUS REGISTER Command

The Status Register indicates when a PROGRAM or ERASE operation is complete and the

success or failure of operation itself. Issue a READ STATUS REGISTER command to read

the Status Register content. The READ STATUS REGISTER command can be issued at

any time, even during PROGRAM or ERASE operations.

The following READ operations output the content of the Status Register of the

addressed bank. The Status Register is latched on the falling edge of CE# or OE# signals,

and can be read until CE# or OE# returns to VIH. Either CE# or OE# must be toggled to

update the latched data. See Table 9 for the description of the Status Register bits. This

mode supports asynchronous or single synchronous reads only.

READ ELECTRONIC SIGNATURE Command

The READ ELECTRONIC SIGNATURE command reads the manufacturer and device

codes, the block locking status, the Protection Register, and the Configuration Register.

The READ ELECTRONIC SIGNATURE command consists of one write cycle to an

address within one of the banks. A subsequent READ operation in the same bank

outputs the manufacturer code, the device code, the protection status of the blocks in

the targeted bank, the Protection Register, or the Configuration Register (see Table 7).

Dual operations between the parameter bank and the electronic signature locations are

not allowed (see Table 15: Dual Operation Limitations).

If a READ ELECTRONIC SIGNATURE command is issued in a bank that is executing a

PROGRAM or ERASE operation, the bank goes into READ ELECTRONIC SIGNATURE

mode, subsequent bus read cycles output the electronic signature data, and the

PROGRAM/ERASE CONTROLLER continues to program or erase in the background.

This mode supports asynchronous or single synchronous reads only; it does not support

page mode or synchronous burst reads.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Standard Commands

READ CFI QUERY Command

The READ CFI QUERY command reads data from the common Flash interface (CFI). The

READ CFI QUERY command consists of one bus write cycle to an address within one of

the banks. Once the command is issued subsequent bus read operations in the same

bank read from the common Flash interface.

If a READ CFI QUERY command is issued in a bank that is executing a PROGRAM or

ERASE operation, the bank goes into READ CFI QUERY mode, subsequent bus read

cycles output the CFI data, and the PROGRAM/ERASE CONTROLLER continues to

PROGRAM or erase in the background. This mode supports asynchronous or single

synchronous reads only; it does not support page mode or synchronous burst reads.

The status of the other banks is not affected by the command (see Table 13). After issuing

a READ CFI QUERY command, a READ ARRAY command should be issued to the

addressed bank to return the bank to READ ARRAY mode.

Dual operations between the parameter bank and the CFI memory space are not

allowed (see Table 15: Dual Operation Limitations for details).

See : Appendix B: Common Flash Interface, Tables 34, 35, 36, 37, 38, 39, 40, 41, 42 and 43

for details on the information contained in the common Flash interface memory area.

CLEAR STATUS REGISTER Command

The CLEAR STATUS REGISTER command resets (set to ‘0’) error bits SR1, SR3, SR4 and

SR5 in the Status Register. One bus write cycle is required to issue the CLEAR STATUS

read mode of the bank.

The error bits in the Status Register do not automatically return to ‘0’ when a new

command is issued. The error bits in the Status Register should be cleared before

attempting a new PROGRAM or ERASE command.

BLOCK ERASE Command

The BLOCK ERASE command erases a block. It sets all the bits within the selected block

to 1. All previous data in the block is lost. If the block is protected then the ERASE opera-

tion aborts, the data in the block does not change, and the Status Register outputs the

error. The BLOCK ERASE command can be issued at any moment, regardless of whether

the block has been programmed or not.

Two bus write cycles are required to issue the command:

• The first bus cycle sets up the ERASE command

• The second latches the block address in the PROGRAM/ERASE CONTROLLER and

starts it

If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5

are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity

cannot be guaranteed when the ERASE operation is aborted, the block must be erased

again.

Once the command is issued, the device outputs the Status Register data when any

address within the bank is read. At the end of the operation the bank remains in READ

STATUS REGISTER mode until a READ ARRAY, READ CFI QUERY, or READ ELEC-

TRONIC SIGNATURE command is issued.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Standard Commands

During erase operations the bank containing the block being erased only accepts the

READ ARRAY, READ STATUS REGISTER, READ ELECTRONIC SIGNATURE, READ CFI

QUERY and the PROGRAM/ERASE SUSPEND commands; all other commands are

ignored. Refer to Section for detailed information about simultaneous operations

allowed in banks not being erased. Typical erase times are given in Table 17: Program,

Erase Times and Endurance Cycles.

See Appendix C: Flowcharts and Pseudo Codes, Figure 24: BLOCK ERASE Flowchart and

Pseudo Code for a suggested flowchart for using the BLOCK ERASE command.

PROGRAM Command

The memory array can be programmed word-by-word. Only one word in one bank can

be programmed at any one time. If the block is protected, the PROGRAM operation

aborts, the data in the block does not change, and the Status Register outputs the error.

Two bus write cycles are required to issue the PROGRAM command:

• The first bus cycle sets up the PROGRAM command

• The second latches the address and the data to be written and starts the PROGRAM/

ERASE CONTROLLER

After programming has started, read operations in the bank being programmed output

the Status Register content.

During PROGRAM operations the bank being programmed only accepts the READ

ARRAY, READ STATUS REGISTER, READ ELECTRONIC SIGNATURE, READ CFI QUERY

and the PROGRAM/ERASE SUSPEND commands. Refer to Section for detailed informa-

tion about simultaneous operations allowed in banks not being programmed. Typical

program times are given in Table 17: Program, Erase Times and Endurance Cycles.

Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when

the PROGRAM operation is aborted, the memory location must be reprogrammed.

See , Figure 20: Program Flowchart and Pseudo Code for the flowchart for using the

PROGRAM command.

PROGRAM/ERASE SUSPEND Command

The PROGRAM/ERASE SUSPEND command pauses a PROGRAM or BLOCK ERASE

operation.

One bus write cycle is required to issue the PROGRAM/ERASE SUSPEND command.

Once the PROGRAM/ERASE CONTROLLER has paused bits SR7, SR6 and/ or SR2 of the

Status Register are set to ‘1’. The command can be addressed to any bank.

During PROGRAM/ERASE SUSPEND the command interface accepts the PROGRAM/

ERASE RESUME, READ ARRAY (cannot read the erase-suspended block or the

PROGRAM-suspended word), READ STATUS REGISTER, READ ELECTRONIC SIGNA-

TURE, CLEAR STATUS REGISTER, and READ CFI QUERY commands. In addition, if the

suspended operation is erase then the SET CONFIGURATION REGISTER, PROGRAM,

BLOCK LOCK, BLOCK LOCK-DOWN or BLOCK UNLOCK commands are also accepted.

The block being erased may be protected by issuing the BLOCK LOCK, or BLOCK LOCK-

DOWN commands. Only the blocks not being erased may be read or programmed

correctly. When the PROGRAM/ERASE RESUME command is issued the operation

completes. Refer to Section for detailed information about simultaneous operations

allowed during PROGRAM/ERASE SUSPEND.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Standard Commands

During a PROGRAM/ERASE SUSPEND, the device is placed in standby mode by taking

Chip Enable to VIH. PROGRAM/ERASE is aborted if Reset turns to VIL.

See Appendix C: Flowcharts and Pseudo Codes, Figure 23: PROGRAM SUSPEND STATUS

and RESUME Flowchart and Pseudo Code, and Figure 25: ERASE SUSPEND and

RESUME Flowchart and Pseudo Code for flowcharts for using the PROGRAM/ERASE

SUSPEND command.

PROGRAM/ERASE RESUME Command

The PROGRAM/ERASE RESUME command restarts the PROGRAM/ERASE

CONTROLLER after a PROGRAM/ERASE SUSPEND command has paused it. One bus

write cycle is required to issue the command. The command can be written to any

address.

The PROGRAM/ERASE RESUME command does not change the read mode of the

banks. If the suspended bank is in READ STATUS REGISTER, READ ELECTRONIC

SIGNATURE, or READ CFI QUERY mode the bank remains in that mode and outputs the

corresponding data. If the bank is in READ ARRAY mode, subsequent READ operations

output invalid data.

If a PROGRAM command is issued during a block erase suspend, the ERASE cannot be

resumed until the programming operation has completed. It is possible to accumulate

suspend operations. For example, it is possible to suspend an ERASE operation, start a

programming operation, suspend the programming operation, and then read the array.

See , Figure 23: PROGRAM SUSPEND STATUS and RESUME Flowchart and Pseudo Code

and Figure 25: ERASE SUSPEND and RESUME Flowchart and Pseudo Code for flow-

charts for using the PROGRAM/ERASE RESUME command.

PROTECTION REGISTER PROGRAM Command

The PROTECTION REGISTER PROGRAM command programs the 128-bit user OTP

segment of the Protection Register and the Protection Register lock. The segment is

programmed 16 bits at a time. When shipped, all bits in the segment are set to ‘1’. The

user can only program the bits to ‘0’.

Two write cycles are required to issue the PROTECTION REGISTER PROGRAM

command:

• The first bus cycle sets up the PROTECTION REGISTER PROGRAM command.

• The second latches the address and the data to be written to the Protection Register

and starts the PROGRAM/ERASE CONTROLLER.

Read operations output the Status Register content after the programming has started.

The segment can be protected by programming bit 1 of the Protection Lock Register (see

Figure 5: Protection Register Memory Map). Attempting to program a previously

protected Protection Register results in a Status Register error. The protection of the

Protection Register is not reversible. The PROTECTION REGISTER PROGRAM cannot be

suspended. Dual operations between the parameter bank and the Protection Register

memory space are not allowed (see Table 15: Dual Operation Limitations).

SET CONFIGURATION REGISTER Command

The SET CONFIGURATION REGISTER command writes a new value to the Configura-

tion Register, which defines the burst length, type, X latency, synchronous/asynchro-

nous read mode, and the valid Clock edge configuration.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Standard Commands

Two bus write cycles are required to issue the SET CONFIGURATION REGISTER

command:

• The first cycle writes the setup command and the address corresponding to the

Configuration Register content.

• The second cycle writes the Configuration Register data and the confirm command.

Read operations output the memory array content after the SET CONFIGURATION

The value for the Configuration Register is always presented on A0-A15. CR0 is on A0,

CR1 on A1, etc.; the other address bits are ignored.

BLOCK LOCK Command

The BLOCK LOCK command locks a block and prevents PROGRAM or ERASE operations

from changing the data in it. All blocks are locked at power-up or reset.

Two bus write cycles are required to issue the BLOCK LOCK command:

• The first bus cycle sets up the BLOCK LOCK command.

• The second bus write cycle latches the block address.

The lock status can be monitored for each block using the READ ELECTRONIC SIGNA-

TURE command. Table 16 shows the lock status after issuing a BLOCK LOCK command.

The block lock bits are volatile; once set they remain set until a hardware reset or power-

down/power-up. They are cleared by a BLOCK UNLOCK command. Refer to Section :

Block Locking for a detailed explanation. See , Figure 26: Locking Operations Flowchart

and Pseudo Code for a flowchart for using the Lock command.

BLOCK UNLOCK Command

The BLOCK UNLOCK command unlocks a block, allowing the block to be programmed

or erased. Two bus write cycles are required to issue the BLOCK UNLOCK command:

• The first bus cycle sets up the BLOCK UNLOCK command.

• The second bus write cycle latches the block address.

The lock status can be monitored for each block using the READ ELECTRONIC SIGNA-

TURE command. Table 16 shows the protection status after issuing a BLOCK UNLOCK

command. Refer to Section : Block Locking for a detailed explanation and , Figure 26:

Locking Operations Flowchart and Pseudo Code for a flowchart for using the Unlock

command.

BLOCK LOCK-DOWN Command

A locked or unlocked block can be locked down by issuing the BLOCK LOCK-DOWN

command. A locked-down block cannot be programmed or erased, or have its protec-

tion status changed when WPE is low, VIL. When WP# is high, VIH, the lock-down func-

tion is disabled and the locked blocks can be individually unlocked by the BLOCK

UNLOCK command.

Two bus write cycles are required to issue the BLOCK LOCK-DOWN command:

• The first bus cycle sets up the BLOCK LOCK command.

• The second bus write cycle latches the block address.

The lock status can be monitored for each block using the READ ELECTRONIC SIGNA-

TURE command. Locked-down blocks revert to the locked (and not locked-down) state

when the device is reset on power-down. Table 16 shows the lock status after issuing a

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Standard Commands

BLOCK LOCK-DOWN command. Refer to Section : Block Locking for a detailed explana-

tion and Appendix C: Flowcharts and Pseudo Codes, Figure 26: Locking Operations

Flowchart and Pseudo Code for a flowchart for using the Lock-Down command.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Standard Commands

Notes: 1. X = ‘don't care’, WA = Word Address in targeted bank, RD = READ DATA, SRD = Status Reg-

ister Data, ESD = Electronic Signature Data, QD = Query Data, BA = Block Address, BKA =

Bank Address, PD = PROGRAM Data, PRA = Protection Register Address, PRD = Protection

2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7.

3. Any address within the bank can be used.

Table 6: Standard Commands

Commands

Cycles

Bus operations1

1st cycle 2nd cycle

Op. Add Data Op. Add Data

Read Array 1+ Write BKA FFh Read WA RD

Read Status Register 1+ Write BKA 70h Read BKA2SRD

Read Electronic Signature 1+ Write BKA 90h Read BKA2ESD

Read CFI Query 1+ Write BKA 98h Read BKA2QD

Clear Status Register 1 Write X 50h

Block Erase 2 Write BKA or BA320h Write BA D0h

Program 2 Write BKA or WA340h or 10h Write WA PD

Program/Erase Suspend 1 Write X B0h

Program/Erase Resume 1 Write X D0h

Protection Register Program 2 Write PRA C0h Write PRA PRD

Set Configuration Register 2 Write CRD 60h Write CRD 03h

Block Lock 2 Write BKA or BA360h Write BA 01h

Block Unlock 2 Write BKA or BA360h Write BA D0h

Block Lock-Down 2 Write BKA or BA360h Write BA 2Fh

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Command Interface - Standard Commands

Notes: 1. CR = Configuration Register.

Figure 5: Protection Register Memory Map

Table 7: Electronic Signature Codes

Code Address (h) Data (h)

Manufacturer code Bank address + 00 0020

Device code Top Bank address + 01 8814 (M58WR032KT)

8810 (M58WR064KT)

Bottom Bank address + 01 8815 (M58WR032KB)

8811 (M58WR064KB)

Block protection Locked Block address + 02 0001

Unlocked 0000

Locked and locked-down 0003

Unlocked and locked-down 0002

Reserved Bank address + 03 Reserved

Configuration Register Bank address + 05 CR1

Protection Register lock Numonyx factory default Bank address + 80 0002

OTP area permanently locked 0000

Protection Register Bank address + 81

Bank address + 84

Unique device number

Bank address + 85

Bank address + 8C

OTP Area

AI08149

User Programmable OTP

Unique device number

Protection Register Lock 1 0

8Ch

85h

84h

81h

80h

PROTECTION REGISTER

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Factory PROGRAM Commands

The factory PROGRAM commands are specifically designed to speed up programming.

They require VPP to be at VPPH. Refer to Table 8: Factory Program Commands in conjunc-

tion with the descriptions in this section.

The use of factory PROGRAM commands requires certain operating conditions:

•V

PP must be set to VPPH.

•V

DD must be within operating range.

•Ambient temperature, T

A must be 25°C ± 5°C.

• The targeted block must be unlocked.

DOUBLE WORD PROGRAM Command

The DOUBLE WORD PROGRAM command improves the programming throughput by

writing a page of two adjacent words in parallel. The two words must only differ for the

address A0.

If the block is protected, then the DOUBLE WORD PROGRAM operation aborts, the data

in the block does not change, and the Status Register outputs the error.

VPP must be set to VPPH during DOUBLE WORD PROGRAM, otherwise the command is

ignored and the Status Register does not output any error.

Three bus write cycles are necessary to issue the DOUBLE WORD PROGRAM command:

• The first bus cycle sets up the DOUBLE WORD PROGRAM command.

• The second bus cycle latches the address and the data of the first word to be written.

• The third bus cycle latches the address and the data of the second word to be written

and starts the PROGRAM/ERASE CONTROLLER.

READ operations in the bank being programmed output the Status Register content

after the programming has started.

During DOUBLE WORD PROGRAM operations the bank being programmed only

accepts the READ ARRAY, READ STATUS REGISTER, READ ELECTRONIC SIGNATURE

and READ CFI QUERY commands; all other commands are ignored. Dual operations are

not supported during DOUBLE WORD PROGRAM operations and the command cannot

be suspended. Typical program times are given in Table 17: Program, Erase Times and

Endurance Cycles.

Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when

the PROGRAM operation is aborted, the memory locations must be reprogrammed.

See Appendix C: Flowcharts and Pseudo Codes, Figure 21: DOUBLE WORD PROGRAM

Flowchart and Pseudo Code for the flowchart for using the DOUBLE WORD PROGRAM

command.

QUADRUPLE WORD PROGRAM Command

The QUADRUPLE WORD PROGRAM command improves the programming throughput

by writing a page of four adjacent words in parallel. The four words must only differ for

the addresses A0 and A1.

VPP must be set to VPPH during QUADRUPLE WORD PROGRAM, otherwise the

command is ignored and the Status Register does not output any error.

If the block is protected, then the QUADRUPLE WORD PROGRAM operation aborts, the

data in the block does not change, and the Status Register outputs the error.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Factory PROGRAM Commands

Five bus write cycles are necessary to issue the QUADRUPLE WORD PROGRAM

command:

• The first bus cycle sets up the DOUBLE WORD PROGRAM command.

• The second bus cycle latches the address and the data of the first word to be written.

• The third bus cycle latches the address and the data of the second word to be written.

• The fourth bus cycle latches the address and the data of the third word to be written.

• The fifth bus cycle latches the address and the data of the fourth word to be written

and starts the PROGRAM/ERASE CONTROLLER.

READ operations to the bank being programmed output the Status Register content

after the programming has started.

Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when

the PROGRAM operation is aborted, the memory locations must be reprogrammed.

During QUADRUPLE WORD PROGRAM operations the bank being programmed only

accepts the READ ARRAY, READ STATUS REGISTER, READ ELECTRONIC SIGNATURE

and READ CFI QUERY commands; all other commands are ignored.

Dual operations are not supported during QUADRUPLE WORD PROGRAM operations

and the command cannot be suspended. Typical program times are given in Table 17:

Program, Erase Times and Endurance Cycles.

See , Figure 22: QUADRUPLE WORD PROGRAM Flowchart and Pseudo Code for the

flowchart for using the QUADRUPLE WORD PROGRAM command.

ENHANCED FACTORY PROGRAM Command

The ENHANCED FACTORY PROGRAM command programs large streams of data within

any one block. It greatly reduces the total programming time when a large number of

words are written to a block at any one time.

Dual operations are not supported during the ENHANCED FACTORY PROGRAM opera-

tion and the command cannot be suspended.

For optimum performance the ENHANCED FACTORY PROGRAM commands should be

limited to a maximum of 10 PROGRAM/ERASE cycles per block. If this limit is exceeded

the internal algorithm continues to work properly but some degradation in performance

is possible. Typical program times are given in Table 17.

If the block is protected then the ENHANCED FACTORY PROGRAM operation aborts,

the data in the block does not change, and the Status Register outputs the error.

The ENHANCED FACTORY PROGRAM command has four phases: the setup phase, the

PROGRAM phase to program the data to the memory, the verify phase to check that the

data has been correctly programmed and reprogram if necessary and the exit phase.

Refer to Table 8: Factory Program Commands, and Figure 28: ENHANCED FACTORY

PROGRAM Flowchart.

Setup Phase

The ENHANCED FACTORY PROGRAM command requires two bus write operations to

initiate the command:

• The first bus cycle sets up the ENHANCED FACTORY PROGRAM command

• The second bus cycle confirms the command.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Factory PROGRAM Commands

The Status Register P/EC bit SR7 should be read to check that the P/EC is ready. After the

confirm command is issued, read operations output the Status Register data. The READ

STATUS REGISTER command must not be issued or it is interpreted as data to program.

If the second bus cycle is not EFP confirm (D0h), Status Register bits SR4 and SR5 are set

and the command aborts.

VPP value must be in the VPPH range during the confirm command, otherwise SR4 and

SR3 are set and command are aborted.

PROGRAM Phase

The PROGRAM phase requires n+1 cycles, where n is the number of words (refer to

Table 8: Factory Program Commands, and Figure 28: ENHANCED FACTORY PROGRAM

Flowchart).

Three successive steps are required to issue and execute the PROGRAM phase of the

command:

1. Use one bus write operation to latch the start address and the first word to be pro-

grammed, where the start address is the location of the first data to be programmed.

The Status Register Bank Write Status bit SR0 should be read to check that the P/EC is

ready for the next word.

2. Each subsequent word to be programmed is latched with a new bus write operation.

The address can either remain the start address, in which case the P/EC increments

the address location. Or the address can be incremented, in which case the P/EC

jumps to the new address. If any address is given that is not in the same block as the

start address, the PROGRAM phase terminates and the verify phase begins. The Status

ready for the next word.

3. Finally, after all words have been programmed, write one bus write operation to any

address outside the block containing the start address, to terminate the programming

phase.

The memory is now set to enter the verify phase.

Verify Phase

The verify phase is similar to the PROGRAM phase in that all words must be resent to the

memory for them to be checked against the programmed data. The PROGRAM/ERASE

CONTROLLER checks the stream of data with the data that was programmed in the

PROGRAM phase and reprograms the memory location, if necessary.

Three successive steps are required to execute the verify phase of the command:

1. Use one bus write operation to latch the start address and the first word to be verified.

The Status Register bit SR0 should be read to check that the PROGRAM/ERASE CON-

TROLLER is ready for the next word.

2. Each subsequent word to be verified is latched with a new bus write operation. The

words must be written in the same order as in the PROGRAM phase. The address can

remain the start address or be incremented. If any address that is not in the same

block as the start address is given, the verify phase terminates. Status Register bit SR0

should be read to check that the P/EC is ready for the next word.

3. Finally, after all words have been verified, write one bus write operation to any

address outside the block containing the start address, to terminate the verify phase.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Factory PROGRAM Commands

If the verify phase is successfully completed, the memory remains in READ STATUS

location, the error is signaled in the Status Register.

Exit Phase

Status Register P/EC bit SR7 set to ‘1’ indicates that the device has returned to read

mode. A full Status Register check should be done to ensure that the block has been

successfully programmed. See Section : Status Register for more details.

QUADRUPLE ENHANCED FACTORY PROGRAM Command

The QUADRUPLE ENHANCED FACTORY PROGRAM command programs one or more

pages of four adjacent words in parallel. The four words must only differ for the

addresses A0 and A1.

VPP must be set to VPPH during the QUADRUPLE ENHANCED FACTORY PROGRAM,

otherwise the command is ignored and the Status Register does not output any error.

Dual operations are not supported during QUADRUPLE ENHANCED FACTORY

PROGRAM operations and the command cannot be suspended.

If the block is protected then the QUADRUPLE ENHANCED FACTORY PROGRAM opera-

tion aborts, the data in the block does not change, and the Status Register outputs the

error.

The QUADRUPLE ENHANCED FACTORY PROGRAM command has four phases: the

setup phase, the load phase where the data is loaded into the buffer, the combined

PROGRAM and VERIFY phase where the loaded data is programmed to the memory and

then automatically checked and reprogrammed if necessary and the exit phase. Unlike

the ENHANCED FACTORY PROGRAM it is not necessary to resubmit the data for the

verify phase. The load phase and the PROGRAM and VERIFY phase can be repeated to

program any number of pages within the block.

Setup Phase

The QUADRUPLE ENHANCED FACTORY PROGRAM command requires one bus write

operation to initiate the load phase. After the setup command is issued, READ

operations output the Status Register data. The READ STATUS REGISTER command

must not be issued or it is interpreted as data to program.

Load Phase

The load phase requires 4 cycles to load the data (refer to Table 8: Factory Program

Commands and Figure 29: QUADRUPLE ENHANCED FACTORY PROGRAM Flowchart).

Once the first word of each page is written it is impossible to exit the load phase until all

four words have been written.

Two successive steps are required to issue and execute the load phase of the

QUADRUPLE ENHANCED FACTORY PROGRAM command.

1. Use one bus write operation to latch the start address and the first word of the first

page to be programmed, where the start address is the location of the first data to be

programmed. For subsequent pages the first word address can remain the start

address (in which case the next page is programmed) or can be any address in the

same block. If any address is given that is not in the same block as the start address,

the device enters the exit phase. For the first load phase Status Register bit SR7 should

be read after the first word has been issued to check that the command has been

accepted (bit SR7 set to ‘0’). This check is not required for subsequent load phases.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Factory PROGRAM Commands

2. Each subsequent word to be programmed is latched with a new bus write operation.

The address is only checked for the first word of each page as the order of the words to

be programmed is fixed.

The memory is now set to enter the PROGRAM and VERIFY phase.

PROGRAM and VERIFY Phase

In the PROGRAM and VERIFY phase the four words that were loaded in the load phase

are programmed in the memory array and then verified by the PROGRAM/ERASE

CONTROLLER. If any errors are found, the PROGRAM/ERASE CONTROLLER repro-

grams the location. During this phase the Status Register shows that the PROGRAM/

ERASE CONTROLLER is busy, the Status Register bit SR7 is set to ‘0’, and that the device

is not waiting for new data (Status Register bit SR0 set to ‘1’). When Status Register bit

SR0 is set to ‘0’ the PROGRAM and VERIFY phase has terminated.

Once the verify phase has successfully completed, subsequent pages in the same block

can be loaded and programmed. The device returns to the beginning of the load phase

by issuing one bus write operation to latch the address and the first of the four new

words to be programmed.

Exit Phase

Finally, after all the pages have been programmed, write one bus write operation to any

address outside the block containing the start address, to terminate the load and

PROGRAM and VERIFY phases.

Status Register bit SR7 set to ‘1’ and bit SR0 set to ‘0’ indicate that the QUADRUPLE

ENHANCED FACTORY PROGRAM command has terminated. A full Status Register

check should be done to ensure that the block has been successfully programmed. See

Section : Status Register for more details.

If the PROGRAM and VERIFY phase has successfully completed the memory returns to

read mode. If the P/EC fails to program and reprogram a given location, the error is

signaled in the Status Register.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Command Interface - Factory PROGRAM Commands

Notes: 1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block

Address.

2. Word addresses 1 and 2 must be consecutive Addresses differing only for A0.

3. Any address within the bank can be used.

4. Word addresses 1,2,3 and 4 must be consecutive addresses differing only for A0 and A1.

5. A bus read must be done between each write cycle where the data is programmed or veri-

fied to read the Status Register and check that the memory is ready to accept the next data.

n = number of words, i = number of pages to be programmed.

6. Any address within the block can be used.

7. WA1 is the start address. NOT WA1 is any address that is not in the same block as WA1.

8. Address can remain starting address WA1 or be incremented.

9. Address is only checked for the first word of each page as the order to program the words

in each page is fixed so subsequent words in each page can be written to any address.

Table 8: Factory Program Commands

Command Phase

Cycles

Bus write operations1

1st 2nd 3rd Final -1 Final

Add Data Add Data Add Data Add Data Add Data

Double Word Program23BKA or

WA1335h WA1 PD1 WA2 PD2

Quadruple Word

Program4

5BKA or

WA1356h WA1 PD1 WA2 PD2 WA3 PD3 WA4 PD4

Enhanced

Factory

Program 5

Setup,

Program

2+n+

BKA or

WA1330h BA or

WA16D0h WA1 PD1 WAn8PAn NOT

WA17

Verify, Exit n+1 WA17PD1 WA28PD2 WA38PD3 WAn8PAn NOT

WA17

Quadruple

Enhanced

Factory

Program 4,5

Setup,

first Load

5BKA or

WA1375h WA17PD1 WA29PD2 WA37PD3 WA49PD4

First Program

& Verify

Automatic

Subsequent

Loads

4WA1i

7PD1i WA2i9PD2i WA3i9PD3i WA4i9PD4i

Subsequent

Program &

Verify

Automatic

Exit 1 NOT

WA17

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Status Register

The Status Register provides information on the current or previous PROGRAM or

ERASE operations. Issue a READ STATUS REGISTER command to read the contents of

the Status Register (refer to Section : READ STATUS REGISTER Command for more

details). To output the contents, the Status Register is latched and updated on the falling

edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or

Output Enable returns to VIH. The Status Register can only be read using single asyn-

chronous or single synchronous reads. Bus read operations from any address within the

bank always read the Status Register during PROGRAM and ERASE operations, as long as

no READ ARRAY command has been issued.

The various bits convey information about the status and any errors of the operation.

Bits SR7, SR6, SR2 and SR0 provide information on the status of the device and are set

and reset by the device. Bits SR5, SR4, SR3 and SR1 provide information on errors. They

are set by the device but must be reset by issuing a CLEAR STATUS REGISTER command

or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before

issuing another command. SR7 to SR1 refer to the status of the device while SR0 refers to

the status of the addressed bank.

The bits in the Status Register are summarized in Table 9: Status Register Bits. Refer to

Table 9 in conjunction with the descriptions in the following sections.

PROGRAM/ERASE CONTROLLER STATUS Bit (SR7)

The PROGRAM/ERASE CONTROLLER status bit indicates whether the PROGRAM/ERASE

CONTROLLER is active or inactive in any bank. When the PROGRAM/ERASE

CONTROLLER status bit is Low (set to ‘0’), the PROGRAM/ERASE CONTROLLER is

active; when the bit is High (set to ‘1’), the PROGRAM/ERASE CONTROLLER is inactive,

and the device is ready to process a new command.

The PROGRAM/ERASE CONTROLLER status is Low immediately after a PROGRAM/

ERASE SUSPEND command is issued until the PROGRAM/ERASE CONTROLLER

pauses. After the PROGRAM/ERASE CONTROLLER pauses the bit is High.

During PROGRAM and ERASE operations the PROGRAM/ERASE CONTROLLER status

bit can be polled to find the end of the operation. Other bits in the Status Register should

not be tested until the PROGRAM/ERASE CONTROLLER completes the operation and

the bit is High.

After the PROGRAM/ERASE CONTROLLER completes its operation the ERASE STATUS,

PROGRAM status, VPP status and block lock status bits should be tested for errors.

ERASE SUSPEND STATUS Bit (SR6)

The ERASE SUSPEND status bit indicates that an ERASE operation has been suspended

or is going to be suspended in the addressed block. When the ERASE SUSPEND status

bit is High (set to ‘1’), a PROGRAM/ERASE SUSPEND command has been issued and the

memory is waiting for a PROGRAM/ERASE RESUME command.

The ERASE SUSPEND status should only be considered valid when the PROGRAM/

ERASE CONTROLLER status bit is High (PROGRAM/ERASE CONTROLLER inactive). SR7

is set within the erase suspend latency time of the PROGRAM/ERASE SUSPEND

command being issued, therefore, the memory may still complete the operation rather

than entering the suspend mode.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Status Register

When a PROGRAM/ERASE RESUME command is issued the ERASE SUSPEND status bit

returns Low.

ERASE STATUS Bit (SR5)

The ERASE STATUS bit identifies if the memory has failed to verify that the block has

erased correctly. When the ERASE STATUS bit is High (set to ‘1’), the PROGRAM/ERASE

CONTROLLER has applied the maximum number of pulses to the block and still failed

to verify that it has erased correctly. The ERASE STATUS bit should be read once the

PROGRAM/ERASE CONTROLLER status bit is High (PROGRAM/ERASE CONTROLLER

inactive).

Once set High, the ERASE STATUS bit can only be reset Low by a CLEAR STATUS

PROGRAM or ERASE command is issued, otherwise the new command appears to fail.

PROGRAM STATUS Bit (SR4)

The PROGRAM status bit identifies a program failure or an attempt to program a ‘1’ to an

already programmed bit when VPP = VPPH.

When the PROGRAM status bit is High (set to ‘1’), the PROGRAM/ERASE CONTROLLER

has applied the maximum number of pulses to the byte and still failed to verify that it

has programmed correctly.

After an attempt to program a '1' to an already programmed bit, the PROGRAM status bit

SR4 only goes High (set to '1') if VPP = VPPH (if VPP is different from VPPH, SR4 remains

Low (set to '0') and the attempt is not shown).

The PROGRAM status bit should be read once the PROGRAM/ERASE CONTROLLER

status bit is High (PROGRAM/ERASE CONTROLLER inactive).

Once set High, the PROGRAM status bit can only be reset Low by a CLEAR STATUS

command is issued, otherwise the new command appears to fail.

VPP Status Bit (SR3)

The VPP status bit identifies an invalid voltage on the VPP pin during PROGRAM and

ERASE operations. The VPP pin is only sampled at the beginning of a PROGRAM or

ERASE operation. Indeterminate results can occur if VPP becomes invalid during an

operation.

When the VPP status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a

valid voltage. When the VPP status bit is High (set to ‘1’), the VPP pin has a voltage that is

below the VPP lockout voltage, VPPLK, the memory is protected and PROGRAM and

ERASE operations cannot be performed.

Once set High, the VPP status bit can only be reset Low by a CLEAR STATUS REGISTER

command or a hardware reset. If set High it should be reset before a new PROGRAM or

ERASE command is issued, otherwise the new command appears to fail.

PROGRAM SUSPEND STATUS Bit (SR2)

The PROGRAM SUSPEND STATUS bit indicates that a PROGRAM operation has been

suspended in the addressed block. When the PROGRAM SUSPEND STATUS bit is High

(set to ‘1’), a PROGRAM/ERASE SUSPEND command has been issued and the memory is

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Status Register

waiting for a PROGRAM/ERASE RESUME command. The PROGRAM SUSPEND STATUS

should only be considered valid when the PROGRAM/ERASE CONTROLLER status bit is

High (PROGRAM/ERASE CONTROLLER inactive). SR2 is set within the program

suspend latency time of the PROGRAM/ERASE SUSPEND command being issued,

therefore, the memory may still complete the operation rather than entering the

suspend mode.

When a PROGRAM/ERASE RESUME command is issued, the PROGRAM SUSPEND

STATUS bit returns Low.

Block Protection Status Bit (SR1)

The block protection status bit can be used to identify if a PROGRAM or BLOCK ERASE

operation has tried to modify the contents of a locked or locked-down block.

When the block protection status bit is High (set to ‘1’), a PROGRAM or ERASE operation

has been attempted on a locked or locked-down block.

Once set High, the block protection status bit can only be reset Low by a CLEAR STATUS

command is issued, otherwise the new command appears to fail.

Bank Write/Multiple Word PROGRAM Status Bit (SR0)

The bank write status bit indicates whether the addressed bank is programming or

erasing. In ENHANCED FACTORY PROGRAM mode the multiple word PROGRAM bit

shows if a word has finished programming or verifying depending on the phase. The

bank write status bit should only be considered valid when the PROGRAM/ERASE

CONTROLLER status SR7 is Low (set to ‘0’).

When both the PROGRAM/ERASE CONTROLLER status bit and the bank write status bit

are Low (set to ‘0’), the addressed bank is executing a PROGRAM or ERASE operation.

When the PROGRAM/ERASE CONTROLLER status bit is Low (set to ‘0’) and the bank

write status bit is High (set to ‘1’), a PROGRAM or ERASE operation is being executed in a

bank other than the one being addressed.

In ENHANCED FACTORY PROGRAM mode if the multiple word program status bit is

Low (set to ‘0’), the device is ready for the next word. If the multiple word program status

bit is High (set to ‘1’) the device is not ready for the next word.

Refer to : Appendix C: Flowcharts and Pseudo Codes for using the Status Register.

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Status Register

Notes: 1. Logic level '1' is High, '0' is Low.

Table 9: Status Register Bits

Bit Name Type

Logic

level1Definition

SR7 P/EC status Status '1' Ready

'0' Busy

SR6 Erase suspend status Status '1' Erase suspended

'0' Erase in progress or completed

SR5 Erase status Error '1' Erase error

'0' Erase success

SR4 Program status Error '1' Program error

'0' Program success

SR3 VPP status Error '1' VPP invalid, abort

'0' VPP OK

SR2 Program suspend status Status '1' Program suspended

'0' Program in progress or completed

SR1 Block protection status Error '1' Program/erase on protected block, abort

'0' No operation to protected blocks

SR0 Bank write status Status '1' SR7 = ‘1’ Not allowed

SR7 = ‘0’ Program or erase operation in a bank other

than the addressed bank

'0' SR7 = ‘1’ No program or erase operation in the device

SR7 = ‘0’ Program or erase operation in addressed

bank

Multiple word program status

(enhanced factory program

mode)

Status '1' SR7 = ‘1’ Not allowed

SR7 = ‘0’ The device is NOT ready for the next word

'0' SR7 = ‘1’ The device is exiting EFP

SR7 = ‘0’ The device is ready for the next word

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Configuration Register

The Configuration Register configures the type of bus access that the memory performs.

Refer to Section : Read Modes for details on READ operations.

The Configuration Register is set through the command interface. After a reset or power-

up the device is configured for asynchronous page read (CR15 = 1). The Configuration

burst type, burst X latency, and the READ operation. Refer to Figures 6 and 7 for exam-

ples of synchronous burst configurations.

READ Select Bit (CR15)

The READ select bit, CR15, switches between asynchronous and synchronous bus read

operations. When the read select bit is set to 1, READ operations are asynchronous;

when the read select bit is set to 0, READ operations are synchronous. Synchronous

burst read is supported in both parameter and main blocks and can be performed across

banks.

On reset or power-up the read select bit is set to 1 for asynchronous access.

X-latency Bits (CR13-CR11)

The X-latency bits are used during synchronous READ operations to set the number of

clock cycles between the address being latched and the first data becoming available.

For correct operation the X-latency bits can only assume the values in Table 11: Configu-

ration Register.

Table 10shows how to set the X-latency parameter, taking into account the speed class of

the device and the frequency used to read the Flash memory in synchronous mode.

Wait Polarity Bit (CR10)

In synchronous burst mode the Wait signal indicates whether the output data are valid

or a WAIT state must be inserted. The wait polarity bit is used to set the polarity of the

Wait signal. When the wait polarity bit is set to ‘0’ the Wait signal is active Low. When the

wait polarity bit is set to ‘1’ the Wait signal is active High.

Data Output Configuration Bit (CR9)

The Data Output Configuration bit determines whether the output remains valid for one

or two clock cycles. When the data output configuration bit is 0 the output data is valid

for one clock cycle. When the data output configuration bit is 1 the output data is valid

for two clock cycles.

The data output configuration depends on the condition:

tK > tKQV + tQVK_CPU

Table 10: Latency Settings

fmax tKmin X-latency min

30 MHz 33 ns 2

40 MHz 25 ns 3

54 MHz 19 ns 4

66 MHz 15 ns 4

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Configuration Register

where tK is the clock period, tQVK_CPU is the data setup time required by the system

CPU and tKQV is the clock to data valid time. If this condition is not satisfied, the data

output configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 6: X-

latency and Data Output Configuration Example.

Wait Configuration Bit (CR8)

In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When WAIT

is asserted, data is not valid and when WAIT is de-asserted, data is valid. When the Wait

bit is 0 the Wait output pin is asserted during the wait state. When the Wait bit is 1 the

Wait output pin is asserted one clock cycle before the wait state.

Burst Type Bit (CR7)

The burst type bit configures the sequence of addresses read as sequential or inter-

leaved. When the burst type bit is 0 the memory outputs from interleaved addresses.

When the burst type bit is 1 the memory outputs from sequential addresses. See

Table 12: Burst Type Definition for the sequence of addresses output from a given

starting address in each mode.

Valid Clock Edge Bit (CR6)

The valid clock edge bit, CR6, configures the active edge of the Clock, CLK, during

SYCHRONOUS BURST READ operations. When the valid clock edge bit is 0 the falling

edge of the Clock is the active edge. When the Valid Clock Edge bit is 1 the rising edge of

the Clock is active.

Wrap Burst Bit (CR3)

The burst reads can be confined inside the 4 or 8 word boundary (wrap) or overcome the

boundary (no wrap). The wrap burst bit selects between wrap and no wrap. When the

wrap burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does

not wrap.

Burst Length Bits (CR2-CR0)

The burst length bits set the number of words to be output during a SYCHRONOUS

BURST READ operation as result of a single Address Latch cycle. They can be set for 4

words, 8 words, 16 words or continuous burst, where all the words are read sequentially.

In continuous burst mode the burst sequence can cross bank boundaries.

In continuous burst mode or in 4, 8, 16 words no-wrap, depending on the starting

address, the device asserts the WAIT output to indicate that a delay is necessary before

the data is output.

If the starting address is aligned to a 4 word boundary no wait states are needed and the

WAIT output is not asserted.

If the starting address is shifted by 1, 2 or 3 positions from the 4 word boundary, WAIT is

asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 16 word

boundary to indicate that the device needs an internal delay to read the successive

words in the array. WAIT is asserted only once during a continuous burst access. See also

Table 12: Burst Type Definition.

CR14, CR5 and CR4 are reserved for future use.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Configuration Register

Table 11: Configuration Register

Bit Description Value Description

CR15 Read select 0Synchronous read

1Asynchronous read (default at power-on)

CR14 Reserved

CR13-CR11 X-latency 010 2 clock latency

011 3 clock latency

100 4 clock latency

101 5 clock latency

111 Reserved (default)

Other configurations reserved

CR10 Wait polarity 0WAIT is active Low

1WAIT is active High (default)

CR9 Data output

configuration

0Data held for one clock cycle

1Data held for two clock cycles (default)

CR8 Wait configuration 0WAIT is active during wait state

1WAIT is active one data cycle before wait state (default)

CR7 Burst type 0Interleaved

1Sequential (default)

CR6 Valid clock edge 0Falling Clock edge

1Rising Clock edge (default)

CR5-CR4 Reserved

CR3 Wrap burst 0Wrap

1No wrap (default)

CR2-CR0 Burst length 001 4 words

010 8 words

011 16 words

111 Continuous (CR7 must be set to ‘1’) (default)

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Configuration Register

Table 12: Burst Type Definition

Mode

Start

add

4 words 8 words 16 words

Continuous

burstSequential Interleaved Sequential Interleaved Sequential Interleaved

Wrap

0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-

6-7

0-1-2-3-4-5-

6-7

0-1-2-3-4-5-6-7-

8-9-10-11-12-13-

14-15

0-1-2-3-4-5-6-

7-8-9-10-11-12-

13-14-15

0-1-2-3-4-5-6...

1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-

7-0

1-0-3-2-5-4-

7-6

1-2-3-4-5-6-7-8-

9-10-11-12-13-

14-15-0

1-0-3-2-5-4-7-

6-9-8-11-10-13-

12-15-14

1-2-3-4-5-6-7-

...15-WAIT-16-17-

18...

2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-

0-1

2-3-0-1-6-7-

4-5

2-3-4-5-6-7-8-9-

10-11-12-13-14-

15-0-1

2-3-0-1-6-7-4-

5-10-11-8-9-14-

15-12-13

2-3-4-5-6-7...15-

WAIT-WAIT-16-

17-18...

3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-

1-2

3-2-1-0-7-6-

5-4

3-4-5-6-7-8-9-10-

11-12-13-14-15-

0-1-2

3-2-1-0-7-6-5-

4-11-10-9-8-15-

14-13-12

3-4-5-6-7...15-

WAIT-WAIT-

WAIT-16-17-18...

...

7 7-4-5-6 7-6-5-4 7-0-1-2-3-4-

5-6

7-6-5-4-3-2-

1-0

7-8-9-10-11-12-

13-14-15-0-1-2-3-

4-5-6

7-6-5-4-3-2-1-

0-15-14-13-12-

11-10-9-8

7-8-9-10-11-12-

13-14-15-WAIT-

WAIT-WAIT-16-

17...

...

12 12-13-14-15-16-

17-18...

13 13-14-15-WAIT-

16-17-18...

14 14-15-WAIT-

WAIT-16-17-18....

15 15-WAIT-WAIT-

WAIT-16-17-18...

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Configuration Register

No-wrap

0 0-1-2-3 0-1-2-3-4-5-

6-7

0-1-2-3-4-5-6-7-

8-9-10-11-12-13-

14-15

Same as for

Wrap

(Wrap /No Wrap

has no effect on

Continuous

Burst)

1 1-2-3-4 1-2-3-4-5-6-

7-8

1-2-3-4-5-6-7-8-

9-10-11-12-13-

14-15-WAIT-16

2 2-3-4-5 2-3-4-5-6-7-

8-9...

2-3-4-5-6-7-8-9-

10-11-12-13-14-

15-WAIT-WAIT-

16-17

3 3-4-5-6 3-4-5-6-7-8-

9-10

3-4-5-6-7-8-9-10-

11-12-13-14-15-

WAIT-WAIT-

WAIT-16-17-18

...

7 7-8-9-10 7-8-9-10-11-

12-13-14

7-8-9-10-11-12-

13-14-15-WAIT-

WAIT-WAIT-16-

17-18-19-20-21-

...

12 12-13-14-15 12-13-14-15-

16-17-18-19

12-13-14-15-16-

17-18-19-20-21-

22-23-24-25-26-

13 13-14-15-

WAIT-16

13-14-15-

WAIT-16-17-

18-19-20

13-14-15-WAIT-

16-17-18-19-20-

21-22-23-24-25-

26-27-28

14 14-15-WAIT-

WAIT-16-17

14-15-WAIT-

WAIT-16-17-

18-19-20-21

14-15-WAIT-

WAIT-16-17-18-

19-20-21-22-23-

24-25-26-27-28-

15 15-WAIT-

WAIT-WAIT-

16-17-18

15-WAIT-

WAIT-WAIT-

16-17-18-19-

20-21-22

15-WAIT-WAIT-

WAIT-16-17-18-

19-20-21-22-23-

24-25-26-27-28-

29-30

Table 12: Burst Type Definition (Continued)

Mode

Start

add

4 words 8 words 16 words

Continuous

burst

Sequential Interleaved Sequential Interleaved Sequential Interleaved

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Configuration Register

Figure 6: X-latency and Data Output Configuration Example

Notes: 1. AMAX is equal to A20 in the M58WR032KT/B and, to A21 in the M58WR064KT/B.

2. Settings shown: X-latency = 4, data output held for one clock cycle.

Figure 7: Wait Configuration Example

Notes: 1. AMAX is equal to A20 in the M58WR032KT/B and, to A21 in the M58WR064KT/B.

Ai13422b

A[MAX:0](1) VALID ADDRESS

CLK

ADV#

DQ[15:0]

VALID DATA

X-latency

VALID DATA

tKtQVK_CPU

tKQV

1st cycle 2nd cycle 3rd cycle 4th cycle

CE#

AI13423b

A[MAX:0]

(1)

VALID ADDRESS

CLK

ADV#

DQ[15:0] VALID DATA

WAIT

CR8 = '0'

CR10 = '0'

WAIT

CR8 = '1'

CR10 = '0'

VALID DATA NOT VALID VALID DATA

CE#

WAIT

CR8 = '0'

CR10 = '1'

WAIT

CR8 = '1'

CR10 = '1'

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Read Modes

Read operations can be performed in two different ways depending on the settings in

the Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read

operation is asynchronous. If the data output is synchronized with clock, the read opera-

tion is synchronous.

The read mode and data output format are determined by the Configuration Register

(see Section : Configuration Register for details). All banks supports both asynchronous

and synchronous read operations. The multiple bank architecture allows read opera-

tions in one bank, while write operations are being executed in another (see Tables 13

and 14).

ASYCHRONOUS READ Mode

In ASYCHRONOUS READ operations the clock signal is ‘don’t care’. The device outputs

the data corresponding to the address latched, that is the memory array, Status Register,

common Flash interface or electronic signature, depending on the command issued.

CR15 in the Configuration Register must be set to ‘1’ for asynchronous operations.

In ASYCHRONOUS READ Mode a page of data is internally read and stored in a page

buffer. The page has a size of 4 words and is addressed by A0 and A1 address inputs. The

address inputs A0 and A1 are not gated by Latch Enable in ASYCHRONOUS READ Mode.

The first read operation within the page has a longer access time (Tacc, random access

time), and subsequent reads within the same page have much shorter access times. If

the page changes then the normal, longer timings apply again.

ASYCHRONOUS READ operations can be performed in two different ways, Asynchro-

nous random access read and asynchronous page read. Only asynchronous page read

takes full advantage of the internal page storage so different timings are applied.

During ASYCHRONOUS READ operations, after a bus inactivity of 150ns, the device

automatically switches to automatic standby mode. In this condition the power

consumption is reduced to the standby value and the outputs are still driven.

In ASYCHRONOUS READ mode, the WAIT signal is always asserted.

See Table 23: ASYCHRONOUS READ AC Characteristics, Figure 10: ASYCHRONOUS

RANDOM ACCESS READ AC Waveforms and Figure 11: Asynchronous Page Read AC

Waveforms for details.

SYCHRONOUS BURST READ Mode

In SYCHRONOUS BURST READ mode the data is output in bursts synchronized with the

clock. It is possible to perform burst reads across bank boundaries.

SYCHRONOUS BURST READ mode can only be used to read the memory array. For

other read operations, such as READ STATUS REGISTER, read CFI, and READ ELEC-

TRONIC SIGNATURE, SINGLE SYCHRONOUS READ or ASYCHRONOUS RANDOM

ACCESS READ must be used.

In SYCHRONOUS BURST READ mode the flow of the data output depends on parame-

ters that are configured in the Configuration Register.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Read Modes

A burst sequence is started at the first clock edge (rising or falling depending on valid

clock edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or

Chip Enable, whichever occurs last. Addresses are internally incremented and after a

delay of 2 to 5 clock cycles (X latency bits CR13-CR11) the corresponding data is output

on each clock cycle.

The number of words to be output during a SYCHRONOUS BURST READ operation can

be configured as 4, 8, 16 words, or continuous (burst length bits CR2-CR0). The data can

be configured to remain valid for one or two clock cycles (data output configuration bit

CR9).

The order of the data output can be modified through the burst type and the wrap burst

bits in the Configuration Register. The burst sequence may be configured to be sequen-

tial or interleaved (CR7). The burst reads can be confined inside the 4, 8, or 16 word

boundary (wrap) or overcome the boundary (no wrap). If the starting address is aligned

to the burst length (4, 8, or 16 words) the wrapped configuration has no impact on the

output sequence. Interleaved mode is not allowed in continuous burst read mode or

with no wrap sequences.

A WAIT signal may be asserted to indicate to the system that an output delay occurs.

This delay depends on the starting address of the burst sequence. The worst case delay

occurs when the sequence is crossing a 16 word boundary and the starting address was

at the end of a four word boundary.

WAIT is asserted during X latency, the Wait state, and at the end of 4, 8 or, 16 word burst.

It is only de-asserted when output data are valid. In continuous burst read mode a Wait

state occurs when crossing the first 16 word boundary. If the burst starting address is

aligned to a 4 word page, the Wait state does not occur.

The WAIT signal can be configured to be active Low or active High by setting CR10 in the

Configuration Register. The WAIT signal is meaningful only in SYCHRONOUS BURST

READ mode. In other modes, WAIT is always asserted (except for READ ARRAY mode).

See Table 24: Synchronous Read AC Characteristics and Figure 12: SYCHRONOUS

BURST READ AC Waveforms for details.

SYCHRONOUS BURST READ Suspend

A SYCHRONOUS BURST READ operation can be suspended, freeing the data bus for

other higher priority devices. It can be suspended during the initial access latency time

(before data is output), or after the device has output data. When the SYCHRONOUS

BURST READ operation is suspended, internal array sensing continues and any previ-

ously latched internal data is retained. A burst sequence can be suspended and resumed

as often as required as long as the operating conditions of the device are met.

A SYCHRONOUS BURST READ operation is suspended when CE# is low and the current

address has been latched (on a Latch Enable rising edge or on a valid clock edge). The

clock signal is then halted at VIH or at VIL, and OE# goes high.

When OE# becomes low again and the clock signal restarts, the SYCHRONOUS BURST

READ operation is resumed exactly where it stopped.

WAIT being gated by CE# remains active and does not revert to high-impedance when

OE# goes high. Therefore, if two or more devices are connected to the system’s READY

signal, to prevent bus contention the WAIT signal of the Flash memory should not be

directly connected to the system’s READY signal.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Read Modes

See Table 24: Synchronous Read AC Characteristics and Figure 14: SYCHRONOUS

BURST READ Suspend AC Waveforms for details.

SINGLE SYCHRONOUS READ Mode

SINGLE SYCHRONOUS READ operations are similar to SYCHRONOUS BURST READ

operations except that only the first data output after the X latency is valid. Synchronous

single reads are used to read the electronic signature, Status Register, CFI, block protec-

tion status, Configuration Register status or Protection Register status. When the

addressed bank is in read CFI, READ STATUS REGISTER or READ ELECTRONIC SIGNA-

TURE mode, the WAIT signal is always asserted.

See Table 24: Synchronous Read AC Characteristics and Figure 13: SINGLE SYCHRO-

NOUS READ AC Waveforms for details.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Dual Operations and Multiple Bank Architecture

The multiple bank architecture of the M58WRxxxKT/B provides flexibility for software

developers by allowing code and data to be split with 4Mb granularity. The dual opera-

tions feature simplifies the software management of the device and allows code to be

executed from one bank while another bank is being programmed or erased.

The dual operations feature means that while programming or erasing in one bank, read

operations are possible in another bank with zero latency (only one bank at a time is

allowed to be in PROGRAM or ERASE mode). If a Read operation is required in a bank

that is programming or erasing, the PROGRAM or ERASE operation can be suspended.

Also, if the suspended operation is ERASE then a PROGRAM command can be issued to

another block. This means the device can have one block in ERASE SUSPEND mode, one

programming, and other banks in read mode. Bus read operations are allowed in

another bank between setup and confirm cycles of PROGRAM or ERASE operations. The

combination of these features means that read operations are possible at any moment.

Dual operations between the parameter bank and either the CFI, OTP, or the electronic

signature memory space are not allowed. Table 15, however, shows dual operations that

are allowed between the CFI, OTP, electronic signature locations, and the memory array.

Tables 13 and 14 show the dual operations possible in other banks and in the same bank.

For a complete list of possible commands refer to Appendix A: Command Interface State

Tab les .

Table 13: Dual Operations Allowed in Other Banks

Status of bank

Commands allowed in another bank

Read

Array

Read

Status

Read

CFI

Query

Read

Electronic

Signature Program

Block

Erase

Program/

Erase

Suspend

Program/

Erase

Resume

Idle Yes Yes Yes Yes Yes Yes Yes Yes

Programming Yes Yes Yes Yes – – Yes –

Erasing Yes Yes Yes Yes – – Yes –

Program suspended Yes Yes Yes Yes – – – Yes

Erase suspended Yes Yes Yes Yes Yes – – Yes

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Dual Operations and Multiple Bank Architecture

Notes: 1. Not allowed in the block or word that is being erased or programmed.

2. The READ ARRAY command is accepted but the data output is no guaranteed until the pro-

gram or erase has completed.

Table 14: Dual Operations Allowed in Same Bank

Status of bank

Commands allowed in same bank

Read

Array

Read

Status

Read

CFI

Query

Read

Electronic

Signature Program

Block

Erase

Program/

Erase

Suspend

Program/

Erase

Resume

Idle Yes Yes Yes Yes Yes Yes Yes Yes

Programming –2Yes Yes Yes – – Yes –

Erasing –2Yes Yes Yes – – Yes –

Program suspended Yes1Yes Yes Yes – – – Yes

Erase suspended Yes1Yes Yes Yes Yes1–– Yes

Table 15: Dual Operation Limitations

Current status

Commands allowed

Read CFI / OTP /

Electronic

Signature

Read

Parameter

Blocks

Read Main Blocks

Located in

parameter bank

Not located in

parameter bank

Programming/erasing parameter blocks No No No Yes

Programming/

erasing main

blocks

Located in

parameter bank

Yes No No Yes

Not located in

parameter bank

Yes Yes Yes In different bank

only

Programming OTP No No No No

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Block Locking

The M58WRxxxKT/B features an instant, individual block locking scheme that enables

any block to be locked or unlocked with no latency. This locking scheme has three levels

of protection.

• Lock/unlock - this first level allows software-only control of block locking.

• Lock-down - this second level requires hardware interaction before locking can be

changed.

•V

PP VPPLK - the third level offers a complete hardware protection against program

and erase on all blocks.

The protection status of each block can be set to locked, unlocked, and lock-down.

Table 16, defines all of the possible protection states (WP#, DQ1, and DQ0), and

Figure 26, shows a flowchart for the locking operations.

Reading a Block’s Lock Status

The lock status of every block can be read in the READ ELECTRONIC SIGNATURE mode

of the device. To enter this mode write 90h to the device. Subsequent reads at the

address specified in Table 7 output the protection status of that block. The lock status is

represented by DQ0 and DQ1. DQ0 indicates the block lock/unlock status and is set by

the Lock command and cleared by the Unlock command. It is also automatically set

when entering lock-down. DQ1 indicates the lock-down status and is set by the Lock-

Down command. It cannot be cleared by software, only by a hardware reset or power-

down.

The following sections explain the operation of the locking system.

Locked State

The default status of all blocks on power-up or after a hardware reset is locked (states

(0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any

program or ERASE operations attempted on a locked block returns an error in the Status

the appropriate software commands. An unlocked block can be locked by issuing the

Lock command.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All

unlocked blocks return to the locked state after a hardware reset or when the device is

powered-down. The status of an unlocked block can be changed to locked or locked-

down using the appropriate software commands. A locked block can be unlocked by

issuing the Unlock command.

Lock-down State

Blocks that are locked-down (state (0,1,x)) are protected from PROGRAM and ERASE

operations (as for locked blocks) but their protection status cannot be changed using

software commands alone. A locked or unlocked block can be locked-down by issuing

the Lock-Down command. Locked-down blocks revert to the locked state when the

device is reset or powered-down.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Block Locking

The lock-down function is dependent on the WP# input pin. When WP#=0 (VIL), the

blocks in the lock-down state (0,1,x) are protected from program, erase and protection

status changes. When WP#=1 (VIH) the lock-down function is disabled (1,1,x) and

locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the soft-

ware command, where they can be erased and programmed. These blocks can then be

re-locked (1,1,1) and unlocked (1,1,0) as desired while WP# remains high. When WP# is

Low, blocks that were previously locked-down return to the lock-down state (0,1,x)

regardless of any changes made while WP# was High. Device reset or power-down resets

all blocks, including those in lock-down, to the locked state.

Locking Operations During Erase Suspend

Changes to block lock status can be performed during an ERASE SUSPEND by using the

standard locking command sequences to unlock, lock or lock down a block. This is

useful in the case when another block needs to be updated while an ERASE operation is

in progress.

To change block locking during an ERASE operation, first write the ERASE SUSPEND

command, then check the status register until it indicates that the ERASE operation has

been suspended. Next ,write the desired lock command sequence to a block and the lock

status changes. After completing any desired lock, read, or program operations, resume

the ERASE operation with the ERASE RESUME command.

If a block is locked or locked down during an ERASE SUSPEND of the same block, the

locking status bits change immediately. But when the ERASE is resumed, the ERASE

operation completes. Locking operations cannot be performed during a program

suspend. Refer to Appendix A: Command Interface State Tables for detailed information

on which commands are valid during ERASE SUSPEND.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Block Locking

Notes: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block)

and DQ0 (‘1’ for a locked block) as read in the READ ELECTRONIC SIGNATURE command

with A1 = VIH and A0 = VIL.

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to

WP# status.

3. A WP# transition to VIH on a locked block restores the previous DQ0 value, giving a 111 or

110.

Table 16: Lock Status

Current protection status1

(WP#, DQ1, DQ0)

Next protection status1

(WP#, DQ1, DQ0)

Current state

Program/erase

allowed

After Block Lock

command

After Block

Unlock

command

After Block

Lock-Down

command

After WP#

transition

1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0

1,0,12no 1,0,1 1,0,0 1,1,1 0,0,1

1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1

1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1

0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0

0,0,12no 0,0,1 0,0,0 0,1,1 1,0,1

0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,03

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Program and Erase Times and Endurance Cycles

The program and erase times and the number of program/ erase cycles per block are

shown in Table 17. Exact erase times may change depending on the memory array

condition. The best case is when all the bits in the block or bank are at ‘0’ (pre-

programmed). The worst case is when all the bits in the block or bank are at ‘1’ (not pre-

programmed). Usually, the system overhead is negligible with respect to the erase time.

In the M58WRxxxKT/B the maximum number of program/ erase cycles depends on the

VPP voltage supply used.

Notes: 1. TA = –40 to 85°C; VDD = VDDQ = 1.7V to 2V.

2. The difference between pre-programmed and not pre-programmed is not significant (<

30ms).

3. Values are liable to change with the external system-level overhead (command sequence

and Status Register polling execution).

4. Measurements performed at 25°C. TA = 30°C ±10°C for quadruple word, double word and

QUADRUPLE ENHANCED FACTORY PROGRAM.

Table 17: Program, Erase Times and Endurance Cycles

See Note 1

Parameter Condition Min Typ

Typical after

100 k W/E

cycles Max Unit

VPP = VDD

Erase Parameter block (4 Kword)20.3 1 2.5 s

Main block (32

Kword)

Pre-programmed 0.8 3 4 s

Not pre-programmed 14s

Program3Word 12 12 100 µs

Parameter block (4 Kword) 40 ms

Main block (32 Kword) 300 ms

Suspend latency Program 510µs

Erase 520µs

Program/Erase Cycles

(per Block)

Main blocks 100,000 cycles

Parameter blocks 100,000 cycles

VPP = VPPH

Erase Parameter block (4 Kword) 0.25 2.5 s

Main block (32 Kword) 0.8 4 s

Program3Word/ double word/ quadruple word410 100 µs

Parameter block

(4 Kword)

Quad-enhanced factory 11 ms

Enhanced factory 45 ms

Quadruple word410 ms

Word 40 ms

Main block (

32 Kword)

Quad-enhanced factory 94 ms

Enhanced factory 360 ms

Quadruple word480 ms

Word 328 ms

Bank (4Mb) Quad-enhanced factory40.75 s

Quadruple word40.65 s

Program/erase cycles

(per block)

Main blocks 1000 cycles

Parameter blocks 2500 cycles

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Maximum Ratings

Stressing the device above the ratings listed in Table 18: Absolute Maximum Ratings may

cause permanent damage to the device. These are stress ratings only and operation of

the device at these or any other conditions above those indicated in the operating

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability. Refer also to relevant

Micron quality documents.

Table 18: Absolute Maximum Ratings

Symbol Parameter

Value

UnitMin Max

TAAmbient operating temperature –40 85 °C

TBIAS Temperature under bias –40 125 °C

TSTG Storage temperature –65 155 °C

VIO Input or output voltage –0.5 VDDQ + 0.6 V

VDD Supply voltage –0.2 2.45 V

VDDQ Input/output supply voltage –0.2 2.45 V

VPP Program voltage –0.2 10 V

IOOutput short circuit current 100 mA

tVPPH Time for VPP at VPPH 100 hours

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics tables in

this section are derived from tests performed under the measurement conditions

summarized in Table 19: Operating and AC Measurement Conditions. Designers should

check that the operating conditions in their circuit match the operating conditions when

relying on the quoted parameters.

Figure 8: AC Measurement I/O Waveform

Table 19: Operating and AC Measurement Conditions

Parameter Min Max Unit

VDD supply voltage 1.7 2 V

VDDQ supply voltage 1.7 2 V

VPP supply voltage (factory environment) 8.5 9.5 V

VPP supply voltage (application environment) –0.4 VDDQ+0.4 V

Ambient operating temperature –40 85 °C

Load capacitance (CL)30 pF

Input rise and fall times 5ns

Input pulse voltages 0 to VDDQ V

Input and output timing ref. voltages VDDQ/2 V

AI06161

VDDQ

VDDQ/2

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Figure 9: AC Measurement Load Circuit

Notes: 1. Sampled only, not 100% tested.

Table 20: Capacitance

See Note 1

Symbol Parameter Test condition Min Max Unit

CIN Input capacitance VIN = 0 V 6 8 pF

COUT Output capacitance VOUT = 0 V 8 12 pF

AI06162

VDDQ

CL includes JIG capacitance

16.7kΩ

DEVICE

UNDER

TEST

0.1µF

VDD

0.1µF

VDDQ

16.7kΩ

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Notes: 1. Sampled only, not 100% tested.

2. VDD dual operation current is the sum of read and program or erase currents.

Table 21: DC Characteristics - Currents

Symbol Parameter Test condition Min Typ Max Unit

ILI Input leakage current 0V  VIN  VDDQ ±1 µA

ILO Output leakage current 0V  VOUT  VDDQ ±1 µA

IDD1 Supply current

asynchronous read (f = 5 MHz)

CE# = Vil, G = VIH 10 20 mA

Supply current

synchronous Read (f = 66 MHz)

4 word 11 20 mA

8 word 13 22 mA

16 word 15 27 mA

Continuous 17 30 mA

IDD2 Supply current

(reset)

RP# = VSS ± 0.2V 15 50 µA

IDD3 Supply current (standby) CE# = VDDQ ± 0.2V,

CLK = VSS

15 50 µA

IDD4 Supply current (automatic standby) CE# = VIL, G = VIH 15 50 µA

IDD51Supply current (program) VPP = VPPH 815mA

VPP = VDD 540mA

Supply current (erase) VPP = VPPH 815mA

VPP = VDD 10 40 mA

IDD61,2 Supply current

(dual operations)

Erase in one bank,

asynchronous read in another

bank

20 60 mA

Erase in one bank, synchronous

read (continuous burst 66

MHz) in another bank

27 70 mA

IDD71Supply current program/ erase

suspended (standby)

CE# = VDDQ ± 0.2V,

CLK = VSS

15 50 µA

IPP11VPP supply current (program) VPP = VPPH 210mA

VPP = VDD 0.2 5 µA

VPP supply current (erase) VPP = VPPH 210mA

VPP = VDD 0.2 5 µA

IPP2 VPP supply current (read) VPP = VPPH 100 400 µA

VPP  VDD 0.2 5 µA

IPP31VPP supply current (standby) VPP  VDD 0.2 5 µA

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Table 22: DC Characteristics - Voltages

Symbol Parameter Test condition Min Typ Max Unit

VIL Input low voltage –0.5 0.4 V

VIH Input high voltage VDDQ –0.4 VDDQ + 0.4 V

VOL Output low voltage IOL = 100 µA 0.1 V

VOH Output high voltage IOH = –100 µA VDDQ –0.1 V

VPP1 VPP program voltage-logic Program, erase 1.3 2.4 V

VPPH VPP program voltage factory Program, erase 8.5 9 9.5 V

VPPLK Program or erase lockout 0.4 V

VLKO VDD lock voltage 1V

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Figure 10: ASYCHRONOUS RANDOM ACCESS READ AC Waveforms

Notes: 1. AMAX is equal to A20 in the M58WR032KT/B and, to A21 in the M58WR064KT/B.

2. Write Enable, WE#, is High, WAIT is active Low.

AI13424c

tAVAV

tAVQV

tELQX

tEHQX

tGLQV

tGLQX

tGHQX

DQ[15:0]

CE#

OE#

tELQV

tEHQZ

tGHQZ

VALID

A[MAX:0](1) VALID VALID

ADV#

tELLH

tLLQV

tLLLH

tAVLH tLHAX tAXQX

WAIT

tELTV tEHTZ

Valid Address Latch Outputs Enabled Data Valid Standby

Hi-Z

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Figure 11: Asynchronous Page Read AC Waveforms

AI13425c

A[MAX:2](1)

CE#

OE#

A[1:0] VALID ADDRESS

ADV#

DQ[15:0]

VALID ADDRESSVALID ADDRESSVALID ADDRESS

VALID ADDRESS

VALID DATAVALID DATA VALID DATA VALID DATA

tLHAX

tAVLH

tLLQV

tAVQV1tGLQX

tLLLH

tELLH

WAIT

tAVAV

tELQV

tELQX

tELTV

tGLQV

(2)

Notes: 1. AMAX is equal to A20 in the M58WR032KT/B and, to A21 in the M58WR064KT/B.

2. WAIT is active Low.

Valid Address Latch Outputs

Enabled Valid Data Standby

Hi-Z

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Notes: 1. Sampled only, not 100% tested.

2. OE# may be delayed by up to tELQV - tGLQV after the falling edge of CE# without increasing tELQV.

Table 23: ASYCHRONOUS READ AC Characteristics

Symbol Alt Parameter Value Unit

Read Timings

tAVAV tRC Address Valid to Next Address Valid Min 70 ns

tAVQV tACC Address Valid to Output Valid (Random) Max 70 ns

tAVQV1 tPAGE Address Valid to Output Valid (page) Max 20 ns

tAXQX1t

OH Address Transition to Output Transition Min 0 ns

tELTV – Chip Enable Low to Wait Valid Max 14 ns

tELQV2t

CE Chip Enable Low to Output Valid Max 70 ns

tELQX1t

LZ Chip Enable Low to Output Transition Min 0 ns

tEHTZ – Chip Enable High to Wait Hi-Z Max 17 ns

tEHQX1t

OH Chip Enable High to Output Transition Min 0 ns

tEHQZ1t

HZ Chip Enable High to Output Hi-Z Max 17 ns

tGLQV2t

OE Output Enable Low to Output Valid Max 20 ns

tGLQX1t

OLZ Output Enable Low to Output Transition Min 0 ns

tGHQX1t

OH Output Enable High to Output Transition Min 0 ns

tGHQZ1t

DF Output Enable High to Output Hi-Z Max 14 ns

Latch Timings

tAVLH tAVADVH Address Valid to Latch Enable High Min 9 ns

tELLH tELADVH Chip Enable Low to Latch Enable High Min 10 ns

tLHAX tADVHAX Latch Enable High to Address Transition Min 9 ns

tLLLH tADVLADVH Latch Enable Pulse Width Min 9 ns

tLLQV tADVLQV Latch Enable Low to Output Valid (Random) Max 70 ns

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Figure 12: SYCHRONOUS BURST READ AC Waveforms

AI13426b

DQ[15:0]

CE#

OE#

A[MAX:0]

(4)

ADV#

WAIT

CLK(3)

VALID VALID

VALID ADDRESS

tLLLH

tAVLH

tGLQX

tAVKH

tLLKH

tELKH tKHAX

NOT VALID VALID

Note 1

Note 2 Note 2

tKHTX

tEHQX

tEHQZ

tGHQX

tGHQZ

Hi-Z

VALID

Note 2

tELTV tKHTV tEHTZ

Address

Latch X Latency Valid Data Flow Boundary

Crossing

Valid

Data Standby

Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.

2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.

3. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, CLK, can be configured as the active edge.

Here the active edge of CLK is the rising one.

4. AMAX is equal to A20 in the M58WR032KT/B and, to A21 in the M58WR064KT/B.

tEHEL

tKHQV tKHQX

Hi-Z

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Figure 13: SINGLE SYCHRONOUS READ AC Waveforms

DQ[15:0]

CE#

OE#

A[MAX:0]

(5)

ADV#

WAIT

(2)

CLK

(4)

VALID

NOT VALID

VALID ADDRESS

tLLLH

tAVLH

tGLQV

tAVKH

tLLKH

tELKH tKHAX

NOT VALID

Note 1

tEHQX

tEHQZ

tGH

Hi-Z

NOT VALID

Note 3

tELTV

tKHQV

Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.

2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.

3. WAIT is always asserted when addressed bank is in Read CFI, Read SR or Read electronic signature mode.

WAIT signals valid data if the addressed bank is in Read Array mode.

4. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, CLK, can be configured as the

Here the active edge of CLK is the rising one.

5. AMAX is equal to A20 in the M58WR032KT/B and, to A21 in the M58WR064KT/B.

NOT VALID

tGLQX

tEHEL

tKHTV

Hi-Z

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Figure 14: SYCHRONOUS BURST READ Suspend AC Waveforms

AI13428b

DQ[15:0]

CE#

OE#

A[MAX:0}(5)

ADV#

WAIT(2)

CLK(4)

VALID VALID

VALID ADDRESS

tLLLH

tAVLH

tGLQV

tAVKH

tLLKH

tELKH tKHAX

VALID VALID

Note 1

tEHQX

tEHQZ

tGHQX

Hi-Z

tELTV

tKHQV

tEHTZ

Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.

3. The CLOCK signal can be held High or Low

4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, CLK, can be configured as the active edge.

Here, the active edge of K is the rising one.

5. AMAX is equal to A20 in the M58WR032KT/B and, to A21 in the M58WR064KT/B.

tGLQX

tEHEL

tGHQZ

Note 3

Hi-Z

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Figure 15: Clock Input AC Waveform

Notes: 1. Sampled only, not 100% tested.

2. For other timings please refer to Table Table 23: ASYCHRONOUS READ AC Characteristics.

Table 24: Synchronous Read AC Characteristics

See Notes 1,2

Symbol Alt Parameter Value Unit

Synchronous read timings

tAVKH tAVCLKH Address Valid to Clock High Min 9 ns

tELKH tELCLKH Chip Enable Low to Clock High Min 9 ns

tELTV – Chip Enable Low to Wait Valid Max 14 ns

tEHEL – Chip Enable Pulse Width (subsequent

synchronous reads)

Min 14 ns

tEHTZ – Chip Enable High to Wait Hi-Z Max 14 ns

tKHAX tCLKHAX Clock High to Address Transition Min 9 ns

tKHQV

tKHTV

tCLKHQV Clock High to Output Valid

Clock High to WAIT Valid

Max 11 ns

tKHQX

tKHTX

tCLKHQX Clock High to Output Transition

Clock High to WAIT Transition

Min 3 ns

tLLKH tADVLCLKH Latch Enable Low to Clock High Min 9 ns

Clock specifications

tKHKH tCLK Clock Period (f=66MHz) Min 15 ns

tKHKL

tKLKH

–Clock High to Clock Low

Clock Low to Clock High

Min 4.5 ns

–Clock Fall or Rise Time Max 3 ns

AI06981

tKHKH

tf tr

tKHKL

tKLKH

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Figure 16: Write AC Waveforms, Write Enable Controlled

CE#

OE#

WE#

DQ[15:0] COMMAND CMD or DATA STATUS REGISTER

VPP

VALID ADDRESSA[MAX:0]

(1)

tAVAV

tQVVPL

tAVWH tWHAX

PROGRAM OR ERASE

tELWL tWHEH

tWHDXtDVWH

tWLWH

tWHWL

tVPHWH

SET-UP COMMAND CONFIRM COMMAND

OR DATA INPUT

STATUS REGISTER

READ

1st POLLING

tELQV

Ai13429b

tWPHWH

WP#

tWHGL

tQVWPL

tWHEL

BANK ADDRESS VALID ADDRESS

ADV#

tAVLH

tLLLH

tELLH

tLHAX

tGHWL

tWHWPL

tWHVPL

tELKV

CLK

tWHLL

tWHAV

Note 1: Amax is equal to A20 in the M58WR032KT/B and, to A21 in the M58WR064KT/B.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Notes: 1. Sampled only, not 100% tested.

2. Meaningful only if ADV# is always kept low.

3. tWHEL and tWHLL have this value when reading in the targeted bank or when reading fol-

lowing a SET CONFIGURATION REGISTER command. System designers should take this into

account and may insert a software No-Op instruction to delay the first read in the same

bank after issuing any command and to delay the first read to any address after issuing a

SET CONFIGURATION REGISTER command. If the first read after the command is a READ

ARRAY operation in a different bank and no changes to the Configuration Register have

been issued, tWHEL and tWHLL are 0ns.

Table 25: Write AC Characteristics, Write Enable Controlled

See Note 1

Symbol Alt Parameter Value Unit

Write Enable controlled timings

tAVAV tWC Address Valid to Next Address Valid Min 70 ns

tAVLH Address Valid to Latch Enable High Min 9 ns

tAVWH2Address Valid to Write Enable High Min 45 ns

tDVWH tDS Data Valid to Write Enable High Min 45 ns

tELLH Chip Enable Low to Latch Enable High Min 10 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 ns

tELQV Chip Enable Low to Output Valid Min 70 ns

tELKV Chip Enable Low to Clock Valid Min 9 ns

tGHWL Output Enable High to Write Enable Low Min 17 ns

tLHAX Latch Enable High to Address Transition Min 9 ns

tLLLH Latch Enable Pulse Width Min 9 ns

tWHAV2Write Enable High to Address Valid Min 0 ns

tWHAX2t

AH Write Enable High to Address Transition Min 0 ns

tWHDX tDH Write Enable High to Input Transition Min 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 ns

tWHEL3Write Enable High to Chip Enable Low Min 25 ns

tWHGL Write Enable High to Output Enable Low Min 0 ns

tWHLL3Write Enable High to Latch Enable Low Min 25 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 25 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 ns

Protection timings

tQVVPL Output (Status Register) Valid to VPP Low Min 0 ns

tQVWPL Output (Status Register) Valid to Write Protect Low Min 0 ns

tVPHWH tVPS VPP High to Write Enable High Min 200 ns

tWHVPL Write Enable High to VPP Low Min 200 ns

tWHWPL Write Enable High to Write Protect Low Min 200 ns

tWPHWH Write Protect High to Write Enable High Min 200 ns

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Figure 17: Write AC Waveforms, Chip Enable Controlled

WE#

OE#

CE#

D[15:0] COMMAND CMD or DATA STATUS R

VPP

VALID ADDRESSA[MAX:0]

(1)

tAVAV

tAVEH tEHAX

PROGRAM OR ERASE

tWLEL

tEHWH

tEHDX

tDVEH

tELEH

tEHEL

tVPHEH

SET-UP COMMAND CONFIRM COMMAND

OR DATA INPUT

STATUS REGISTE

READ

1st POLLING

tELQV

tWPHEH

WP#

tEHGL

tWHEL

BANK ADDRESS VALID ADDRESS

ADV#

tAVLH

tLLLH

tLHAX

tGHEL

tEHWPL

tEHVPL

tELKV

CLK

tELLH

Note 1: AMAX is equal to A20 in the M58WR032KT/B and, to A21 in the M58WR064KT/B.

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Notes: 1. Sampled only, not 100% tested.

2. tWHEL has this value when reading in the targeted bank or when reading following a SET

CONFIGURATION REGISTER command. System designers should take this into account and

may insert a software No-Op instruction to delay the first read in the same bank after issu-

ing any command and to delay the first read to any address after issuing a SET CONFIGURA-

TION REGISTER command. If the first read after the command is a READ ARRAY operation in

a different bank and no changes to the Configuration Register have been issued, tWHEL is

0ns.

Table 26: Write AC Characteristics, Chip Enable Controlled

See Note 1

Symbol Alt Parameter Value Unit

Chip Enable controlled timings

tAVAV tWC Address Valid to Next Address Valid Min 70 ns

tAVEH Address Valid to Chip Enable High Min 45 ns

tAVLH Address Valid to Latch Enable High Min 9 ns

tDVEH tDS Data Valid to Chip Enable High Min 45 ns

tEHAX tAH Chip Enable High to Address Transition Min 0 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 25 ns

tEHGL Chip Enable High to Output Enable Low Min 0 ns

tEHWH tCH Chip Enable High to Write Enable High Min 0 ns

tELKV Chip Enable Low to Clock Valid Min 9 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 ns

tELLH Chip Enable Low to Latch Enable High Min 10 ns

tELQV Chip Enable Low to Output Valid Min 70 ns

tGHEL Output Enable High to Chip Enable Low Min 17 ns

tLHAX Latch Enable High to Address Transition Min 9 ns

tLLLH Latch Enable Pulse Width Min 9 ns

tWHEL2Write Enable High to Chip Enable Low Min 25 ns

tWLEL tCS Write Enable Low to Chip Enable Low Min 0 ns

Protection timings

tEHVPL Chip Enable High to VPP Low Min 200 ns

tEHWPL Chip Enable High to Write Protect Low Min 200 ns

tQVVPL Output (Status Register) Valid to VPP Low Min 0 ns

tQVWPL Output (Status Register) Valid to Write Protect Low Min 0 ns

tVPHEH tVPS VPP High to Chip Enable High Min 200 ns

tWPHEH Write Protect High to Chip Enable High Min 200 ns

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

DC and AC Parameters

Figure 18. Reset and Power-up AC Waveforms

Notes: 1. The device Reset is possible but not guaranteed if tPLPH < 50ns.

2. Sampled only, not 100% tested.

3. It is important to assert RP# in order to allow proper CPU initialization during power-up or

reset.

Table 27: Reset and Power-up AC Characteristics

Symbol Parameter Test condition Value Unit

tPLWL

tPLEL

tPLGL

tPLLL

Reset Low to Write Enable Low,

Reset Low to Chip Enable Low,

Reset Low to Output Enable Low,

Reset Low to Latch Enable Low

During program Min 10 µs

During erase Min 20 µs

Other conditions Min 80 ns

tPHWL

tPHEL

tPHGL

tPHLL

Reset High to Write Enable Low

Reset High to Chip Enable Low

Reset High to Output Enable Low

Reset High to Latch Enable Low

Min 30 ns

tPLPH1,2 RP# pulse width Min 50 ns

tVDHPH3Supply Voltages High to Reset High Min 200 µs

AI06976

WE#, CE#, OE# ADV#

RP#

VDD, VDDQ

tVDHPH tPLPH

Power-Up Reset

tPLWL

tPLEL

tPLGL

tPLLL

tPHWL

tPHEL

tPHGL

tPHLL

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Package Dimensions

To meet environmental requirements, Micron offers the M58WRxxxKT/B in RoHS

compliant packages, which have a lead-free, second-level interconnect. In compliance

with JEDEC Standard JESD97, the category of second-level interconnect is marked on

the package and on the inner box label.

The maximum ratings related to soldering conditions are also marked on the inner box

label.

Figure 19: VFBGA56 7.7 × 9 mm - 8 × 7 Active Ball Array, 0.75 mm, Package Outline

Notes: 1. Drawing is not to scale.

E1E

BGA-Z38

ddd

FE SD

BALL "A1"

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Package Dimensions

Table 28: VFBGA56 7.7 × 9 mm - 8 × 7 Active Ball Array, 0.75 mm, Package Mechanical Data

Symbol

Millimeters

Typ Min Max

A1.000

A1 0.200

A2 0.660

b 0.350 0.300 0.400

D 7.700 7.600 7.800

D1 5.250 – –

ddd 0.080

e 0.750 – –

E 9.000 8.900 9.100

E1 4.500 – –

FD 1.225 – –

FE 2.250 – –

SD 0.375 – –

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Part numbering

Devices are shipped from the factory with the memory content bits erased to 1. For a list of available options (speed,

etc.) or for further information on any aspect of this device, please contact the nearest Micron sales office.

Table 29: Ordering Information Scheme

Example: M58WR032KT 70 ZB 6 E

Device type

M58

Architecture

W = Multiple bank, burst mode

Operating voltage

R = VDD = VDDQ = 1.7V to 2V

Density

032 = 32Mb (×16)

064 = 64Mb (×16)

Technology

K = 65nm technology

Parameter bank location

T = top boot

B = bottom boot

Speed

70 = 70ns

7A = Automotive Certified –40 to 85°C

Package

ZB = VFBGA56 7.7 × 9 mm, 0.75mm pitch

Temperature range

6 = –40 to 85°C

Options

E = RoHS compliant, standard packing

F = RoHS compliant, tape and reel packing

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Table 30: Top Boot Block Addresses, M58WR032KT

Bank1#Size (Kword) Address range

Parameter bank

0 4 1FF000-1FFFFF

1 4 1FE000-1FEFFF

2 4 1FD000-1FDFFF

3 4 1FC000-1FCFFF

4 4 1FB000-1FBFFF

5 4 1FA000-1FAFFF

6 4 1F9000-1F9FFF

7 4 1F8000-1F8FFF

8 32 1F0000-1F7FFF

9 32 1E8000-1EFFFF

10 32 1E0000-1E7FFF

11 32 1D8000-1DFFFF

12 32 1D0000-1D7FFF

13 32 1C8000-1CFFFF

14 32 1C0000-1C7FFF

Bank 1

15 32 1B8000-1BFFFF

16 32 1B0000-1B7FFF

17 32 1A8000-1AFFFF

18 32 1A0000-1A7FFF

19 32 198000-19FFFF

20 32 190000-197FFF

21 32 188000-18FFFF

22 32 180000-187FFF

Bank 2

23 32 178000-17FFFF

24 32 170000-177FFF

25 32 168000-16FFFF

26 32 160000-167FFF

27 32 158000-15FFFF

28 32 150000-157FFF

29 32 148000-14FFFF

30 32 140000-147FFF

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Bank 3

31 32 138000-13FFFF

32 32 130000-137FFF

33 32 128000-12FFFF

34 32 120000-127FFF

35 32 118000-11FFFF

36 32 110000-117FFF

37 32 108000-10FFFF

38 32 100000-107FFF

Bank 4

39 32 0F8000-0FFFFF

40 32 0F0000-0F7FFF

41 32 0E8000-0EFFFF

42 32 0E0000-0E7FFF

43 32 0D8000-0DFFFF

44 32 0D0000-0D7FFF

45 32 0C8000-0CFFFF

46 32 0C0000-0C7FFF

Bank 5

47 32 0B8000-0BFFFF

48 32 0B0000-0B7FFF

49 32 0A8000-0AFFFF

50 32 0A0000-0A7FFF

51 32 098000-09FFFF

52 32 090000-097FFF

53 32 088000-08FFFF

54 32 080000-087FFF

Bank 6

55 32 078000-07FFFF

56 32 070000-077FFF

57 32 068000-06FFFF

58 32 060000-067FFF

59 32 058000-05FFFF

60 32 050000-057FFF

61 32 048000-04FFFF

62 32 040000-047FFF

Table 30: Top Boot Block Addresses, M58WR032KT (Continued)

Bank1#Size (Kword) Address range

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Notes: 1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of

main blocks only; Bank Region 2 contains the banks that are made up of the parameter and

main blocks (parameter bank).

Bank 7

63 32 038000-03FFFF

64 32 030000-037FFF

65 32 028000-02FFFF

66 32 020000-027FFF

67 32 018000-01FFFF

68 32 010000-017FFF

69 32 008000-00FFFF

70 32 000000-007FFF

Table 31: Bottom Boot Block Addresses, M58WR032KB

Bank1#Size (Kword) Address range

Bank 7

70 32 1F8000-1FFFFF

69 32 1F0000-1F7FFF

68 32 1E8000-1EFFFF

67 32 1E0000-1E7FFF

66 32 1D8000-1DFFFF

65 32 1D0000-1D7FFF

64 32 1C8000-1CFFFF

63 32 1C0000-1C7FFF

Bank 6

62 32 1B8000-1BFFFF

61 32 1B0000-1B7FFF

60 32 1A8000-1AFFFF

59 32 1A0000-1A7FFF

58 32 198000-19FFFF

57 32 190000-197FFF

56 32 188000-18FFFF

55 32 180000-187FFF

Table 30: Top Boot Block Addresses, M58WR032KT (Continued)

Bank1#Size (Kword) Address range

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Bank 5

54 32 178000-17FFFF

53 32 170000-177FFF

52 32 168000-16FFFF

51 32 160000-167FFF

50 32 158000-15FFFF

49 32 150000-157FFF

48 32 148000-14FFFF

47 32 140000-147FFF

Bank 4

46 32 138000-13FFFF

45 32 130000-137FFF

44 32 128000-12FFFF

43 32 120000-127FFF

42 32 118000-11FFFF

41 32 110000-117FFF

40 32 108000-10FFFF

39 32 100000-107FFF

Bank 3

38 32 0F8000-0FFFFF

37 32 0F0000-0F7FFF

36 32 0E8000-0EFFFF

35 32 0E0000-0E7FFF

34 32 0D8000-0DFFFF

33 32 0D0000-0D7FFF

32 32 0C8000-0CFFFF

31 32 0C0000-0C7FFF

Bank 2

30 32 0B8000-0BFFFF

29 32 0B0000-0B7FFF

28 32 0A8000-0AFFFF

27 32 0A0000-0A7FFF

26 32 098000-09FFFF

25 32 090000-097FFF

24 32 088000-08FFFF

23 32 080000-087FFF

Table 31: Bottom Boot Block Addresses, M58WR032KB (Continued)

Bank1#Size (Kword) Address range

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Notes: 1. There are two bank regions: bank region 2 contains all the banks that are made up of main

blocks only; bank region 1 contains the banks that are made up of the parameter and main

blocks (parameter bank).

Bank 1

22 32 078000-07FFFF

21 32 070000-077FFF

20 32 068000-06FFFF

19 32 060000-067FFF

18 32 058000-05FFFF

17 32 050000-057FFF

16 32 048000-04FFFF

15 32 040000-047FFF

Parameter Bank

14 32 038000-03FFFF

13 32 030000-037FFF

12 32 028000-02FFFF

11 32 020000-027FFF

10 32 018000-01FFFF

9 32 010000-017FFF

8 32 008000-00FFFF

7 4 007000-007FFF

6 4 006000-006FFF

5 4 005000-005FFF

4 4 004000-004FFF

3 4 003000-003FFF

2 4 002000-002FFF

1 4 001000-001FFF

0 4 000000-000FFF

Table 31: Bottom Boot Block Addresses, M58WR032KB (Continued)

Bank1#Size (Kword) Address range

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Table 32: Top Boot Block Addresses, M58WR064KT

Bank1#Size (Kword) Address range

Parameter bank

0 4 3FF000-3FFFFF

1 4 3FE000-3FEFFF

2 4 3FD000-3FDFFF

3 4 3FC000-3FCFFF

4 4 3FB000-3FBFFF

5 4 3FA000-3FAFFF

6 4 3F9000-3F9FFF

7 4 3F8000-3F8FFF

8 32 3F0000-3F7FFF

9 32 3E8000-3EFFFF

10 32 3E0000-3E7FFF

11 32 3D8000-3DFFFF

12 32 3D0000-3D7FFF

13 32 3C8000-3CFFFF

14 32 3C0000-3C7FFF

Bank 1

15 32 3B8000-3BFFFF

16 32 3B0000-3B7FFF

17 32 3A8000-3AFFFF

18 32 3A0000-3A7FFF

19 32 398000-39FFFF

20 32 390000-397FFF

21 32 388000-38FFFF

22 32 380000-387FFF

Bank 2

23 32 378000-37FFFF

24 32 370000-377FFF

25 32 368000-36FFFF

26 32 360000-367FFF

27 32 358000-35FFFF

28 32 350000-357FFF

29 32 348000-34FFFF

30 32 340000-347FFF

Bank 3

31 32 338000-33FFFF

32 32 330000-337FFF

33 32 328000-32FFFF

34 32 320000-327FFF

35 32 318000-31FFFF

36 32 310000-317FFF

37 32 308000-30FFFF

38 32 300000-307FFF

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Bank 4

39 32 2F8000-2FFFFF

40 32 2F0000-2F7FFF

41 32 2E8000-2EFFFF

42 32 2E0000-2E7FFF

43 32 2D8000-2DFFFF

44 32 2D0000-2D7FFF

45 32 2C8000-2CFFFF

46 32 2C0000-2C7FFF

Bank 5

47 32 2B8000-2BFFFF

48 32 2B0000-2B7FFF

49 32 2A8000-2AFFFF

50 32 2A0000-2A7FFF

51 32 298000-29FFFF

52 32 290000-297FFF

53 32 288000-28FFFF

54 32 280000-287FFF

Bank 6

55 32 278000-27FFFF

56 32 270000-277FFF

57 32 268000-26FFFF

58 32 260000-267FFF

59 32 258000-25FFFF

60 32 250000-257FFF

61 32 248000-24FFFF

62 32 240000-247FFF

Bank 7

63 32 238000-23FFFF

64 32 230000-237FFF

65 32 228000-22FFFF

66 32 220000-227FFF

67 32 218000-21FFFF

68 32 210000-217FFF

69 32 208000-20FFFF

70 32 200000-207FFF

Bank 8

71 32 1F8000-1FFFFF

72 32 1F0000-1F7FFF

73 32 1E8000-1EFFFF

74 32 1E0000-1E7FFF

75 32 1D8000-1DFFFF

76 32 1D0000-1D7FFF

77 32 1C8000-1CFFFF

78 32 1C0000-1C7FFF

Table 32: Top Boot Block Addresses, M58WR064KT (Continued)

Bank1#Size (Kword) Address range

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Bank 9

79 32 1B8000-1BFFFF

80 32 1B0000-1B7FFF

81 32 1A8000-1AFFFF

82 32 1A0000-1A7FFF

83 32 198000-19FFFF

84 32 190000-197FFF

85 32 188000-18FFFF

86 32 180000-187FFF

Bank 10

87 32 178000-17FFFF

88 32 170000-177FFF

89 32 168000-16FFFF

90 32 160000-167FFF

91 32 158000-15FFFF

92 32 150000-157FFF

93 32 148000-14FFFF

94 32 140000-147FFF

Bank 11

95 32 138000-13FFFF

96 32 130000-137FFF

97 32 128000-12FFFF

98 32 120000-127FFF

99 32 118000-11FFFF

100 32 110000-117FFF

101 32 108000-10FFFF

102 32 100000-107FFF

Bank 12

103 32 0F8000-0FFFFF

104 32 0F0000-0F7FFF

105 32 0E8000-0EFFFF

106 32 0E0000-0E7FFF

107 32 0D8000-0DFFFF

108 32 0D0000-0D7FFF

109 32 0C8000-0CFFFF

110 32 0C0000-0C7FFF

Bank 13

111 32 0B8000-0BFFFF

112 32 0B0000-0B7FFF

113 32 0A8000-0AFFFF

114 32 0A0000-0A7FFF

115 32 098000-09FFFF

116 32 090000-097FFF

117 32 088000-08FFFF

118 32 080000-087FFF

Table 32: Top Boot Block Addresses, M58WR064KT (Continued)

Bank1#Size (Kword) Address range

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Notes: 1. There are two bank regions: bank region 1 contains all the banks that are made up of main

blocks only; bank region 2 contains the banks that are made up of the parameter and main

blocks (parameter bank).

Bank 14

119 32 078000-07FFFF

120 32 070000-077FFF

121 32 068000-06FFFF

122 32 060000-067FFF

123 32 058000-05FFFF

124 32 050000-057FFF

125 32 048000-04FFFF

126 32 040000-047FFF

Bank 15

127 32 038000-03FFFF

128 32 030000-037FFF

129 32 028000-02FFFF

130 32 020000-027FFF

131 32 018000-01FFFF

132 32 010000-017FFF

133 32 008000-00FFFF

134 32 000000-007FFF

Table 33: Bottom Boot Block Addresses, M58WR064KB

Bank1#Size (Kword) Address range

Bank 15

134 32 3F8000-3FFFFF

133 32 3F0000-3F7FFF

132 32 3E8000-3EFFFF

131 32 3E0000-3E7FFF

130 32 3D8000-3DFFFF

129 32 3D0000-3D7FFF

128 32 3C8000-3CFFFF

127 32 3C0000-3C7FFF

Bank 14

126 32 3B8000-3BFFFF

125 32 3B0000-3B7FFF

124 32 3A8000-3AFFFF

123 32 3A0000-3A7FFF

122 32 398000-39FFFF

121 32 390000-397FFF

120 32 388000-38FFFF

119 32 380000-387FFF

Table 32: Top Boot Block Addresses, M58WR064KT (Continued)

Bank1#Size (Kword) Address range

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Bank 13

118 32 378000-37FFFF

117 32 370000-377FFF

116 32 368000-36FFFF

115 32 360000-367FFF

114 32 358000-35FFFF

113 32 350000-357FFF

112 32 348000-34FFFF

111 32 340000-347FFF

Bank 12

110 32 338000-33FFFF

109 32 330000-337FFF

108 32 328000-32FFFF

107 32 320000-327FFF

106 32 318000-31FFFF

105 32 310000-317FFF

104 32 308000-30FFFF

103 32 300000-307FFF

Bank 11

102 32 2F8000-2FFFFF

101 32 2F0000-2F7FFF

100 32 2E8000-2EFFFF

99 32 2E0000-2E7FFF

98 32 2D8000-2DFFFF

97 32 2D0000-2D7FFF

96 32 2C8000-2CFFFF

95 32 2C0000-2C7FFF

Bank 10

94 32 2B8000-2BFFFF

93 32 2B0000-2B7FFF

92 32 2A8000-2AFFFF

91 32 2A0000-2A7FFF

90 32 298000-29FFFF

89 32 290000-297FFF

88 32 288000-28FFFF

87 32 280000-287FFF

Table 33: Bottom Boot Block Addresses, M58WR064KB (Continued)

Bank1#Size (Kword) Address range

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Bank 9

86 32 278000-27FFFF

85 32 270000-277FFF

84 32 268000-26FFFF

83 32 260000-267FFF

82 32 258000-25FFFF

81 32 250000-257FFF

80 32 248000-24FFFF

79 32 240000-247FFF

Bank 8

78 32 238000-23FFFF

77 32 230000-237FFF

76 32 228000-22FFFF

75 32 220000-227FFF

74 32 218000-21FFFF

73 32 210000-217FFF

72 32 208000-20FFFF

71 32 200000-207FFF

Bank 7

70 32 1F8000-1FFFFF

69 32 1F0000-1F7FFF

68 32 1E8000-1EFFFF

67 32 1E0000-1E7FFF

66 32 1D8000-1DFFFF

65 32 1D0000-1D7FFF

64 32 1C8000-1CFFFF

63 32 1C0000-1C7FFF

Bank 6

62 32 1B8000-1BFFFF

61 32 1B0000-1B7FFF

60 32 1A8000-1AFFFF

59 32 1A0000-1A7FFF

58 32 198000-19FFFF

57 32 190000-197FFF

56 32 188000-18FFFF

55 32 180000-187FFF

Table 33: Bottom Boot Block Addresses, M58WR064KB (Continued)

Bank1#Size (Kword) Address range

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Bank 5

54 32 178000-17FFFF

53 32 170000-177FFF

52 32 168000-16FFFF

51 32 160000-167FFF

50 32 158000-15FFFF

49 32 150000-157FFF

48 32 148000-14FFFF

47 32 140000-147FFF

Bank 4

46 32 138000-13FFFF

45 32 130000-137FFF

44 32 128000-12FFFF

43 32 120000-127FFF

42 32 118000-11FFFF

41 32 110000-117FFF

40 32 108000-10FFFF

39 32 100000-107FFF

Bank 3

38 32 0F8000-0FFFFF

37 32 0F0000-0F7FFF

36 32 0E8000-0EFFFF

35 32 0E0000-0E7FFF

34 32 0D8000-0DFFFF

33 32 0D0000-0D7FFF

32 32 0C8000-0CFFFF

31 32 0C0000-0C7FFF

Bank 2

30 32 0B8000-0BFFFF

29 32 0B0000-0B7FFF

28 32 0A8000-0AFFFF

27 32 0A0000-0A7FFF

26 32 098000-09FFFF

25 32 090000-097FFF

24 32 088000-08FFFF

23 32 080000-087FFF

Table 33: Bottom Boot Block Addresses, M58WR064KB (Continued)

Bank1#Size (Kword) Address range

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix A: Block Address Tables

Notes: 1. There are two bank regions: bank region 2 contains all the banks that are made up of main

blocks only; bank region 1 contains the banks that are made up of the parameter and main

blocks (parameter bank).

Bank 1

22 32 078000-07FFFF

21 32 070000-077FFF

20 32 068000-06FFFF

19 32 060000-067FFF

18 32 058000-05FFFF

17 32 050000-057FFF

16 32 048000-04FFFF

15 32 040000-047FFF

Parameter bank

14 32 038000-03FFFF

13 32 030000-037FFF

12 32 028000-02FFFF

11 32 020000-027FFF

10 32 018000-01FFFF

9 32 010000-017FFF

8 32 008000-00FFFF

7 4 007000-007FFF

6 4 006000-006FFF

5 4 005000-005FFF

4 4 004000-004FFF

3 4 003000-003FFF

2 4 002000-002FFF

1 4 001000-001FFF

0 4 000000-000FFF

Table 33: Bottom Boot Block Addresses, M58WR064KB (Continued)

Bank1#Size (Kword) Address range

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix B: Common Flash Interface

The common Flash interface is a JEDEC approved, standardized data structure that can

be read from the Flash memory device. It allows a system software to query the device to

determine various electrical and timing parameters, density information and functions

supported by the memory. The system can interface easily with the device, enabling the

software to upgrade itself when necessary.

When the READ CFI QUERY command is issued the device enters CFI query mode and

the data structure is read from the memory. Tables 34, 35, 36, 37, 38, 39, 40, 41, 42 and 43

show the addresses used to retrieve the data. The query data is always presented on the

lowest order data outputs (DQ[7:0]), the other outputs (DQ[15:8]) are set to 0.

The CFI data structure also contains a security area where a 64-bit unique security

number is written (see Figure 5: Protection Register Memory Map). This area can be

accessed only in read mode by the final user. It is impossible to change the security

number after it has been written by Micron. Issue a READ ARRAY command to return to

read mode.

Notes: 1. The Flash memory display the CFI data structure when CFI Query command is issued. In this

table are listed the main sub-sections detailed in Tables 35, 36, 37 and 38. Query data is

always presented on the lowest order data outputs.

Table 34: Query Structure Overview

See Note 1

Offset Sub-section name Description

00h Reserved Reserved for algorithm-specific information

10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

PPrimary Algorithm-specific Extended Query table Additional information specific to the Primary

Algorithm (optional)

AAlternate Algorithm-specific Extended Query table Additional information specific to the Alternate

Algorithm (optional)

80h Security Code Area Lock Protection Register

Unique device Number and

User Programmable OTP

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix B: Common Flash Interface

Table 35: CFI Query Identification String

Offset Sub-section name Description Value

00h 0020h Manufacturer code Micron

01h 8814h

8810h

8815h

8811h

Device code M58WR032KT (Top)

M58WR064KT (Top)

M58WR032KB (Bottom)

M58WR064KB (Bottom)

02h reserved Reserved

03h reserved Reserved

04h-0Fh reserved Reserved

10h 0051h Query Unique ASCII String "QRY" "Q"

11h 0052h "R"

12h 0059h "Y"

13h 0003h Primary Algorithm Command Set and Control

Interface ID code 16 bit ID code defining a specific

algorithm

14h 0000h

15h offset = P = 0039h Address for Primary Algorithm extended Query

table (see Table 38)

p = 39h

16h 0000h

17h 0000h Alternate Vendor Command Set and Control

Interface ID Code second vendor - specified

algorithm supported

18h 0000h

19h value = A = 0000h Address for Alternate Algorithm extended Query

table

1Ah 0000h

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix B: Common Flash Interface

Table 36: CFI Query System Interface Information

Offset Data Description Value

1Bh 0017h VDD Logic Supply Minimum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 millivolts

1.7V

1Ch 0020h VDD Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 millivolts

1Dh 0085h VPP [Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 millivolts

8.5V

1Eh 0095h VPP [Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 millivolts

9.5V

1Fh 0004h Typical time-out per single byte/word program = 2n µs 16µs

20h 0000h Typical time-out for multi-byte programming = 2n µs NA

21h 000Ah Typical time-out per individual block erase = 2n ms 1s

22h 0000h Typical time-out for full chip erase = 2n ms NA

23h 0003h Maximum time-out for word program = 2n times typical 128µs

24h 0000h Maximum time-out for multi-byte programming = 2n times typical NA

25h 0002h Maximum time-out per individual block erase = 2n times typical 4s

26h 0000h Maximum time-out for chip erase = 2n times typical NA

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix B: Common Flash Interface

Table 37: Device Geometry Definition

Offset word

mode Data Description Value

27h 0016h M58WR032KT/B Device Size = 2n in number of bytes 4Mb

0017h M58WR064KT/B Device Size = 2n in number of bytes 8Mb

28h

29h

0001h

0000h

Flash Device Interface Code description x16

Async

2Ah

2Bh

0000h

Maximum number of bytes in multi-byte program or page = 2n NA

2Ch 0002h Number of identical sized erase block regions within the device

bit 7 to 0 = x = number of Erase Block Regions

Top devices

2Dh

2Eh

003Eh

0000h

M58WR032KT Region 1 Information

Number of identical-size erase blocks = 003Eh+1

007Eh

0000h

M58WR064KT Region 1 Information

Number of identical-size erase blocks = 007Eh+1

127

2Fh

30h

0000h

0001h

Region 1 Information

Block size in Region 1 = 0100h * 256 byte

64Kb

31h

32h

0007h

0000h

Region 2 Information

Number of identical-size erase blocks = 0007h+1

33h

34h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 byte

8Kb

35h

38h

Reserved for future erase block region information NA

Bottom devices

2Dh

2Eh

0007h

0000h

Region 1 Information

Number of identical-size erase block = 0007h+1

2Fh

30h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 byte

8Kb

31h

32h

003Eh

0000h

M58WR032KB Region 1 Information

Number of identical-size erase blocks = 003Eh+1

007Eh

0000h

M58WR064KB Region 1 Information

Number of identical-size erase blocks = 007Eh+1

127

33h

34h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 byte

64Kb

35h

38h

Reserved for future erase block region information NA

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix B: Common Flash Interface

Notes: 1. The variable P is a pointer that is defined at CFI offset 15h (See Table 35).

Table 38: Primary Algorithm-Specific Extended Query Table

See Note 1

Offset Data Description Value

(P)h = 39h 0050h Primary Algorithm extended Query table unique ASCII string “PRI” "P"

0052h "R"

0049h "I"

(P+3)h = 3Ch 0031h Major version number, ASCII "1"

(P+4)h = 3Dh 0033h Minor version number, ASCII "3"

(P+5)h = 3Eh 00E6h Extended Query table contents for Primary Algorithm. Address (P+5)h contains less

significant byte.

bit 0 Chip Erase supported (1 = Yes, 0 = No)

bit 1 Erase Suspend supported (1 = Yes, 0 = No)

bit 2 Program Suspend supported (1 = Yes, 0 = No)

bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No)

bit 4 Queued Erase supported (1 = Yes, 0 = No)

bit 5 Instant individual block locking supported (1 = Yes, 0 = No)

bit 6 Protection bits supported (1 = Yes, 0 = No)

bit 7 Page mode read supported (1 = Yes, 0 = No)

bit 8 Synchronous read supported (1 = Yes, 0 = No)

bit 9 Simultaneous operation supported (1 = Yes, 0 = No)

bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is 1 then another 31 bit field of

optional features follows at the end of the bit-30 field.

Yes

0003h

(P+7)h = 40h 0000h

(P+8)h = 41h 0000h

(P+9)h = 42h 0001h Supported Functions after Suspend

Read Array, Read Status Register and CFI Query

bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1 Reserved; undefined bits are ‘0’

Yes

(P+A)h = 43h 0003h Block Protect status

Defines which bits in the Block Status Register section of the Query are implemented.

bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No)

bit 1 Block Lock Status Register lock-down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’ Yes

Yes

(P+B)h = 44h 0000h

(P+C)h = 45h 0018h VDD Logic Supply Optimum Program/Erase voltage (highest performance)

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100mV

1.8V

(P+D)h = 46h 0090h VPP Supply Optimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100mV

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix B: Common Flash Interface

Notes: 1. The variable P is a pointer that is defined at CFI offset 15h (See Table 35).

2. Bank Regions. There are two Bank Regions, see Tables 30, 31, 32 and 33.

Table 39: Protection Register Information

See Note 1

Offset Data Description Value

(P+E)h = 47h 0001h Number of protection register fields in JEDEC ID space. 0000h indicates that 256

fields are available.

(P+F)h = 48h 0080h Protection Field 1: Protection Description

Bits 0-7 Lower byte of protection register address

Bits 8-15 Upper byte of protection register address

Bits 16-23 2n bytes in factory pre-programmed region

Bits 24-31 2n bytes in user programmable region

0080h

(P+10)h = 49h 0000h

(P+11)h = 4Ah 0003h 8 bytes

(P+12)h= 4Bh 0004h 16 bytes

Table 40: Burst Read Information

See Note Table 1

Offset Data Description Value

(P+13)h = 4Ch 0003h Page-mode read capability

bits 0-7 ’n’ such that 2n HEX value represents the number of read-page bytes.

See offset 28h for device word width to determine page-mode data output

width.

8 bytes

(P+14)h = 4Dh 0004h Number of synchronous mode read configuration fields that follow. 4

(P+15)h = 4Eh 0001h Synchronous mode read capability configuration 1

bit 3-7 Reserved

bit 0-2 ’n’ such that 2n+1 HEX value represents the maximum number of

continuous synchronous reads when the device is configured for its maximum

word width. A value of 07h indicates that the device is capable of continuous

linear bursts that will output data until the internal burst counter reaches the

end of the device’s burstable address space. This field’s 3-bit value can be written

directly to the read configuration register bit 0-2 if the device is configured for

its maximum word width. See offset 28h for word width to determine the burst

data output width.

(P+16)h = 4Fh 0002h Synchronous mode read capability configuration 2 8

(P+17)h = 50h 0003h Synchronous mode read capability configuration 3 16

(P+18)h = 51h 0007h Synchronous mode read capability configuration 4 Cont.

Table 41: Bank and Erase Block Region Information

See Notes 1,2

M58WR032KT,

M58WR064KT

M58WR032KB,

M58WR064KB

DescriptionOffset Data Offset Data

(P+19)h = 52h 02h (P+19)h = 52h 02h Number of Bank Regions within the device

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix B: Common Flash Interface

Table 42: Bank and Erase Block Region 1 Information

See Note 1

M58WR032KT,

M58WR064KT

M58WR032KB,

M58WR064KB

DescriptionOffset Data Offset Data

(P+1A)h = 53h 07h2

0Fh3(P+1A)h = 53h 01h Number of identical banks within Bank Region 1

(P+1B)h = 54h 00h (P+1B)h = 54h 00h

(P+1C)h = 55h 11h (P+1C)h = 55h 11h Number of program or erase operations allowed in Bank Region

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+1D)h = 56h 00h (P+1D)h = 56h 00h Number of program or erase operations allowed in other banks

while a bank in same region is programming

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+1E)h = 57h 00h (P+1E)h = 57h 00h Number of program or erase operations allowed in other banks

while a bank in this region is erasing

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+1F)h = 58h 01h (P+1F)h = 58h 02h Types of erase block regions in Bank Region 1

n = number of erase block regions with contiguous same-size

erase blocks.

Symmetrically blocked banks have one blocking region.4

(P+20)h = 59h 07h (P+20)h = 59h 07h Bank Region 1 Erase Block Type 1 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

(P+21)h = 5Ah 00h (P+21)h = 5Ah 00h

(P+22)h = 5Bh 00h (P+22)h = 5Bh 20h

(P+23)h = 5Ch 01h (P+23)h = 5Ch 00h

(P+24)h = 5Dh 64h (P+24)h = 5Dh 64h Bank Region 1 (Erase Block Type 1)

Minimum block erase cycles × 1000

(P+25)h = 5Eh 00h (P+25)h = 5Eh 00h

(P+26)h = 5Fh 01h (P+26)h = 5Fh 01h Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved 5Eh 01 5Eh 01

(P+27)h = 60h 03h (P+27)h = 60h 03h Bank Region 1 (Erase Block Type 1): page mode and synchronous

mode capabilities

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+28)h = 61h 06h Bank Region 1 Erase Block Type 2 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

(P+29)h = 62h 00h

(P+2A)h = 63h 00h

(P+2B)h = 64h 01h

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix B: Common Flash Interface

Notes: 1. The variable P is a pointer which is defined at CFI offset 15h (See Table 35).

2. Applies to M58WR032KT.

3. Applies to M58WR064KT.

4. Bank Regions. There are two Bank Regions, see Tables 30, 31, 32 and 33.

(P+2C)h = 65h 64h Bank Region 1 (Erase Block Type 2)

Minimum block erase cycles × 1000

(P+2D)h = 66h 00h

(P+2E)h = 67h 01h Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

(P+2F)h = 68h 03h Bank Region 1 (Erase Block Type 2): page mode and synchronous

mode capabilities

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

Table 42: Bank and Erase Block Region 1 Information (Continued)

See Note 1

M58WR032KT,

M58WR064KT

M58WR032KB,

M58WR064KB

DescriptionOffset Data Offset Data

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix B: Common Flash Interface

Table 43: Bank and Erase Block Region 2 Information

See Note 1

M58WR032KT,

M58WR064KT

M58WR032KB,

M58WR064KB

DescriptionOffset Data Offset Data

(P+28)h = 61h 01h (P+30)h = 69h 07h2

0Fh3Number of identical banks within Bank Region 2

(P+29)h = 62h 00h (P+31)h = 6Ah 00h

(P+2A)h = 63h 11h (P+32)h = 6Bh 11h Number of program or erase operations allowed in Bank Region

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+2B)h = 64h 00h (P+33)h = 6Ch 00h Number of program or erase operations allowed in other banks

while a bank in this region is programming

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+2C)h = 65h 00h (P+34)h = 6Dh 00h Number of program or erase operations allowed in other banks

while a bank in this region is erasing

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+2D)h = 66h 02h (P+35)h = 6Eh 01h Types of erase block regions in Bank Region 2

n = number of erase block regions with contiguous same-size

erase blocks.

Symmetrically blocked banks have one blocking region.4

(P+2E)h = 67h 06h (P+36)h = 6Fh 07h Bank Region 2 Erase Block Type 1 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

(P+2F)h = 68h 00h (P+37)h = 70h 00h

(P+30)h = 69h 00h (P+38)h = 71h 00h

(P+31)h = 6Ah 01h (P+39)h = 72h 01h

(P+32)h = 6Bh 64h (P+3A)h = 73h 64h Bank Region 2 (Erase Block Type 1)

Minimum block erase cycles × 1000

(P+33)h = 6Ch 00h (P+3B)h = 74h 00h

(P+34)h = 6Dh 01h (P+3C)h = 75h 01h Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

(P+35)h = 6Eh 03h (P+3D)h = 76h 03h Bank Region 2 (Erase Block Type 1): page mode and synchronous

mode capabilities (defined in Table 40)

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+36)h = 6Fh 07h Bank Region 2 Erase Block Type 2 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

(P+37)h = 70h 00h

(P+38)h = 71h 20h

(P+39)h = 72h 00h

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix B: Common Flash Interface

Notes: 1. The variable P is a pointer which is defined at CFI offset 15h (See Table 35).

2. Applies to M58WR032KB.

3. Applies to M58WR064KB.

4. Bank Regions. There are two Bank Regions, see Tables 30, 31, 32 and 33.

(P+3A)h = 73h 64h Bank Region 2 (Erase Block Type 2)

Minimum block erase cycles × 1000

(P+3B)h = 74h 00h

(P+3C)h = 75h 01h Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

(P+3D)h = 76h 03h Bank Region 2 (Erase Block Type 2): page mode and synchronous

mode capabilities (defined in Table 40)

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+3E)h = 77h (P+3E)h = 77h Feature Space definitions

(P+3F)h = 78h (P+3F)h = 78h Reserved

Table 43: Bank and Erase Block Region 2 Information (Continued)

See Note 1

M58WR032KT,

M58WR064KT

M58WR032KB,

M58WR064KB

DescriptionOffset Data Offset Data

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Figure 20: Program Flowchart and Pseudo Code

Notes: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be

made after each program operation or after a sequence.

2. If an error is found, the Status Register must be cleared before further PROGRAM/ERASE

CONTROLLER operations.

3. Any address within the bank can equally be used.

Write 40h or 10h (3)

AI06170b

Start

Write Address

& Data

Read Status

YES

SR7 = 1

YES

SR3 = 0

SR4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

program_command (addressToProgram, dataToProgram) {:

writeToFlash (addressToProgram, 0x40);

/*writeToFlash (addressToProgram, 0x10);*/

/*see note (3)*/

do {

status_register=readFlash (addressToProgram);

"see note (3)";

/* CE# or OE# must be toggled*/

} while (status_register.SR7== 0) ;

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

YES

End

YES

SR1 = 0 Program to Protected

Block Error (1, 2)

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

}

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Figure 21: DOUBLE WORD PROGRAM Flowchart and Pseudo Code

Notes: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be

made after each program operation or after a sequence.

2. If an error is found, the Status Register must be cleared before further PROGRAM/ERASE

operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

4. Any address within the bank can equally be used.

Write 35h

AI06171b

Start

Write Address 1

& Data 1 (3, 4)

Read Status

YES

SR7 = 1

YES

SR3 = 0

SR4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

YES

End

YES

SR1 = 0 Program to Protected

Block Error (1, 2)

Write Address 2

& Data 2 (3)

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (addressToProgram1, 0x35);

/*see note (4)*/

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (addressToProgram) ;

"see note (4)"

/* CE# or OE# must be toggled*/

} while (status_register.SR7== 0) ;

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

}

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Figure 22: QUADRUPLE WORD PROGRAM Flowchart and Pseudo Code

Notes: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be

made after each program operation or after a sequence.

2. If an error is found, the Status Register must be cleared before further PROGRAM/ERASE

operations.

3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.

4. Any address within the bank can equally be used.

Write 56h

AI06977b

Start

Write Address 1

& Data 1 (3, 4)

Read Status

YES

SR7 = 1

YES

SR3 = 0

SR4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

YES

End

YES

SR1 = 0 Program to Protected

Block Error (1, 2)

Write Address 2

& Data 2 (3)

quadruple_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2,

addressToProgram3, dataToProgram3,

addressToProgram4, dataToProgram4)

{

writeToFlash (addressToProgram1, 0x56);

/*see note (4) */

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ;

/*see note (3) */

writeToFlash (addressToProgram4, dataToProgram4) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (addressToProgram) ;

/"see note (4) "/

/* CE# or OE# must be toggled*/

} while (status_register.SR7== 0) ;

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

if (status_register.SR==1) /*program to protect block error */

error_handler ( ) ;

}

Write Address 3

& Data 3 (3)

Write Address 4

& Data 4 (3)

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Figure 23: PROGRAM SUSPEND STATUS and RESUME Flowchart and Pseudo Code

Notes: 1. The READ STATUS REGISTER command (Write 70h) can be issued just before or just after the

Program Resume command.

Write 70h

AI10117b

Read Status

YES

SR7 = 1

YES

SR2 = 1

Write D0h

Read data from

another address

Start

Write B0h

Program Complete

Write FFh

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

writeToFlash (bank_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (bank_address) ;

/* CE# or OE# must be toggled*/

} while (status_register.SR7== 0) ;

if (status_register.SR2==0) /*program completed */

{ writeToFlash (bank_address, 0xFF) ;

read_data ( ) ;

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

}

else

{ writeToFlash (bank_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

writeToFlash (bank_address, 0x70) ;

/*read status register to check if program has completed */

}

Write FFh

Program Continues with

Bank in Read Status

Read Data

Write 70h(1)

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Figure 24: BLOCK ERASE Flowchart and Pseudo Code

Notes: 1. If an error is found, the Status Register must be cleared before further PROGRAM/ERASE

operations.

2. Any address within the bank can be used also.

Write 20h (2)

AI13431

Start

Write Block

Address & D0h

Read Status

YES

SR7 = 1

YES

SR3 = 0

YES

SR4, SR5 = 1

VPP Invalid

Error (1)

Command

Sequence Error (1)

SR5 = 0 Erase Error (1)

End

YES

SR1 = 0 Erase to Protected

Block Error (1)

YES

erase_command ( blockToErase ) {

writeToFlash (blockToErase, 0x20) ;

/*see note (2) */

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significant */

/* Memory enters read status state after

the Erase Command */

} while (status_register.SR7== 0) ;

do {

status_register=readFlash (blockToErase) ;

/* see note (2) */

/* CE# or OE# must be toggled*/

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

if ( (status_register.SR4==1) && (status_register.SR5==1) )

/* command sequence error */

error_handler ( ) ;

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

if ( (status_register.SR5==1) )

/* erase error */

error_handler ( ) ;

}

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Figure 25: ERASE SUSPEND and RESUME Flowchart and Pseudo Code

Notes: 1. The READ STATUS REGISTER command (Write 70h) can be issued just before or just after the

ERASE RESUME command.

Write 70h

AI10116d

Read Status

YES

SR7 = 1

YES

SR6 = 1

Erase Continues with

Bank in Read Status

Write D0h

Read data from another block,

Program,

Set Configuration Register

Block Lock/Unlock/Lock-Down

Start

Write B0h

Erase Complete

Write FFh

Read Data

Write FFh

erase_suspend_command ( ) {

writeToFlash (bank_address, 0xB0) ;

writeToFlash (bank_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

status_register=readFlash (bank_address) ;

/* CE# or OE# must be toggled*/

} while (status_register.SR7== 0) ;

if (status_register.SR6==0) /*erase completed */

{ writeToFlash (bank_address, 0xFF) ;

read_data ( ) ;

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

}

else

{ writeToFlash (bank_address, 0xFF) ;

read_program_data ( );

/*read or program data from another block*/

writeToFlash (bank_address, 0xD0) ;

/*write 0xD0 to resume erase*/

writeToFlash (bank_address, 0x70) ;

/*read status register to check if erase has completed */

}

Write 70h

(1)

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Figure 26: Locking Operations Flowchart and Pseudo Code

Notes: 1. Any address within the bank can equally be used.

Write

01h, D0h or 2Fh

AI06176b

Read Block

Lock States

YES

Locking

change

confirmed?

Start

Write 60h (1) locking_operation_command (address, lock_operation) {

writeToFlash (address, 0x60) ; /*configuration setup*/

/* see note (1) */

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

/*Check the locking state (see Read Block Signature table )*/

writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/

/*see note (1) */

}

Write FFh (1)

Write 90h (1)

End

if (lock_operation==LOCK) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNLOCK) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

else if (lock_operation==LOCK-DOWN) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (address, 0x90) ;

/*see note (1) */

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Figure 27: PROTECTION REGISTER PROGRAM Flowchart and Pseudo Code

Notes: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be

made after each program operation or after a sequence.

2. If an error is found, the Status Register must be cleared before further PROGRAM/ERASE

CONTROLLER operations.

3. Any address within the bank can equally be used.

Write C0h (3)

AI06177b

Start

Write Address

& Data

Read Status

YES

SR7 = 1

YES

SR3 = 0

SR4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

protection_register_program_command (addressToProgram, dataToProgram) {:

writeToFlash (addressToProgram, 0xC0) ;

/*see note (3) */

do {

status_register=readFlash (addressToProgram) ;

/* see note (3) */

/* CE# or OE# must be toggled*/

} while (status_register.SR7== 0) ;

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

YES

End

YES

SR1 = 0 Program to Protected

Block Error (1, 2)

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

}

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Figure 28: ENHANCED FACTORY PROGRAM Flowchart

Notes: 1. Address can remain Starting Address WA1 or be incremented.

Write 30h

Address WA1

AI06160b

Start

Read Status

YES

SR0 = 0?

End

Write D0h

Address WA1

Write PD1

Address WA1

Write PD2

Address WA2(1)

YES

Read Status

Write PDn

Address WAn(1)

YES

Read Status

Write PD1

Address WA1(1)

Write PDn

Address WAn(1)

Read Status

Address Block WA1

SETUP PHASE VERIFY PHASE

SR0 = 0?

Read Status

YES

SR0 = 0?

Address Block WA1

SR7 = 0?

YES

Check SR4, SR3

and SR1 for program,

VPP and Lock Errors

Exit Read Status

Write PD2

Address WA2(1)

SR0 = 0?

YES

Read Status

SR7 = 1?

Check Status

YES

PROGRAM PHASE

EXIT PHASE

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

ENHANCED FACTORY PROGRAM Pseudo Code

efp_command(addressFlow,dataFlow,n)

/* n is the number of data to be programmed */

{

/* setup phase */

writeToFlash(addressFlow[0],0x30);

writeToFlash(addressFlow[0],0xD0);

status_register=readFlash(any_address);

if (status_register.SR7==1){

/*EFP aborted for an error*/

if (status_register.SR4==1) /*program error*/

error_handler();

if (status_register.SR3==1) /*VPP invalid error*/

error_handler();

if (status_register.SR1==1) /*program to protect block error*/

error_handler();

}

else{

/*Program Phase*/

do{

status_register=readFlash(any_address);

/* CE# or OE# must be toggled*/

} while (status_register.SR0==1)

/*Ready for first data*/

for (i=0; i++; i< n){

writeToFlash(addressFlow[i],dataFlow[i]);

/* status register polling*/

do{

status_register=readFlash(any_address);

/* CE# or OE# must be toggled*/

} while (status_register.SR0==1);

/* Ready for a new data */

}

writeToFlash(another_block_address,any_data);

/* Verify Phase */

for (i=0; i++; i< n){

writeToFlash(addressFlow[i],dataFlow[i]);

/* status register polling*/

do{

status_register=readFlash(any_address);

/* CE# or OE# must be toggled*/

} while (status_register.SR0==1);

/* Ready for a new data */

}

writeToFlash(another_block_address,any_data);

/* exit program phase */

/* Exit Phase */

/* status register polling */

do{

status_register=readFlash(any_address);

/* E or G must be toggled */

} while (status_register.SR7==0);

if (status_register.SR4==1) /*program failure error*/

error_handler();

if (status_register.SR3==1) /*VPP invalid error*/

error_handler();

if (status_register.SR1==1) /*program to protect block error*/

error_handler();

}

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Figure 29: QUADRUPLE ENHANCED FACTORY PROGRAM Flowchart

Notes: 1. Address can remain Starting Address WA1 (in which case the next page is programmed) or

can be any address in the same block.

2. The address is only checked for the first word of each page as the order to program the

words is fixed, so subsequent words in each page can be written to any address.

Write 75h

Address WA1

AI06178c

Start

End

Write PD1

Address WA1(1)

Write PD2

Address WA2(2)

Write PD3

Address WA3(2)

Read Status

SETUP PHASE

PROGRAM AND

VERIFY PHASE

SR7 = 0?

YES

Check SR4, SR3

and SR1 for program,

VPP and Lock Errors

Exit

Check SR4 for

Programming Errors

YES

LOAD PHASE

EXIT PHASE

Write PD4

Address WA4(2)

SR0 = 0?

Last Page?

YES

Address Block WA1

Write PD1

Address WA1

Read Status

FIRST

LOAD PHASE

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

QUADRUPLE ENHANCED FACTORY PROGRAM Pseudo Code

quad_efp_command(addressFlow,dataFlow,n)

/* n is the number of pages to be programmed.*/

{

/* Setup phase */

writeToFlash(addressFlow[0],0x75);

for (i=0; i++; i< n){

/*Data Load Phase*/

/*First Data*/

writeToFlash(addressFlow[i],dataFlow[i,0]);

/*at the first data of the first page, Quad-EFP may be aborted*/

if (First_Page) {

status_register=readFlash(any_address);

if (status_register.SR7==1){

/*EFP aborted for an error*/

if (status_register.SR4==1) /*program error*/

error_handler();

if (status_register.SR3==1) /*VPP invalid error*/

error_handler();

if (status_register.SR1==1) /*program to protect block error*/

error_handler();

}

/*2nd data*/

writeToFlash(addressFlow[i],dataFlow[i,1]);

/*3rd data*/

writeToFlash(addressFlow[i],dataFlow[i,2]);

/*4th data*/

writeToFlash(addressFlow[i],dataFlow[i,3]);

/* Program&Verify Phase */

do{

status_register=readFlash(any_address);

/* E or G must be toggled*/

}while (status_register.SR0==1)

}

/* Exit Phase */

writeToFlash(another_block_address,any_data);

/* status register polling */

do{

status_register=readFlash(any_address);

/* CE# or OE# must be toggled */

} while (status_register.SR7==0);

if (status_register.SR1==1) /*program to protected block error*/

error_handler();

if (status_register.SR3==1) /*VPP invalid error*/

error_handler();

if (status_register.SR4==1) /*program failure error*/

error_handler();

}

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Appendix A Command Interface State Tables

Table 44: Command Interface States - Modify Table, Next State

See Note 1

Current CI State

Command Input

Read

Array2

(FFh)

setup3,4

(10/40h)

DWP,

QWP

Setup3,4

(35h,

56h)

Block

Erase

Setup3,4

(20h)

EFP

Setup

(30h)

Quad-

EFP

Setup

(75h)

Erase

Confirm, P/E

Resume,

Block

Unlock

confirm, EFP

Confirm

(D0h)

Progra

m/ Erase

Suspend

(B0h)

Read

Status

(70h)

Clear

Status

(50h)

Read

Electronic

signature

, Read CFI

Query

(90h,

98h)

Ready Ready Program

Setup

Program

Setup

Erase

Setup

EFP

Setup

Quad-EFP

Setup

Ready

Lock/CR Setup Ready (Lock Error) Ready Ready (Lock Error)

OTP Setup OTP Busy

Busy OTP Busy IS in OTP busy OTP Busy

IS in OTP

busy

OTP busy

Progra

Setup Program Busy

Busy Program

busy

IS in Program busy Program busy PS Program busy

IS in

Program

busy

Program Busy

Suspend PS IS in Program Suspend Program Busy Program Suspend

IS in PS Program suspend

Erase Setup Ready (error) Erase Busy Ready (error)

Busy Erase Busy IS in Erase busy Erase Busy ES Erase Busy

IS in Erase

busy

Erase busy

Suspend ES Program

IS in Erase Suspend Erase Busy Erase Suspend

IS in ES Erase Suspend

Progra

m in ES

Setup Program Busy in Erase Suspend

Busy Program

Busy in ES

IS in Program Busy in Erase Suspend Program Busy

in ES

PS in ES Program Busy in Erase

Suspend

IS in

Program

busy in ES

Program Busy in Erase Suspend

Suspend PS in ES IS in Program suspend in ES Program Busy

in ES

Program Suspend in Erase Suspend

IS in PS in ES Program Suspend in Erase Suspend

Lock/CR Setup in ES Erase Suspend (Lock Error) ES Erase Suspend (Lock Error)

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Notes: 1. CI = Command Interface, CR = Configuration Register, EFP = ENHANCED FACTORY PRO-

GRAM, Quad EFP = QUADRUPLE ENHANCED FACTORY PROGRAM, DWP = DOUBLE WORD

PROGRAM, QWP = QUADRUPLE WORD PROGRAM, P/EC = PROGRAM/ERASE CONTROLLER,

PS = PROGRAM SUSPEND, ES = ERASE SUSPEND, IS = ILLEGAL STATE.

2. At Power-Up, all banks are in READ ARRAY mode. A READ ARRAY command issued to a

busy bank, results in undetermined data output.

3. The two cycle command should be issued to the same bank address.

4. If the P/EC is active, both cycles are ignored.

5. The CLEAR STATUS REGISTER command clears the Status Register error bits except when the

P/EC is busy or suspended.

6. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’.EFP and Quad

EFP are busy if Block Address is first EFP Address. Any other commands are treated as data.

EFP Setup Ready (error) EFP Busy Ready (error)

Busy EFP Busy6

Verify EFP Verify6

Quad

EFP

Setup Quad EFP Busy6

Busy Quad EFP Busy6

Table 44: Command Interface States - Modify Table, Next State (Continued)

See Note 1

Current CI State

Command Input

Read

Array2

(FFh)

setup3,4

(10/40h)

DWP,

QWP

Setup3,4

(35h,

56h)

Block

Erase

Setup3,4

(20h)

EFP

Setup

(30h)

Quad-

EFP

Setup

(75h)

Erase

Confirm, P/E

Resume,

Block

Unlock

confirm, EFP

Confirm

(D0h)

Progra

m/ Erase

Suspend

(B0h)

Read

Status

(70h)

Clear

Status

(50h)

Read

Electronic

signature

, Read CFI

Query

(90h,

98h)

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Notes: 1. CI = Command Interface, CR = Configuration Register, EFP = ENHANCED FACTORY PRO-

GRAM, Quad EFP = QUADRUPLE ENHANCED FACTORY PROGRAM, DWP = DOUBLE WORD

PROGRAM, QWP = QUADRUPLE WORD PROGRAM, P/EC = PROGRAM/ERASE CONTROLLER,

IS = ILLEGAL STATE, ES = ERASE SUSPEND, PS = PROGRAM SUSPEND.

2. The output state shows the type of data that appears at the outputs if the bank address is

the same as the command address. A bank can be placed in READ ARRAY, READ STATUS

command issued. Each bank remains in its last output state until a new command is issued.

The next state does not depend on the bank’s output state.

3. At Power-Up, all banks are in READ ARRAY mode. A READ ARRAY command issued to a

busy bank, results in undetermined data output.

4. The two cycle command should be issued to the same bank address.

5. If the P/EC is active, both cycles are ignored.

Table 45: Command Interface States - Modify Table, Next Output

See Note 1

Current CI State

Command Input2

Read

Array3

(FFh)

DWP,

QWP

Setup4,5

(35h, 56h)

Block

Erase

Setup4,5

(20h)

EFP

Setup

(30h)

Quad-

EFP

Setup

(75h)

Erase

Confirm

P/E Resume,

Block Unlock

confirm, EFP

Confirm

(D0h)

Program/

Erase

Suspend

(B0h)

Read

Status

(70h)

Clear Status

Register6

(50h)

Read

Electronic

signature,

Read CFI

Query (90h,

98h)

Program Setup Status Register

Erase Setup

OTP Setup

Program Setup in

Erase Suspend

EFP Setup

EFP Busy

EFP Verify

Quad EFP Setup

Quad EFP Busy

Lock/CR Setup

Lock/CR Setup in

Erase Suspend

OTP Busy Array Status Register Output Unchanged Status

Output

Unchanged

Status Register

Ready Electronic

Signature/CFI

Program Busy

Erase Busy

Program/Erase

Suspend

Program Busy in

Erase Suspend

Program Suspend

in Erase Suspend

Illegal State Output Unchanged

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

6. The CLEAR STATUS REGISTER command clears the Status Register error bits except when the

P/EC is busy or suspended.

Notes: 1. CI = Command Interface, CR = Configuration Register, EFP = ENHANCED FACTORY PRO-

GRAM, Quad EFP = QUADRUPLE ENHANCED FACTORY PROGRAM, P/EC = PROGRAM/ERASE

CONTROLLER, IS = ILLEGAL STATE, ES = ERASE SUSPEND, PS = PROGRAM SUSPEND.

2. If the P/EC is active, both cycles are ignored.

3. EFP and Quad EFP exit when block address is different from first block address.

4. Illegal commands are those not defined in the command set.

5. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’. EFP and Quad

EFP are busy if Block Address is first EFP Address. Any other commands are treated as data.

Table 46: Command Interface States - Lock Table, Next State

See Note 1

Current CI State

Command Input

Lock/CR

Setup2

(60h)

OTP

Setup2

(C0h)

Block Lock

Confirm

(01h)

Block Lock-

Down

Confirm

(2Fh)

Set CR

Confir

(03h)

EFP Exit,

Quad EFP

Exit3Illegal

Command4

P/E. C.

Operation

Completed

Ready Lock/CR Setup OTP Setup Ready N/A

Lock/CR Setup Ready (Lock error) Ready Ready (Lock error) N/A

OTP Setup OTP Busy

Busy IS in OTP busy OTP Busy Ready

IS in OTP busy OTP Busy IS Ready

Program Setup Program Busy N/A

Busy IS in Program busy Program Busy Ready

IS in Program

busy

Program busy IS Ready

Suspend IS in PS Program Suspend N/A

IS in PS Program Suspend N/A

Erase Setup Ready (error) N/A

Busy IS in Erase Busy Erase Busy Ready

IS in Erase Busy Erase Busy IS Ready

Suspend Lock/CR Setup

in ES

IS in Erase

Suspend

Erase Suspend N/A

IS in ES Erase Suspend N/A

Program

in Erase

Suspend

Setup Program Busy in Erase Suspend

Busy IS in Program busy in ES Program Busy in Erase Suspend ES

IS in Program

busy in ES

Program busy in ES IS in ES

Suspend IS in PS in ES Program Suspend in Erase Suspend N/A

IS in PS in ES Program Suspend in Erase Suspend

Lock/CR Setup in ES Erase Suspend (Lock error) Erase Suspend Erase Suspend (Lock error) N/A

EFP Setup Ready (error) N/A

Busy EFP Busy5EFP Verify EFP Busy5N/A

Verify EFP Verify5Ready EFP Verify5Ready

QuadEFP Setup Quad EFP Busy5N/A

Busy Quad EFP Busy5Ready Quad EFP

Busy4

Ready

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M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Appendix C: Flowcharts and Pseudo Codes

Notes: 1. CI = Command Interface, CR = Configuration Register, EFP = ENHANCED FACTORY PRO-

GRAM, Quad EFP = QUADRUPLE ENHANCED FACTORY PROGRAM, P/E. C. = PROGRAM/

ERASE CONTROLLER.

2. If the P/EC is active, both cycles are ignored.

3. EFP and Quad EFP exit when Block Address is different from first Block Address.

4. Illegal commands are those not defined in the command set.

Table 47: Command Interface States - Lock Table, Next Output

See Note 1

Current CI State

Command Input

Lock/CR

Setup2

(60h)

OTP Setup2

(C0h)

Block Lock

Confirm

(01h)

Block Lock-

Down

Confirm

(2Fh)

Set CR

Confirm

(03h)

EFP Exit,

Quad EFP

Exit3Illegal

Command4

P/E. C.

Operation

Completed

Program Setup Status Register Output

Unchanged

Erase Setup

OTP Setup

Program Setup in

Erase Suspend

EFP Setup

EFP Busy

EFP Verify

Quad EFP Setup

Quad EFP Busy

Lock/CR Setup Status Register Array Status Register

Lock/CR Setup in

Erase Suspend

OTP Busy Status Register Output Unchanged Array Output

Unchanged

Ready

Program Busy

Erase Busy

Program/Erase

Suspend

Program Busy in

Erase Suspend

Program Suspend in

Erase Suspend

Illegal State Output Unchanged

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.

M58WRxxxKT/B - 32Mb - 64Mb, 1.8V, x16 Multi Bank Burst, Flash

Revision History

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Revision History

Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/11

• Applied Micron branding and style.

• Removed M58WR016KT/B and related info.

• Removed ZQ package (FBGA88 8 x 10 mm, 0.8 mm pitch).

Rev. 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .04/09

• Added the following information to support automotive:

– “Automotive Certified Parts Available” on cover page;

– “7A = Automotive Certified -40 to 85 °C” to order information.

Rev. 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/08

• Replaced references to ECOPACK with RoHS compliant;

• Changed FBGA88 package part number from ZAQ to ZQ;

• Changed FBGA88 package thickness from 1.2mm to 1.0mm.

Rev. 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .04/08

• Changed several values in Table 22: DC characteristics - currents.

• Applied Numonyx branding.

Rev. 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .03/08

• Added the ZAQ package information in Figure 3: TFBGA88 connections (top view

through package), Figure 22: VFBGA88 8x10mm - 8 x 10 ball array, 0.8 mm pitch,

bottom view outline, Table 30: VFBGA88 8 x 10 mm - 8 x 10 ball array, 0.8 mm pitch,

package data, and Table 31: Ordering information scheme. Changed the IDD2 values

from 2 and 10 to 15 and 50 respectively in Table 22: DC characteristics - currents.

Removed tLHGL from Figure 12: Asynchronous random access read AC waveforms,

Figure 13: Asynchronous page read AC waveforms, and Table 22: DC characteristics -

currents.

Rev. 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/07

• Changed Section 6.3.1 through Section 6.3.4, and Section 6.4.1 through Section 6.4.4

to third-level headings. Changed NOT VALID to VALID for the DQ0-DQ15 timing in

Figure 16: Synchronous burst read suspend AC waveforms. Changed the Synchronous

burst read mode value from 86 MHz to 66 MHz in the Features on page 1 and in

Section 1: Description. Removed the 60 ns speed class from the entire document,

specifically Table 11: Latency settings, Table 20: Operating and AC measurement

conditions, Table 24: Asynchronous read AC characteristics, Table 25: Synchronous

read AC characteristics, Table 26: Write AC characteristics, Write Enable controlled,

Table 27: Write AC characteristics, Chip Enable controlled, Table 28: Reset and power-

up AC characteristics, and Table 31: Ordering information scheme. Deleted the 86

MHz currents from Table 22: DC characteristics - currents and Table 25. Changed the

tKHQX value from 3 ns to 4 ns in Table 25.

Rev. 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .02/07

•Initial release.