CY7C130, CY7C130A
CY7C131, CY7C131A
1K x 8 Dual-Port Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06002 Rev. *F Revised March 22, 2010
Features
■True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■1K x 8 organization
■0.65 micron CMOS for optimum speed and power
■High speed access: 15 ns
■Low operating power: ICC = 110 mA (maximum)
■Fully asynchronous operation
■Automatic power down
■Master CY7C130/130A/CY7C131/131A easily expands data
bus width to 16 or more bits using slave CY7C140/CY7C141
■BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY
input on CY7C140/CY7C141
■INT flag for port-to-port communication
■Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,
52-pin TQFP
■Pb-free packages available
Functional Description
The CY7C130/130A/CY7C131/131A/CY7C140[1] and CY7C141
are high speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/130A/ CY7C131/131A can be used as
either a standalone 8-bit dual-port static RAM or as a master
dual-port RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multi-
processor designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. BUSY signals that the port is trying
to access the same location currently being accessed by the
other port. INT is an interrupt flag indicating that data is placed
in a unique location (3FF for the left port and 3FE for the right
port). An automatic power down feature is controlled indepen-
dently on each port by the chip enable (CE) pins.
The CY7C130/130A and CY7C140 are available in 48-pin DIP.
The CY7C131/131A and CY7C141 are available in 52-pin
PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free
PQFP.
R/WL
BUSYL
CEL
OEL
A9L
A0L A0R
A9R
R/WR
CER
OER
CER
OER
CEL
OEL
R/WLR/WR
I/O7L
I/O0L
I/O7R
I/O0R
BUSYR
INTLINTR
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY ADDRESS
DECODER
ADDRESS
DECODER
[2]
[3] [3]
Logic Block Diagram
Notes
1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.
2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.
CY7C140/CY7C141 (Slave): BUSY is input.
3. Open drain outputs: pull-up resistor required.
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 2 of 19
Pin Configurations
Figure 1. Pin Diagram - DIP (Top View)
Figure 2. Pin Diagram - PLCC (Top View) Figure 3. Pin Diagram - PQFP (Top View)
13
14
15
16
17
18
19
20
21
22
23 26
27
28
32
31
30
29
33
36
35
34
24 25
GND
1
2
3
4
5
6
7
8
9
10
11 38
39
40
44
43
42
41
45
48
47
46
12 37
R/WL
CEL
BUSY L
INT
L
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
CER
R/WR
BUSY
R
INT
R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
VCC
7C130
7C140
1
VCC
OER
A0R
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2 52 51 50 49 48 47
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
NC
I/O7R
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4L
5L
6L
7L
0R
1R
2R
3R
4R
5R
6R
NC
GND
OE
BUSY
INT
A
NC
R/W
CE
R/W
BUSY
INT
NC
0L
L
L
L
L
L
CER
R
R
R
7C131
7C141
46
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
1415 16 17 18 19 20 21 22 23 24 25 26
52 5150 49 48 47 45 44 43 42 41 40
VCC
OE
BUSY
INT
A
NC
R/W
CE
R/W
BUSY
INT
NC
0L
L
L
L
L
L
CER
R
R
R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
NC
I/O7R
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4L
5L
6L
7L
0R
1R
2R
3R
4R
5R
6R
NC
GND
7C131
7C141
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 3 of 19
Pin Definitions
Left Port Right Port Description
CELCERChip Enable
R/WLR/WRRead/Write Enable
OELOEROutput Enable
A0L–A11/12L A0R–A11/12R Address
I/O0L–I/O15/17L I/O0R–I/O15/17R Data Bus Input/Output
INTLINTRInterrupt Flag
BUSYLBUSYRBusy Flag
VCC Power
GND Ground
Selection Guide
Parameter
7C131-15[4]
7C131A-15
7C141-15
7C131-25[4]
7C141-25
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
Unit
Maximum Access Time 15 25 30 35 45 55 ns
Maximum Operating
Current Com’l/Ind 190 170 170 120 120 110 mA
Maximum Standby
Current Com’l/Ind 75 65 65 45 45 35 mA
Shaded areas contain preliminary information.
Note
4. 15 and 25 ns version available only in PLCC/PQFP packages.
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 4 of 19
Maximum Ratings[5]
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................. –65C to +150C
Ambient Temperature with
Power Applied ............................................ –55C to +125C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24)............................................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ................................................–0.5V to +7.0V
DC Input Voltage ............................................–3.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch Up Current .................................................... >200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0C to +70C 5V ± 10%
Industrial –40C to +85C 5V ± 10%
Military[6] –55C to +125C 5V ± 10%
Electrical Characteristics Over the Operating Range[7]
Parameter Description Test Conditions
7C131-15[4]
7C131A-15
7C141-15
7C130-30[4]
7C130A-30
7C131-25,30
7C140-30
7C141-25,30
7C130-35,45
7C131-35,45
7C140-35,45
7C141-35,45
7C130-55
7C131-55
7C140-55
7C141-55 Unit
Min Max Min Max Min Max Min Max
VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 2.4 2.4 2.4 V
VOL Output LOW Voltage IOL = 4.0 mA 0.4 0.4 0.4 0.4 V
IOL = 16.0 mA[8] 0.5 0.5 0.5 0.5
VIH Input HIGH Voltage 2.2 2.2 2.2 2.2 V
VIL Input LOW Voltage 0.8 0.8 0.8 0.8 V
IIX Input Leakage Current GND < VI < VCC –5 +5 –5 +5 –5 +5 –5 +5 A
IOZ Output Leakage
Current GND < VO < VCC,
Output Disabled –5 +5 –5 +5 –5 +5 –5 +5 A
IOS Output Short
Circuit Current[9, 10] VCC = Max,
VOUT = GND
–350 –350 –350 –350 mA
ICC VCC Operating
Supply Current
CE = VIL,
Outputs Open, f = fMAX[11] Com’l 190 170 120 110 mA
ISB1 Standby Current
Both Ports, TTL Inputs CEL and CER > VIH,
f = fMAX[11] Com’l 75 65 45 35 mA
ISB2 Standby Current
One Port,
TTL Inputs
CEL or CER > VIH,
Active Port Outputs Open
f = fMAX[11]
Com’l 135 115 90 75 mA
ISB3 Standby Current
Both Ports,
CMOS Inputs
Both Ports CEL and CER >
VCC – 0.2V,
VIN > VCC – 0.2V
or VIN < 0.2V, f = 0
Com’l 15 15 15 15 mA
ISB4 Standby Current
One Port,
CMOS Inputs
One Port CEL or
CER > VCC – 0.2V,
VIN > VCC – 0.2V
or VIN < 0.2V,
Active Port Outputs Open, f =
fMAX[11]
Com’l 125 105 85 70 mA
Shaded areas contain preliminary information.
Notes
5. The voltage on any input or I/O pin cannot exceed the power pin during power up.
6. TA is the “instant on” case temperature
7. See the last page of this specification for Group A subgroup testing information.
8. BUSY and INT pins only.
9. Duration of the short circuit should not exceed 30 seconds.
10. This parameter is guaranteed but not tested.
11. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V.
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 5 of 19
Capacitance[10]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25C, f = 1 MHz,
VCC = 5.0V 15 pF
COUT Output Capacitance 10 pF
Figure 4. AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 893
R2
347
30 pF
INCLUDING
JIGAND
SCOPE
GND
90% 90%
10%
5ns 5ns
5V
OUTPUT
R1 893
R2
347
5pF
INCLUDING
JIGAND
SCOPE
(a) (b)
OUTPUT 1.40V
Equivalent to: THÉVENIN EQUIVALENT
5V
281
30
pF
BUSY
OR
INT
BUSY Output Load
(CY7C130/CY7C131 ONLY)
10%
ALL INPUT PULSES
250
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 6 of 19
Switching Characteristics Over the Operating Range[7, 12]
Parameter Description
7C131-15[4]
7C131A-15
7C141-15
7C130-25[4]
7C131-25
7C140-25
7C141-25
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30
Unit
Min Max Min Max Min Max
Read Cycle
tRC Read Cycle Time 15 25 30 ns
tAA Address to Data Valid[13] 15 25 30 ns
tOHA Data Hold from Address Change 000ns
tACE CE LOW to Data Valid[13] 15 25 30 ns
tDOE OE LOW to Data Valid[13] 10 15 20 ns
tLZOE OE LOW to Low Z[10, 14, 15] 333ns
tHZOE OE HIGH to High Z[10, 14, 15] 10 15 15 ns
tLZCE CE LOW to Low Z[10, 14, 15] 355ns
tHZCE CE HIGH to High Z[10, 14, 15] 10 15 15 ns
tPU CE LOW to Power Up[10] 000ns
tPD CE HIGH to Power Down[10] 15 25 25 ns
Write Cycle[16]
tWC Write Cycle Time 15 25 30 ns
tSCE CE LOW to Write End 12 20 25 ns
tAW Address Setup to Write End 12 20 25 ns
tHA Address Hold from Write End 222ns
tSA Address Setup to Write Start 000ns
tPWE R/W Pulse Width 12 15 25 ns
tSD Data Setup to Write End 10 15 15 ns
tHD Data Hold from Write End 000ns
tHZWE R/W LOW to High Z[15] 10 15 15 ns
tLZWE R/W HIGH to Low Z[15] 000ns
Shaded areas contain preliminary information.
Notes
12. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
IOL/IOH, and 30 pF load capacitance.
13. AC Test Conditions use VOH = 1.6V and VOL = 1.4V.
14. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
15. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
16. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 7 of 19
Busy/Interrupt Timing
tBLA BUSY LOW from Address Match 15 20 20 ns
tBHA BUSY HIGH from Address Mismatch[17] 15 20 20 ns
tBLC BUSY LOW from CE LOW 15 20 20 ns
tBHC BUSY HIGH from CE HIGH[17] 15 20 20 ns
tPS Port Set Up for Priority 555ns
tWB[18] R/W LOW after BUSY LOW 000ns
tWH R/W HIGH after BUSY HIGH 13 20 30 ns
tBDD BUSY HIGH to Valid Data 15 25 30 ns
tDDD Write Data Valid to Read Data Valid Note 19 Note 19 Note 19 ns
tWDD Write Pulse to Data Delay Note 19 Note 19 Note 19 ns
Interrupt Timing
tWINS R/W to INTERRUPT Set Time 15 25 25 ns
tEINS CE to INTERRUPT Set Time 15 25 25 ns
tINS Address to INTERRUPT Set Time 15 25 25 ns
tOINR OE to INTERRUPT Reset Time[17] 15 25 25 ns
tEINR CE to INTERRUPT Reset Time[17] 15 25 25 ns
tINR Address to INTERRUPT Reset Time[17] 15 25 25 ns
Shaded areas contain preliminary information.
Switching Characteristics Over the Operating Range[7, 12] (continued)
Parameter Description
7C131-15[4]
7C131A-15
7C141-15
7C130-25[4]
7C131-25
7C140-25
7C141-25
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30
Unit
Min Max Min Max Min Max
Notes
17. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
18. CY7C140/CY7C141 only.
19. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 8 of 19
Switching Characteristics Over the Operating Range[7,12]
Parameter Description
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55 Unit
Min Max Min Max Min Max
Read Cycle
tRC Read Cycle Time 35 45 55 ns
tAA Address to Data Valid[13] 35 45 55 ns
tOHA Data Hold from Address Change 0 0 0 ns
tACE CE LOW to Data Valid[13] 35 45 55 ns
tDOE OE LOW to Data Valid[13] 20 25 25 ns
tLZOE OE LOW to Low Z[10, 14, 15] 333ns
tHZOE OE HIGH to High Z[10, 14, 15] 20 20 25 ns
tLZCE CE LOW to Low Z[10, 14, 15] 555ns
tHZCE CE HIGH to High Z[10, 14, 15] 20 20 25 ns
tPU CE LOW to Power Up[10] 000ns
tPD CE HIGH to Power Down[10] 35 35 35 ns
Write Cycle[16]
tWC Write Cycle Time 35 45 55 ns
tSCE CE LOW to Write End 30 35 40 ns
tAW Address Setup to Write End 30 35 40 ns
tHA Address Hold from Write End 2 2 2 ns
tSA Address Setup to Write Start 0 0 0 ns
tPWE R/W Pulse Width 25 30 30 ns
tSD Data Setup to Write End 15 20 20 ns
tHD Data Hold from Write End 0 0 0 ns
tHZWE R/W LOW to High Z[15] 20 20 25 ns
tLZWE R/W HIGH to Low Z[15] 000ns
Busy/Interrupt Timing
tBLA BUSY LOW from Address Match 20 25 30 ns
tBHA BUSY HIGH from Address Mismatch[17] 20 25 30 ns
tBLC BUSY LOW from CE LOW 20 25 30 ns
tBHC BUSY HIGH from CE HIGH[17] 20 25 30 ns
tPS Port Set Up for Priority 5 5 5 ns
tWB[18] R/W LOW after BUSY LOW 0 0 0 ns
tWH R/W HIGH after BUSY HIGH 30 35 35 ns
tBDD BUSY HIGH to Valid Data 35 45 45 ns
tDDD Write Data Valid to Read Data Valid Note 19 Note 19 Note 19 ns
tWDD Write Pulse to Data Delay Note 19 Note 19 Note 19 ns
Interrupt Timing
tWINS R/W to INTERRUPT Set Time 25 35 45 ns
tEINS CE to INTERRUPT Set Time 25 35 45 ns
tINS Address to INTERRUPT Set Time 25 35 45 ns
tOINR OE to INTERRUPT Reset Time[17] 25 35 45 ns
tEINR CE to INTERRUPT Reset Time[17] 25 35 45 ns
tINR Address to INTERRUPT Reset Time[17] 25 35 45 ns
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 9 of 19
Switching Waveforms
Figure 5. Read Cycle No. 1[20, 21]
Figure 6. Read Cycle No. 2[20, 22]
Figure 7. Read Cycle No. 3[21]
Notes
20. R/W is HIGH for read cycle.
21. Device is continuously selected, CE = VIL and OE = VIL.
22. Address valid prior to or coincident with CE transition LOW.
tRC
tAA
tOHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
Either Port Address Access
tACE
tLZOE
tDOE tHZOE
tHZCE
DATA VALID
DATA OUT
CE
OE
tLZCE
tPU
ICC
ISB
tPD
Either Port CE/OE Access
tBHA
tBDD
VALID
tDDD
tWDD
ADDRESS MATCH
ADDRESS MATCH
R/WR
ADDRESSR
DINR
ADDRESSL
BUSY
L
DOUTL
tPS
tBLA
Read with BUSY, Master: CY7C130 and CY7C131
tRC
tPWE
VALID
tHD
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 10 of 19
Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port[16, 23]
Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[17, 24]
Switching Waveforms (continued)
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA tPWE
tHD
tSD
tHA
CE
R/W
ADDRESS
tHZOE
OE
DOUT
DATAIN
Either Port
tAW
tWC
tSCE
tSA tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
DATA VALID
tLZWE
ADDRESS
CE
R/W
DATAOUT
DATAIN
Notes
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required tSD.
24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 11 of 19
Figure 10. Busy Timing Diagram No. 1 (CE Arbitration)
Figure 11. Busy Timing Diagram No. 2 (Address Arbitration)
Switching Waveforms (continued)
ADDRESS MATCH
tPS
CEL Valid First:
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESS L,R
BUSYR
CEL
CER
BUSYL
CER
CEL
ADDRESSL,R
CER Valid First:
Left Address Valid First:
ADDRESS MATCH
tPS
ADDRESSL
BUSY
R
ADDRESS MISMATCH
tRC or tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MISMATCH
tPS
ADDRESSL
BUSY
L
tRC or tWC
tBLA tBHA
ADDRESSR
Right Address Valid First:
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 13 of 19
Figure 13. Interrupt Timing Diagrams
Switching Waveforms (continued)
WRITE 3FF
tINS
tWC
tEINS
Right Side Clears INTR
tHA
tSA tWINS
READ 3FF
tRC
tEINR
tHA tINT
tOINR
WRITE 3FE
tINS
tWC
tEINS
tHA
tSA tWINS
Right Side Sets INTL
Left Side Sets INTR
Left Side Clears INTL
READ 3FE
tEINR
tHA tINR
tOINR
tRC
ADDR
R
CEL
R/WL
INTL
OEL
ADDRR
R/WR
CER
INTL
ADDR
R
CER
R/WR
INTR
OER
ADDR
L
R/WL
CEL
INTR
[+] Feedback [+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 14 of 19
Typical DC and AC Characteristics
1.4
1.0
0.4
4.0 4.5 5.0 5.5 6.0 –55 25 125
1.2
1.0
120
100
80
60
40
20
0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (C) OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
0.8
0.6
0.6
NORMALIZED ICC, ISB
VCC = 5.0V
VIN = 5.0V
VCC = 5.0V
TA = 25C
0
ICC
1.6
1.4
1.2
1.0
0.8
–55 125
NORMALIZED tAA
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (C)
1.4
1.3
1.2
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED tAA
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.8
1.25
1.0
0.75
10 40
NORMALIZED ICC
0.50
NORMALIZED ICC vs. CYCLE TIME
CYCLE FREQUENCY (MHz)
3.0
2.5
2.0
1.5
0.5
0 1.0 2.0 3.0 5.0
NORMALIZED tPC
25.0
30.0
20.0
10.0
5.0
0 200 400 600 800
DELTA tAA (ns)
0
15.0
0.0
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
4.0 1000
1.0
20 30
0.2
0.6
1.2
ISB3 0.2
0.4
25
1.1
VCC = 4.5V
VIN = 0.5V
NORMALIZED ICC, ISB
ICC
ISB3
TA = 25CVCC = 5.0V
VCC = 5.0V
TA = 25C
TA = 25C
VCC = 4.5V
VCC = 4.5V
TA = 25C
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CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 15 of 19
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
55 CY7C130-55PC P25 48-Pin (600 Mil) Molded DIP Commercial
15 CY7C131A-15JXI J69 52-Pin Pb-Free Plastic Leaded Chip Carrier Industrial
CY7C131-15NXI N52 52-Pin Pb-Free Plastic Quad Flatpack
25 CY7C131-25JXC J69 52-Pin Pb-Free Plastic Leaded Chip Carrier Commercial
CY7C131-25NC N52 52-Pin Plastic Quad Flatpack
CY7C131-25NXC N52 52-Pin Pb-Free Plastic Quad Flatpack
55 CY7C131-55JC J69 52-Pin Plastic Leaded Chip Carrier Commercial
CY7C131-55JXC J69 52-Pin Pb-Free Plastic Leaded Chip Carrier
CY7C131-55NXC N52 52-Pin Pb-Free Plastic Quad Flatpack
CY7C131-55JXI J69 52-Pin Pb-Free Plastic Leaded Chip Carrier Industrial
CY7C131-55NXI N52 52-Pin Pb-Free Plastic Quad Flatpack
Package Diagrams
Figure 14. 48-Pin (600 Mil) Sidebraze DIP D26
MIL-STD-1835 D-14 Config. C
51-80044 **
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CY7C130, CY7C130A
CY7C131, CY7C131A
Document #: 38-06002 Rev. *F Page 18 of 19
Document History Page
Document Title: CY7C130/CY7C130A/CY7C131/CY7C131A 1K x 8 Dual-Port Static RAM
Document Number: 38-06002
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 110169 SZV 09/29/01 Change from Spec number: 38-00027 to 38-06002
*A 122255 RBI 12/26/02 Power up requirements added to Maximum Ratings Information
*B 236751 YDT See ECN Removed cross information from features section
*C 325936 RUY See ECN Added pin definitions table, 52-pin PQFP package diagram and Pb-free
information
*D 393153 YIM See ECN Added CY7C131-15JI to ordering information
Added Pb-Free parts to ordering information:
CY7C131-15JXI
*E 2623540 VKN/PYRS 12/17/08 Added CY7C130A and CY7C131A parts
Removed military information
Updated ordering information table
*F 2897217 RAME 03/22/2010 Updated Ordering Information
Updated Package Diagrams
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Document #: 38-06002 Rev. *F Revised March 22, 2010 Page 19 of 19
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C130, CY7C130A
CY7C131, CY7C131A
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a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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