Kinetis KL46 Sub-Family
48 MHz Cortex-M0+ Based Microcontroller
Designed with efficiency in mind. Compatible with all other
Kinetis L families as well as Kinetis K4x family. General purpose
MCU with USB 2.0 and segment LCD, featuring market leading
ultra low-power to provide developers an appropriate entry-level
32-bit solution.
This product offers:
Run power consumption down to 50 μA/MHz in very low
power run mode
Static power consumption down to 2 μA with full state
retention and 4.5 μs wakeup
Ultra-efficient Cortex-M0+ processor running up to 48 MHz
with industry leading throughput
Memory option is up to 256 KB Flash and 32 KB RAM
Energy-saving architecture is optimized for low power with
90 nm TFS technology, clock and power gating techniques,
and zero wait state flash memory controller
Performance
48 MHz ARM® Cortex®-M0+ core
Memories and memory interfaces
Up to 256 KB program flash memory
Up to 32 KB SRAM
System peripherals
Nine low-power modes to provide power optimization
based on application requirements
COP Software watchdog
4-channel DMA controller, supporting up to 63 request
sources
Low-leakage wakeup unit
SWD debug interface and Micro Trace Buffer
Bit Manipulation Engine
Clocks
32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
Multi-purpose clock source
Operating Characteristics
Voltage range: 1.71 to 3.6 V
Flash write voltage range: 1.71 to 3.6 V
Temperature range (ambient): -40 to 105°C
Human-machine interface
Segment LCD controller supporting up to 47
frontplanes and 8 backplanes, or 51 frontplanes and
4 backplanes
Low-power hardware touch sensor interface (TSI)
Up to 84 general-purpose input/output (GPIO)
Communication interfaces
USB full-/low-speed On-the-Go controller with on-
chip transceiver and 5 V to 3.3 V regulator
Two 16-bit SPI modules
I2S (SAI) module
One low power UART module
Two UART modules
Two I2C module
Analog Modules
16-bit SAR ADC
12-bit DAC
Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
Timers
Six channel Timer/PWM (TPM)
Two 2-channel Timer/PWM modules
MKL46ZxxxVLH4
MKL46Z256VMP4
MKL46ZxxxVLL4
MKL46ZxxxVMC4
64-pin LQFP (LH)
10 x 10 x 1.4 Pitch 0.5
mm
64-pin MAPBGA (MP)
5 x 5 x 1.23 Pitch 0.5
mm
100-pin LQFP (LL)
14 x 14 x 1.4 Pitch 0.5
mm
121-pin MAPBGA (MP)
8 x 8 x 0.8 Pitch 0.65
mm
Freescale Semiconductor, Inc. Document Number: KL46P121M48SF4
Data Sheet: Technical Data Rev 5 08/2014
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2012–2014 Freescale
Semiconductor, Inc. All rights reserved.
Periodic interrupt timers
16-bit low-power timer (LPTMR)
Real time clock
Security and integrity modules
80-bit unique identification number per chip
Ordering Information 1
Part Number Memory Maximum number of I\O's
Flash (KB) SRAM (KB)
MKL46Z128VLH4 128 16 50
MKL46Z256VLH4 256 32 50
MKL46Z256VMP4 256 32 50
MKL46Z128VLL4 128 16 84
MKL46Z256VLL4 256 32 84
MKL46Z128VMC4 128 16 84
MKL46Z256VMC4 256 32 84
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type Description Resource
Selector Guide The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Reference
Manual
The Reference Manual contains a comprehensive description of
the structure and function (operation) of a device.
KL46P121M48SF4RM1
Data Sheet The Data Sheet includes electrical characteristics and signal
connections.
KL46P121M48SF41
Chip Errata The chip mask set Errata provides additional or corrective
information for a particular device mask set.
KINETIS_L_xN40H2
Package
drawing
Package dimensions are provided in package drawings. LQFP 64-pin: 98ASS23234W1
MAPBGA 64-pin: 98ASA00420D1
LQFP 100-pin: 98ASS23308W1
MAPBGA 121-pin: 98ASA00344D1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x
replaced by the revision of the device you are using.
2Kinetis KL46 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings..................................................................................4
1.1 Thermal handling ratings............................................... 4
1.2 Moisture handling ratings...............................................4
1.3 ESD handling ratings..................................................... 4
1.4 Voltage and current operating ratings............................4
2 General................................................................................. 5
2.1 AC electrical characteristics...........................................5
2.2 Nonswitching electrical specifications............................6
2.2.1 Voltage and current operating requirements......6
2.2.2 LVD and POR operating requirements.............. 6
2.2.3 Voltage and current operating behaviors...........7
2.2.4 Power mode transition operating behaviors.......8
2.2.5 Power consumption operating behaviors...........9
2.2.6 EMC radiated emissions operating behaviors... 15
2.2.7 Designing with radiated emissions in mind........16
2.2.8 Capacitance attributes....................................... 16
2.3 Switching specifications.................................................16
2.3.1 Device clock specifications................................ 16
2.3.2 General switching specifications........................17
2.4 Thermal specifications................................................... 17
2.4.1 Thermal operating requirements........................17
2.4.2 Thermal attributes..............................................17
3 Peripheral operating requirements and behaviors................ 18
3.1 Core modules................................................................ 18
3.1.1 SWD electricals .................................................18
3.2 System modules............................................................ 20
3.3 Clock modules............................................................... 20
3.3.1 MCG specifications............................................20
3.3.2 Oscillator electrical specifications...................... 22
3.4 Memories and memory interfaces................................. 24
3.4.1 Flash electrical specifications............................ 24
3.5 Security and integrity modules.......................................26
3.6 Analog............................................................................26
3.6.1 ADC electrical specifications..............................26
3.6.2 CMP and 6-bit DAC electrical specifications......31
3.6.3 12-bit DAC electrical characteristics.................. 33
3.7 Timers............................................................................36
3.8 Communication interfaces............................................. 36
3.8.1 USB electrical specifications..............................36
3.8.2 USB VREG electrical specifications...................37
3.8.3 SPI switching specifications...............................37
3.8.4 Inter-Integrated Circuit Interface (I2C) timing.....42
3.8.5 UART................................................................. 43
3.8.6 I2S/SAI switching specifications........................ 43
3.9 Human-machine interfaces (HMI)..................................47
3.9.1 TSI electrical specifications................................47
3.9.2 LCD electrical characteristics.............................48
4 Dimensions........................................................................... 49
4.1 Obtaining package dimensions......................................49
5 Pinout....................................................................................50
5.1 KL46 Signal Multiplexing and Pin Assignments.............50
5.2 KL46 pinouts..................................................................54
6 Ordering parts....................................................................... 58
6.1 Determining valid orderable parts..................................58
7 Part identification...................................................................59
7.1 Description.....................................................................59
7.2 Format........................................................................... 59
7.3 Fields............................................................................. 59
7.4 Example.........................................................................60
8 Terminology and guidelines.................................................. 60
8.1 Definition: Operating requirement..................................60
8.2 Definition: Operating behavior....................................... 60
8.3 Definition: Attribute........................................................ 61
8.4 Definition: Rating........................................................... 61
8.5 Result of exceeding a rating.......................................... 61
8.6 Relationship between ratings and operating
requirements..................................................................62
8.7 Guidelines for ratings and operating requirements........62
8.8 Definition: Typical value.................................................63
8.9 Typical value conditions.................................................64
9 Revision history.....................................................................64
Kinetis KL46 Sub-Family, Rev5 08/2014. 3
Freescale Semiconductor, Inc.
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level 3 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
–500 +500 V 2
ILAT Latch-up current at ambient temperature of 105 °C –100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
Ratings
4Kinetis KL46 Sub-Family, Rev5 08/2014.
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1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current 120 mA
VIO IO pin input voltage –0.3 VDD + 0.3 V
IDInstantaneous maximum current single pin limit (applies to
all port pins)
–25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB_DP USB_DP input voltage –0.3 3.63 V
VUSB_DM USB_DM input voltage –0.3 3.63 V
VREGIN USB regulator input –0.3 6.0 V
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume the output
pins have the following characteristics.
CL=30 pF loads
Slew rate disabled
Normal drive strength
General
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2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VIH Input high voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
V
V
VIL Input low voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD V
IICIO IO pin negative DC injection current — single pin
VIN < VSS-0.3V -3 mA
1
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
Negative current injection -25 mA
VODPU Open drain pullup voltage level VDD VDD V2
VRAM VDD voltage required to retain RAM 1.2 V
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
Table continues on the next page...
General
6Kinetis KL46 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
VLVDH Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
±60 mV
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
±40 mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
VOH Output high voltage — Normal drive pad (except
RESET_b)
2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
VDD – 0.5
VDD – 0.5
V
V
1, 2
VOH Output high voltage — High drive pad (except
RESET_b)
2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
VDD – 0.5
VDD – 0.5
V
V
1, 2
IOHT Output high current total for all ports 100 mA
Table continues on the next page...
General
Kinetis KL46 Sub-Family, Rev5 08/2014. 7
Freescale Semiconductor, Inc.
Table 7. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
VOL Output low voltage — Normal drive pad
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
0.5
0.5
V
V
1
VOL Output low voltage — High drive pad
2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
0.5
0.5
V
V
1
IOLT Output low current total for all ports 100 mA
IIN Input leakage current (per pin) for full temperature
range
1 μA 3
IIN Input leakage current (per pin) at 25 °C 0.025 μA 3
IIN Input leakage current (total all pins) for full
temperature range
μA 3
IOZ Hi-Z (off-state) leakage current (per pin) 1 μA
RPU Internal pullup resistors 20 50 4
1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSxRUN recovery times in the following table
assume this clock configuration:
CPU and system clocks = 48 MHz
Bus and flash clock = 24 MHz
FEI clock mode
POR and VLLSxRUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 8. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
tPOR After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
300 μs 1
Table continues on the next page...
General
8Kinetis KL46 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table 8. Power mode transition operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
VLLS0 RUN
113
124
μs
VLLS1 RUN
112
124
μs
VLLS3 RUN
53
60
μs
LLS RUN
4.5
5.0
μs
VLPS RUN
4.5
5.0
μs
STOP RUN
4.5
5.0
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 9. Power consumption operating behaviors
Symbol Description Typ. Max Unit Note
IDDA Analog supply current See note mA 1
IDD_RUNCO_ CM Run mode current in compute operation
- 48 MHz core / 24 MHz flash/ bus
disabled, LPTMR running using 4 MHz
internal reference clock, CoreMark®
benchmark code executing from flash,
at 3.0 V
6.7 mA 2
IDD_RUNCO Run mode current in compute operation
- 48 MHz core / 24 MHz flash / bus
clock disabled, code of while(1) loop
executing from flash, at 3.0 V
4.5 5.1 mA 3
IDD_RUN Run mode current - 48 MHz core / 24
MHz bus and flash, all peripheral clocks
disabled, code executing from flash
at 1.8 V 5.6 6.3 mA 3
at 3.0 V 5.4 6.0 mA
IDD_RUN Run mode current - 48 MHz core / 24
MHz bus and flash, all peripheral clocks
enabled, code executing from flash, at
1.8 V
6.9 7.3 mA 3, 4
Table continues on the next page...
General
Kinetis KL46 Sub-Family, Rev5 08/2014. 9
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Table 9. Power consumption operating behaviors (continued)
Symbol Description Typ. Max Unit Note
Run mode current - 48 MHz core / 24
MHz bus and flash, all peripheral clocks
enabled, code executing from flash, at
3.0 V
at 25 °C 6.9 7.1 mA
at 125 °C 7.3 7.6 mA
IDD_WAIT Wait mode current - core disabled / 48
MHz system / 24 MHz bus / flash
disabled (flash doze enabled), all
peripheral clocks disabled, at 3.0 V
2.9 3.5 mA 3
IDD_WAIT Wait mode current - core disabled / 24
MHz system / 24 MHz bus / flash
disabled (flash doze enabled), wait
mode reduced frequency current at 3.0
V — all peripheral clocks disabled
2.2 2.8 mA 3
IDD_PSTOP2 Stop mode current with partial stop 2
clocking option - core and system
disabled / 10.5 MHz bus, at 3.0 V
1.6 2.1 mA 3
IDD_VLPRCO _CM Very-low-power run mode current in
compute operation - 4 MHz core / 0.8
MHz flash / bus clock disabled, LPTMR
running with 4 MHz internal reference
clock, CoreMark benchmark code
executing from flash, at 3.0 V
798 µA 5
IDD_VLPRCO Very low power run mode current in
compute operation - 4 MHz core / 0.8
MHz flash / bus clock disabled, code
executing from flash, at 3.0 V
167 336 µA 6
IDD_VLPR Very low power run mode current - 4
MHz core / 0.8 MHz bus and flash, all
peripheral clocks disabled, code
executing from flash, at 3.0 V
192 354 µA 6
IDD_VLPR Very low power run mode current - 4
MHz core / 0.8 MHz bus and flash, all
peripheral clocks enabled, code
executing from flash, at 3.0 V
257 431 µA 4, 6
IDD_VLPW Very low power wait mode current -
core disabled / 4 MHz system / 0.8
MHz bus / flash disabled (flash doze
enabled), all peripheral clocks disabled,
at 3.0 V
112 286 µA 6
IDD_STOP Stop mode current at 3.0 V at 25 °C 306 328 µA
at 50 °C 322 349 µA
at 70 °C 348 382 µA
at 85 °C 384 433 µA
at 105 °C 481 578 µA
IDD_VLPS Very-low-power stop mode current at
3.0 V
at 25 °C 2.71 5.03 µA
at 50 °C 7.05 11.94 µA
at 70 °C 15.80 26.87 µA
Table continues on the next page...
General
10 Kinetis KL46 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table 9. Power consumption operating behaviors (continued)
Symbol Description Typ. Max Unit Note
at 85 °C 29.60 47.30 µA
at 105 °C 69.13 106.04 µA
IDD_LLS Low leakage stop mode current at 3.0
V
at 25 °C 2.00 2.7 µA
at 50 °C 3.96 5.14 µA
at 70 °C 7.77 10.71 µA
at 85 °C 14.15 18.79 µA
at 105 °C 33.20 43.67 µA
IDD_VLLS3 Very low-leakage stop mode 3 current
at 3.0 V
at 25 °C 1.5 2.2 µA
at 50 °C 2.83 3.55 µA
at 70 °C 5.53 7.26 µA
at 85 °C 9.92 12.71 µA
at 105 °C 22.90 29.23 µA
IDD_VLLS1 Very low-leakage stop mode 1 current
at 3.0V
at 25 °C 0.71 1.2 µA
at 50 °C 1.27 1.9 µA
at 70 °C 2.48 3.51 µA
at 85 °C 4.65 6.29 µA
at 105 °C 11.55 14.34 µA
IDD_VLLS0 Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0
V
at 25 °C 0.41 0.9 µA
at 50 °C 0.96 1.56 µA
at 70 °C 2.17 3.1 µA
at 85 °C 4.35 5.32 µA
at 105 °C 11.24 14.00 µA
IDD_VLLS0 Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0
V
at 25 °C 0.23 0.69 µA 7
at 50 °C 0.77 1.35 µA
at 70 °C 1.98 2.52 µA
at 85 °C 4.16 5.14 µA
at 105 °C 11.05 13.80 µA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. MCG configured for PEE mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
3. MCG configured for FEI mode.
4. Incremental current consumption from peripheral activity is not included.
5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
6. MCG configured for BLPI mode.
7. No brownout.
General
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Table 10. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
32 kHz IRC enabled.
52 52 52 52 52 52 µA
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS mode
with the crystal enabled.
206 228 237 245 251 258 µA
IEREFSTEN32KHz External 32 kHz crystal clock
adder by means of the
OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured
by entering all modes with the
crystal enabled.
VLLS1 440 490 540 560 570 580 nA
VLLS3 440 490 540 560 570 580
LLS 490 490 540 560 570 680
VLPS 510 560 560 560 610 680
STOP 510 560 560 560 610 680
ICMP CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP enabled
using the 6-bit DAC and a single external
input for compare. Includes 6-bit DAC power
consumption.
22 22 22 22 22 22 µA
IRTC RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
RTC_CR[OSCE] bit and the RTC ALARM set
for 1 minute. Includes ERCLK32K (32 kHz
external crystal) power consumption.
432 357 388 475 532 810 nA
IUART UART peripheral adder
measured by placing the
device in STOP or VLPS
mode with selected clock
source waiting for RX data at
115200 baud rate. Includes
selected clock source power
consumption.
MCGIRCLK
(4 MHz
internal
reference
clock)
66 66 66 66 66 66 µA
OSCERCLK
(4 MHz
external
crystal)
214 237 246 254 260 268
ITPM TPM peripheral adder
measured by placing the
device in STOP or VLPS
mode with selected clock
source configured for output
compare generating 100 Hz
clock signal. No load is
placed on the I/O generating
the clock signal. Includes
selected clock source and I/O
switching currents.
MCGIRCLK
(4 MHz
internal
reference
clock)
86 86 86 86 86 86 µA
OSCERCLK
(4 MHz
external
crystal)
235 256 265 274 280 287
Table continues on the next page...
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12 Kinetis KL46 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IBG Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by placing
the device in STOP or VLPS mode. ADC is
configured for low power mode using the
internal clock and continuous conversions.
366 366 366 366 366 366 µA
ILCD LCD peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
OSC0_CR[EREFSTEN, EREFSTEN] bits.
VIREG disabled, resistor bias network
enabled, 1/8 duty cycle, 8 x 36 configuration
for driving 288 Segments, 32 Hz frame rate,
no LCD glass connected. Includes
ERCLK32K (32 kHz external crystal) power
consumption.
555555µA
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
MCG in FBE for run mode, and BLPE for VLPR mode
USB regulator disabled
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFA
General
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4.00E-03
5.00E-03
6.00E-03
7.00E-03
8.00E-03
All Off
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
All Peripheral CLK Gates
000.00E+00
1.00E-03
2.00E-03
3.00E-03
'1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2
1 2 3 4 6 12 24 48
All On
CLK Ratio
Flash-Core
Core Freq (MHz)
Current Consumption on VDD(A)
Run Mode Current Vs Core Frequency
Figure 3. Run mode supply current vs. core frequency
General
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200.00E-06
250.00E-06
300.00E-06
350.00E-06
VLPR Mode Current Vs Core Frequency
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE
All Peripheral CLK Gates
000.00E+00
50.00E-06
100.00E-06
150.00E-06
'1
-
1
'1
-
2
'1
-
2
'1
-
4
1 2 4
All Off
All On
CLK Ratio
Flash-Core
Core Freq (MHz)
Current Consumption on VDD (A)
Figure 4. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors
Symbol Description Frequency
band
(MHz)
Typ. Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 12 dBμV 1,2
VRE2 Radiated emissions voltage, band 2 50–150 8 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 7 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 4 dBμV
VRE_IEC IEC level 0.15–1000 M 2,3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits -
Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM
Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic
application code. The reported emission level is the value of the maximum measured emission, rounded up to the next
whole number, from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 24 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
General
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2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
Symbol Description Min. Max. Unit
CIN Input capacitance 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications
Symbol Description Min. Max. Unit
Normal run mode
fSYS System and core clock 48 MHz
fBUS Bus clock 24 MHz
fFLASH Flash clock 24 MHz
fSYS_USB System and core clock when Full Speed USB in operation 20 MHz
fLPTMR LPTMR clock 24 MHz
VLPR and VLPS modes1
fSYS System and core clock 4 MHz
fBUS Bus clock 1 MHz
fFLASH Flash clock 1 MHz
fLPTMR LPTMR clock2 24 MHz
fERCLK External reference clock 16 MHz
fLPTMR_ERCLK LPTMR external reference clock 16 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
16 MHz
fTPM TPM asynchronous clock 8 MHz
fUART0 UART0 asynchronous clock 8 MHz
General
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1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 14. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled)
— Synchronous path
1.5 Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100 ns 2
GPIO pin interrupt pulse width — Asynchronous path 16 ns 2
Port rise and fall time 36 ns 3
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C
General
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2.4.2 Thermal attributes
Table 16. Thermal attributes
Board type Symbol Description 121
MAPBG
A
100
LQFP
64
LQFP
64
MAPBG
A
Unit Notes
Single-layer (1S) RθJA Thermal resistance, junction
to ambient (natural
convection)
94 64 69 49.8 °C/W 1
Four-layer (2s2p) RθJA Thermal resistance, junction
to ambient (natural
convection)
57 51 51 42.3 °C/W
Single-layer (1S) RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
81 54 58 40.9 °C/W
Four-layer (2s2p) RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
53 45 44 37.7 °C/W
RθJB Thermal resistance, junction
to board
40 37 33 39.2 °C/W 2
RθJC Thermal resistance, junction
to case
30 19 19 50.3 °C/W 3
ΨJT Thermal characterization
parameter, junction to
package top outside center
(natural convection)
8 4 4 2.2 °C/W 4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
Peripheral operating requirements and behaviors
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3.1.1 SWD electricals
Table 17. SWD full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 SWD_CLK frequency of operation
Serial wire debug
0
25
MHz
J2 SWD_CLK cycle period 1/J1 ns
J3 SWD_CLK clock pulse width
Serial wire debug
20
ns
J4 SWD_CLK rise and fall times 3 ns
J9 SWD_DIO input data setup time to SWD_CLK rise 10 ns
J10 SWD_DIO input data hold time after SWD_CLK rise 0 ns
J11 SWD_CLK high to SWD_DIO data valid 32 ns
J12 SWD_CLK high to SWD_DIO high-Z 5 ns
J2
J3 J3
J4 J4
SWD_CLK (input)
Figure 5. Serial wire clock input timing
Peripheral operating requirements and behaviors
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Figure 6. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 18. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
fints_ft Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
32.768 kHz
fints_t Internal reference frequency (slow clock) —
user trimmed
31.25 39.0625 kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using C3[SCTRIM] and C4[SCFTRIM]
± 0.3 ± 0.6 %fdco 1
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 18. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
Δfdco_t Total deviation of trimmed average DCO output
frequency over voltage and temperature
+0.5/-0.7 ± 3 %fdco 1, 2
Δfdco_t Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70 °C
± 0.4 ± 1.5 %fdco 1, 2
fintf_ft Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
4 MHz
Δfintf_ft Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
+1/-2 ± 3 %fintf_ft 2
fintf_t Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3 5 MHz
floc_low Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
kHz
floc_high Loss of external clock minimum frequency — (16/5) x
fints_t
kHz
FLL
ffll_ref FLL reference frequency range 31.25 39.0625 kHz
fdco DCO output
frequency range
Low range (DRS = 00)
640 × ffll_ref
20 20.97 25 MHz 3, 4
Mid range (DRS = 01)
1280 × ffll_ref
40 41.94 48 MHz
fdco_t_DMX3
2
DCO output
frequency
Low range (DRS = 00)
732 × ffll_ref
23.99 MHz 5, 6
Mid range (DRS = 01)
1464 × ffll_ref
47.97 MHz
Jcyc_fll FLL period jitter
fVCO = 48 MHz
180 ps 7
tfll_acquire FLL target frequency acquisition time 1 ms 8
PLL
fvco VCO operating frequency 48.0 100 MHz
Ipll PLL operating current
PLL at 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
1060 µA 9
Ipll PLL operating current
PLL at 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
600 µA 9
fpll_ref PLL reference frequency range 2.0 4.0 MHz
Jcyc_pll PLL period jitter (RMS)
fvco = 48 MHz
fvco = 100 MHz
120
ps
ps
10
Table continues on the next page...
Peripheral operating requirements and behaviors
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