U6264BDC07LLG1 - ZMD AG - Datasheet.Live

April 20, 2004

U6264B

Standard 8K x 8 SRAM

The U6264B is a static RAM manu-

factured using a CMOS process

technology with the following ope-

rating modes:

- Read - Standby

- Write - Data Retention

The memory array is based on a

6-transistor cell.

The circuit is activated by the rising

edge of E2 (at E1 = L), or the falling

edge of E1 (at E2 = H). The

address and control inputs open

simultaneously. According to the

information of W and G, the data

inputs, or outputs, are active. In a

Read cycle, the data outputs are

activated by the falling edge of G,

afterwards the data word read will

be available at the outputs DQ0 -

DQ7. After the address change, the

data outputs go High-Z until the

new read information is available.

The data outputs have no preferred

state. If the memory is driven by

CMOS levels in the active state,

and if there is no change of the

address, data input and control

signals W or G, the operating cur-

rent (at IO = 0 mA) drops to the

value of the operating current in the

Standby mode. The Read cycle is

finished by the falling edge of E2 or

W, or by the rising edge of E1,

respectively.

Data retention is guaranteed down

to 2 V. With the exception of E2, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required. This gate circuit

allows to achieve low power

standby requirements by activation

with TTL-levels too.

If the circuit is inactivated by

E2 = L, the standby current (TTL)

drops to 150 µA typ.

!8192 x 8 bit static CMOS RAM

!70 ns Access Times

!Common data inputs and

outputs

!Three-state outputs

!Typ. operating supply current

70 ns: 10 mA

!Standby current:

< 2 µA at Ta ≤ 70 °C

!Data retention current at 2 V:

< 1 µA at Ta ≤ 70 °C

!TTL/CMOS-compatible

!Automatic reduction of power

dissipation in long Read or Write

cycles

!Power supply voltage 5 V

!Operating temperature ranges:

0 to 70 °C

-40 to 85 °C

-40 to 125 °C

!QS 9000 Quality Standard

!ESD protection > 2000 V

(MIL STD 883C M3015.7)

!Latch-up immunity > 100 mA

!Packages: PDIP28 (600 mil)

SOP28 (330 mil)

Pin Description

Signal Name Signal Description

A0 - A12 Address Inputs

DQ0 - DQ7 Data In/Out

E1 Chip Enable 1

E2 Chip Enable 2

GOutput Enable

WWrite Enable

VCC Power Supply Voltage

VSS Ground

n.c. not connected

Pin Configuration

n.c. VCC

A12 W (WE)

A6 A8

A5 A9

A7 E2 (CE2)

A4 A11

A3 G (OE)

A2 A10

DQ1 DQ5

A1 E1 (CE1)

A0 DQ7

DQ0 DQ6

DQ2 DQ4

VSS DQ3

PDIP

Top View

SOP

Features Description

2 April 20, 2004

U6264B

Block Diagram

*H or L

Operating Mode E1 E2 W GDQ0 - DQ7

Standby/not selected

* L * * High-Z

H*** High-Z

Internal Read L H H H High-Z

Read L H H L Data Outputs Low-Z

Write L H L * Data Inputs High-Z

Truth Table

Address

Change

Detector

A10

Memory Cell

Array

256 Rows x

256 Columns

Row Decoder

Row Address

Inputs

Column Decoder

Common Data I/O

Sense Amplifier/

Write Control Logic

Clock

Generator

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Column Address

Inputs

VCC VSS W G

A11

A12

April 20, 2004

U6264B

aStresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating

only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability

bMaximum voltage is 7 V

cNot more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

Absolute Maximum Ratings aSymbol Min. Max. Unit

Power Supply Voltage VCC -0.3 7 V

Input Voltage VI-0.3 VCC + 0.5 bV

Output Voltage VO-0.3 VCC + 0.5 bV

Power Dissipation PD-1W

Operating Temperature C-Type

K-Type

A-Type

Ta0

-40

125

°C

Storage Temperature C/K-Type

A-Type

Tstg -55

-65

125

150

°C

Output Short-Circuit Current

at VCC = 5 V and VO = 0 V c| IOS |100mA

Characteristics

All voltages are referenced to VSS = 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.

Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI,as well as

input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,

with the exception of the tdis-times, in which cases transition is measured ± 200 mV from steady-state voltage.

d-2 V at Pulse Width 10 ns

Recommended

Operating Conditions Symbol Conditions Min. Max. Unit

Power Supply Voltage VCC 4.5 5.5 V

Data Retention Voltage VCC(DR) 2.0 V

Input Low Voltage dVIL -0.3 0.8 V

Input High Voltage VIH 2.2 VCC + 0.3 V

4 April 20, 2004

U6264B

Electrical Characteristics Symbol Conditions Min. Max. Unit

Supply Current - Operating Mode ICC(OP) VCC

VIL

VIH

tcW

= 5.5 V

= 0.8 V

= 2.2 V

= 70 ns

55 mA

Supply Current - Standby Mode

(CMOS level)

ICC(SB) VCC

VE1 = VE2

or VE2

C-Type

K-Type

A-Type

= 5.5 V

= VCC - 0.2 V

= 0.2 V

100

µA

Supply Current - Standby Mode

(TTL level)

ICC(SB)1 VCC

VE1 = VE2

or VE2

= 5.5 V

= 2.2 V

= 0.8 V

3mA

Supply Current - Data Retention

Mode

ICC(DR) VCC(DR)

VE1 = VE2

or VE2

C-Type

K-Type

A-Type

= 2 V

= VCC(DR) - 0.2 V

= 0.2 V

µA

Output High Voltage

Output Low Voltage

VOH

VOL

VCC

IOH

VCC

IOL

= 4.5 V

= -1.0 mA

= 4.5 V

= 3.2 mA

2.4

0.4

Output High Current

Output Low Current

IOH

IOL

VCC

VOH

VCC

VOL

= 4.5 V

= 2.4 V

= 4.5 V

= 0.4 V

3.2

-1 mA

Input Leakage Current

High

Low

IIH

IIL

VCC

VIH

C/K-Type

A-Type

VCC

VIL

C/K-Type

A-Type

= 5.5 V

= 0 V

-1

-2

µA

Output Leakage Current

High at Three-State Outputs

Low at Three-State Outputs

IOHZ

IOLZ

VCC

VOH

C/K-Type

A-Type

VCC

VOL

C/K-Type

A-Type

= 5.5 V

= 0 V

-1

-2

µA

April 20, 2004

U6264B

Switching Characteristics

Symbol

Min. Max. Unit

Alt. IEC

Time to Output in Low-Z tLZ tt(QX) 510ns

Cycle Time

Write Cycle Time

Read Cycle Time

tWC

tRC

tcW

tcR

Access Time

E1 LOW or E2 HIGH to Data Valid

G LOW to Data Valid

Address to Data Valid

tACE

tOE

tAA

ta(E)

ta(G)

ta(A)

Pulse Widths

Write Pulse Width

Chip Enable to End of Write

tWP

tCW

tw(W)

tw(E)

Setup Times

Address Setup Time

Chip Enable to End of Write

Write Pulse Width

Data Setup Time

tAS

tCW

tWP

tDS

tsu(A)

tsu(E)

tsu(W)

tsu(D)

Data Hold Time

Address Hold from End of Write

tDH

tAH

th(D)

th(A)

Output Hold Time from Address Change tOH tv(A) 5ns

E1 HIGH or E2 LOW to Output in High-Z

W LOW to Output in High-Z

G HIGH to Output in High-Z

tHZCE

tHZWE

tHZOE

tdis(E)

tdis(W)

tdis(G)

Data Retention Mode E1-Controlled

Data Retention

4.5 V

tDR trec

VCC

VCC(DR) ≥ 2 V

VE2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V

VCC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V

0 V

2.2 V

VCC(DR) ≥ 2 V

Data Retention Mode E2-Controlled

Data Retention trec

tDR

0.8 V

0.8 V VE2(DR) ≤ 0.2 V

4.5 V

0 V

VCC

Chip Deselect to Data Retention Time tDR : min 0 ns

Operating Recovery Time trec : min tcR

6 April 20, 2004

U6264B

Test Configuration for Functional Check

VIH

VIL

VSS

VCC

5 V

960

510

30 pFe

Simultaneous measure-

ment of all 8 output pins

Input level according to the

relevant test measurement

e In measurement of tdis(E), tdis(W), tdis(G) the capacitance is 5 pF.

All pins not under test must be connected with ground by capacitors.

A10

A11

A12

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Capacitance Conditions Symbol Min. Max. Unit

Input Capacitance VCC = 5.0 V

VI = VSS

CI8pF

Output Capacitance f = 1 MHz

Ta = 25 °CCO10 pF

Date of manufacture

(The first 2 digits indicating

the year, and the last 2

digits the calendar week.)

Leadfree Green Package

Product specification

Assembly location and

trace code

Internal Code

Ordering Code

Device Marking (example)

ZMD

U6264BS2K

07LL C 0425

1 ZZ G1

Access Time

07 = 70 ns

LLS2 07KU6264B

Typ e

Package

D = PDIP28 (600 mil, only C/K-Type)

S = SOP28 (330 mil) Type 1

S2 = SOP28 (330 mil) Type 2

Operating Temperature Range

C = 0 to 70 °C

K = -40 to 85 °C

A = -40 to 125 °C

Leadfree Option

blank = Standard Package

G1 = Leadfree Green Package f

Power Consumption

blank = Standard (only A-Type)

LL = Very Low Power (C/K-Type)

f on special request

Example

April 20, 2004

U6264B

th(D)

Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH)

Read Cycle 2 (during Read cycle: W = VIH)

Write Cycle 1 (W-controlled)

ta(A)

Previous Data Valid Output Data Valid

tcR

Addresses Valid

tv(A)

DQi

Output

tdis(E)

tcR

tsu(A) ta(E)

tsu(A)

tt(QX)

ta(G)

ta(E) tdis(E)

tdis(G)

Addresses Valid

Output Data Valid

DQi

Input

DQi

Output

tcW

tsu(E) th(A)

tw(W)

tsu(A)

tsu(E)

tsu(D)

tdis(W) tt(QX)

Addresses Valid

Input Data Valid

High-Z

8 April 20, 2004

U6264B

High-Z

tsu(A)

Input Data Valid

th(D)

tsu(W)

tw(E)

tsu(D)

tcW

Addresses Valid

tsu(E) th(A)

tt(QX) tdis(W)

DQi

Input

DQi

Output

tsu(A)

undefined L- or H-level

Write Cycle 2 (E1-controlled)

Write Cycle 3 (E2-controlled)

th(D)

DQi

Input

DQi

Output

tcW

tw(E) th(A)

tsu(W)

tsu(E)

tsu(D)

tdis(W)

tt(QX)

Addresses Valid

Input Data Valid

High-Z

The information describes the type of component and shall not be considered as assured characteristic. Terms of

delivery and rights to change design reserved.

Zentrum Mikroelektronik Dresden AG

Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany

Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de

April 20, 2004

U6264B

LIFE SUPPORT POLICY

ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or other applications intended to support or sustain life, or for any other application in which

the failure of the ZMD product could create a situation where personal injury or death may occur.

Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.

LIMITED WARRANTY

The information in this document has been carefully checked and is believed to be reliable. However Zentrum

Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information

and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.

The information in this document describes the type of component and shall not be considered as assured charac-

teristics.

ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-

mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This

document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and

conditions of sale.

ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,

presented in this publication at any time and without notice.